diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2009-02-25 09:25:00 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-27 02:16:36 -0500 |
commit | e4f341103e4a2b35f56a0f89802f1b1448e8d04b (patch) | |
tree | 8c5c2789c3ba29ecb62587e2a8016b02dedfe714 | |
parent | ffbcfed441b9ba74ce77f215eed6925f6a0b82a3 (diff) |
tg3: Invert nvram_read() and nvram_read_swab()
This patch removes the blind byteswap of NVRAM data as it is read in.
To preserve the logic at the call sites, this patch also inverts every
call to tg3_nvram_read() and tg3_nvram_read_swab(). The call swap gets
confusing within tg3_nvram_read_le() (LE is a misnomer), but the reader
should be able to convince himself / herself that the resulting behavior
is still unchanged.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/tg3.c | 50 |
1 files changed, 28 insertions, 22 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index d32b3efb2175..a2ca6ab2df00 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -2245,6 +2245,12 @@ static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |||
2245 | return addr; | 2245 | return addr; |
2246 | } | 2246 | } |
2247 | 2247 | ||
2248 | /* NOTE: Data read in from NVRAM is byteswapped according to | ||
2249 | * the byteswapping settings for all other register accesses. | ||
2250 | * tg3 devices are BE devices, so on a BE machine, the data | ||
2251 | * returned will be exactly as it is seen in NVRAM. On a LE | ||
2252 | * machine, the 32-bit value will be byteswapped. | ||
2253 | */ | ||
2248 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | 2254 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2249 | { | 2255 | { |
2250 | int ret; | 2256 | int ret; |
@@ -2268,7 +2274,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | |||
2268 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | 2274 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); |
2269 | 2275 | ||
2270 | if (ret == 0) | 2276 | if (ret == 0) |
2271 | *val = swab32(tr32(NVRAM_RDDATA)); | 2277 | *val = tr32(NVRAM_RDDATA); |
2272 | 2278 | ||
2273 | tg3_disable_nvram_access(tp); | 2279 | tg3_disable_nvram_access(tp); |
2274 | 2280 | ||
@@ -2290,7 +2296,7 @@ static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val) | |||
2290 | static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val) | 2296 | static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val) |
2291 | { | 2297 | { |
2292 | u32 v; | 2298 | u32 v; |
2293 | int res = tg3_nvram_read(tp, offset, &v); | 2299 | int res = tg3_nvram_read_swab(tp, offset, &v); |
2294 | if (!res) | 2300 | if (!res) |
2295 | *val = cpu_to_le32(v); | 2301 | *val = cpu_to_le32(v); |
2296 | return res; | 2302 | return res; |
@@ -9197,7 +9203,7 @@ static int tg3_test_nvram(struct tg3 *tp) | |||
9197 | __le32 *buf; | 9203 | __le32 *buf; |
9198 | int i, j, k, err = 0, size; | 9204 | int i, j, k, err = 0, size; |
9199 | 9205 | ||
9200 | if (tg3_nvram_read_swab(tp, 0, &magic) != 0) | 9206 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
9201 | return -EIO; | 9207 | return -EIO; |
9202 | 9208 | ||
9203 | if (magic == TG3_EEPROM_MAGIC) | 9209 | if (magic == TG3_EEPROM_MAGIC) |
@@ -10146,7 +10152,7 @@ static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |||
10146 | 10152 | ||
10147 | tp->nvram_size = EEPROM_CHIP_SIZE; | 10153 | tp->nvram_size = EEPROM_CHIP_SIZE; |
10148 | 10154 | ||
10149 | if (tg3_nvram_read_swab(tp, 0, &magic) != 0) | 10155 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
10150 | return; | 10156 | return; |
10151 | 10157 | ||
10152 | if ((magic != TG3_EEPROM_MAGIC) && | 10158 | if ((magic != TG3_EEPROM_MAGIC) && |
@@ -10162,7 +10168,7 @@ static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |||
10162 | cursize = 0x10; | 10168 | cursize = 0x10; |
10163 | 10169 | ||
10164 | while (cursize < tp->nvram_size) { | 10170 | while (cursize < tp->nvram_size) { |
10165 | if (tg3_nvram_read_swab(tp, cursize, &val) != 0) | 10171 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
10166 | return; | 10172 | return; |
10167 | 10173 | ||
10168 | if (val == magic) | 10174 | if (val == magic) |
@@ -10178,7 +10184,7 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp) | |||
10178 | { | 10184 | { |
10179 | u32 val; | 10185 | u32 val; |
10180 | 10186 | ||
10181 | if (tg3_nvram_read_swab(tp, 0, &val) != 0) | 10187 | if (tg3_nvram_read(tp, 0, &val) != 0) |
10182 | return; | 10188 | return; |
10183 | 10189 | ||
10184 | /* Selfboot format */ | 10190 | /* Selfboot format */ |
@@ -10187,7 +10193,7 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp) | |||
10187 | return; | 10193 | return; |
10188 | } | 10194 | } |
10189 | 10195 | ||
10190 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { | 10196 | if (tg3_nvram_read_swab(tp, 0xf0, &val) == 0) { |
10191 | if (val != 0) { | 10197 | if (val != 0) { |
10192 | tp->nvram_size = (val >> 16) * 1024; | 10198 | tp->nvram_size = (val >> 16) * 1024; |
10193 | return; | 10199 | return; |
@@ -11342,14 +11348,14 @@ static void __devinit tg3_read_partno(struct tg3 *tp) | |||
11342 | unsigned int i; | 11348 | unsigned int i; |
11343 | u32 magic; | 11349 | u32 magic; |
11344 | 11350 | ||
11345 | if (tg3_nvram_read_swab(tp, 0x0, &magic)) | 11351 | if (tg3_nvram_read(tp, 0x0, &magic)) |
11346 | goto out_not_found; | 11352 | goto out_not_found; |
11347 | 11353 | ||
11348 | if (magic == TG3_EEPROM_MAGIC) { | 11354 | if (magic == TG3_EEPROM_MAGIC) { |
11349 | for (i = 0; i < 256; i += 4) { | 11355 | for (i = 0; i < 256; i += 4) { |
11350 | u32 tmp; | 11356 | u32 tmp; |
11351 | 11357 | ||
11352 | if (tg3_nvram_read(tp, 0x100 + i, &tmp)) | 11358 | if (tg3_nvram_read_swab(tp, 0x100 + i, &tmp)) |
11353 | goto out_not_found; | 11359 | goto out_not_found; |
11354 | 11360 | ||
11355 | vpd_data[i + 0] = ((tmp >> 0) & 0xff); | 11361 | vpd_data[i + 0] = ((tmp >> 0) & 0xff); |
@@ -11441,9 +11447,9 @@ static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) | |||
11441 | { | 11447 | { |
11442 | u32 val; | 11448 | u32 val; |
11443 | 11449 | ||
11444 | if (tg3_nvram_read_swab(tp, offset, &val) || | 11450 | if (tg3_nvram_read(tp, offset, &val) || |
11445 | (val & 0xfc000000) != 0x0c000000 || | 11451 | (val & 0xfc000000) != 0x0c000000 || |
11446 | tg3_nvram_read_swab(tp, offset + 4, &val) || | 11452 | tg3_nvram_read(tp, offset + 4, &val) || |
11447 | val != 0) | 11453 | val != 0) |
11448 | return 0; | 11454 | return 0; |
11449 | 11455 | ||
@@ -11475,7 +11481,7 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) | |||
11475 | return; | 11481 | return; |
11476 | } | 11482 | } |
11477 | 11483 | ||
11478 | if (tg3_nvram_read_swab(tp, offset, &val)) | 11484 | if (tg3_nvram_read(tp, offset, &val)) |
11479 | return; | 11485 | return; |
11480 | 11486 | ||
11481 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | 11487 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> |
@@ -11501,7 +11507,7 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp) | |||
11501 | u32 ver_offset; | 11507 | u32 ver_offset; |
11502 | int i, bcnt; | 11508 | int i, bcnt; |
11503 | 11509 | ||
11504 | if (tg3_nvram_read_swab(tp, 0, &val)) | 11510 | if (tg3_nvram_read(tp, 0, &val)) |
11505 | return; | 11511 | return; |
11506 | 11512 | ||
11507 | if (val != TG3_EEPROM_MAGIC) { | 11513 | if (val != TG3_EEPROM_MAGIC) { |
@@ -11511,14 +11517,14 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp) | |||
11511 | return; | 11517 | return; |
11512 | } | 11518 | } |
11513 | 11519 | ||
11514 | if (tg3_nvram_read_swab(tp, 0xc, &offset) || | 11520 | if (tg3_nvram_read(tp, 0xc, &offset) || |
11515 | tg3_nvram_read_swab(tp, 0x4, &start)) | 11521 | tg3_nvram_read(tp, 0x4, &start)) |
11516 | return; | 11522 | return; |
11517 | 11523 | ||
11518 | offset = tg3_nvram_logical_addr(tp, offset); | 11524 | offset = tg3_nvram_logical_addr(tp, offset); |
11519 | 11525 | ||
11520 | if (!tg3_fw_img_is_valid(tp, offset) || | 11526 | if (!tg3_fw_img_is_valid(tp, offset) || |
11521 | tg3_nvram_read_swab(tp, offset + 8, &ver_offset)) | 11527 | tg3_nvram_read(tp, offset + 8, &ver_offset)) |
11522 | return; | 11528 | return; |
11523 | 11529 | ||
11524 | offset = offset + ver_offset - start; | 11530 | offset = offset + ver_offset - start; |
@@ -11537,7 +11543,7 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp) | |||
11537 | for (offset = TG3_NVM_DIR_START; | 11543 | for (offset = TG3_NVM_DIR_START; |
11538 | offset < TG3_NVM_DIR_END; | 11544 | offset < TG3_NVM_DIR_END; |
11539 | offset += TG3_NVM_DIRENT_SIZE) { | 11545 | offset += TG3_NVM_DIRENT_SIZE) { |
11540 | if (tg3_nvram_read_swab(tp, offset, &val)) | 11546 | if (tg3_nvram_read(tp, offset, &val)) |
11541 | return; | 11547 | return; |
11542 | 11548 | ||
11543 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) | 11549 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
@@ -11549,12 +11555,12 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp) | |||
11549 | 11555 | ||
11550 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | 11556 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) |
11551 | start = 0x08000000; | 11557 | start = 0x08000000; |
11552 | else if (tg3_nvram_read_swab(tp, offset - 4, &start)) | 11558 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
11553 | return; | 11559 | return; |
11554 | 11560 | ||
11555 | if (tg3_nvram_read_swab(tp, offset + 4, &offset) || | 11561 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
11556 | !tg3_fw_img_is_valid(tp, offset) || | 11562 | !tg3_fw_img_is_valid(tp, offset) || |
11557 | tg3_nvram_read_swab(tp, offset + 8, &val)) | 11563 | tg3_nvram_read(tp, offset + 8, &val)) |
11558 | return; | 11564 | return; |
11559 | 11565 | ||
11560 | offset += val - start; | 11566 | offset += val - start; |
@@ -12349,8 +12355,8 @@ static int __devinit tg3_get_device_address(struct tg3 *tp) | |||
12349 | } | 12355 | } |
12350 | if (!addr_ok) { | 12356 | if (!addr_ok) { |
12351 | /* Next, try NVRAM. */ | 12357 | /* Next, try NVRAM. */ |
12352 | if (!tg3_nvram_read(tp, mac_offset + 0, &hi) && | 12358 | if (!tg3_nvram_read_swab(tp, mac_offset + 0, &hi) && |
12353 | !tg3_nvram_read(tp, mac_offset + 4, &lo)) { | 12359 | !tg3_nvram_read_swab(tp, mac_offset + 4, &lo)) { |
12354 | dev->dev_addr[0] = ((hi >> 16) & 0xff); | 12360 | dev->dev_addr[0] = ((hi >> 16) & 0xff); |
12355 | dev->dev_addr[1] = ((hi >> 24) & 0xff); | 12361 | dev->dev_addr[1] = ((hi >> 24) & 0xff); |
12356 | dev->dev_addr[2] = ((lo >> 0) & 0xff); | 12362 | dev->dev_addr[2] = ((lo >> 0) & 0xff); |