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authorAlex Deucher <alexdeucher@gmail.com>2008-10-16 19:19:33 -0400
committerDave Airlie <airlied@linux.ie>2008-10-17 17:10:54 -0400
commitb2ceddfa52cbeb244b90096f1e8d3e9f7e0ce299 (patch)
tree85d16b999760daaff85f68feafe7bfbbd60fa8f8
parentf0738e92403466d45cfb5008da668260c77fff4b (diff)
radeon: add RS400 family support.
This adds support for the RS400 family of IGPs for Intel CPUs. Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h1
-rw-r--r--include/drm/drm_pciids.h6
3 files changed, 9 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index e6e0c2933efd..a83d7615ba7f 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -133,9 +133,10 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
133 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 133 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
134 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); 134 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
135 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); 135 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
136 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) { 136 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
137 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
137 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 138 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
138 RADEON_WRITE(RS480_AGP_BASE_2, 0); 139 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
139 } else { 140 } else {
140 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 141 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
141 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) 142 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
@@ -352,6 +353,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
352 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || 353 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
353 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || 354 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
354 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || 355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
356 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 357 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
356 DRM_INFO("Loading R300 Microcode\n"); 358 DRM_INFO("Loading R300 Microcode\n");
357 for (i = 0; i < 256; i++) { 359 for (i = 0; i < 256; i++) {
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 9d752bc0602b..9278429af9ed 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -123,6 +123,7 @@ enum radeon_family {
123 CHIP_RV380, 123 CHIP_RV380,
124 CHIP_R420, 124 CHIP_R420,
125 CHIP_RV410, 125 CHIP_RV410,
126 CHIP_RS400,
126 CHIP_RS480, 127 CHIP_RS480,
127 CHIP_RS690, 128 CHIP_RS690,
128 CHIP_RS740, 129 CHIP_RS740,
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index e3a7b93fdefc..401cc8b7e88c 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -113,8 +113,10 @@
113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ 115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
116 {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 116 {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
117 {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 117 {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
118 {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
119 {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
118 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 120 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
119 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 121 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
120 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 122 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \