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authorMagnus Damm <damm@opensource.se>2010-03-10 00:13:12 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-03-14 23:06:45 -0400
commit9615b37c5c8fed963811c100053d495c412880fb (patch)
tree288017e4a66ce9f97d2175bf188da9a210782bdc
parent6676a1701b0b135dacbb7cfeef48004315300df0 (diff)
ARM: mach-shmobile: sh7367 SDHI vector merge
Merge the SDHI vectors for sh7367 using the recently merged INTC force_enable/disable feature. With this in place SDHI hotplug is supported using the drivers sh_mobile_sdhi and tmio_mmc. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/arm/mach-shmobile/intc-sh7367.c46
1 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
index 6a547b47aabb..5ff70cadfc32 100644
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ b/arch/arm/mach-shmobile/intc-sh7367.c
@@ -27,6 +27,8 @@
27 27
28enum { 28enum {
29 UNUSED_INTCA = 0, 29 UNUSED_INTCA = 0,
30 ENABLED,
31 DISABLED,
30 32
31 /* interrupt sources INTCA */ 33 /* interrupt sources INTCA */
32 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A, 34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
@@ -46,8 +48,8 @@ enum {
46 MSIOF2, MSIOF1, 48 MSIOF2, MSIOF1,
47 SCIFA4, SCIFA5, SCIFB, 49 SCIFA4, SCIFA5, SCIFB,
48 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, 50 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
49 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3, 51 SDHI0,
50 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2, SDHI1_SDHI1I3, 52 SDHI1,
51 MSU_MSU, MSU_MSU2, 53 MSU_MSU, MSU_MSU2,
52 IREM, 54 IREM,
53 SIU, 55 SIU,
@@ -59,7 +61,7 @@ enum {
59 TTI20, 61 TTI20,
60 MISTY, 62 MISTY,
61 DDM, 63 DDM,
62 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3, 64 SDHI2,
63 RWDT0, RWDT1, 65 RWDT0, RWDT1,
64 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3, 66 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
65 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR, 67 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
@@ -70,7 +72,7 @@ enum {
70 72
71 /* interrupt groups INTCA */ 73 /* interrupt groups INTCA */
72 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, 74 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2,
73 ETM11, ARM11, USBHS, FLCTL, IIC1, SDHI0, SDHI1, SDHI2, 75 ETM11, ARM11, USBHS, FLCTL, IIC1
74}; 76};
75 77
76static struct intc_vect intca_vectors[] = { 78static struct intc_vect intca_vectors[] = {
@@ -105,10 +107,10 @@ static struct intc_vect intca_vectors[] = {
105 INTC_VECT(SCIFB, 0x0d60), 107 INTC_VECT(SCIFB, 0x0d60),
106 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0), 108 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
107 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0), 109 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
108 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20), 110 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
109 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60), 111 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
110 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0), 112 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
111 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0), INTC_VECT(SDHI1_SDHI1I3, 0x0ee0), 113 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
112 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40), 114 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
113 INTC_VECT(IREM, 0x0f60), 115 INTC_VECT(IREM, 0x0f60),
114 INTC_VECT(SIU, 0x0fa0), 116 INTC_VECT(SIU, 0x0fa0),
@@ -122,8 +124,8 @@ static struct intc_vect intca_vectors[] = {
122 INTC_VECT(TTI20, 0x1100), 124 INTC_VECT(TTI20, 0x1100),
123 INTC_VECT(MISTY, 0x1120), 125 INTC_VECT(MISTY, 0x1120),
124 INTC_VECT(DDM, 0x1140), 126 INTC_VECT(DDM, 0x1140),
125 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220), 127 INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
126 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260), 128 INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
127 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0), 129 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
128 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020), 130 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
129 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060), 131 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
@@ -158,12 +160,6 @@ static struct intc_group intca_groups[] __initdata = {
158 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, 160 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
159 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I), 161 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
160 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1), 162 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
161 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
162 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
163 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
164 SDHI1_SDHI1I2, SDHI1_SDHI1I3),
165 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
166 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
167}; 163};
168 164
169static struct intc_mask_reg intca_mask_registers[] = { 165static struct intc_mask_reg intca_mask_registers[] = {
@@ -193,10 +189,10 @@ static struct intc_mask_reg intca_mask_registers[] = {
193 { SCIFB, SCIFA5, SCIFA4, MSIOF1, 189 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
194 0, 0, MSIOF2, 0 } }, 190 0, 0, MSIOF2, 0 } },
195 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */ 191 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
196 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0, 192 { DISABLED, DISABLED, ENABLED, ENABLED,
197 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } }, 193 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
198 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */ 194 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
199 { SDHI1_SDHI1I3, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0, 195 { DISABLED, DISABLED, ENABLED, ENABLED,
200 TTI20, USBDMAC_USHDMI, SPU, SIU } }, 196 TTI20, USBDMAC_USHDMI, SPU, SIU } },
201 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */ 197 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
202 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10, 198 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
@@ -211,7 +207,7 @@ static struct intc_mask_reg intca_mask_registers[] = {
211 { 0, 0, TPU0, TPU1, 207 { 0, 0, TPU0, TPU1,
212 TPU2, TPU3, TPU4, 0 } }, 208 TPU2, TPU3, TPU4, 0 } },
213 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */ 209 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
214 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0, 210 { DISABLED, DISABLED, ENABLED, ENABLED,
215 MISTY, CMT3, RWDT1, RWDT0 } }, 211 MISTY, CMT3, RWDT1, RWDT0 } },
216}; 212};
217 213
@@ -258,10 +254,14 @@ static struct intc_mask_reg intca_ack_registers[] __initdata = {
258 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } }, 254 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
259}; 255};
260 256
261static DECLARE_INTC_DESC_ACK(intca_desc, "sh7367-intca", 257static struct intc_desc intca_desc __initdata = {
262 intca_vectors, intca_groups, 258 .name = "sh7367-intca",
263 intca_mask_registers, intca_prio_registers, 259 .force_enable = ENABLED,
264 intca_sense_registers, intca_ack_registers); 260 .force_disable = DISABLED,
261 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
262 intca_mask_registers, intca_prio_registers,
263 intca_sense_registers, intca_ack_registers),
264};
265 265
266void __init sh7367_init_irq(void) 266void __init sh7367_init_irq(void)
267{ 267{