diff options
| author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-03-15 13:46:02 -0400 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-03-16 11:56:34 -0400 |
| commit | 73b34ead7429789f35eea147a3e185abd61c7d94 (patch) | |
| tree | bc70d0508b5ca6caf276d42e733e79d6838c6e1a | |
| parent | da34183e640ed380f708bf9ebcd592afda619028 (diff) | |
ASoC: Add GPIO configuration support for WM8903
Allow users to pass in a default configuration for the GPIOs of
the WM8903 as platform data. This allows configuration of the pin
muxing of the device.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
| -rw-r--r-- | include/sound/wm8903.h | 216 | ||||
| -rw-r--r-- | sound/soc/codecs/wm8903.c | 13 | ||||
| -rw-r--r-- | sound/soc/codecs/wm8903.h | 195 |
3 files changed, 228 insertions, 196 deletions
diff --git a/include/sound/wm8903.h b/include/sound/wm8903.h new file mode 100644 index 000000000000..00458589fe85 --- /dev/null +++ b/include/sound/wm8903.h | |||
| @@ -0,0 +1,216 @@ | |||
| 1 | /* | ||
| 2 | * linux/sound/wm8903.h -- Platform data for WM8903 | ||
| 3 | * | ||
| 4 | * Copyright 2010 Wolfson Microelectronics. PLC. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __LINUX_SND_WM8903_H | ||
| 12 | #define __LINUX_SND_WM8903_H | ||
| 13 | |||
| 14 | /* Used to enable configuration of a GPIO to all zeros */ | ||
| 15 | #define WM8903_GPIO_NO_CONFIG 0x8000 | ||
| 16 | |||
| 17 | /* | ||
| 18 | * R116 (0x74) - GPIO Control 1 | ||
| 19 | */ | ||
| 20 | #define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ | ||
| 21 | #define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ | ||
| 22 | #define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ | ||
| 23 | #define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ | ||
| 24 | #define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ | ||
| 25 | #define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ | ||
| 26 | #define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ | ||
| 27 | #define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ | ||
| 28 | #define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ | ||
| 29 | #define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ | ||
| 30 | #define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ | ||
| 31 | #define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ | ||
| 32 | #define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ | ||
| 33 | #define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ | ||
| 34 | #define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ | ||
| 35 | #define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ | ||
| 36 | #define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ | ||
| 37 | #define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ | ||
| 38 | #define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ | ||
| 39 | #define WM8903_GP1_PD 0x0008 /* GP1_PD */ | ||
| 40 | #define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ | ||
| 41 | #define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ | ||
| 42 | #define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ | ||
| 43 | #define WM8903_GP1_PU 0x0004 /* GP1_PU */ | ||
| 44 | #define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ | ||
| 45 | #define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ | ||
| 46 | #define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ | ||
| 47 | #define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ | ||
| 48 | #define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ | ||
| 49 | #define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ | ||
| 50 | #define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ | ||
| 51 | #define WM8903_GP1_DB 0x0001 /* GP1_DB */ | ||
| 52 | #define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ | ||
| 53 | #define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ | ||
| 54 | #define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ | ||
| 55 | |||
| 56 | /* | ||
| 57 | * R117 (0x75) - GPIO Control 2 | ||
| 58 | */ | ||
| 59 | #define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ | ||
| 60 | #define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ | ||
| 61 | #define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ | ||
| 62 | #define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ | ||
| 63 | #define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ | ||
| 64 | #define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ | ||
| 65 | #define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ | ||
| 66 | #define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ | ||
| 67 | #define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ | ||
| 68 | #define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ | ||
| 69 | #define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ | ||
| 70 | #define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ | ||
| 71 | #define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ | ||
| 72 | #define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ | ||
| 73 | #define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ | ||
| 74 | #define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ | ||
| 75 | #define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ | ||
| 76 | #define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ | ||
| 77 | #define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ | ||
| 78 | #define WM8903_GP2_PD 0x0008 /* GP2_PD */ | ||
| 79 | #define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ | ||
| 80 | #define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ | ||
| 81 | #define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ | ||
| 82 | #define WM8903_GP2_PU 0x0004 /* GP2_PU */ | ||
| 83 | #define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ | ||
| 84 | #define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ | ||
| 85 | #define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ | ||
| 86 | #define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ | ||
| 87 | #define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ | ||
| 88 | #define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ | ||
| 89 | #define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ | ||
| 90 | #define WM8903_GP2_DB 0x0001 /* GP2_DB */ | ||
| 91 | #define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ | ||
| 92 | #define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ | ||
| 93 | #define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ | ||
| 94 | |||
| 95 | /* | ||
| 96 | * R118 (0x76) - GPIO Control 3 | ||
| 97 | */ | ||
| 98 | #define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ | ||
| 99 | #define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ | ||
| 100 | #define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ | ||
| 101 | #define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ | ||
| 102 | #define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ | ||
| 103 | #define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ | ||
| 104 | #define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ | ||
| 105 | #define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ | ||
| 106 | #define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ | ||
| 107 | #define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ | ||
| 108 | #define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ | ||
| 109 | #define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ | ||
| 110 | #define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ | ||
| 111 | #define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ | ||
| 112 | #define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ | ||
| 113 | #define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ | ||
| 114 | #define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ | ||
| 115 | #define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ | ||
| 116 | #define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ | ||
| 117 | #define WM8903_GP3_PD 0x0008 /* GP3_PD */ | ||
| 118 | #define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ | ||
| 119 | #define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ | ||
| 120 | #define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ | ||
| 121 | #define WM8903_GP3_PU 0x0004 /* GP3_PU */ | ||
| 122 | #define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ | ||
| 123 | #define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ | ||
| 124 | #define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ | ||
| 125 | #define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ | ||
| 126 | #define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ | ||
| 127 | #define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ | ||
| 128 | #define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ | ||
| 129 | #define WM8903_GP3_DB 0x0001 /* GP3_DB */ | ||
| 130 | #define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ | ||
| 131 | #define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ | ||
| 132 | #define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ | ||
| 133 | |||
| 134 | /* | ||
| 135 | * R119 (0x77) - GPIO Control 4 | ||
| 136 | */ | ||
| 137 | #define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ | ||
| 138 | #define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ | ||
| 139 | #define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ | ||
| 140 | #define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ | ||
| 141 | #define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ | ||
| 142 | #define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ | ||
| 143 | #define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ | ||
| 144 | #define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ | ||
| 145 | #define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ | ||
| 146 | #define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ | ||
| 147 | #define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ | ||
| 148 | #define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ | ||
| 149 | #define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ | ||
| 150 | #define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ | ||
| 151 | #define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ | ||
| 152 | #define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ | ||
| 153 | #define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ | ||
| 154 | #define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ | ||
| 155 | #define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ | ||
| 156 | #define WM8903_GP4_PD 0x0008 /* GP4_PD */ | ||
| 157 | #define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ | ||
| 158 | #define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ | ||
| 159 | #define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ | ||
| 160 | #define WM8903_GP4_PU 0x0004 /* GP4_PU */ | ||
| 161 | #define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ | ||
| 162 | #define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ | ||
| 163 | #define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ | ||
| 164 | #define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ | ||
| 165 | #define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ | ||
| 166 | #define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ | ||
| 167 | #define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ | ||
| 168 | #define WM8903_GP4_DB 0x0001 /* GP4_DB */ | ||
| 169 | #define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ | ||
| 170 | #define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ | ||
| 171 | #define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ | ||
| 172 | |||
| 173 | /* | ||
| 174 | * R120 (0x78) - GPIO Control 5 | ||
| 175 | */ | ||
| 176 | #define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ | ||
| 177 | #define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ | ||
| 178 | #define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ | ||
| 179 | #define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ | ||
| 180 | #define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ | ||
| 181 | #define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ | ||
| 182 | #define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ | ||
| 183 | #define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ | ||
| 184 | #define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ | ||
| 185 | #define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ | ||
| 186 | #define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ | ||
| 187 | #define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ | ||
| 188 | #define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ | ||
| 189 | #define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ | ||
| 190 | #define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ | ||
| 191 | #define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ | ||
| 192 | #define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ | ||
| 193 | #define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ | ||
| 194 | #define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ | ||
| 195 | #define WM8903_GP5_PD 0x0008 /* GP5_PD */ | ||
| 196 | #define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ | ||
| 197 | #define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ | ||
| 198 | #define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ | ||
| 199 | #define WM8903_GP5_PU 0x0004 /* GP5_PU */ | ||
| 200 | #define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ | ||
| 201 | #define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ | ||
| 202 | #define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ | ||
| 203 | #define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ | ||
| 204 | #define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ | ||
| 205 | #define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ | ||
| 206 | #define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ | ||
| 207 | #define WM8903_GP5_DB 0x0001 /* GP5_DB */ | ||
| 208 | #define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ | ||
| 209 | #define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ | ||
| 210 | #define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ | ||
| 211 | |||
| 212 | struct wm8903_platform_data { | ||
| 213 | u32 gpio_cfg[5]; /* Default register values for GPIO pin mux */ | ||
| 214 | }; | ||
| 215 | |||
| 216 | #endif | ||
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c index 3595bd57c4eb..36952d77c271 100644 --- a/sound/soc/codecs/wm8903.c +++ b/sound/soc/codecs/wm8903.c | |||
| @@ -1531,7 +1531,7 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, | |||
| 1531 | { | 1531 | { |
| 1532 | struct wm8903_priv *wm8903; | 1532 | struct wm8903_priv *wm8903; |
| 1533 | struct snd_soc_codec *codec; | 1533 | struct snd_soc_codec *codec; |
| 1534 | int ret; | 1534 | int ret, i; |
| 1535 | u16 val; | 1535 | u16 val; |
| 1536 | 1536 | ||
| 1537 | wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL); | 1537 | wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL); |
| @@ -1578,6 +1578,17 @@ static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, | |||
| 1578 | 1578 | ||
| 1579 | wm8903_reset(codec); | 1579 | wm8903_reset(codec); |
| 1580 | 1580 | ||
| 1581 | /* Set up GPIOs */ | ||
| 1582 | if (pdata) { | ||
| 1583 | for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { | ||
| 1584 | if (!pdata->gpio_cfg[i]) | ||
| 1585 | continue; | ||
| 1586 | |||
| 1587 | snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i, | ||
| 1588 | pdata->gpio_cfg[i] & 0xffff); | ||
| 1589 | } | ||
| 1590 | } | ||
| 1591 | |||
| 1581 | /* power on device */ | 1592 | /* power on device */ |
| 1582 | wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | 1593 | wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
| 1583 | 1594 | ||
diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h index 0ea27e2b9963..551736cf2195 100644 --- a/sound/soc/codecs/wm8903.h +++ b/sound/soc/codecs/wm8903.h | |||
| @@ -1135,201 +1135,6 @@ extern struct snd_soc_codec_device soc_codec_dev_wm8903; | |||
| 1135 | #define WM8903_MASK_WRITE_ENA_WIDTH 1 /* MASK_WRITE_ENA */ | 1135 | #define WM8903_MASK_WRITE_ENA_WIDTH 1 /* MASK_WRITE_ENA */ |
| 1136 | 1136 | ||
| 1137 | /* | 1137 | /* |
| 1138 | * R116 (0x74) - GPIO Control 1 | ||
| 1139 | */ | ||
| 1140 | #define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ | ||
| 1141 | #define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ | ||
| 1142 | #define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ | ||
| 1143 | #define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ | ||
| 1144 | #define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ | ||
| 1145 | #define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ | ||
| 1146 | #define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ | ||
| 1147 | #define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ | ||
| 1148 | #define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ | ||
| 1149 | #define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ | ||
| 1150 | #define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ | ||
| 1151 | #define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ | ||
| 1152 | #define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ | ||
| 1153 | #define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ | ||
| 1154 | #define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ | ||
| 1155 | #define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ | ||
| 1156 | #define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ | ||
| 1157 | #define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ | ||
| 1158 | #define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ | ||
| 1159 | #define WM8903_GP1_PD 0x0008 /* GP1_PD */ | ||
| 1160 | #define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ | ||
| 1161 | #define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ | ||
| 1162 | #define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ | ||
| 1163 | #define WM8903_GP1_PU 0x0004 /* GP1_PU */ | ||
| 1164 | #define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ | ||
| 1165 | #define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ | ||
| 1166 | #define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ | ||
| 1167 | #define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ | ||
| 1168 | #define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ | ||
| 1169 | #define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ | ||
| 1170 | #define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ | ||
| 1171 | #define WM8903_GP1_DB 0x0001 /* GP1_DB */ | ||
| 1172 | #define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ | ||
| 1173 | #define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ | ||
| 1174 | #define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ | ||
| 1175 | |||
| 1176 | /* | ||
| 1177 | * R117 (0x75) - GPIO Control 2 | ||
| 1178 | */ | ||
| 1179 | #define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ | ||
| 1180 | #define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ | ||
| 1181 | #define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ | ||
| 1182 | #define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ | ||
| 1183 | #define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ | ||
| 1184 | #define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ | ||
| 1185 | #define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ | ||
| 1186 | #define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ | ||
| 1187 | #define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ | ||
| 1188 | #define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ | ||
| 1189 | #define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ | ||
| 1190 | #define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ | ||
| 1191 | #define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ | ||
| 1192 | #define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ | ||
| 1193 | #define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ | ||
| 1194 | #define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ | ||
| 1195 | #define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ | ||
| 1196 | #define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ | ||
| 1197 | #define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ | ||
| 1198 | #define WM8903_GP2_PD 0x0008 /* GP2_PD */ | ||
| 1199 | #define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ | ||
| 1200 | #define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ | ||
| 1201 | #define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ | ||
| 1202 | #define WM8903_GP2_PU 0x0004 /* GP2_PU */ | ||
| 1203 | #define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ | ||
| 1204 | #define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ | ||
| 1205 | #define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ | ||
| 1206 | #define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ | ||
| 1207 | #define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ | ||
| 1208 | #define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ | ||
| 1209 | #define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ | ||
| 1210 | #define WM8903_GP2_DB 0x0001 /* GP2_DB */ | ||
| 1211 | #define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ | ||
| 1212 | #define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ | ||
| 1213 | #define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ | ||
| 1214 | |||
| 1215 | /* | ||
| 1216 | * R118 (0x76) - GPIO Control 3 | ||
| 1217 | */ | ||
| 1218 | #define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ | ||
| 1219 | #define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ | ||
| 1220 | #define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ | ||
| 1221 | #define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ | ||
| 1222 | #define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ | ||
| 1223 | #define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ | ||
| 1224 | #define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ | ||
| 1225 | #define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ | ||
| 1226 | #define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ | ||
| 1227 | #define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ | ||
| 1228 | #define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ | ||
| 1229 | #define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ | ||
| 1230 | #define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ | ||
| 1231 | #define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ | ||
| 1232 | #define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ | ||
| 1233 | #define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ | ||
| 1234 | #define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ | ||
| 1235 | #define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ | ||
| 1236 | #define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ | ||
| 1237 | #define WM8903_GP3_PD 0x0008 /* GP3_PD */ | ||
| 1238 | #define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ | ||
| 1239 | #define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ | ||
| 1240 | #define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ | ||
| 1241 | #define WM8903_GP3_PU 0x0004 /* GP3_PU */ | ||
| 1242 | #define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ | ||
| 1243 | #define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ | ||
| 1244 | #define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ | ||
| 1245 | #define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ | ||
| 1246 | #define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ | ||
| 1247 | #define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ | ||
| 1248 | #define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ | ||
| 1249 | #define WM8903_GP3_DB 0x0001 /* GP3_DB */ | ||
| 1250 | #define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ | ||
| 1251 | #define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ | ||
| 1252 | #define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ | ||
| 1253 | |||
| 1254 | /* | ||
| 1255 | * R119 (0x77) - GPIO Control 4 | ||
| 1256 | */ | ||
| 1257 | #define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ | ||
| 1258 | #define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ | ||
| 1259 | #define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ | ||
| 1260 | #define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ | ||
| 1261 | #define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ | ||
| 1262 | #define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ | ||
| 1263 | #define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ | ||
| 1264 | #define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ | ||
| 1265 | #define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ | ||
| 1266 | #define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ | ||
| 1267 | #define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ | ||
| 1268 | #define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ | ||
| 1269 | #define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ | ||
| 1270 | #define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ | ||
| 1271 | #define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ | ||
| 1272 | #define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ | ||
| 1273 | #define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ | ||
| 1274 | #define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ | ||
| 1275 | #define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ | ||
| 1276 | #define WM8903_GP4_PD 0x0008 /* GP4_PD */ | ||
| 1277 | #define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ | ||
| 1278 | #define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ | ||
| 1279 | #define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ | ||
| 1280 | #define WM8903_GP4_PU 0x0004 /* GP4_PU */ | ||
| 1281 | #define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ | ||
| 1282 | #define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ | ||
| 1283 | #define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ | ||
| 1284 | #define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ | ||
| 1285 | #define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ | ||
| 1286 | #define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ | ||
| 1287 | #define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ | ||
| 1288 | #define WM8903_GP4_DB 0x0001 /* GP4_DB */ | ||
| 1289 | #define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ | ||
| 1290 | #define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ | ||
| 1291 | #define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ | ||
| 1292 | |||
| 1293 | /* | ||
| 1294 | * R120 (0x78) - GPIO Control 5 | ||
| 1295 | */ | ||
| 1296 | #define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ | ||
| 1297 | #define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ | ||
| 1298 | #define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ | ||
| 1299 | #define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ | ||
| 1300 | #define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ | ||
| 1301 | #define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ | ||
| 1302 | #define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ | ||
| 1303 | #define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ | ||
| 1304 | #define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ | ||
| 1305 | #define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ | ||
| 1306 | #define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ | ||
| 1307 | #define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ | ||
| 1308 | #define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ | ||
| 1309 | #define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ | ||
| 1310 | #define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ | ||
| 1311 | #define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ | ||
| 1312 | #define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ | ||
| 1313 | #define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ | ||
| 1314 | #define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ | ||
| 1315 | #define WM8903_GP5_PD 0x0008 /* GP5_PD */ | ||
| 1316 | #define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ | ||
| 1317 | #define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ | ||
| 1318 | #define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ | ||
| 1319 | #define WM8903_GP5_PU 0x0004 /* GP5_PU */ | ||
| 1320 | #define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ | ||
| 1321 | #define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ | ||
| 1322 | #define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ | ||
| 1323 | #define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ | ||
| 1324 | #define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ | ||
| 1325 | #define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ | ||
| 1326 | #define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ | ||
| 1327 | #define WM8903_GP5_DB 0x0001 /* GP5_DB */ | ||
| 1328 | #define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ | ||
| 1329 | #define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ | ||
| 1330 | #define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ | ||
| 1331 | |||
| 1332 | /* | ||
| 1333 | * R121 (0x79) - Interrupt Status 1 | 1138 | * R121 (0x79) - Interrupt Status 1 |
| 1334 | */ | 1139 | */ |
| 1335 | #define WM8903_MICSHRT_EINT 0x8000 /* MICSHRT_EINT */ | 1140 | #define WM8903_MICSHRT_EINT 0x8000 /* MICSHRT_EINT */ |