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authorLinus Walleij <linus.walleij@stericsson.com>2010-09-12 18:35:22 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2010-10-24 19:33:48 -0400
commit6c009ab89a212b4364cdb74192d438f542fb291c (patch)
tree8306b42b83b25401ddd1faa017187a0f3a94faed
parent3866f673ebd86e5be2533923f5c0aed91fe1669f (diff)
mtd: generic FSMC NAND MTD driver
This is the same driver submitted by ST Micros SPEAr team but generalized and tested on the ST-Ericsson U300. It probably easily works on the NHK8815 too. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat
-rw-r--r--drivers/mtd/nand/Kconfig7
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/fsmc_nand.c866
-rw-r--r--include/linux/mtd/fsmc.h181
4 files changed, 1055 insertions, 0 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index a6f22f5bbef6..a494cce704b9 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -524,4 +524,11 @@ config MTD_NAND_JZ4740
524 help 524 help
525 Enables support for NAND Flash on JZ4740 SoC based boards. 525 Enables support for NAND Flash on JZ4740 SoC based boards.
526 526
527config MTD_NAND_FSMC
528 tristate "Support for NAND on ST Micros FSMC"
529 depends on PLAT_SPEAR || PLAT_NOMADIK || MACH_U300
530 help
531 Enables support for NAND Flash chips on the ST Microelectronics
532 Flexible Static Memory Controller (FSMC)
533
527endif # MTD_NAND 534endif # MTD_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index ac83dcdac5d6..8ad6faec72cb 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o
19obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o 19obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o
20obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o 20obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o
21obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o 21obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o
22obj-$(CONFIG_MTD_NAND_FSMC) += fsmc_nand.o
22obj-$(CONFIG_MTD_NAND_H1900) += h1910.o 23obj-$(CONFIG_MTD_NAND_H1900) += h1910.o
23obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o 24obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o
24obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o 25obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
new file mode 100644
index 000000000000..02edfba25b0c
--- /dev/null
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -0,0 +1,866 @@
1/*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/resource.h>
24#include <linux/sched.h>
25#include <linux/types.h>
26#include <linux/mtd/mtd.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/nand_ecc.h>
29#include <linux/platform_device.h>
30#include <linux/mtd/partitions.h>
31#include <linux/io.h>
32#include <linux/slab.h>
33#include <linux/mtd/fsmc.h>
34#include <mtd/mtd-abi.h>
35
36static struct nand_ecclayout fsmc_ecc1_layout = {
37 .eccbytes = 24,
38 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
39 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
40 .oobfree = {
41 {.offset = 8, .length = 8},
42 {.offset = 24, .length = 8},
43 {.offset = 40, .length = 8},
44 {.offset = 56, .length = 8},
45 {.offset = 72, .length = 8},
46 {.offset = 88, .length = 8},
47 {.offset = 104, .length = 8},
48 {.offset = 120, .length = 8}
49 }
50};
51
52static struct nand_ecclayout fsmc_ecc4_lp_layout = {
53 .eccbytes = 104,
54 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
55 9, 10, 11, 12, 13, 14,
56 18, 19, 20, 21, 22, 23, 24,
57 25, 26, 27, 28, 29, 30,
58 34, 35, 36, 37, 38, 39, 40,
59 41, 42, 43, 44, 45, 46,
60 50, 51, 52, 53, 54, 55, 56,
61 57, 58, 59, 60, 61, 62,
62 66, 67, 68, 69, 70, 71, 72,
63 73, 74, 75, 76, 77, 78,
64 82, 83, 84, 85, 86, 87, 88,
65 89, 90, 91, 92, 93, 94,
66 98, 99, 100, 101, 102, 103, 104,
67 105, 106, 107, 108, 109, 110,
68 114, 115, 116, 117, 118, 119, 120,
69 121, 122, 123, 124, 125, 126
70 },
71 .oobfree = {
72 {.offset = 15, .length = 3},
73 {.offset = 31, .length = 3},
74 {.offset = 47, .length = 3},
75 {.offset = 63, .length = 3},
76 {.offset = 79, .length = 3},
77 {.offset = 95, .length = 3},
78 {.offset = 111, .length = 3},
79 {.offset = 127, .length = 1}
80 }
81};
82
83/*
84 * ECC placement definitions in oobfree type format.
85 * There are 13 bytes of ecc for every 512 byte block and it has to be read
86 * consecutively and immediately after the 512 byte data block for hardware to
87 * generate the error bit offsets in 512 byte data.
88 * Managing the ecc bytes in the following way makes it easier for software to
89 * read ecc bytes consecutive to data bytes. This way is similar to
90 * oobfree structure maintained already in generic nand driver
91 */
92static struct fsmc_eccplace fsmc_ecc4_lp_place = {
93 .eccplace = {
94 {.offset = 2, .length = 13},
95 {.offset = 18, .length = 13},
96 {.offset = 34, .length = 13},
97 {.offset = 50, .length = 13},
98 {.offset = 66, .length = 13},
99 {.offset = 82, .length = 13},
100 {.offset = 98, .length = 13},
101 {.offset = 114, .length = 13}
102 }
103};
104
105static struct nand_ecclayout fsmc_ecc4_sp_layout = {
106 .eccbytes = 13,
107 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
108 9, 10, 11, 12, 13, 14
109 },
110 .oobfree = {
111 {.offset = 15, .length = 1},
112 }
113};
114
115static struct fsmc_eccplace fsmc_ecc4_sp_place = {
116 .eccplace = {
117 {.offset = 0, .length = 4},
118 {.offset = 6, .length = 9}
119 }
120};
121
122/*
123 * Default partition tables to be used if the partition information not
124 * provided through platform data
125 */
126#define PARTITION(n, off, sz) {.name = n, .offset = off, .size = sz}
127
128/*
129 * Default partition layout for small page(= 512 bytes) devices
130 * Size for "Root file system" is updated in driver based on actual device size
131 */
132static struct mtd_partition partition_info_16KB_blk[] = {
133 PARTITION("X-loader", 0, 4 * 0x4000),
134 PARTITION("U-Boot", 0x10000, 20 * 0x4000),
135 PARTITION("Kernel", 0x60000, 256 * 0x4000),
136 PARTITION("Root File System", 0x460000, 0),
137};
138
139/*
140 * Default partition layout for large page(> 512 bytes) devices
141 * Size for "Root file system" is updated in driver based on actual device size
142 */
143static struct mtd_partition partition_info_128KB_blk[] = {
144 PARTITION("X-loader", 0, 4 * 0x20000),
145 PARTITION("U-Boot", 0x80000, 12 * 0x20000),
146 PARTITION("Kernel", 0x200000, 48 * 0x20000),
147 PARTITION("Root File System", 0x800000, 0),
148};
149
150#ifdef CONFIG_MTD_CMDLINE_PARTS
151const char *part_probes[] = { "cmdlinepart", NULL };
152#endif
153
154/**
155 * struct fsmc_nand_data - atructure for FSMC NAND device state
156 *
157 * @mtd: MTD info for a NAND flash.
158 * @nand: Chip related info for a NAND flash.
159 * @partitions: Partition info for a NAND Flash.
160 * @nr_partitions: Total number of partition of a NAND flash.
161 *
162 * @ecc_place: ECC placing locations in oobfree type format.
163 * @bank: Bank number for probed device.
164 * @clk: Clock structure for FSMC.
165 *
166 * @data_va: NAND port for Data.
167 * @cmd_va: NAND port for Command.
168 * @addr_va: NAND port for Address.
169 * @regs_va: FSMC regs base address.
170 */
171struct fsmc_nand_data {
172 struct mtd_info mtd;
173 struct nand_chip nand;
174 struct mtd_partition *partitions;
175 unsigned int nr_partitions;
176
177 struct fsmc_eccplace *ecc_place;
178 unsigned int bank;
179 struct clk *clk;
180
181 struct resource *resregs;
182 struct resource *rescmd;
183 struct resource *resaddr;
184 struct resource *resdata;
185
186 void __iomem *data_va;
187 void __iomem *cmd_va;
188 void __iomem *addr_va;
189 void __iomem *regs_va;
190
191 void (*select_chip)(uint32_t bank, uint32_t busw);
192};
193
194/* Assert CS signal based on chipnr */
195static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
196{
197 struct nand_chip *chip = mtd->priv;
198 struct fsmc_nand_data *host;
199
200 host = container_of(mtd, struct fsmc_nand_data, mtd);
201
202 switch (chipnr) {
203 case -1:
204 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
205 break;
206 case 0:
207 case 1:
208 case 2:
209 case 3:
210 if (host->select_chip)
211 host->select_chip(chipnr,
212 chip->options & NAND_BUSWIDTH_16);
213 break;
214
215 default:
216 BUG();
217 }
218}
219
220/*
221 * fsmc_cmd_ctrl - For facilitaing Hardware access
222 * This routine allows hardware specific access to control-lines(ALE,CLE)
223 */
224static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
225{
226 struct nand_chip *this = mtd->priv;
227 struct fsmc_nand_data *host = container_of(mtd,
228 struct fsmc_nand_data, mtd);
229 struct fsmc_regs *regs = host->regs_va;
230 unsigned int bank = host->bank;
231
232 if (ctrl & NAND_CTRL_CHANGE) {
233 if (ctrl & NAND_CLE) {
234 this->IO_ADDR_R = (void __iomem *)host->cmd_va;
235 this->IO_ADDR_W = (void __iomem *)host->cmd_va;
236 } else if (ctrl & NAND_ALE) {
237 this->IO_ADDR_R = (void __iomem *)host->addr_va;
238 this->IO_ADDR_W = (void __iomem *)host->addr_va;
239 } else {
240 this->IO_ADDR_R = (void __iomem *)host->data_va;
241 this->IO_ADDR_W = (void __iomem *)host->data_va;
242 }
243
244 if (ctrl & NAND_NCE) {
245 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ENABLE,
246 &regs->bank_regs[bank].pc);
247 } else {
248 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ENABLE,
249 &regs->bank_regs[bank].pc);
250 }
251 }
252
253 mb();
254
255 if (cmd != NAND_CMD_NONE)
256 writeb(cmd, this->IO_ADDR_W);
257}
258
259/*
260 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
261 *
262 * This routine initializes timing parameters related to NAND memory access in
263 * FSMC registers
264 */
265static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
266 uint32_t busw)
267{
268 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
269
270 if (busw)
271 writel(value | FSMC_DEVWID_16, &regs->bank_regs[bank].pc);
272 else
273 writel(value | FSMC_DEVWID_8, &regs->bank_regs[bank].pc);
274
275 writel(readl(&regs->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1,
276 &regs->bank_regs[bank].pc);
277 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
278 &regs->bank_regs[bank].comm);
279 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
280 &regs->bank_regs[bank].attrib);
281}
282
283/*
284 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
285 */
286static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
287{
288 struct fsmc_nand_data *host = container_of(mtd,
289 struct fsmc_nand_data, mtd);
290 struct fsmc_regs *regs = host->regs_va;
291 uint32_t bank = host->bank;
292
293 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
294 &regs->bank_regs[bank].pc);
295 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCEN,
296 &regs->bank_regs[bank].pc);
297 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ECCEN,
298 &regs->bank_regs[bank].pc);
299}
300
301/*
302 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
303 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction upto
304 * max of 8-bits)
305 */
306static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
307 uint8_t *ecc)
308{
309 struct fsmc_nand_data *host = container_of(mtd,
310 struct fsmc_nand_data, mtd);
311 struct fsmc_regs *regs = host->regs_va;
312 uint32_t bank = host->bank;
313 uint32_t ecc_tmp;
314 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
315
316 do {
317 if (readl(&regs->bank_regs[bank].sts) & FSMC_CODE_RDY)
318 break;
319 else
320 cond_resched();
321 } while (!time_after_eq(jiffies, deadline));
322
323 ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
324 ecc[0] = (uint8_t) (ecc_tmp >> 0);
325 ecc[1] = (uint8_t) (ecc_tmp >> 8);
326 ecc[2] = (uint8_t) (ecc_tmp >> 16);
327 ecc[3] = (uint8_t) (ecc_tmp >> 24);
328
329 ecc_tmp = readl(&regs->bank_regs[bank].ecc2);
330 ecc[4] = (uint8_t) (ecc_tmp >> 0);
331 ecc[5] = (uint8_t) (ecc_tmp >> 8);
332 ecc[6] = (uint8_t) (ecc_tmp >> 16);
333 ecc[7] = (uint8_t) (ecc_tmp >> 24);
334
335 ecc_tmp = readl(&regs->bank_regs[bank].ecc3);
336 ecc[8] = (uint8_t) (ecc_tmp >> 0);
337 ecc[9] = (uint8_t) (ecc_tmp >> 8);
338 ecc[10] = (uint8_t) (ecc_tmp >> 16);
339 ecc[11] = (uint8_t) (ecc_tmp >> 24);
340
341 ecc_tmp = readl(&regs->bank_regs[bank].sts);
342 ecc[12] = (uint8_t) (ecc_tmp >> 16);
343
344 return 0;
345}
346
347/*
348 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
349 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction upto
350 * max of 1-bit)
351 */
352static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
353 uint8_t *ecc)
354{
355 struct fsmc_nand_data *host = container_of(mtd,
356 struct fsmc_nand_data, mtd);
357 struct fsmc_regs *regs = host->regs_va;
358 uint32_t bank = host->bank;
359 uint32_t ecc_tmp;
360
361 ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
362 ecc[0] = (uint8_t) (ecc_tmp >> 0);
363 ecc[1] = (uint8_t) (ecc_tmp >> 8);
364 ecc[2] = (uint8_t) (ecc_tmp >> 16);
365
366 return 0;
367}
368
369/*
370 * fsmc_read_page_hwecc
371 * @mtd: mtd info structure
372 * @chip: nand chip info structure
373 * @buf: buffer to store read data
374 * @page: page number to read
375 *
376 * This routine is needed for fsmc verison 8 as reading from NAND chip has to be
377 * performed in a strict sequence as follows:
378 * data(512 byte) -> ecc(13 byte)
379 * After this read, fsmc hardware generates and reports error data bits(upto a
380 * max of 8 bits)
381 */
382static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
383 uint8_t *buf, int page)
384{
385 struct fsmc_nand_data *host = container_of(mtd,
386 struct fsmc_nand_data, mtd);
387 struct fsmc_eccplace *ecc_place = host->ecc_place;
388 int i, j, s, stat, eccsize = chip->ecc.size;
389 int eccbytes = chip->ecc.bytes;
390 int eccsteps = chip->ecc.steps;
391 uint8_t *p = buf;
392 uint8_t *ecc_calc = chip->buffers->ecccalc;
393 uint8_t *ecc_code = chip->buffers->ecccode;
394 int off, len, group = 0;
395 /*
396 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
397 * end up reading 14 bytes (7 words) from oob. The local array is
398 * to maintain word alignment
399 */
400 uint16_t ecc_oob[7];
401 uint8_t *oob = (uint8_t *)&ecc_oob[0];
402
403 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
404
405 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
406 chip->ecc.hwctl(mtd, NAND_ECC_READ);
407 chip->read_buf(mtd, p, eccsize);
408
409 for (j = 0; j < eccbytes;) {
410 off = ecc_place->eccplace[group].offset;
411 len = ecc_place->eccplace[group].length;
412 group++;
413
414 /*
415 * length is intentionally kept a higher multiple of 2
416 * to read at least 13 bytes even in case of 16 bit NAND
417 * devices
418 */
419 len = roundup(len, 2);
420 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
421 chip->read_buf(mtd, oob + j, len);
422 j += len;
423 }
424
425 memcpy(&ecc_code[i], oob, 13);
426 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
427
428 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
429 if (stat < 0)
430 mtd->ecc_stats.failed++;
431 else
432 mtd->ecc_stats.corrected += stat;
433 }
434
435 return 0;
436}
437
438/*
439 * fsmc_correct_data
440 * @mtd: mtd info structure
441 * @dat: buffer of read data
442 * @read_ecc: ecc read from device spare area
443 * @calc_ecc: ecc calculated from read data
444 *
445 * calc_ecc is a 104 bit information containing maximum of 8 error
446 * offset informations of 13 bits each in 512 bytes of read data.
447 */
448static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
449 uint8_t *read_ecc, uint8_t *calc_ecc)
450{
451 struct fsmc_nand_data *host = container_of(mtd,
452 struct fsmc_nand_data, mtd);
453 struct fsmc_regs *regs = host->regs_va;
454 unsigned int bank = host->bank;
455 uint16_t err_idx[8];
456 uint64_t ecc_data[2];
457 uint32_t num_err, i;
458
459 /* The calculated ecc is actually the correction index in data */
460 memcpy(ecc_data, calc_ecc, 13);
461
462 /*
463 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
464 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
465 *
466 * calc_ecc is a 104 bit information containing maximum of 8 error
467 * offset informations of 13 bits each. calc_ecc is copied into a
468 * uint64_t array and error offset indexes are populated in err_idx
469 * array
470 */
471 for (i = 0; i < 8; i++) {
472 if (i == 4) {
473 err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0];
474 ecc_data[1] >>= 1;
475 continue;
476 }
477 err_idx[i] = (ecc_data[i/4] & 0x1FFF);
478 ecc_data[i/4] >>= 13;
479 }
480
481 num_err = (readl(&regs->bank_regs[bank].sts) >> 10) & 0xF;
482
483 if (num_err == 0xF)
484 return -EBADMSG;
485
486 i = 0;
487 while (num_err--) {
488 change_bit(0, (unsigned long *)&err_idx[i]);
489 change_bit(1, (unsigned long *)&err_idx[i]);
490
491 if (err_idx[i] <= 512 * 8) {
492 change_bit(err_idx[i], (unsigned long *)dat);
493 i++;
494 }
495 }
496 return i;
497}
498
499/*
500 * fsmc_nand_probe - Probe function
501 * @pdev: platform device structure
502 */
503static int __init fsmc_nand_probe(struct platform_device *pdev)
504{
505 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
506 struct fsmc_nand_data *host;
507 struct mtd_info *mtd;
508 struct nand_chip *nand;
509 struct fsmc_regs *regs;
510 struct resource *res;
511 int nr_parts, ret = 0;
512
513 if (!pdata) {
514 dev_err(&pdev->dev, "platform data is NULL\n");
515 return -EINVAL;
516 }
517
518 /* Allocate memory for the device structure (and zero it) */
519 host = kzalloc(sizeof(*host), GFP_KERNEL);
520 if (!host) {
521 dev_err(&pdev->dev, "failed to allocate device structure\n");
522 return -ENOMEM;
523 }
524
525 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
526 if (!res) {
527 ret = -EIO;
528 goto err_probe1;
529 }
530
531 host->resdata = request_mem_region(res->start, resource_size(res),
532 pdev->name);
533 if (!host->resdata) {
534 ret = -EIO;
535 goto err_probe1;
536 }
537
538 host->data_va = ioremap(res->start, resource_size(res));
539 if (!host->data_va) {
540 ret = -EIO;
541 goto err_probe1;
542 }
543
544 host->resaddr = request_mem_region(res->start + PLAT_NAND_ALE,
545 resource_size(res), pdev->name);
546 if (!host->resaddr) {
547 ret = -EIO;
548 goto err_probe1;
549 }
550
551 host->addr_va = ioremap(res->start + PLAT_NAND_ALE, resource_size(res));
552 if (!host->addr_va) {
553 ret = -EIO;
554 goto err_probe1;
555 }
556
557 host->rescmd = request_mem_region(res->start + PLAT_NAND_CLE,
558 resource_size(res), pdev->name);
559 if (!host->rescmd) {
560 ret = -EIO;
561 goto err_probe1;
562 }
563
564 host->cmd_va = ioremap(res->start + PLAT_NAND_CLE, resource_size(res));
565 if (!host->cmd_va) {
566 ret = -EIO;
567 goto err_probe1;
568 }
569
570 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
571 if (!res) {
572 ret = -EIO;
573 goto err_probe1;
574 }
575
576 host->resregs = request_mem_region(res->start, resource_size(res),
577 pdev->name);
578 if (!host->resregs) {
579 ret = -EIO;
580 goto err_probe1;
581 }
582
583 host->regs_va = ioremap(res->start, resource_size(res));
584 if (!host->regs_va) {
585 ret = -EIO;
586 goto err_probe1;
587 }
588
589 host->clk = clk_get(&pdev->dev, NULL);
590 if (IS_ERR(host->clk)) {
591 dev_err(&pdev->dev, "failed to fetch block clock\n");
592 ret = PTR_ERR(host->clk);
593 host->clk = NULL;
594 goto err_probe1;
595 }
596
597 ret = clk_enable(host->clk);
598 if (ret)
599 goto err_probe1;
600
601 host->bank = pdata->bank;
602 host->select_chip = pdata->select_bank;
603 regs = host->regs_va;
604
605 /* Link all private pointers */
606 mtd = &host->mtd;
607 nand = &host->nand;
608 mtd->priv = nand;
609 nand->priv = host;
610
611 host->mtd.owner = THIS_MODULE;
612 nand->IO_ADDR_R = host->data_va;
613 nand->IO_ADDR_W = host->data_va;
614 nand->cmd_ctrl = fsmc_cmd_ctrl;
615 nand->chip_delay = 30;
616
617 nand->ecc.mode = NAND_ECC_HW;
618 nand->ecc.hwctl = fsmc_enable_hwecc;
619 nand->ecc.size = 512;
620 nand->options = pdata->options;
621 nand->select_chip = fsmc_select_chip;
622
623 if (pdata->width == FSMC_NAND_BW16)
624 nand->options |= NAND_BUSWIDTH_16;
625
626 fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16);
627
628 if (get_fsmc_version(host->regs_va) == FSMC_VER8) {
629 nand->ecc.read_page = fsmc_read_page_hwecc;
630 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
631 nand->ecc.correct = fsmc_correct_data;
632 nand->ecc.bytes = 13;
633 } else {
634 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
635 nand->ecc.correct = nand_correct_data;
636 nand->ecc.bytes = 3;
637 }
638
639 /*
640 * Scan to find existance of the device
641 */
642 if (nand_scan_ident(&host->mtd, 1, NULL)) {
643 ret = -ENXIO;
644 dev_err(&pdev->dev, "No NAND Device found!\n");
645 goto err_probe;
646 }
647
648 if (get_fsmc_version(host->regs_va) == FSMC_VER8) {
649 if (host->mtd.writesize == 512) {
650 nand->ecc.layout = &fsmc_ecc4_sp_layout;
651 host->ecc_place = &fsmc_ecc4_sp_place;
652 } else {
653 nand->ecc.layout = &fsmc_ecc4_lp_layout;
654 host->ecc_place = &fsmc_ecc4_lp_place;
655 }
656 } else {
657 nand->ecc.layout = &fsmc_ecc1_layout;
658 }
659
660 /* Second stage of scan to fill MTD data-structures */
661 if (nand_scan_tail(&host->mtd)) {
662 ret = -ENXIO;
663 goto err_probe;
664 }
665
666 /*
667 * The partition information can is accessed by (in the same precedence)
668 *
669 * command line through Bootloader,
670 * platform data,
671 * default partition information present in driver.
672 */
673#ifdef CONFIG_MTD_PARTITIONS
674#ifdef CONFIG_MTD_CMDLINE_PARTS
675 /*
676 * Check if partition info passed via command line
677 */
678 host->mtd.name = "nand";
679 nr_parts = parse_mtd_partitions(&host->mtd, part_probes,
680 &host->partitions, 0);
681 if (nr_parts > 0) {
682 host->nr_partitions = nr_parts;
683 } else {
684#endif
685 /*
686 * Check if partition info passed via command line
687 */
688 if (pdata->partitions) {
689 host->partitions = pdata->partitions;
690 host->nr_partitions = pdata->nr_partitions;
691 } else {
692 struct mtd_partition *partition;
693 int i;
694
695 /* Select the default partitions info */
696 switch (host->mtd.size) {
697 case 0x01000000:
698 case 0x02000000:
699 case 0x04000000:
700 host->partitions = partition_info_16KB_blk;
701 host->nr_partitions =
702 sizeof(partition_info_16KB_blk) /
703 sizeof(struct mtd_partition);
704 break;
705 case 0x08000000:
706 case 0x10000000:
707 case 0x20000000:
708 case 0x40000000:
709 host->partitions = partition_info_128KB_blk;
710 host->nr_partitions =
711 sizeof(partition_info_128KB_blk) /
712 sizeof(struct mtd_partition);
713 break;
714 default:
715 ret = -ENXIO;
716 pr_err("Unsupported NAND size\n");
717 goto err_probe;
718 }
719
720 partition = host->partitions;
721 for (i = 0; i < host->nr_partitions; i++, partition++) {
722 if (partition->size == 0) {
723 partition->size = host->mtd.size -
724 partition->offset;
725 break;
726 }
727 }
728 }
729#ifdef CONFIG_MTD_CMDLINE_PARTS
730 }
731#endif
732
733 if (host->partitions) {
734 ret = add_mtd_partitions(&host->mtd, host->partitions,
735 host->nr_partitions);
736 if (ret)
737 goto err_probe;
738 }
739#else
740 dev_info(&pdev->dev, "Registering %s as whole device\n", mtd->name);
741 if (!add_mtd_device(mtd)) {
742 ret = -ENXIO;
743 goto err_probe;
744 }
745#endif
746
747 platform_set_drvdata(pdev, host);
748 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
749 return 0;
750
751err_probe:
752 clk_disable(host->clk);
753err_probe1:
754 if (host->clk)
755 clk_put(host->clk);
756 if (host->regs_va)
757 iounmap(host->regs_va);
758 if (host->resregs)
759 release_mem_region(host->resregs->start,
760 resource_size(host->resregs));
761 if (host->cmd_va)
762 iounmap(host->cmd_va);
763 if (host->rescmd)
764 release_mem_region(host->rescmd->start,
765 resource_size(host->rescmd));
766 if (host->addr_va)
767 iounmap(host->addr_va);
768 if (host->resaddr)
769 release_mem_region(host->resaddr->start,
770 resource_size(host->resaddr));
771 if (host->data_va)
772 iounmap(host->data_va);
773 if (host->resdata)
774 release_mem_region(host->resdata->start,
775 resource_size(host->resdata));
776
777 kfree(host);
778 return ret;
779}
780
781/*
782 * Clean up routine
783 */
784static int fsmc_nand_remove(struct platform_device *pdev)
785{
786 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
787
788 platform_set_drvdata(pdev, NULL);
789
790 if (host) {
791#ifdef CONFIG_MTD_PARTITIONS
792 del_mtd_partitions(&host->mtd);
793#else
794 del_mtd_device(&host->mtd);
795#endif
796 clk_disable(host->clk);
797 clk_put(host->clk);
798
799 iounmap(host->regs_va);
800 release_mem_region(host->resregs->start,
801 resource_size(host->resregs));
802 iounmap(host->cmd_va);
803 release_mem_region(host->rescmd->start,
804 resource_size(host->rescmd));
805 iounmap(host->addr_va);
806 release_mem_region(host->resaddr->start,
807 resource_size(host->resaddr));
808 iounmap(host->data_va);
809 release_mem_region(host->resdata->start,
810 resource_size(host->resdata));
811
812 kfree(host);
813 }
814 return 0;
815}
816
817#ifdef CONFIG_PM
818static int fsmc_nand_suspend(struct device *dev)
819{
820 struct fsmc_nand_data *host = dev_get_drvdata(dev);
821 if (host)
822 clk_disable(host->clk);
823 return 0;
824}
825
826static int fsmc_nand_resume(struct device *dev)
827{
828 struct fsmc_nand_data *host = dev_get_drvdata(dev);
829 if (host)
830 clk_enable(host->clk);
831 return 0;
832}
833
834static const struct dev_pm_ops fsmc_nand_pm_ops = {
835 .suspend = fsmc_nand_suspend,
836 .resume = fsmc_nand_resume,
837};
838#endif
839
840static struct platform_driver fsmc_nand_driver = {
841 .remove = fsmc_nand_remove,
842 .driver = {
843 .owner = THIS_MODULE,
844 .name = "fsmc-nand",
845#ifdef CONFIG_PM
846 .pm = &fsmc_nand_pm_ops,
847#endif
848 },
849};
850
851static int __init fsmc_nand_init(void)
852{
853 return platform_driver_probe(&fsmc_nand_driver,
854 fsmc_nand_probe);
855}
856module_init(fsmc_nand_init);
857
858static void __exit fsmc_nand_exit(void)
859{
860 platform_driver_unregister(&fsmc_nand_driver);
861}
862module_exit(fsmc_nand_exit);
863
864MODULE_LICENSE("GPL");
865MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
866MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h
new file mode 100644
index 000000000000..5d2556700ec2
--- /dev/null
+++ b/include/linux/mtd/fsmc.h
@@ -0,0 +1,181 @@
1/*
2 * incude/mtd/fsmc.h
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * platform data interface and header file
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#ifndef __MTD_FSMC_H
17#define __MTD_FSMC_H
18
19#include <linux/platform_device.h>
20#include <linux/mtd/physmap.h>
21#include <linux/types.h>
22#include <linux/mtd/partitions.h>
23#include <asm/param.h>
24
25#define FSMC_NAND_BW8 1
26#define FSMC_NAND_BW16 2
27
28/*
29 * The placement of the Command Latch Enable (CLE) and
30 * Address Latch Enable (ALE) is twised around in the
31 * SPEAR310 implementation.
32 */
33#if defined(CONFIG_MACH_SPEAR310)
34#define PLAT_NAND_CLE (1 << 17)
35#define PLAT_NAND_ALE (1 << 16)
36#else
37#define PLAT_NAND_CLE (1 << 16)
38#define PLAT_NAND_ALE (1 << 17)
39#endif
40
41#define FSMC_MAX_NOR_BANKS 4
42#define FSMC_MAX_NAND_BANKS 4
43
44#define FSMC_FLASH_WIDTH8 1
45#define FSMC_FLASH_WIDTH16 2
46
47struct fsmc_nor_bank_regs {
48 uint32_t ctrl;
49 uint32_t ctrl_tim;
50};
51
52/* ctrl register definitions */
53#define BANK_ENABLE (1 << 0)
54#define MUXED (1 << 1)
55#define NOR_DEV (2 << 2)
56#define WIDTH_8 (0 << 4)
57#define WIDTH_16 (1 << 4)
58#define RSTPWRDWN (1 << 6)
59#define WPROT (1 << 7)
60#define WRT_ENABLE (1 << 12)
61#define WAIT_ENB (1 << 13)
62
63/* ctrl_tim register definitions */
64
65struct fsms_nand_bank_regs {
66 uint32_t pc;
67 uint32_t sts;
68 uint32_t comm;
69 uint32_t attrib;
70 uint32_t ioata;
71 uint32_t ecc1;
72 uint32_t ecc2;
73 uint32_t ecc3;
74};
75
76#define FSMC_NOR_REG_SIZE 0x40
77
78struct fsmc_regs {
79 struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
80 uint8_t reserved_1[0x40 - 0x20];
81 struct fsms_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
82 uint8_t reserved_2[0xfe0 - 0xc0];
83 uint32_t peripid0; /* 0xfe0 */
84 uint32_t peripid1; /* 0xfe4 */
85 uint32_t peripid2; /* 0xfe8 */
86 uint32_t peripid3; /* 0xfec */
87 uint32_t pcellid0; /* 0xff0 */
88 uint32_t pcellid1; /* 0xff4 */
89 uint32_t pcellid2; /* 0xff8 */
90 uint32_t pcellid3; /* 0xffc */
91};
92
93#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
94
95/* pc register definitions */
96#define FSMC_RESET (1 << 0)
97#define FSMC_WAITON (1 << 1)
98#define FSMC_ENABLE (1 << 2)
99#define FSMC_DEVTYPE_NAND (1 << 3)
100#define FSMC_DEVWID_8 (0 << 4)
101#define FSMC_DEVWID_16 (1 << 4)
102#define FSMC_ECCEN (1 << 6)
103#define FSMC_ECCPLEN_512 (0 << 7)
104#define FSMC_ECCPLEN_256 (1 << 7)
105#define FSMC_TCLR_1 (1 << 9)
106#define FSMC_TAR_1 (1 << 13)
107
108/* sts register definitions */
109#define FSMC_CODE_RDY (1 << 15)
110
111/* comm register definitions */
112#define FSMC_TSET_0 (0 << 0)
113#define FSMC_TWAIT_6 (6 << 8)
114#define FSMC_THOLD_4 (4 << 16)
115#define FSMC_THIZ_1 (1 << 24)
116
117/* peripid2 register definitions */
118#define FSMC_REVISION_MSK (0xf)
119#define FSMC_REVISION_SHFT (0x4)
120
121#define FSMC_VER1 1
122#define FSMC_VER2 2
123#define FSMC_VER3 3
124#define FSMC_VER4 4
125#define FSMC_VER5 5
126#define FSMC_VER6 6
127#define FSMC_VER7 7
128#define FSMC_VER8 8
129
130static inline uint32_t get_fsmc_version(struct fsmc_regs *regs)
131{
132 return (readl(&regs->peripid2) >> FSMC_REVISION_SHFT) &
133 FSMC_REVISION_MSK;
134}
135
136/*
137 * There are 13 bytes of ecc for every 512 byte block in FSMC version 8
138 * and it has to be read consecutively and immediately after the 512
139 * byte data block for hardware to generate the error bit offsets
140 * Managing the ecc bytes in the following way is easier. This way is
141 * similar to oobfree structure maintained already in u-boot nand driver
142 */
143#define MAX_ECCPLACE_ENTRIES 32
144
145struct fsmc_nand_eccplace {
146 uint8_t offset;
147 uint8_t length;
148};
149
150struct fsmc_eccplace {
151 struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES];
152};
153
154/**
155 * fsmc_nand_platform_data - platform specific NAND controller config
156 * @partitions: partition table for the platform, use a default fallback
157 * if this is NULL
158 * @nr_partitions: the number of partitions in the previous entry
159 * @options: different options for the driver
160 * @width: bus width
161 * @bank: default bank
162 * @select_bank: callback to select a certain bank, this is
163 * platform-specific. If the controller only supports one bank
164 * this may be set to NULL
165 */
166struct fsmc_nand_platform_data {
167 struct mtd_partition *partitions;
168 unsigned int nr_partitions;
169 unsigned int options;
170 unsigned int width;
171 unsigned int bank;
172 void (*select_bank)(uint32_t bank, uint32_t busw);
173};
174
175extern int __init fsmc_nor_init(struct platform_device *pdev,
176 unsigned long base, uint32_t bank, uint32_t width);
177extern void __init fsmc_init_board_info(struct platform_device *pdev,
178 struct mtd_partition *partitions, unsigned int nr_partitions,
179 unsigned int width);
180
181#endif /* __MTD_FSMC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 15:49:04 -0500