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authorKishon Vijay Abraham I <kishon@ti.com>2011-02-24 04:46:52 -0500
committerTony Lindgren <tony@atomide.com>2011-02-24 16:02:53 -0500
commit64bcbd33c7c70d0aea4e614212a2568321a0396b (patch)
tree15cbd3720e7cffdf180c4bed78f78759204b0493
parent8b1906f12a60d377b11d8a3dd256ce0a0ef6c614 (diff)
OMAP2+: McBSP: hwmod adaptation for McBSP
Modify OMAP2+ McBSP to use omap hwmod framework APIs Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Jarkko Nikula <jhnikula@gmail.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/mcbsp.c595
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h2
2 files changed, 46 insertions, 551 deletions
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 765ebe7da723..275d6cfa0b24 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -22,10 +22,10 @@
22#include <plat/dma.h> 22#include <plat/dma.h>
23#include <plat/cpu.h> 23#include <plat/cpu.h>
24#include <plat/mcbsp.h> 24#include <plat/mcbsp.h>
25#include <plat/omap_device.h>
25 26
26#include "control.h" 27#include "control.h"
27 28
28
29/* McBSP internal signal muxing functions */ 29/* McBSP internal signal muxing functions */
30 30
31void omap2_mcbsp1_mux_clkr_src(u8 mux) 31void omap2_mcbsp1_mux_clkr_src(u8 mux)
@@ -101,573 +101,68 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
101} 101}
102EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); 102EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
103 103
104 104struct omap_device_pm_latency omap2_mcbsp_latency[] = {
105/* Platform data */
106
107#ifdef CONFIG_SOC_OMAP2420
108struct resource omap2420_mcbsp_res[][6] = {
109 { 105 {
110 { 106 .deactivate_func = omap_device_idle_hwmods,
111 .start = OMAP24XX_MCBSP1_BASE, 107 .activate_func = omap_device_enable_hwmods,
112 .end = OMAP24XX_MCBSP1_BASE + SZ_256, 108 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
113 .flags = IORESOURCE_MEM,
114 },
115 {
116 .name = "rx",
117 .start = INT_24XX_MCBSP1_IRQ_RX,
118 .flags = IORESOURCE_IRQ,
119 },
120 {
121 .name = "tx",
122 .start = INT_24XX_MCBSP1_IRQ_TX,
123 .flags = IORESOURCE_IRQ,
124 },
125 {
126 .name = "rx",
127 .start = OMAP24XX_DMA_MCBSP1_RX,
128 .flags = IORESOURCE_DMA,
129 },
130 {
131 .name = "tx",
132 .start = OMAP24XX_DMA_MCBSP1_TX,
133 .flags = IORESOURCE_DMA,
134 },
135 },
136 {
137 {
138 .start = OMAP24XX_MCBSP2_BASE,
139 .end = OMAP24XX_MCBSP2_BASE + SZ_256,
140 .flags = IORESOURCE_MEM,
141 },
142 {
143 .name = "rx",
144 .start = INT_24XX_MCBSP2_IRQ_RX,
145 .flags = IORESOURCE_IRQ,
146 },
147 {
148 .name = "tx",
149 .start = INT_24XX_MCBSP2_IRQ_TX,
150 .flags = IORESOURCE_IRQ,
151 },
152 {
153 .name = "rx",
154 .start = OMAP24XX_DMA_MCBSP2_RX,
155 .flags = IORESOURCE_DMA,
156 },
157 {
158 .name = "tx",
159 .start = OMAP24XX_DMA_MCBSP2_TX,
160 .flags = IORESOURCE_DMA,
161 },
162 }, 109 },
163}; 110};
164#define OMAP2420_MCBSP_RES_SZ ARRAY_SIZE(omap2420_mcbsp_res[1])
165#define OMAP2420_MCBSP_COUNT ARRAY_SIZE(omap2420_mcbsp_res)
166#else
167#define omap2420_mcbsp_res NULL
168#define OMAP2420_MCBSP_RES_SZ 0
169#define OMAP2420_MCBSP_COUNT 0
170#endif
171 111
172#define omap2420_mcbsp_pdata NULL 112static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
113{
114 int id, count = 1;
115 char *name = "omap-mcbsp";
116 struct omap_hwmod *oh_device[2];
117 struct omap_mcbsp_platform_data *pdata = NULL;
118 struct omap_device *od;
173 119
174#ifdef CONFIG_SOC_OMAP2430 120 sscanf(oh->name, "mcbsp%d", &id);
175struct resource omap2430_mcbsp_res[][6] = {
176 {
177 {
178 .start = OMAP24XX_MCBSP1_BASE,
179 .end = OMAP24XX_MCBSP1_BASE + SZ_256,
180 .flags = IORESOURCE_MEM,
181 },
182 {
183 .name = "rx",
184 .start = INT_24XX_MCBSP1_IRQ_RX,
185 .flags = IORESOURCE_IRQ,
186 },
187 {
188 .name = "tx",
189 .start = INT_24XX_MCBSP1_IRQ_TX,
190 .flags = IORESOURCE_IRQ,
191 },
192 {
193 .name = "rx",
194 .start = OMAP24XX_DMA_MCBSP1_RX,
195 .flags = IORESOURCE_DMA,
196 },
197 {
198 .name = "tx",
199 .start = OMAP24XX_DMA_MCBSP1_TX,
200 .flags = IORESOURCE_DMA,
201 },
202 },
203 {
204 {
205 .start = OMAP24XX_MCBSP2_BASE,
206 .end = OMAP24XX_MCBSP2_BASE + SZ_256,
207 .flags = IORESOURCE_MEM,
208 },
209 {
210 .name = "rx",
211 .start = INT_24XX_MCBSP2_IRQ_RX,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .name = "tx",
216 .start = INT_24XX_MCBSP2_IRQ_TX,
217 .flags = IORESOURCE_IRQ,
218 },
219 {
220 .name = "rx",
221 .start = OMAP24XX_DMA_MCBSP2_RX,
222 .flags = IORESOURCE_DMA,
223 },
224 {
225 .name = "tx",
226 .start = OMAP24XX_DMA_MCBSP2_TX,
227 .flags = IORESOURCE_DMA,
228 },
229 },
230 {
231 {
232 .start = OMAP2430_MCBSP3_BASE,
233 .end = OMAP2430_MCBSP3_BASE + SZ_256,
234 .flags = IORESOURCE_MEM,
235 },
236 {
237 .name = "rx",
238 .start = INT_24XX_MCBSP3_IRQ_RX,
239 .flags = IORESOURCE_IRQ,
240 },
241 {
242 .name = "tx",
243 .start = INT_24XX_MCBSP3_IRQ_TX,
244 .flags = IORESOURCE_IRQ,
245 },
246 {
247 .name = "rx",
248 .start = OMAP24XX_DMA_MCBSP3_RX,
249 .flags = IORESOURCE_DMA,
250 },
251 {
252 .name = "tx",
253 .start = OMAP24XX_DMA_MCBSP3_TX,
254 .flags = IORESOURCE_DMA,
255 },
256 },
257 {
258 {
259 .start = OMAP2430_MCBSP4_BASE,
260 .end = OMAP2430_MCBSP4_BASE + SZ_256,
261 .flags = IORESOURCE_MEM,
262 },
263 {
264 .name = "rx",
265 .start = INT_24XX_MCBSP4_IRQ_RX,
266 .flags = IORESOURCE_IRQ,
267 },
268 {
269 .name = "tx",
270 .start = INT_24XX_MCBSP4_IRQ_TX,
271 .flags = IORESOURCE_IRQ,
272 },
273 {
274 .name = "rx",
275 .start = OMAP24XX_DMA_MCBSP4_RX,
276 .flags = IORESOURCE_DMA,
277 },
278 {
279 .name = "tx",
280 .start = OMAP24XX_DMA_MCBSP4_TX,
281 .flags = IORESOURCE_DMA,
282 },
283 },
284 {
285 {
286 .start = OMAP2430_MCBSP5_BASE,
287 .end = OMAP2430_MCBSP5_BASE + SZ_256,
288 .flags = IORESOURCE_MEM,
289 },
290 {
291 .name = "rx",
292 .start = INT_24XX_MCBSP5_IRQ_RX,
293 .flags = IORESOURCE_IRQ,
294 },
295 {
296 .name = "tx",
297 .start = INT_24XX_MCBSP5_IRQ_TX,
298 .flags = IORESOURCE_IRQ,
299 },
300 {
301 .name = "rx",
302 .start = OMAP24XX_DMA_MCBSP5_RX,
303 .flags = IORESOURCE_DMA,
304 },
305 {
306 .name = "tx",
307 .start = OMAP24XX_DMA_MCBSP5_TX,
308 .flags = IORESOURCE_DMA,
309 },
310 },
311};
312#define OMAP2430_MCBSP_RES_SZ ARRAY_SIZE(omap2430_mcbsp_res[1])
313#define OMAP2430_MCBSP_COUNT ARRAY_SIZE(omap2430_mcbsp_res)
314#else
315#define omap2430_mcbsp_res NULL
316#define OMAP2430_MCBSP_RES_SZ 0
317#define OMAP2430_MCBSP_COUNT 0
318#endif
319 121
320#define omap2430_mcbsp_pdata NULL 122 pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
123 if (!pdata) {
124 pr_err("%s: No memory for mcbsp\n", __func__);
125 return -ENOMEM;
126 }
321 127
322#ifdef CONFIG_ARCH_OMAP3 128 if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
323struct resource omap34xx_mcbsp_res[][7] = { 129 if (id == 2)
324 { 130 /* The FIFO has 1024 + 256 locations */
325 { 131 pdata->buffer_size = 0x500;
326 .start = OMAP34XX_MCBSP1_BASE, 132 else
327 .end = OMAP34XX_MCBSP1_BASE + SZ_256, 133 /* The FIFO has 128 locations */
328 .flags = IORESOURCE_MEM, 134 pdata->buffer_size = 0x80;
329 }, 135 }
330 {
331 .name = "rx",
332 .start = INT_24XX_MCBSP1_IRQ_RX,
333 .flags = IORESOURCE_IRQ,
334 },
335 {
336 .name = "tx",
337 .start = INT_24XX_MCBSP1_IRQ_TX,
338 .flags = IORESOURCE_IRQ,
339 },
340 {
341 .name = "rx",
342 .start = OMAP24XX_DMA_MCBSP1_RX,
343 .flags = IORESOURCE_DMA,
344 },
345 {
346 .name = "tx",
347 .start = OMAP24XX_DMA_MCBSP1_TX,
348 .flags = IORESOURCE_DMA,
349 },
350 },
351 {
352 {
353 .start = OMAP34XX_MCBSP2_BASE,
354 .end = OMAP34XX_MCBSP2_BASE + SZ_256,
355 .flags = IORESOURCE_MEM,
356 },
357 {
358 .name = "sidetone",
359 .start = OMAP34XX_MCBSP2_ST_BASE,
360 .end = OMAP34XX_MCBSP2_ST_BASE + SZ_256,
361 .flags = IORESOURCE_MEM,
362 },
363 {
364 .name = "rx",
365 .start = INT_24XX_MCBSP2_IRQ_RX,
366 .flags = IORESOURCE_IRQ,
367 },
368 {
369 .name = "tx",
370 .start = INT_24XX_MCBSP2_IRQ_TX,
371 .flags = IORESOURCE_IRQ,
372 },
373 {
374 .name = "rx",
375 .start = OMAP24XX_DMA_MCBSP2_RX,
376 .flags = IORESOURCE_DMA,
377 },
378 {
379 .name = "tx",
380 .start = OMAP24XX_DMA_MCBSP2_TX,
381 .flags = IORESOURCE_DMA,
382 },
383 },
384 {
385 {
386 .start = OMAP34XX_MCBSP3_BASE,
387 .end = OMAP34XX_MCBSP3_BASE + SZ_256,
388 .flags = IORESOURCE_MEM,
389 },
390 {
391 .name = "sidetone",
392 .start = OMAP34XX_MCBSP3_ST_BASE,
393 .end = OMAP34XX_MCBSP3_ST_BASE + SZ_256,
394 .flags = IORESOURCE_MEM,
395 },
396 {
397 .name = "rx",
398 .start = INT_24XX_MCBSP3_IRQ_RX,
399 .flags = IORESOURCE_IRQ,
400 },
401 {
402 .name = "tx",
403 .start = INT_24XX_MCBSP3_IRQ_TX,
404 .flags = IORESOURCE_IRQ,
405 },
406 {
407 .name = "rx",
408 .start = OMAP24XX_DMA_MCBSP3_RX,
409 .flags = IORESOURCE_DMA,
410 },
411 {
412 .name = "tx",
413 .start = OMAP24XX_DMA_MCBSP3_TX,
414 .flags = IORESOURCE_DMA,
415 },
416 },
417 {
418 {
419 .start = OMAP34XX_MCBSP4_BASE,
420 .end = OMAP34XX_MCBSP4_BASE + SZ_256,
421 .flags = IORESOURCE_MEM,
422 },
423 {
424 .name = "rx",
425 .start = INT_24XX_MCBSP4_IRQ_RX,
426 .flags = IORESOURCE_IRQ,
427 },
428 {
429 .name = "tx",
430 .start = INT_24XX_MCBSP4_IRQ_TX,
431 .flags = IORESOURCE_IRQ,
432 },
433 {
434 .name = "rx",
435 .start = OMAP24XX_DMA_MCBSP4_RX,
436 .flags = IORESOURCE_DMA,
437 },
438 {
439 .name = "tx",
440 .start = OMAP24XX_DMA_MCBSP4_TX,
441 .flags = IORESOURCE_DMA,
442 },
443 },
444 {
445 {
446 .start = OMAP34XX_MCBSP5_BASE,
447 .end = OMAP34XX_MCBSP5_BASE + SZ_256,
448 .flags = IORESOURCE_MEM,
449 },
450 {
451 .name = "rx",
452 .start = INT_24XX_MCBSP5_IRQ_RX,
453 .flags = IORESOURCE_IRQ,
454 },
455 {
456 .name = "tx",
457 .start = INT_24XX_MCBSP5_IRQ_TX,
458 .flags = IORESOURCE_IRQ,
459 },
460 {
461 .name = "rx",
462 .start = OMAP24XX_DMA_MCBSP5_RX,
463 .flags = IORESOURCE_DMA,
464 },
465 {
466 .name = "tx",
467 .start = OMAP24XX_DMA_MCBSP5_TX,
468 .flags = IORESOURCE_DMA,
469 },
470 },
471};
472 136
473static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { 137 oh_device[0] = oh;
474 {
475 .buffer_size = 0x80, /* The FIFO has 128 locations */
476 },
477 {
478 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
479 },
480 {
481 .buffer_size = 0x80, /* The FIFO has 128 locations */
482 },
483 {
484 .buffer_size = 0x80, /* The FIFO has 128 locations */
485 },
486 {
487 .buffer_size = 0x80, /* The FIFO has 128 locations */
488 },
489};
490#define OMAP34XX_MCBSP_RES_SZ ARRAY_SIZE(omap34xx_mcbsp_res[1])
491#define OMAP34XX_MCBSP_COUNT ARRAY_SIZE(omap34xx_mcbsp_res)
492#else
493#define omap34xx_mcbsp_pdata NULL
494#define omap34XX_mcbsp_res NULL
495#define OMAP34XX_MCBSP_RES_SZ 0
496#define OMAP34XX_MCBSP_COUNT 0
497#endif
498 138
499struct resource omap44xx_mcbsp_res[][6] = { 139 if (oh->dev_attr) {
500 { 140 oh_device[1] = omap_hwmod_lookup((
501 { 141 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
502 .name = "mpu", 142 count++;
503 .start = OMAP44XX_MCBSP1_BASE, 143 }
504 .end = OMAP44XX_MCBSP1_BASE + SZ_256, 144 od = omap_device_build_ss(name, id, oh_device, count, pdata,
505 .flags = IORESOURCE_MEM, 145 sizeof(*pdata), omap2_mcbsp_latency,
506 }, 146 ARRAY_SIZE(omap2_mcbsp_latency), false);
507 { 147 kfree(pdata);
508 .name = "dma", 148 if (IS_ERR(od)) {
509 .start = OMAP44XX_MCBSP1_DMA_BASE, 149 pr_err("%s: Cant build omap_device for %s:%s.\n", __func__,
510 .end = OMAP44XX_MCBSP1_DMA_BASE + SZ_256, 150 name, oh->name);
511 .flags = IORESOURCE_MEM, 151 return PTR_ERR(od);
512 }, 152 }
513 { 153 omap_mcbsp_count++;
514 .name = "rx", 154 return 0;
515 .start = 0, 155}
516 .flags = IORESOURCE_IRQ,
517 },
518 {
519 .name = "tx",
520 .start = OMAP44XX_IRQ_MCBSP1,
521 .flags = IORESOURCE_IRQ,
522 },
523 {
524 .name = "rx",
525 .start = OMAP44XX_DMA_MCBSP1_RX,
526 .flags = IORESOURCE_DMA,
527 },
528 {
529 .name = "tx",
530 .start = OMAP44XX_DMA_MCBSP1_TX,
531 .flags = IORESOURCE_DMA,
532 },
533 },
534 {
535 {
536 .name = "mpu",
537 .start = OMAP44XX_MCBSP2_BASE,
538 .end = OMAP44XX_MCBSP2_BASE + SZ_256,
539 .flags = IORESOURCE_MEM,
540 },
541 {
542 .name = "dma",
543 .start = OMAP44XX_MCBSP2_DMA_BASE,
544 .end = OMAP44XX_MCBSP2_DMA_BASE + SZ_256,
545 .flags = IORESOURCE_MEM,
546 },
547 {
548 .name = "rx",
549 .start = 0,
550 .flags = IORESOURCE_IRQ,
551 },
552 {
553 .name = "tx",
554 .start = OMAP44XX_IRQ_MCBSP2,
555 .flags = IORESOURCE_IRQ,
556 },
557 {
558 .name = "rx",
559 .start = OMAP44XX_DMA_MCBSP2_RX,
560 .flags = IORESOURCE_DMA,
561 },
562 {
563 .name = "tx",
564 .start = OMAP44XX_DMA_MCBSP2_TX,
565 .flags = IORESOURCE_DMA,
566 },
567 },
568 {
569 {
570 .name = "mpu",
571 .start = OMAP44XX_MCBSP3_BASE,
572 .end = OMAP44XX_MCBSP3_BASE + SZ_256,
573 .flags = IORESOURCE_MEM,
574 },
575 {
576 .name = "dma",
577 .start = OMAP44XX_MCBSP3_DMA_BASE,
578 .end = OMAP44XX_MCBSP3_DMA_BASE + SZ_256,
579 .flags = IORESOURCE_MEM,
580 },
581 {
582 .name = "rx",
583 .start = 0,
584 .flags = IORESOURCE_IRQ,
585 },
586 {
587 .name = "tx",
588 .start = OMAP44XX_IRQ_MCBSP3,
589 .flags = IORESOURCE_IRQ,
590 },
591 {
592 .name = "rx",
593 .start = OMAP44XX_DMA_MCBSP3_RX,
594 .flags = IORESOURCE_DMA,
595 },
596 {
597 .name = "tx",
598 .start = OMAP44XX_DMA_MCBSP3_TX,
599 .flags = IORESOURCE_DMA,
600 },
601 },
602 {
603 {
604 .start = OMAP44XX_MCBSP4_BASE,
605 .end = OMAP44XX_MCBSP4_BASE + SZ_256,
606 .flags = IORESOURCE_MEM,
607 },
608 {
609 .name = "rx",
610 .start = 0,
611 .flags = IORESOURCE_IRQ,
612 },
613 {
614 .name = "tx",
615 .start = OMAP44XX_IRQ_MCBSP4,
616 .flags = IORESOURCE_IRQ,
617 },
618 {
619 .name = "rx",
620 .start = OMAP44XX_DMA_MCBSP4_RX,
621 .flags = IORESOURCE_DMA,
622 },
623 {
624 .name = "tx",
625 .start = OMAP44XX_DMA_MCBSP4_TX,
626 .flags = IORESOURCE_DMA,
627 },
628 },
629};
630#define omap44xx_mcbsp_pdata NULL
631#define OMAP44XX_MCBSP_RES_SZ ARRAY_SIZE(omap44xx_mcbsp_res[1])
632#define OMAP44XX_MCBSP_COUNT ARRAY_SIZE(omap44xx_mcbsp_res)
633 156
634static int __init omap2_mcbsp_init(void) 157static int __init omap2_mcbsp_init(void)
635{ 158{
636 if (cpu_is_omap2420()) 159 omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
637 omap_mcbsp_count = OMAP2420_MCBSP_COUNT;
638 else if (cpu_is_omap2430())
639 omap_mcbsp_count = OMAP2430_MCBSP_COUNT;
640 else if (cpu_is_omap34xx())
641 omap_mcbsp_count = OMAP34XX_MCBSP_COUNT;
642 else if (cpu_is_omap44xx())
643 omap_mcbsp_count = OMAP44XX_MCBSP_COUNT;
644 160
645 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 161 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
646 GFP_KERNEL); 162 GFP_KERNEL);
647 if (!mcbsp_ptr) 163 if (!mcbsp_ptr)
648 return -ENOMEM; 164 return -ENOMEM;
649 165
650 if (cpu_is_omap2420())
651 omap_mcbsp_register_board_cfg(omap2420_mcbsp_res[0],
652 OMAP2420_MCBSP_RES_SZ,
653 omap2420_mcbsp_pdata,
654 OMAP2420_MCBSP_COUNT);
655 if (cpu_is_omap2430())
656 omap_mcbsp_register_board_cfg(omap2430_mcbsp_res[0],
657 OMAP2420_MCBSP_RES_SZ,
658 omap2430_mcbsp_pdata,
659 OMAP2430_MCBSP_COUNT);
660 if (cpu_is_omap34xx())
661 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_res[0],
662 OMAP34XX_MCBSP_RES_SZ,
663 omap34xx_mcbsp_pdata,
664 OMAP34XX_MCBSP_COUNT);
665 if (cpu_is_omap44xx())
666 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_res[0],
667 OMAP44XX_MCBSP_RES_SZ,
668 omap44xx_mcbsp_pdata,
669 OMAP44XX_MCBSP_COUNT);
670
671 return omap_mcbsp_init(); 166 return omap_mcbsp_init();
672} 167}
673arch_initcall(omap2_mcbsp_init); 168arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 1fe06372c9ce..c6cabfc77a12 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -421,8 +421,8 @@ struct omap_mcbsp_platform_data {
421#ifdef CONFIG_ARCH_OMAP3 421#ifdef CONFIG_ARCH_OMAP3
422 /* Sidetone block for McBSP 2 and 3 */ 422 /* Sidetone block for McBSP 2 and 3 */
423 unsigned long phys_base_st; 423 unsigned long phys_base_st;
424 u16 buffer_size;
425#endif 424#endif
425 u16 buffer_size;
426}; 426};
427 427
428struct omap_mcbsp_st_data { 428struct omap_mcbsp_st_data {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-08 11:47:50 -0500