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authorNathan Lynch <ntl@pobox.com>2007-08-09 17:43:28 -0400
committerPaul Mackerras <paulus@samba.org>2007-08-16 21:01:54 -0400
commit0f7f2fb85a67953acd6bf379681f22f5c83d4f60 (patch)
tree1e96f7ae260afdc3cd3c24901e6f03bdcdcb385c
parentb139f1fb0f1e4bfe06f2c88ba8c9a55d9513d871 (diff)
[POWERPC] Remove gratuitous reads from powermac pci config space methods
The powermac pci configuration space write methods read the written location immediately after the write is performed, presumably in order to flush the write. However, configuration space writes are not allowed to be posted, making these reads gratuitous. Furthermore, this behavior potentially causes us to violate the PCI PM spec when changing between e.g. D0 and D3 states, because a delay of up to 10ms may be required before the OS accesses configuration space after the write which initiates the transition. Remove the unnecessary reads from macrisc_write_config, u3_ht_write_config, and u4_pcie_write_config. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--arch/powerpc/platforms/powermac/pci.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 69d67ff07004..ec49099830d5 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -209,15 +209,12 @@ static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
209 switch (len) { 209 switch (len) {
210 case 1: 210 case 1:
211 out_8(addr, val); 211 out_8(addr, val);
212 (void) in_8(addr);
213 break; 212 break;
214 case 2: 213 case 2:
215 out_le16(addr, val); 214 out_le16(addr, val);
216 (void) in_le16(addr);
217 break; 215 break;
218 default: 216 default:
219 out_le32(addr, val); 217 out_le32(addr, val);
220 (void) in_le32(addr);
221 break; 218 break;
222 } 219 }
223 return PCIBIOS_SUCCESSFUL; 220 return PCIBIOS_SUCCESSFUL;
@@ -440,15 +437,12 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
440 switch (len) { 437 switch (len) {
441 case 1: 438 case 1:
442 out_8(addr, val); 439 out_8(addr, val);
443 (void) in_8(addr);
444 break; 440 break;
445 case 2: 441 case 2:
446 out_le16(addr, val); 442 out_le16(addr, val);
447 (void) in_le16(addr);
448 break; 443 break;
449 default: 444 default:
450 out_le32((u32 __iomem *)addr, val); 445 out_le32((u32 __iomem *)addr, val);
451 (void) in_le32(addr);
452 break; 446 break;
453 } 447 }
454 return PCIBIOS_SUCCESSFUL; 448 return PCIBIOS_SUCCESSFUL;
@@ -545,15 +539,12 @@ static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
545 switch (len) { 539 switch (len) {
546 case 1: 540 case 1:
547 out_8(addr, val); 541 out_8(addr, val);
548 (void) in_8(addr);
549 break; 542 break;
550 case 2: 543 case 2:
551 out_le16(addr, val); 544 out_le16(addr, val);
552 (void) in_le16(addr);
553 break; 545 break;
554 default: 546 default:
555 out_le32(addr, val); 547 out_le32(addr, val);
556 (void) in_le32(addr);
557 break; 548 break;
558 } 549 }
559 return PCIBIOS_SUCCESSFUL; 550 return PCIBIOS_SUCCESSFUL;