diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-03-30 08:59:57 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2012-04-24 04:50:14 -0400 |
commit | f122c6109b1a79153cfb1e188c665ce3f312a886 (patch) | |
tree | 9b8d9211c0be59a0a96a906373bd85d187d23ab4 | |
parent | 3a2a67aa28725bb500505087067e7830cfa9c137 (diff) |
drm/radeon/kms: fix up audio interrupt handling
- add support for rs6xx
- add support for DCE4/5
- fixup 6xx/7xx
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 128 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 115 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600_audio.c | 63 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600_hdmi.c | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 17 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_irq_kms.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rs600.c | 40 |
8 files changed, 281 insertions, 105 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index cfa372cb1cb3..eed7acefb492 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -2594,6 +2594,7 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
2594 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; | 2594 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
2595 | u32 grbm_int_cntl = 0; | 2595 | u32 grbm_int_cntl = 0; |
2596 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; | 2596 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
2597 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; | ||
2597 | 2598 | ||
2598 | if (!rdev->irq.installed) { | 2599 | if (!rdev->irq.installed) { |
2599 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); | 2600 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
@@ -2614,6 +2615,13 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
2614 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | 2615 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2615 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | 2616 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
2616 | 2617 | ||
2618 | afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2619 | afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2620 | afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2621 | afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2622 | afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2623 | afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2624 | |||
2617 | if (rdev->family >= CHIP_CAYMAN) { | 2625 | if (rdev->family >= CHIP_CAYMAN) { |
2618 | /* enable CP interrupts on all rings */ | 2626 | /* enable CP interrupts on all rings */ |
2619 | if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { | 2627 | if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { |
@@ -2690,6 +2698,30 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
2690 | DRM_DEBUG("evergreen_irq_set: hpd 6\n"); | 2698 | DRM_DEBUG("evergreen_irq_set: hpd 6\n"); |
2691 | hpd6 |= DC_HPDx_INT_EN; | 2699 | hpd6 |= DC_HPDx_INT_EN; |
2692 | } | 2700 | } |
2701 | if (rdev->irq.afmt[0]) { | ||
2702 | DRM_DEBUG("evergreen_irq_set: hdmi 0\n"); | ||
2703 | afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2704 | } | ||
2705 | if (rdev->irq.afmt[1]) { | ||
2706 | DRM_DEBUG("evergreen_irq_set: hdmi 1\n"); | ||
2707 | afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2708 | } | ||
2709 | if (rdev->irq.afmt[2]) { | ||
2710 | DRM_DEBUG("evergreen_irq_set: hdmi 2\n"); | ||
2711 | afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2712 | } | ||
2713 | if (rdev->irq.afmt[3]) { | ||
2714 | DRM_DEBUG("evergreen_irq_set: hdmi 3\n"); | ||
2715 | afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2716 | } | ||
2717 | if (rdev->irq.afmt[4]) { | ||
2718 | DRM_DEBUG("evergreen_irq_set: hdmi 4\n"); | ||
2719 | afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2720 | } | ||
2721 | if (rdev->irq.afmt[5]) { | ||
2722 | DRM_DEBUG("evergreen_irq_set: hdmi 5\n"); | ||
2723 | afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK; | ||
2724 | } | ||
2693 | if (rdev->irq.gui_idle) { | 2725 | if (rdev->irq.gui_idle) { |
2694 | DRM_DEBUG("gui idle\n"); | 2726 | DRM_DEBUG("gui idle\n"); |
2695 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; | 2727 | grbm_int_cntl |= GUI_IDLE_INT_ENABLE; |
@@ -2732,6 +2764,13 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
2732 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | 2764 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
2733 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | 2765 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
2734 | 2766 | ||
2767 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); | ||
2768 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); | ||
2769 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); | ||
2770 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); | ||
2771 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); | ||
2772 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); | ||
2773 | |||
2735 | return 0; | 2774 | return 0; |
2736 | } | 2775 | } |
2737 | 2776 | ||
@@ -2756,6 +2795,13 @@ static void evergreen_irq_ack(struct radeon_device *rdev) | |||
2756 | rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); | 2795 | rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); |
2757 | } | 2796 | } |
2758 | 2797 | ||
2798 | rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); | ||
2799 | rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); | ||
2800 | rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); | ||
2801 | rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); | ||
2802 | rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); | ||
2803 | rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); | ||
2804 | |||
2759 | if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) | 2805 | if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) |
2760 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); | 2806 | WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); |
2761 | if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) | 2807 | if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) |
@@ -2829,6 +2875,36 @@ static void evergreen_irq_ack(struct radeon_device *rdev) | |||
2829 | tmp |= DC_HPDx_INT_ACK; | 2875 | tmp |= DC_HPDx_INT_ACK; |
2830 | WREG32(DC_HPD6_INT_CONTROL, tmp); | 2876 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
2831 | } | 2877 | } |
2878 | if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { | ||
2879 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); | ||
2880 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | ||
2881 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); | ||
2882 | } | ||
2883 | if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { | ||
2884 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); | ||
2885 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | ||
2886 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); | ||
2887 | } | ||
2888 | if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { | ||
2889 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); | ||
2890 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | ||
2891 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); | ||
2892 | } | ||
2893 | if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { | ||
2894 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); | ||
2895 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | ||
2896 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); | ||
2897 | } | ||
2898 | if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { | ||
2899 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); | ||
2900 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | ||
2901 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); | ||
2902 | } | ||
2903 | if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { | ||
2904 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | ||
2905 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | ||
2906 | WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); | ||
2907 | } | ||
2832 | } | 2908 | } |
2833 | 2909 | ||
2834 | void evergreen_irq_disable(struct radeon_device *rdev) | 2910 | void evergreen_irq_disable(struct radeon_device *rdev) |
@@ -2878,6 +2954,7 @@ int evergreen_irq_process(struct radeon_device *rdev) | |||
2878 | u32 ring_index; | 2954 | u32 ring_index; |
2879 | unsigned long flags; | 2955 | unsigned long flags; |
2880 | bool queue_hotplug = false; | 2956 | bool queue_hotplug = false; |
2957 | bool queue_hdmi = false; | ||
2881 | 2958 | ||
2882 | if (!rdev->ih.enabled || rdev->shutdown) | 2959 | if (!rdev->ih.enabled || rdev->shutdown) |
2883 | return IRQ_NONE; | 2960 | return IRQ_NONE; |
@@ -3111,6 +3188,55 @@ restart_ih: | |||
3111 | break; | 3188 | break; |
3112 | } | 3189 | } |
3113 | break; | 3190 | break; |
3191 | case 44: /* hdmi */ | ||
3192 | switch (src_data) { | ||
3193 | case 0: | ||
3194 | if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { | ||
3195 | rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; | ||
3196 | queue_hdmi = true; | ||
3197 | DRM_DEBUG("IH: HDMI0\n"); | ||
3198 | } | ||
3199 | break; | ||
3200 | case 1: | ||
3201 | if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { | ||
3202 | rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; | ||
3203 | queue_hdmi = true; | ||
3204 | DRM_DEBUG("IH: HDMI1\n"); | ||
3205 | } | ||
3206 | break; | ||
3207 | case 2: | ||
3208 | if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { | ||
3209 | rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; | ||
3210 | queue_hdmi = true; | ||
3211 | DRM_DEBUG("IH: HDMI2\n"); | ||
3212 | } | ||
3213 | break; | ||
3214 | case 3: | ||
3215 | if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { | ||
3216 | rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; | ||
3217 | queue_hdmi = true; | ||
3218 | DRM_DEBUG("IH: HDMI3\n"); | ||
3219 | } | ||
3220 | break; | ||
3221 | case 4: | ||
3222 | if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { | ||
3223 | rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; | ||
3224 | queue_hdmi = true; | ||
3225 | DRM_DEBUG("IH: HDMI4\n"); | ||
3226 | } | ||
3227 | break; | ||
3228 | case 5: | ||
3229 | if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { | ||
3230 | rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; | ||
3231 | queue_hdmi = true; | ||
3232 | DRM_DEBUG("IH: HDMI5\n"); | ||
3233 | } | ||
3234 | break; | ||
3235 | default: | ||
3236 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | ||
3237 | break; | ||
3238 | } | ||
3239 | break; | ||
3114 | case 176: /* CP_INT in ring buffer */ | 3240 | case 176: /* CP_INT in ring buffer */ |
3115 | case 177: /* CP_INT in IB1 */ | 3241 | case 177: /* CP_INT in IB1 */ |
3116 | case 178: /* CP_INT in IB2 */ | 3242 | case 178: /* CP_INT in IB2 */ |
@@ -3154,6 +3280,8 @@ restart_ih: | |||
3154 | goto restart_ih; | 3280 | goto restart_ih; |
3155 | if (queue_hotplug) | 3281 | if (queue_hotplug) |
3156 | schedule_work(&rdev->hotplug_work); | 3282 | schedule_work(&rdev->hotplug_work); |
3283 | if (queue_hdmi) | ||
3284 | schedule_work(&rdev->audio_work); | ||
3157 | rdev->ih.rptr = rptr; | 3285 | rdev->ih.rptr = rptr; |
3158 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | 3286 | WREG32(IH_RB_RPTR, rdev->ih.rptr); |
3159 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | 3287 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 4added1c7ee9..ba637d95965b 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -2968,6 +2968,15 @@ static void r600_disable_interrupt_state(struct radeon_device *rdev) | |||
2968 | WREG32(DC_HPD5_INT_CONTROL, tmp); | 2968 | WREG32(DC_HPD5_INT_CONTROL, tmp); |
2969 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; | 2969 | tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; |
2970 | WREG32(DC_HPD6_INT_CONTROL, tmp); | 2970 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
2971 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
2972 | WREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET0, tmp); | ||
2973 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
2974 | WREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET1, tmp); | ||
2975 | } else { | ||
2976 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
2977 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); | ||
2978 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
2979 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); | ||
2971 | } | 2980 | } |
2972 | } else { | 2981 | } else { |
2973 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); | 2982 | WREG32(DACA_AUTODETECT_INT_CONTROL, 0); |
@@ -2978,6 +2987,10 @@ static void r600_disable_interrupt_state(struct radeon_device *rdev) | |||
2978 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); | 2987 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
2979 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; | 2988 | tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; |
2980 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); | 2989 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); |
2990 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
2991 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); | ||
2992 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
2993 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); | ||
2981 | } | 2994 | } |
2982 | } | 2995 | } |
2983 | 2996 | ||
@@ -3074,7 +3087,7 @@ int r600_irq_set(struct radeon_device *rdev) | |||
3074 | u32 mode_int = 0; | 3087 | u32 mode_int = 0; |
3075 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | 3088 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
3076 | u32 grbm_int_cntl = 0; | 3089 | u32 grbm_int_cntl = 0; |
3077 | u32 hdmi1, hdmi2; | 3090 | u32 hdmi0, hdmi1; |
3078 | u32 d1grph = 0, d2grph = 0; | 3091 | u32 d1grph = 0, d2grph = 0; |
3079 | 3092 | ||
3080 | if (!rdev->irq.installed) { | 3093 | if (!rdev->irq.installed) { |
@@ -3089,9 +3102,7 @@ int r600_irq_set(struct radeon_device *rdev) | |||
3089 | return 0; | 3102 | return 0; |
3090 | } | 3103 | } |
3091 | 3104 | ||
3092 | hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; | ||
3093 | if (ASIC_IS_DCE3(rdev)) { | 3105 | if (ASIC_IS_DCE3(rdev)) { |
3094 | hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; | ||
3095 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; | 3106 | hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3096 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; | 3107 | hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3097 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; | 3108 | hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
@@ -3099,12 +3110,18 @@ int r600_irq_set(struct radeon_device *rdev) | |||
3099 | if (ASIC_IS_DCE32(rdev)) { | 3110 | if (ASIC_IS_DCE32(rdev)) { |
3100 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; | 3111 | hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3101 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; | 3112 | hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3113 | hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | ||
3114 | hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; | ||
3115 | } else { | ||
3116 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
3117 | hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
3102 | } | 3118 | } |
3103 | } else { | 3119 | } else { |
3104 | hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN; | ||
3105 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; | 3120 | hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3106 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; | 3121 | hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3107 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; | 3122 | hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
3123 | hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
3124 | hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; | ||
3108 | } | 3125 | } |
3109 | 3126 | ||
3110 | if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { | 3127 | if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) { |
@@ -3146,13 +3163,13 @@ int r600_irq_set(struct radeon_device *rdev) | |||
3146 | DRM_DEBUG("r600_irq_set: hpd 6\n"); | 3163 | DRM_DEBUG("r600_irq_set: hpd 6\n"); |
3147 | hpd6 |= DC_HPDx_INT_EN; | 3164 | hpd6 |= DC_HPDx_INT_EN; |
3148 | } | 3165 | } |
3149 | if (rdev->irq.hdmi[0]) { | 3166 | if (rdev->irq.afmt[0]) { |
3150 | DRM_DEBUG("r600_irq_set: hdmi 1\n"); | 3167 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); |
3151 | hdmi1 |= R600_HDMI_INT_EN; | 3168 | hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; |
3152 | } | 3169 | } |
3153 | if (rdev->irq.hdmi[1]) { | 3170 | if (rdev->irq.afmt[1]) { |
3154 | DRM_DEBUG("r600_irq_set: hdmi 2\n"); | 3171 | DRM_DEBUG("r600_irq_set: hdmi 0\n"); |
3155 | hdmi2 |= R600_HDMI_INT_EN; | 3172 | hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; |
3156 | } | 3173 | } |
3157 | if (rdev->irq.gui_idle) { | 3174 | if (rdev->irq.gui_idle) { |
3158 | DRM_DEBUG("gui idle\n"); | 3175 | DRM_DEBUG("gui idle\n"); |
@@ -3164,9 +3181,7 @@ int r600_irq_set(struct radeon_device *rdev) | |||
3164 | WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); | 3181 | WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); |
3165 | WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); | 3182 | WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); |
3166 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); | 3183 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
3167 | WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1); | ||
3168 | if (ASIC_IS_DCE3(rdev)) { | 3184 | if (ASIC_IS_DCE3(rdev)) { |
3169 | WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2); | ||
3170 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | 3185 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
3171 | WREG32(DC_HPD2_INT_CONTROL, hpd2); | 3186 | WREG32(DC_HPD2_INT_CONTROL, hpd2); |
3172 | WREG32(DC_HPD3_INT_CONTROL, hpd3); | 3187 | WREG32(DC_HPD3_INT_CONTROL, hpd3); |
@@ -3174,12 +3189,18 @@ int r600_irq_set(struct radeon_device *rdev) | |||
3174 | if (ASIC_IS_DCE32(rdev)) { | 3189 | if (ASIC_IS_DCE32(rdev)) { |
3175 | WREG32(DC_HPD5_INT_CONTROL, hpd5); | 3190 | WREG32(DC_HPD5_INT_CONTROL, hpd5); |
3176 | WREG32(DC_HPD6_INT_CONTROL, hpd6); | 3191 | WREG32(DC_HPD6_INT_CONTROL, hpd6); |
3192 | WREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET0, hdmi0); | ||
3193 | WREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET1, hdmi1); | ||
3194 | } else { | ||
3195 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); | ||
3196 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); | ||
3177 | } | 3197 | } |
3178 | } else { | 3198 | } else { |
3179 | WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2); | ||
3180 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); | 3199 | WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
3181 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | 3200 | WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
3182 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); | 3201 | WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); |
3202 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); | ||
3203 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); | ||
3183 | } | 3204 | } |
3184 | 3205 | ||
3185 | return 0; | 3206 | return 0; |
@@ -3193,10 +3214,19 @@ static void r600_irq_ack(struct radeon_device *rdev) | |||
3193 | rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); | 3214 | rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); |
3194 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); | 3215 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); |
3195 | rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); | 3216 | rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); |
3217 | if (ASIC_IS_DCE32(rdev)) { | ||
3218 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + HDMI_OFFSET0); | ||
3219 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + HDMI_OFFSET1); | ||
3220 | } else { | ||
3221 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); | ||
3222 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); | ||
3223 | } | ||
3196 | } else { | 3224 | } else { |
3197 | rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); | 3225 | rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
3198 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); | 3226 | rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); |
3199 | rdev->irq.stat_regs.r600.disp_int_cont2 = 0; | 3227 | rdev->irq.stat_regs.r600.disp_int_cont2 = 0; |
3228 | rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); | ||
3229 | rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); | ||
3200 | } | 3230 | } |
3201 | rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); | 3231 | rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); |
3202 | rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); | 3232 | rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); |
@@ -3262,17 +3292,32 @@ static void r600_irq_ack(struct radeon_device *rdev) | |||
3262 | tmp |= DC_HPDx_INT_ACK; | 3292 | tmp |= DC_HPDx_INT_ACK; |
3263 | WREG32(DC_HPD6_INT_CONTROL, tmp); | 3293 | WREG32(DC_HPD6_INT_CONTROL, tmp); |
3264 | } | 3294 | } |
3265 | } | 3295 | if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { |
3266 | if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { | 3296 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET0); |
3267 | WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | 3297 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; |
3268 | } | 3298 | WREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET0, tmp); |
3269 | if (ASIC_IS_DCE3(rdev)) { | 3299 | } |
3270 | if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { | 3300 | if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { |
3271 | WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | 3301 | tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET1); |
3302 | tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; | ||
3303 | WREG32(AFMT_AUDIO_PACKET_CONTROL + HDMI_OFFSET1, tmp); | ||
3272 | } | 3304 | } |
3273 | } else { | 3305 | } else { |
3274 | if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) { | 3306 | if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { |
3275 | WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK); | 3307 | tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); |
3308 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; | ||
3309 | WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); | ||
3310 | } | ||
3311 | if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { | ||
3312 | if (ASIC_IS_DCE3(rdev)) { | ||
3313 | tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); | ||
3314 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; | ||
3315 | WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); | ||
3316 | } else { | ||
3317 | tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); | ||
3318 | tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; | ||
3319 | WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); | ||
3320 | } | ||
3276 | } | 3321 | } |
3277 | } | 3322 | } |
3278 | } | 3323 | } |
@@ -3348,6 +3393,7 @@ int r600_irq_process(struct radeon_device *rdev) | |||
3348 | u32 ring_index; | 3393 | u32 ring_index; |
3349 | unsigned long flags; | 3394 | unsigned long flags; |
3350 | bool queue_hotplug = false; | 3395 | bool queue_hotplug = false; |
3396 | bool queue_hdmi = false; | ||
3351 | 3397 | ||
3352 | if (!rdev->ih.enabled || rdev->shutdown) | 3398 | if (!rdev->ih.enabled || rdev->shutdown) |
3353 | return IRQ_NONE; | 3399 | return IRQ_NONE; |
@@ -3483,9 +3529,26 @@ restart_ih: | |||
3483 | break; | 3529 | break; |
3484 | } | 3530 | } |
3485 | break; | 3531 | break; |
3486 | case 21: /* HDMI */ | 3532 | case 21: /* hdmi */ |
3487 | DRM_DEBUG("IH: HDMI: 0x%x\n", src_data); | 3533 | switch (src_data) { |
3488 | r600_audio_schedule_polling(rdev); | 3534 | case 4: |
3535 | if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { | ||
3536 | rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; | ||
3537 | queue_hdmi = true; | ||
3538 | DRM_DEBUG("IH: HDMI0\n"); | ||
3539 | } | ||
3540 | break; | ||
3541 | case 5: | ||
3542 | if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { | ||
3543 | rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; | ||
3544 | queue_hdmi = true; | ||
3545 | DRM_DEBUG("IH: HDMI1\n"); | ||
3546 | } | ||
3547 | break; | ||
3548 | default: | ||
3549 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | ||
3550 | break; | ||
3551 | } | ||
3489 | break; | 3552 | break; |
3490 | case 176: /* CP_INT in ring buffer */ | 3553 | case 176: /* CP_INT in ring buffer */ |
3491 | case 177: /* CP_INT in IB1 */ | 3554 | case 177: /* CP_INT in IB1 */ |
@@ -3517,6 +3580,8 @@ restart_ih: | |||
3517 | goto restart_ih; | 3580 | goto restart_ih; |
3518 | if (queue_hotplug) | 3581 | if (queue_hotplug) |
3519 | schedule_work(&rdev->hotplug_work); | 3582 | schedule_work(&rdev->hotplug_work); |
3583 | if (queue_hdmi) | ||
3584 | schedule_work(&rdev->audio_work); | ||
3520 | rdev->ih.rptr = rptr; | 3585 | rdev->ih.rptr = rptr; |
3521 | WREG32(IH_RB_RPTR, rdev->ih.rptr); | 3586 | WREG32(IH_RB_RPTR, rdev->ih.rptr); |
3522 | spin_unlock_irqrestore(&rdev->ih.lock, flags); | 3587 | spin_unlock_irqrestore(&rdev->ih.lock, flags); |
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c index ba66f3093d46..a7c06c330fe1 100644 --- a/drivers/gpu/drm/radeon/r600_audio.c +++ b/drivers/gpu/drm/radeon/r600_audio.c | |||
@@ -29,8 +29,6 @@ | |||
29 | #include "radeon_asic.h" | 29 | #include "radeon_asic.h" |
30 | #include "atom.h" | 30 | #include "atom.h" |
31 | 31 | ||
32 | #define AUDIO_TIMER_INTERVALL 100 /* 1/10 sekund should be enough */ | ||
33 | |||
34 | /* | 32 | /* |
35 | * check if the chipset is supported | 33 | * check if the chipset is supported |
36 | */ | 34 | */ |
@@ -106,20 +104,12 @@ uint8_t r600_audio_category_code(struct radeon_device *rdev) | |||
106 | } | 104 | } |
107 | 105 | ||
108 | /* | 106 | /* |
109 | * schedule next audio update event | ||
110 | */ | ||
111 | void r600_audio_schedule_polling(struct radeon_device *rdev) | ||
112 | { | ||
113 | mod_timer(&rdev->audio_timer, | ||
114 | jiffies + msecs_to_jiffies(AUDIO_TIMER_INTERVALL)); | ||
115 | } | ||
116 | |||
117 | /* | ||
118 | * update all hdmi interfaces with current audio parameters | 107 | * update all hdmi interfaces with current audio parameters |
119 | */ | 108 | */ |
120 | static void r600_audio_update_hdmi(unsigned long param) | 109 | void r600_audio_update_hdmi(struct work_struct *work) |
121 | { | 110 | { |
122 | struct radeon_device *rdev = (struct radeon_device *)param; | 111 | struct radeon_device *rdev = container_of(work, struct radeon_device, |
112 | audio_work); | ||
123 | struct drm_device *dev = rdev->ddev; | 113 | struct drm_device *dev = rdev->ddev; |
124 | 114 | ||
125 | int channels = r600_audio_channels(rdev); | 115 | int channels = r600_audio_channels(rdev); |
@@ -127,9 +117,8 @@ static void r600_audio_update_hdmi(unsigned long param) | |||
127 | int bps = r600_audio_bits_per_sample(rdev); | 117 | int bps = r600_audio_bits_per_sample(rdev); |
128 | uint8_t status_bits = r600_audio_status_bits(rdev); | 118 | uint8_t status_bits = r600_audio_status_bits(rdev); |
129 | uint8_t category_code = r600_audio_category_code(rdev); | 119 | uint8_t category_code = r600_audio_category_code(rdev); |
130 | |||
131 | struct drm_encoder *encoder; | 120 | struct drm_encoder *encoder; |
132 | int changes = 0, still_going = 0; | 121 | int changes = 0; |
133 | 122 | ||
134 | changes |= channels != rdev->audio_channels; | 123 | changes |= channels != rdev->audio_channels; |
135 | changes |= rate != rdev->audio_rate; | 124 | changes |= rate != rdev->audio_rate; |
@@ -146,14 +135,9 @@ static void r600_audio_update_hdmi(unsigned long param) | |||
146 | } | 135 | } |
147 | 136 | ||
148 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | 137 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
149 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
150 | still_going |= radeon_encoder->audio_polling_active; | ||
151 | if (changes || r600_hdmi_buffer_status_changed(encoder)) | 138 | if (changes || r600_hdmi_buffer_status_changed(encoder)) |
152 | r600_hdmi_update_audio_settings(encoder); | 139 | r600_hdmi_update_audio_settings(encoder); |
153 | } | 140 | } |
154 | |||
155 | if (still_going) | ||
156 | r600_audio_schedule_polling(rdev); | ||
157 | } | 141 | } |
158 | 142 | ||
159 | /* | 143 | /* |
@@ -177,7 +161,7 @@ static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable) | |||
177 | } | 161 | } |
178 | 162 | ||
179 | /* | 163 | /* |
180 | * initialize the audio vars and register the update timer | 164 | * initialize the audio vars |
181 | */ | 165 | */ |
182 | int r600_audio_init(struct radeon_device *rdev) | 166 | int r600_audio_init(struct radeon_device *rdev) |
183 | { | 167 | { |
@@ -192,45 +176,10 @@ int r600_audio_init(struct radeon_device *rdev) | |||
192 | rdev->audio_status_bits = 0; | 176 | rdev->audio_status_bits = 0; |
193 | rdev->audio_category_code = 0; | 177 | rdev->audio_category_code = 0; |
194 | 178 | ||
195 | setup_timer( | ||
196 | &rdev->audio_timer, | ||
197 | r600_audio_update_hdmi, | ||
198 | (unsigned long)rdev); | ||
199 | |||
200 | return 0; | 179 | return 0; |
201 | } | 180 | } |
202 | 181 | ||
203 | /* | 182 | /* |
204 | * enable the polling timer, to check for status changes | ||
205 | */ | ||
206 | void r600_audio_enable_polling(struct drm_encoder *encoder) | ||
207 | { | ||
208 | struct drm_device *dev = encoder->dev; | ||
209 | struct radeon_device *rdev = dev->dev_private; | ||
210 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
211 | |||
212 | DRM_DEBUG("r600_audio_enable_polling: %d\n", | ||
213 | radeon_encoder->audio_polling_active); | ||
214 | if (radeon_encoder->audio_polling_active) | ||
215 | return; | ||
216 | |||
217 | radeon_encoder->audio_polling_active = 1; | ||
218 | if (rdev->audio_enabled) | ||
219 | mod_timer(&rdev->audio_timer, jiffies + 1); | ||
220 | } | ||
221 | |||
222 | /* | ||
223 | * disable the polling timer, so we get no more status updates | ||
224 | */ | ||
225 | void r600_audio_disable_polling(struct drm_encoder *encoder) | ||
226 | { | ||
227 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | ||
228 | DRM_DEBUG("r600_audio_disable_polling: %d\n", | ||
229 | radeon_encoder->audio_polling_active); | ||
230 | radeon_encoder->audio_polling_active = 0; | ||
231 | } | ||
232 | |||
233 | /* | ||
234 | * atach the audio codec to the clock source of the encoder | 183 | * atach the audio codec to the clock source of the encoder |
235 | */ | 184 | */ |
236 | void r600_audio_set_clock(struct drm_encoder *encoder, int clock) | 185 | void r600_audio_set_clock(struct drm_encoder *encoder, int clock) |
@@ -297,7 +246,5 @@ void r600_audio_fini(struct radeon_device *rdev) | |||
297 | if (!rdev->audio_enabled) | 246 | if (!rdev->audio_enabled) |
298 | return; | 247 | return; |
299 | 248 | ||
300 | del_timer(&rdev->audio_timer); | ||
301 | |||
302 | r600_audio_engine_enable(rdev, false); | 249 | r600_audio_engine_enable(rdev, false); |
303 | } | 250 | } |
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 0b5920671450..37ac1b06753e 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c | |||
@@ -548,19 +548,10 @@ void r600_hdmi_enable(struct drm_encoder *encoder) | |||
548 | } | 548 | } |
549 | } | 549 | } |
550 | 550 | ||
551 | if (rdev->irq.installed | 551 | if (rdev->irq.installed) { |
552 | && rdev->family != CHIP_RS600 | ||
553 | && rdev->family != CHIP_RS690 | ||
554 | && rdev->family != CHIP_RS740 | ||
555 | && !ASIC_IS_DCE4(rdev)) { | ||
556 | /* if irq is available use it */ | 552 | /* if irq is available use it */ |
557 | rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true; | 553 | rdev->irq.afmt[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true; |
558 | radeon_irq_set(rdev); | 554 | radeon_irq_set(rdev); |
559 | |||
560 | r600_audio_disable_polling(encoder); | ||
561 | } else { | ||
562 | /* if not fallback to polling */ | ||
563 | r600_audio_enable_polling(encoder); | ||
564 | } | 555 | } |
565 | 556 | ||
566 | DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", | 557 | DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
@@ -590,11 +581,9 @@ void r600_hdmi_disable(struct drm_encoder *encoder) | |||
590 | offset, radeon_encoder->encoder_id); | 581 | offset, radeon_encoder->encoder_id); |
591 | 582 | ||
592 | /* disable irq */ | 583 | /* disable irq */ |
593 | rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = false; | 584 | rdev->irq.afmt[offset == R600_HDMI_BLOCK1 ? 0 : 1] = false; |
594 | radeon_irq_set(rdev); | 585 | radeon_irq_set(rdev); |
595 | 586 | ||
596 | /* disable polling */ | ||
597 | r600_audio_disable_polling(encoder); | ||
598 | 587 | ||
599 | if (ASIC_IS_DCE5(rdev)) { | 588 | if (ASIC_IS_DCE5(rdev)) { |
600 | /* TODO */ | 589 | /* TODO */ |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 138b95216d8d..566ca3b3c873 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -560,6 +560,7 @@ struct radeon_unpin_work { | |||
560 | 560 | ||
561 | struct r500_irq_stat_regs { | 561 | struct r500_irq_stat_regs { |
562 | u32 disp_int; | 562 | u32 disp_int; |
563 | u32 hdmi0_status; | ||
563 | }; | 564 | }; |
564 | 565 | ||
565 | struct r600_irq_stat_regs { | 566 | struct r600_irq_stat_regs { |
@@ -568,6 +569,8 @@ struct r600_irq_stat_regs { | |||
568 | u32 disp_int_cont2; | 569 | u32 disp_int_cont2; |
569 | u32 d1grph_int; | 570 | u32 d1grph_int; |
570 | u32 d2grph_int; | 571 | u32 d2grph_int; |
572 | u32 hdmi0_status; | ||
573 | u32 hdmi1_status; | ||
571 | }; | 574 | }; |
572 | 575 | ||
573 | struct evergreen_irq_stat_regs { | 576 | struct evergreen_irq_stat_regs { |
@@ -583,6 +586,12 @@ struct evergreen_irq_stat_regs { | |||
583 | u32 d4grph_int; | 586 | u32 d4grph_int; |
584 | u32 d5grph_int; | 587 | u32 d5grph_int; |
585 | u32 d6grph_int; | 588 | u32 d6grph_int; |
589 | u32 afmt_status1; | ||
590 | u32 afmt_status2; | ||
591 | u32 afmt_status3; | ||
592 | u32 afmt_status4; | ||
593 | u32 afmt_status5; | ||
594 | u32 afmt_status6; | ||
586 | }; | 595 | }; |
587 | 596 | ||
588 | union radeon_irq_stat_regs { | 597 | union radeon_irq_stat_regs { |
@@ -593,7 +602,7 @@ union radeon_irq_stat_regs { | |||
593 | 602 | ||
594 | #define RADEON_MAX_HPD_PINS 6 | 603 | #define RADEON_MAX_HPD_PINS 6 |
595 | #define RADEON_MAX_CRTCS 6 | 604 | #define RADEON_MAX_CRTCS 6 |
596 | #define RADEON_MAX_HDMI_BLOCKS 2 | 605 | #define RADEON_MAX_AFMT_BLOCKS 6 |
597 | 606 | ||
598 | struct radeon_irq { | 607 | struct radeon_irq { |
599 | bool installed; | 608 | bool installed; |
@@ -605,7 +614,7 @@ struct radeon_irq { | |||
605 | bool gui_idle; | 614 | bool gui_idle; |
606 | bool gui_idle_acked; | 615 | bool gui_idle_acked; |
607 | wait_queue_head_t idle_queue; | 616 | wait_queue_head_t idle_queue; |
608 | bool hdmi[RADEON_MAX_HDMI_BLOCKS]; | 617 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
609 | spinlock_t sw_lock; | 618 | spinlock_t sw_lock; |
610 | int sw_refcount[RADEON_NUM_RINGS]; | 619 | int sw_refcount[RADEON_NUM_RINGS]; |
611 | union radeon_irq_stat_regs stat_regs; | 620 | union radeon_irq_stat_regs stat_regs; |
@@ -1546,13 +1555,13 @@ struct radeon_device { | |||
1546 | struct r600_ih ih; /* r6/700 interrupt ring */ | 1555 | struct r600_ih ih; /* r6/700 interrupt ring */ |
1547 | struct si_rlc rlc; | 1556 | struct si_rlc rlc; |
1548 | struct work_struct hotplug_work; | 1557 | struct work_struct hotplug_work; |
1558 | struct work_struct audio_work; | ||
1549 | int num_crtc; /* number of crtcs */ | 1559 | int num_crtc; /* number of crtcs */ |
1550 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ | 1560 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
1551 | struct mutex vram_mutex; | 1561 | struct mutex vram_mutex; |
1552 | 1562 | ||
1553 | /* audio stuff */ | 1563 | /* audio stuff */ |
1554 | bool audio_enabled; | 1564 | bool audio_enabled; |
1555 | struct timer_list audio_timer; | ||
1556 | int audio_channels; | 1565 | int audio_channels; |
1557 | int audio_rate; | 1566 | int audio_rate; |
1558 | int audio_bits_per_sample; | 1567 | int audio_bits_per_sample; |
@@ -1828,6 +1837,8 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev, | |||
1828 | struct radeon_vm *vm, | 1837 | struct radeon_vm *vm, |
1829 | struct radeon_bo *bo); | 1838 | struct radeon_bo *bo); |
1830 | 1839 | ||
1840 | /* audio */ | ||
1841 | void r600_audio_update_hdmi(struct work_struct *work); | ||
1831 | 1842 | ||
1832 | /* | 1843 | /* |
1833 | * R600 vram scratch functions | 1844 | * R600 vram scratch functions |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 3d9f9f1d8f90..b135bec649d1 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h | |||
@@ -369,9 +369,6 @@ int r600_audio_bits_per_sample(struct radeon_device *rdev); | |||
369 | int r600_audio_rate(struct radeon_device *rdev); | 369 | int r600_audio_rate(struct radeon_device *rdev); |
370 | uint8_t r600_audio_status_bits(struct radeon_device *rdev); | 370 | uint8_t r600_audio_status_bits(struct radeon_device *rdev); |
371 | uint8_t r600_audio_category_code(struct radeon_device *rdev); | 371 | uint8_t r600_audio_category_code(struct radeon_device *rdev); |
372 | void r600_audio_schedule_polling(struct radeon_device *rdev); | ||
373 | void r600_audio_enable_polling(struct drm_encoder *encoder); | ||
374 | void r600_audio_disable_polling(struct drm_encoder *encoder); | ||
375 | void r600_audio_fini(struct radeon_device *rdev); | 372 | void r600_audio_fini(struct radeon_device *rdev); |
376 | void r600_hdmi_init(struct drm_encoder *encoder); | 373 | void r600_hdmi_init(struct drm_encoder *encoder); |
377 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); | 374 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); |
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index 66d5fe1c8174..170f1718d92a 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c | |||
@@ -73,6 +73,7 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev) | |||
73 | for (i = 0; i < RADEON_MAX_CRTCS; i++) { | 73 | for (i = 0; i < RADEON_MAX_CRTCS; i++) { |
74 | rdev->irq.crtc_vblank_int[i] = false; | 74 | rdev->irq.crtc_vblank_int[i] = false; |
75 | rdev->irq.pflip[i] = false; | 75 | rdev->irq.pflip[i] = false; |
76 | rdev->irq.afmt[i] = false; | ||
76 | } | 77 | } |
77 | radeon_irq_set(rdev); | 78 | radeon_irq_set(rdev); |
78 | /* Clear bits */ | 79 | /* Clear bits */ |
@@ -108,6 +109,7 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev) | |||
108 | for (i = 0; i < RADEON_MAX_CRTCS; i++) { | 109 | for (i = 0; i < RADEON_MAX_CRTCS; i++) { |
109 | rdev->irq.crtc_vblank_int[i] = false; | 110 | rdev->irq.crtc_vblank_int[i] = false; |
110 | rdev->irq.pflip[i] = false; | 111 | rdev->irq.pflip[i] = false; |
112 | rdev->irq.afmt[i] = false; | ||
111 | } | 113 | } |
112 | radeon_irq_set(rdev); | 114 | radeon_irq_set(rdev); |
113 | } | 115 | } |
@@ -164,6 +166,7 @@ int radeon_irq_kms_init(struct radeon_device *rdev) | |||
164 | int r = 0; | 166 | int r = 0; |
165 | 167 | ||
166 | INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func); | 168 | INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func); |
169 | INIT_WORK(&rdev->audio_work, r600_audio_update_hdmi); | ||
167 | 170 | ||
168 | spin_lock_init(&rdev->irq.sw_lock); | 171 | spin_lock_init(&rdev->irq.sw_lock); |
169 | for (i = 0; i < rdev->num_crtc; i++) | 172 | for (i = 0; i < rdev->num_crtc; i++) |
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index d25cf869d08d..10706c66b84b 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -553,6 +553,12 @@ int rs600_irq_set(struct radeon_device *rdev) | |||
553 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); | 553 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
554 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & | 554 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
555 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); | 555 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
556 | u32 hdmi0; | ||
557 | if (ASIC_IS_DCE2(rdev)) | ||
558 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & | ||
559 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); | ||
560 | else | ||
561 | hdmi0 = 0; | ||
556 | 562 | ||
557 | if (!rdev->irq.installed) { | 563 | if (!rdev->irq.installed) { |
558 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); | 564 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
@@ -579,10 +585,15 @@ int rs600_irq_set(struct radeon_device *rdev) | |||
579 | if (rdev->irq.hpd[1]) { | 585 | if (rdev->irq.hpd[1]) { |
580 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); | 586 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
581 | } | 587 | } |
588 | if (rdev->irq.afmt[0]) { | ||
589 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); | ||
590 | } | ||
582 | WREG32(R_000040_GEN_INT_CNTL, tmp); | 591 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
583 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); | 592 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
584 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); | 593 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
585 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); | 594 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
595 | if (ASIC_IS_DCE2(rdev)) | ||
596 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); | ||
586 | return 0; | 597 | return 0; |
587 | } | 598 | } |
588 | 599 | ||
@@ -622,6 +633,17 @@ static inline u32 rs600_irq_ack(struct radeon_device *rdev) | |||
622 | rdev->irq.stat_regs.r500.disp_int = 0; | 633 | rdev->irq.stat_regs.r500.disp_int = 0; |
623 | } | 634 | } |
624 | 635 | ||
636 | if (ASIC_IS_DCE2(rdev)) { | ||
637 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & | ||
638 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); | ||
639 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { | ||
640 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); | ||
641 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); | ||
642 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); | ||
643 | } | ||
644 | } else | ||
645 | rdev->irq.stat_regs.r500.hdmi0_status = 0; | ||
646 | |||
625 | if (irqs) { | 647 | if (irqs) { |
626 | WREG32(R_000044_GEN_INT_STATUS, irqs); | 648 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
627 | } | 649 | } |
@@ -630,6 +652,9 @@ static inline u32 rs600_irq_ack(struct radeon_device *rdev) | |||
630 | 652 | ||
631 | void rs600_irq_disable(struct radeon_device *rdev) | 653 | void rs600_irq_disable(struct radeon_device *rdev) |
632 | { | 654 | { |
655 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & | ||
656 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); | ||
657 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); | ||
633 | WREG32(R_000040_GEN_INT_CNTL, 0); | 658 | WREG32(R_000040_GEN_INT_CNTL, 0); |
634 | WREG32(R_006540_DxMODE_INT_MASK, 0); | 659 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
635 | /* Wait and acknowledge irq */ | 660 | /* Wait and acknowledge irq */ |
@@ -641,15 +666,20 @@ int rs600_irq_process(struct radeon_device *rdev) | |||
641 | { | 666 | { |
642 | u32 status, msi_rearm; | 667 | u32 status, msi_rearm; |
643 | bool queue_hotplug = false; | 668 | bool queue_hotplug = false; |
669 | bool queue_hdmi = false; | ||
644 | 670 | ||
645 | /* reset gui idle ack. the status bit is broken */ | 671 | /* reset gui idle ack. the status bit is broken */ |
646 | rdev->irq.gui_idle_acked = false; | 672 | rdev->irq.gui_idle_acked = false; |
647 | 673 | ||
648 | status = rs600_irq_ack(rdev); | 674 | status = rs600_irq_ack(rdev); |
649 | if (!status && !rdev->irq.stat_regs.r500.disp_int) { | 675 | if (!status && |
676 | !rdev->irq.stat_regs.r500.disp_int && | ||
677 | !rdev->irq.stat_regs.r500.hdmi0_status) { | ||
650 | return IRQ_NONE; | 678 | return IRQ_NONE; |
651 | } | 679 | } |
652 | while (status || rdev->irq.stat_regs.r500.disp_int) { | 680 | while (status || |
681 | rdev->irq.stat_regs.r500.disp_int || | ||
682 | rdev->irq.stat_regs.r500.hdmi0_status) { | ||
653 | /* SW interrupt */ | 683 | /* SW interrupt */ |
654 | if (G_000044_SW_INT(status)) { | 684 | if (G_000044_SW_INT(status)) { |
655 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); | 685 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
@@ -687,12 +717,18 @@ int rs600_irq_process(struct radeon_device *rdev) | |||
687 | queue_hotplug = true; | 717 | queue_hotplug = true; |
688 | DRM_DEBUG("HPD2\n"); | 718 | DRM_DEBUG("HPD2\n"); |
689 | } | 719 | } |
720 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { | ||
721 | queue_hdmi = true; | ||
722 | DRM_DEBUG("HDMI0\n"); | ||
723 | } | ||
690 | status = rs600_irq_ack(rdev); | 724 | status = rs600_irq_ack(rdev); |
691 | } | 725 | } |
692 | /* reset gui idle ack. the status bit is broken */ | 726 | /* reset gui idle ack. the status bit is broken */ |
693 | rdev->irq.gui_idle_acked = false; | 727 | rdev->irq.gui_idle_acked = false; |
694 | if (queue_hotplug) | 728 | if (queue_hotplug) |
695 | schedule_work(&rdev->hotplug_work); | 729 | schedule_work(&rdev->hotplug_work); |
730 | if (queue_hdmi) | ||
731 | schedule_work(&rdev->audio_work); | ||
696 | if (rdev->msi_enabled) { | 732 | if (rdev->msi_enabled) { |
697 | switch (rdev->family) { | 733 | switch (rdev->family) { |
698 | case CHIP_RS600: | 734 | case CHIP_RS600: |