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authorBruce Allan <bruce.w.allan@intel.com>2010-05-10 11:02:32 -0400
committerDavid S. Miller <davem@davemloft.net>2010-05-13 02:31:14 -0400
commite98cac447cc1cc418dff1d610a5c79c4f2bdec7f (patch)
treefbb290c330f7ffdbb574132460f18f9261cacba9
parenta305595b127fdbe7ab5ba458f7ee470a82a3b82c (diff)
e1000e: Fix/cleanup PHY reset code for ICHx/PCHx
i) Fixes a bug where e1000_sw_lcd_config_ich8lan() was calling e1000_lan_init_done_ich8lan() to poll the STATUS.LAN_INIT_DONE bit to make sure the MAC had completed the PHY configuration. However, e1000_lan_init_done_ich8lan() had already been called in one of the two places where PHY reset occurs for ICHx/PCHx parts, which caused the second call to busy-wait for 150 msec because the LAN_INIT_DONE bit had already been checked and cleared. ii) Cleanup the two separate PHY reset code paths, i.e. the full-chip reset in e1000_reset_hw_ich8lan() and the PHY-only reset in e1000_phy_hw_reset_ich8lan(). There was duplicate code in both paths to be performed post-reset that are now combined into one new function - e1000_post_phy_reset_ich8lan(). This cleanup also included moving the clearing of the PHY Reset Asserted bit in the STATUS register (now done for all ICH/PCH parts) and the check for the indication from h/w that basic configuration has completed back to where it previously was in e1000_get_cfg_done_ich8lan(). iii) Corrected a few comments Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/e1000e/ich8lan.c149
1 files changed, 75 insertions, 74 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 2b2cffc017be..10360fb596aa 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -850,9 +850,6 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
850 if (!(data & sw_cfg_mask)) 850 if (!(data & sw_cfg_mask))
851 goto out; 851 goto out;
852 852
853 /* Wait for basic configuration completes before proceeding */
854 e1000_lan_init_done_ich8lan(hw);
855
856 /* 853 /*
857 * Make sure HW does not configure LCD from PHY 854 * Make sure HW does not configure LCD from PHY
858 * extended configuration before SW configuration 855 * extended configuration before SW configuration
@@ -1260,30 +1257,26 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1260} 1257}
1261 1258
1262/** 1259/**
1263 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 1260 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1264 * @hw: pointer to the HW structure 1261 * @hw: pointer to the HW structure
1265 *
1266 * Resets the PHY
1267 * This is a function pointer entry point called by drivers
1268 * or other shared routines.
1269 **/ 1262 **/
1270static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 1263static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1271{ 1264{
1272 s32 ret_val = 0; 1265 s32 ret_val = 0;
1273 u16 reg; 1266 u16 reg;
1274 1267
1275 ret_val = e1000e_phy_hw_reset_generic(hw); 1268 if (e1000_check_reset_block(hw))
1276 if (ret_val) 1269 goto out;
1277 return ret_val;
1278
1279 /* Allow time for h/w to get to a quiescent state after reset */
1280 mdelay(10);
1281 1270
1282 /* Perform any necessary post-reset workarounds */ 1271 /* Perform any necessary post-reset workarounds */
1283 if (hw->mac.type == e1000_pchlan) { 1272 switch (hw->mac.type) {
1273 case e1000_pchlan:
1284 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 1274 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1285 if (ret_val) 1275 if (ret_val)
1286 return ret_val; 1276 goto out;
1277 break;
1278 default:
1279 break;
1287 } 1280 }
1288 1281
1289 /* Dummy read to clear the phy wakeup bit after lcd reset */ 1282 /* Dummy read to clear the phy wakeup bit after lcd reset */
@@ -1296,11 +1289,32 @@ static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1296 goto out; 1289 goto out;
1297 1290
1298 /* Configure the LCD with the OEM bits in NVM */ 1291 /* Configure the LCD with the OEM bits in NVM */
1299 if (hw->mac.type == e1000_pchlan) 1292 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1300 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1301 1293
1302out: 1294out:
1303 return 0; 1295 return ret_val;
1296}
1297
1298/**
1299 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1300 * @hw: pointer to the HW structure
1301 *
1302 * Resets the PHY
1303 * This is a function pointer entry point called by drivers
1304 * or other shared routines.
1305 **/
1306static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1307{
1308 s32 ret_val = 0;
1309
1310 ret_val = e1000e_phy_hw_reset_generic(hw);
1311 if (ret_val)
1312 goto out;
1313
1314 ret_val = e1000_post_phy_reset_ich8lan(hw);
1315
1316out:
1317 return ret_val;
1304} 1318}
1305 1319
1306/** 1320/**
@@ -2511,9 +2525,8 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2511 * on the last TLP read/write transaction when MAC is reset. 2525 * on the last TLP read/write transaction when MAC is reset.
2512 */ 2526 */
2513 ret_val = e1000e_disable_pcie_master(hw); 2527 ret_val = e1000e_disable_pcie_master(hw);
2514 if (ret_val) { 2528 if (ret_val)
2515 e_dbg("PCI-E Master disable polling has failed.\n"); 2529 e_dbg("PCI-E Master disable polling has failed.\n");
2516 }
2517 2530
2518 e_dbg("Masking off all interrupts\n"); 2531 e_dbg("Masking off all interrupts\n");
2519 ew32(IMC, 0xffffffff); 2532 ew32(IMC, 0xffffffff);
@@ -2552,14 +2565,8 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2552 ctrl = er32(CTRL); 2565 ctrl = er32(CTRL);
2553 2566
2554 if (!e1000_check_reset_block(hw)) { 2567 if (!e1000_check_reset_block(hw)) {
2555 /* Clear PHY Reset Asserted bit */
2556 if (hw->mac.type >= e1000_pchlan) {
2557 u32 status = er32(STATUS);
2558 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
2559 }
2560
2561 /* 2568 /*
2562 * PHY HW reset requires MAC CORE reset at the same 2569 * Full-chip reset requires MAC and PHY reset at the same
2563 * time to make sure the interface between MAC and the 2570 * time to make sure the interface between MAC and the
2564 * external PHY is reset. 2571 * external PHY is reset.
2565 */ 2572 */
@@ -2573,39 +2580,16 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2573 if (!ret_val) 2580 if (!ret_val)
2574 e1000_release_swflag_ich8lan(hw); 2581 e1000_release_swflag_ich8lan(hw);
2575 2582
2576 /* Perform any necessary post-reset workarounds */ 2583 if (ctrl & E1000_CTRL_PHY_RST) {
2577 if (hw->mac.type == e1000_pchlan)
2578 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2579
2580 if (ctrl & E1000_CTRL_PHY_RST)
2581 ret_val = hw->phy.ops.get_cfg_done(hw); 2584 ret_val = hw->phy.ops.get_cfg_done(hw);
2585 if (ret_val)
2586 goto out;
2582 2587
2583 if (hw->mac.type >= e1000_ich10lan) { 2588 ret_val = e1000_post_phy_reset_ich8lan(hw);
2584 e1000_lan_init_done_ich8lan(hw);
2585 } else {
2586 ret_val = e1000e_get_auto_rd_done(hw);
2587 if (ret_val) {
2588 /*
2589 * When auto config read does not complete, do not
2590 * return with an error. This can happen in situations
2591 * where there is no eeprom and prevents getting link.
2592 */
2593 e_dbg("Auto Read Done did not complete\n");
2594 }
2595 }
2596 /* Dummy read to clear the phy wakeup bit after lcd reset */
2597 if (hw->mac.type == e1000_pchlan)
2598 e1e_rphy(hw, BM_WUC, &reg);
2599
2600 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2601 if (ret_val)
2602 goto out;
2603
2604 if (hw->mac.type == e1000_pchlan) {
2605 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2606 if (ret_val) 2589 if (ret_val)
2607 goto out; 2590 goto out;
2608 } 2591 }
2592
2609 /* 2593 /*
2610 * For PCH, this write will make sure that any noise 2594 * For PCH, this write will make sure that any noise
2611 * will be detected as a CRC error and be dropped rather than show up 2595 * will be detected as a CRC error and be dropped rather than show up
@@ -3291,33 +3275,50 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3291} 3275}
3292 3276
3293/** 3277/**
3294 * e1000_get_cfg_done_ich8lan - Read config done bit 3278 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3295 * @hw: pointer to the HW structure 3279 * @hw: pointer to the HW structure
3296 * 3280 *
3297 * Read the management control register for the config done bit for 3281 * Read appropriate register for the config done bit for completion status
3298 * completion status. NOTE: silicon which is EEPROM-less will fail trying 3282 * and configure the PHY through s/w for EEPROM-less parts.
3299 * to read the config done bit, so an error is *ONLY* logged and returns 3283 *
3300 * 0. If we were to return with error, EEPROM-less silicon 3284 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3301 * would not be able to be reset or change link. 3285 * config done bit, so only an error is logged and continues. If we were
3286 * to return with error, EEPROM-less silicon would not be able to be reset
3287 * or change link.
3302 **/ 3288 **/
3303static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 3289static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3304{ 3290{
3291 s32 ret_val = 0;
3305 u32 bank = 0; 3292 u32 bank = 0;
3293 u32 status;
3306 3294
3307 if (hw->mac.type >= e1000_pchlan) { 3295 e1000e_get_cfg_done(hw);
3308 u32 status = er32(STATUS);
3309 3296
3310 if (status & E1000_STATUS_PHYRA) 3297 /* Wait for indication from h/w that it has completed basic config */
3311 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 3298 if (hw->mac.type >= e1000_ich10lan) {
3312 else 3299 e1000_lan_init_done_ich8lan(hw);
3313 e_dbg("PHY Reset Asserted not set - needs delay\n"); 3300 } else {
3301 ret_val = e1000e_get_auto_rd_done(hw);
3302 if (ret_val) {
3303 /*
3304 * When auto config read does not complete, do not
3305 * return with an error. This can happen in situations
3306 * where there is no eeprom and prevents getting link.
3307 */
3308 e_dbg("Auto Read Done did not complete\n");
3309 ret_val = 0;
3310 }
3314 } 3311 }
3315 3312
3316 e1000e_get_cfg_done(hw); 3313 /* Clear PHY Reset Asserted bit */
3314 status = er32(STATUS);
3315 if (status & E1000_STATUS_PHYRA)
3316 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3317 else
3318 e_dbg("PHY Reset Asserted not set - needs delay\n");
3317 3319
3318 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 3320 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3319 if ((hw->mac.type != e1000_ich10lan) && 3321 if (hw->mac.type <= e1000_ich9lan) {
3320 (hw->mac.type != e1000_pchlan)) {
3321 if (((er32(EECD) & E1000_EECD_PRES) == 0) && 3322 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3322 (hw->phy.type == e1000_phy_igp_3)) { 3323 (hw->phy.type == e1000_phy_igp_3)) {
3323 e1000e_phy_init_script_igp3(hw); 3324 e1000e_phy_init_script_igp3(hw);
@@ -3326,11 +3327,11 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3326 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 3327 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3327 /* Maybe we should do a basic PHY config */ 3328 /* Maybe we should do a basic PHY config */
3328 e_dbg("EEPROM not present\n"); 3329 e_dbg("EEPROM not present\n");
3329 return -E1000_ERR_CONFIG; 3330 ret_val = -E1000_ERR_CONFIG;
3330 } 3331 }
3331 } 3332 }
3332 3333
3333 return 0; 3334 return ret_val;
3334} 3335}
3335 3336
3336/** 3337/**