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authorGabor Juhos <juhosg@openwrt.org>2013-04-05 02:27:04 -0400
committerJohn W. Linville <linville@tuxdriver.com>2013-04-10 14:10:32 -0400
commitb9570b66876039620aa36de4eab57f16443e1e18 (patch)
treed12c7945a3808a74e708455e7b7e3e9056b3eb5f
parent1d6205d0da456065a90d16017fd279d86bf33731 (diff)
rt2x00: rt2800pci: use the rt2x00mmio_* routines
Use the recently introduced rt2x00mmio_* routines instead of the rt2x00pci_* variants. The patch contains no functional changes. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Helmut Schaa <helmut.schaa@googlemail.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c241
1 files changed, 123 insertions, 118 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 565a80d0e564..def357eb0586 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -72,7 +72,7 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
72 return; 72 return;
73 73
74 for (i = 0; i < 200; i++) { 74 for (i = 0; i < 200; i++) {
75 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); 75 rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
76 76
77 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || 77 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || 78 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
@@ -86,8 +86,8 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
86 if (i == 200) 86 if (i == 200)
87 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n"); 87 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
88 88
89 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 89 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
90 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 90 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
91} 91}
92 92
93#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X) 93#if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
@@ -116,7 +116,7 @@ static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
116 struct rt2x00_dev *rt2x00dev = eeprom->data; 116 struct rt2x00_dev *rt2x00dev = eeprom->data;
117 u32 reg; 117 u32 reg;
118 118
119 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 119 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
120 120
121 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 121 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
122 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 122 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
@@ -138,7 +138,7 @@ static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
138 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT, 138 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
139 !!eeprom->reg_chip_select); 139 !!eeprom->reg_chip_select);
140 140
141 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); 141 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
142} 142}
143 143
144static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) 144static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
@@ -146,7 +146,7 @@ static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
146 struct eeprom_93cx6 eeprom; 146 struct eeprom_93cx6 eeprom;
147 u32 reg; 147 u32 reg;
148 148
149 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 149 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, &reg);
150 150
151 eeprom.data = rt2x00dev; 151 eeprom.data = rt2x00dev;
152 eeprom.register_read = rt2800pci_eepromregister_read; 152 eeprom.register_read = rt2800pci_eepromregister_read;
@@ -210,20 +210,20 @@ static void rt2800pci_start_queue(struct data_queue *queue)
210 210
211 switch (queue->qid) { 211 switch (queue->qid) {
212 case QID_RX: 212 case QID_RX:
213 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 213 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
214 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); 214 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
215 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 215 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
216 break; 216 break;
217 case QID_BEACON: 217 case QID_BEACON:
218 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 218 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
219 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 219 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
220 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 220 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
221 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 221 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
222 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 222 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
223 223
224 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg); 224 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
225 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1); 225 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
226 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg); 226 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
227 break; 227 break;
228 default: 228 default:
229 break; 229 break;
@@ -241,13 +241,13 @@ static void rt2800pci_kick_queue(struct data_queue *queue)
241 case QID_AC_BE: 241 case QID_AC_BE:
242 case QID_AC_BK: 242 case QID_AC_BK:
243 entry = rt2x00queue_get_entry(queue, Q_INDEX); 243 entry = rt2x00queue_get_entry(queue, Q_INDEX);
244 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), 244 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
245 entry->entry_idx); 245 entry->entry_idx);
246 break; 246 break;
247 case QID_MGMT: 247 case QID_MGMT:
248 entry = rt2x00queue_get_entry(queue, Q_INDEX); 248 entry = rt2x00queue_get_entry(queue, Q_INDEX);
249 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5), 249 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX(5),
250 entry->entry_idx); 250 entry->entry_idx);
251 break; 251 break;
252 default: 252 default:
253 break; 253 break;
@@ -261,20 +261,20 @@ static void rt2800pci_stop_queue(struct data_queue *queue)
261 261
262 switch (queue->qid) { 262 switch (queue->qid) {
263 case QID_RX: 263 case QID_RX:
264 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 264 rt2x00mmio_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
265 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); 265 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
266 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 266 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
267 break; 267 break;
268 case QID_BEACON: 268 case QID_BEACON:
269 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 269 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
270 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0); 270 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
271 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0); 271 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
272 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 272 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
273 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 273 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
274 274
275 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg); 275 rt2x00mmio_register_read(rt2x00dev, INT_TIMER_EN, &reg);
276 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0); 276 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
277 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg); 277 rt2x00mmio_register_write(rt2x00dev, INT_TIMER_EN, reg);
278 278
279 /* 279 /*
280 * Wait for current invocation to finish. The tasklet 280 * Wait for current invocation to finish. The tasklet
@@ -314,19 +314,19 @@ static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
314 */ 314 */
315 reg = 0; 315 reg = 0;
316 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); 316 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
317 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg); 317 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
318 318
319 /* 319 /*
320 * Write firmware to device. 320 * Write firmware to device.
321 */ 321 */
322 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 322 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
323 data, len); 323 data, len);
324 324
325 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); 325 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
326 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); 326 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
327 327
328 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 328 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
329 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 329 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
330 330
331 return 0; 331 return 0;
332} 332}
@@ -336,7 +336,7 @@ static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
336 */ 336 */
337static bool rt2800pci_get_entry_state(struct queue_entry *entry) 337static bool rt2800pci_get_entry_state(struct queue_entry *entry)
338{ 338{
339 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 339 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
340 u32 word; 340 u32 word;
341 341
342 if (entry->queue->qid == QID_RX) { 342 if (entry->queue->qid == QID_RX) {
@@ -352,7 +352,7 @@ static bool rt2800pci_get_entry_state(struct queue_entry *entry)
352 352
353static void rt2800pci_clear_entry(struct queue_entry *entry) 353static void rt2800pci_clear_entry(struct queue_entry *entry)
354{ 354{
355 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 355 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
356 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 356 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
357 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 357 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
358 u32 word; 358 u32 word;
@@ -370,8 +370,8 @@ static void rt2800pci_clear_entry(struct queue_entry *entry)
370 * Set RX IDX in register to inform hardware that we have 370 * Set RX IDX in register to inform hardware that we have
371 * handled this entry and it is available for reuse again. 371 * handled this entry and it is available for reuse again.
372 */ 372 */
373 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 373 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
374 entry->entry_idx); 374 entry->entry_idx);
375 } else { 375 } else {
376 rt2x00_desc_read(entry_priv->desc, 1, &word); 376 rt2x00_desc_read(entry_priv->desc, 1, &word);
377 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1); 377 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
@@ -381,60 +381,65 @@ static void rt2800pci_clear_entry(struct queue_entry *entry)
381 381
382static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev) 382static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
383{ 383{
384 struct queue_entry_priv_pci *entry_priv; 384 struct queue_entry_priv_mmio *entry_priv;
385 385
386 /* 386 /*
387 * Initialize registers. 387 * Initialize registers.
388 */ 388 */
389 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 389 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
390 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma); 390 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
391 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, 391 entry_priv->desc_dma);
392 rt2x00dev->tx[0].limit); 392 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
393 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0); 393 rt2x00dev->tx[0].limit);
394 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0); 394 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
395 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
395 396
396 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 397 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
397 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma); 398 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
398 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, 399 entry_priv->desc_dma);
399 rt2x00dev->tx[1].limit); 400 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
400 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0); 401 rt2x00dev->tx[1].limit);
401 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0); 402 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
403 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
402 404
403 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 405 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
404 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma); 406 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
405 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, 407 entry_priv->desc_dma);
406 rt2x00dev->tx[2].limit); 408 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
407 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0); 409 rt2x00dev->tx[2].limit);
408 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0); 410 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
411 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
409 412
410 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 413 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
411 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma); 414 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
412 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, 415 entry_priv->desc_dma);
413 rt2x00dev->tx[3].limit); 416 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
414 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0); 417 rt2x00dev->tx[3].limit);
415 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0); 418 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
416 419 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
417 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0); 420
418 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0); 421 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
419 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0); 422 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
420 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0); 423 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
421 424 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
422 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0); 425
423 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0); 426 rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
424 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0); 427 rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
425 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0); 428 rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
429 rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
426 430
427 entry_priv = rt2x00dev->rx->entries[0].priv_data; 431 entry_priv = rt2x00dev->rx->entries[0].priv_data;
428 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma); 432 rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
429 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, 433 entry_priv->desc_dma);
430 rt2x00dev->rx[0].limit); 434 rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
431 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 435 rt2x00dev->rx[0].limit);
432 rt2x00dev->rx[0].limit - 1); 436 rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
433 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0); 437 rt2x00dev->rx[0].limit - 1);
438 rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
434 439
435 rt2800_disable_wpdma(rt2x00dev); 440 rt2800_disable_wpdma(rt2x00dev);
436 441
437 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0); 442 rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
438 443
439 return 0; 444 return 0;
440} 445}
@@ -453,8 +458,8 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
453 * should clear the register to assure a clean state. 458 * should clear the register to assure a clean state.
454 */ 459 */
455 if (state == STATE_RADIO_IRQ_ON) { 460 if (state == STATE_RADIO_IRQ_ON) {
456 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 461 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
457 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 462 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
458 } 463 }
459 464
460 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); 465 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
@@ -466,7 +471,7 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
466 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1); 471 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
467 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1); 472 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
468 } 473 }
469 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 474 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
470 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); 475 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
471 476
472 if (state == STATE_RADIO_IRQ_OFF) { 477 if (state == STATE_RADIO_IRQ_OFF) {
@@ -488,7 +493,7 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
488 /* 493 /*
489 * Reset DMA indexes 494 * Reset DMA indexes
490 */ 495 */
491 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 496 rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
492 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 497 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
493 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 498 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
494 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 499 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -496,29 +501,29 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
496 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 501 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
497 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 502 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
498 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 503 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
499 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 504 rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
500 505
501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 506 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
502 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 507 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
503 508
504 if (rt2x00_is_pcie(rt2x00dev) && 509 if (rt2x00_is_pcie(rt2x00dev) &&
505 (rt2x00_rt(rt2x00dev, RT3572) || 510 (rt2x00_rt(rt2x00dev, RT3572) ||
506 rt2x00_rt(rt2x00dev, RT5390) || 511 rt2x00_rt(rt2x00dev, RT5390) ||
507 rt2x00_rt(rt2x00dev, RT5392))) { 512 rt2x00_rt(rt2x00dev, RT5392))) {
508 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg); 513 rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, &reg);
509 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1); 514 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
510 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1); 515 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
511 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg); 516 rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
512 } 517 }
513 518
514 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 519 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
515 520
516 reg = 0; 521 reg = 0;
517 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 522 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
518 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1); 523 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
519 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 524 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
520 525
521 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 526 rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
522 527
523 return 0; 528 return 0;
524} 529}
@@ -538,8 +543,8 @@ static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
538 return retval; 543 return retval;
539 544
540 /* After resume MCU_BOOT_SIGNAL will trash these. */ 545 /* After resume MCU_BOOT_SIGNAL will trash these. */
541 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 546 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
542 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 547 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
543 548
544 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02); 549 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
545 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF); 550 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
@@ -554,8 +559,8 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
554{ 559{
555 if (rt2x00_is_soc(rt2x00dev)) { 560 if (rt2x00_is_soc(rt2x00dev)) {
556 rt2800_disable_radio(rt2x00dev); 561 rt2800_disable_radio(rt2x00dev);
557 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0); 562 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0);
558 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0); 563 rt2x00mmio_register_write(rt2x00dev, TX_PIN_CFG, 0);
559 } 564 }
560} 565}
561 566
@@ -567,10 +572,10 @@ static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
567 0, 0x02); 572 0, 0x02);
568 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP); 573 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
569 } else if (state == STATE_SLEEP) { 574 } else if (state == STATE_SLEEP) {
570 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 575 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
571 0xffffffff); 576 0xffffffff);
572 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, 577 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
573 0xffffffff); 578 0xffffffff);
574 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP, 579 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
575 0xff, 0x01); 580 0xff, 0x01);
576 } 581 }
@@ -629,7 +634,7 @@ static void rt2800pci_write_tx_desc(struct queue_entry *entry,
629 struct txentry_desc *txdesc) 634 struct txentry_desc *txdesc)
630{ 635{
631 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 636 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
632 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 637 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
633 __le32 *txd = entry_priv->desc; 638 __le32 *txd = entry_priv->desc;
634 u32 word; 639 u32 word;
635 640
@@ -683,7 +688,7 @@ static void rt2800pci_write_tx_desc(struct queue_entry *entry,
683static void rt2800pci_fill_rxdone(struct queue_entry *entry, 688static void rt2800pci_fill_rxdone(struct queue_entry *entry,
684 struct rxdone_entry_desc *rxdesc) 689 struct rxdone_entry_desc *rxdesc)
685{ 690{
686 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 691 struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
687 __le32 *rxd = entry_priv->desc; 692 __le32 *rxd = entry_priv->desc;
688 u32 word; 693 u32 word;
689 694
@@ -914,9 +919,9 @@ static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
914 * access needs locking. 919 * access needs locking.
915 */ 920 */
916 spin_lock_irq(&rt2x00dev->irqmask_lock); 921 spin_lock_irq(&rt2x00dev->irqmask_lock);
917 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 922 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
918 rt2x00_set_field32(&reg, irq_field, 1); 923 rt2x00_set_field32(&reg, irq_field, 1);
919 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 924 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
920 spin_unlock_irq(&rt2x00dev->irqmask_lock); 925 spin_unlock_irq(&rt2x00dev->irqmask_lock);
921} 926}
922 927
@@ -957,15 +962,15 @@ static void rt2800pci_tbtt_tasklet(unsigned long data)
957 * interval every 64 beacons by 64us to mitigate this effect. 962 * interval every 64 beacons by 64us to mitigate this effect.
958 */ 963 */
959 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) { 964 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
960 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 965 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
961 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 966 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
962 (rt2x00dev->beacon_int * 16) - 1); 967 (rt2x00dev->beacon_int * 16) - 1);
963 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 968 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
964 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) { 969 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
965 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 970 rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
966 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 971 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
967 (rt2x00dev->beacon_int * 16)); 972 (rt2x00dev->beacon_int * 16));
968 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 973 rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
969 } 974 }
970 drv_data->tbtt_tick++; 975 drv_data->tbtt_tick++;
971 drv_data->tbtt_tick %= BCN_TBTT_OFFSET; 976 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
@@ -978,7 +983,7 @@ static void rt2800pci_tbtt_tasklet(unsigned long data)
978static void rt2800pci_rxdone_tasklet(unsigned long data) 983static void rt2800pci_rxdone_tasklet(unsigned long data)
979{ 984{
980 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; 985 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
981 if (rt2x00pci_rxdone(rt2x00dev)) 986 if (rt2x00mmio_rxdone(rt2x00dev))
982 tasklet_schedule(&rt2x00dev->rxdone_tasklet); 987 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
983 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 988 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
984 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE); 989 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
@@ -1016,7 +1021,7 @@ static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
1016 * need to lock the kfifo. 1021 * need to lock the kfifo.
1017 */ 1022 */
1018 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) { 1023 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
1019 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status); 1024 rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO, &status);
1020 1025
1021 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID)) 1026 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
1022 break; 1027 break;
@@ -1038,8 +1043,8 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1038 u32 reg, mask; 1043 u32 reg, mask;
1039 1044
1040 /* Read status and ACK all interrupts */ 1045 /* Read status and ACK all interrupts */
1041 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 1046 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1042 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 1047 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1043 1048
1044 if (!reg) 1049 if (!reg)
1045 return IRQ_NONE; 1050 return IRQ_NONE;
@@ -1079,9 +1084,9 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1079 * the tasklet will reenable the appropriate interrupts. 1084 * the tasklet will reenable the appropriate interrupts.
1080 */ 1085 */
1081 spin_lock(&rt2x00dev->irqmask_lock); 1086 spin_lock(&rt2x00dev->irqmask_lock);
1082 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 1087 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1083 reg &= mask; 1088 reg &= mask;
1084 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 1089 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
1085 spin_unlock(&rt2x00dev->irqmask_lock); 1090 spin_unlock(&rt2x00dev->irqmask_lock);
1086 1091
1087 return IRQ_HANDLED; 1092 return IRQ_HANDLED;
@@ -1132,13 +1137,13 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1132}; 1137};
1133 1138
1134static const struct rt2800_ops rt2800pci_rt2800_ops = { 1139static const struct rt2800_ops rt2800pci_rt2800_ops = {
1135 .register_read = rt2x00pci_register_read, 1140 .register_read = rt2x00mmio_register_read,
1136 .register_read_lock = rt2x00pci_register_read, /* same for PCI */ 1141 .register_read_lock = rt2x00mmio_register_read, /* same for PCI */
1137 .register_write = rt2x00pci_register_write, 1142 .register_write = rt2x00mmio_register_write,
1138 .register_write_lock = rt2x00pci_register_write, /* same for PCI */ 1143 .register_write_lock = rt2x00mmio_register_write, /* same for PCI */
1139 .register_multiread = rt2x00pci_register_multiread, 1144 .register_multiread = rt2x00mmio_register_multiread,
1140 .register_multiwrite = rt2x00pci_register_multiwrite, 1145 .register_multiwrite = rt2x00mmio_register_multiwrite,
1141 .regbusy_read = rt2x00pci_regbusy_read, 1146 .regbusy_read = rt2x00mmio_regbusy_read,
1142 .read_eeprom = rt2800pci_read_eeprom, 1147 .read_eeprom = rt2800pci_read_eeprom,
1143 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled, 1148 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
1144 .drv_write_firmware = rt2800pci_write_firmware, 1149 .drv_write_firmware = rt2800pci_write_firmware,
@@ -1157,8 +1162,8 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1157 .get_firmware_name = rt2800pci_get_firmware_name, 1162 .get_firmware_name = rt2800pci_get_firmware_name,
1158 .check_firmware = rt2800_check_firmware, 1163 .check_firmware = rt2800_check_firmware,
1159 .load_firmware = rt2800_load_firmware, 1164 .load_firmware = rt2800_load_firmware,
1160 .initialize = rt2x00pci_initialize, 1165 .initialize = rt2x00mmio_initialize,
1161 .uninitialize = rt2x00pci_uninitialize, 1166 .uninitialize = rt2x00mmio_uninitialize,
1162 .get_entry_state = rt2800pci_get_entry_state, 1167 .get_entry_state = rt2800pci_get_entry_state,
1163 .clear_entry = rt2800pci_clear_entry, 1168 .clear_entry = rt2800pci_clear_entry,
1164 .set_device_state = rt2800pci_set_device_state, 1169 .set_device_state = rt2800pci_set_device_state,
@@ -1171,7 +1176,7 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1171 .start_queue = rt2800pci_start_queue, 1176 .start_queue = rt2800pci_start_queue,
1172 .kick_queue = rt2800pci_kick_queue, 1177 .kick_queue = rt2800pci_kick_queue,
1173 .stop_queue = rt2800pci_stop_queue, 1178 .stop_queue = rt2800pci_stop_queue,
1174 .flush_queue = rt2x00pci_flush_queue, 1179 .flush_queue = rt2x00mmio_flush_queue,
1175 .write_tx_desc = rt2800pci_write_tx_desc, 1180 .write_tx_desc = rt2800pci_write_tx_desc,
1176 .write_tx_data = rt2800_write_tx_data, 1181 .write_tx_data = rt2800_write_tx_data,
1177 .write_beacon = rt2800_write_beacon, 1182 .write_beacon = rt2800_write_beacon,
@@ -1192,21 +1197,21 @@ static const struct data_queue_desc rt2800pci_queue_rx = {
1192 .entry_num = 128, 1197 .entry_num = 128,
1193 .data_size = AGGREGATION_SIZE, 1198 .data_size = AGGREGATION_SIZE,
1194 .desc_size = RXD_DESC_SIZE, 1199 .desc_size = RXD_DESC_SIZE,
1195 .priv_size = sizeof(struct queue_entry_priv_pci), 1200 .priv_size = sizeof(struct queue_entry_priv_mmio),
1196}; 1201};
1197 1202
1198static const struct data_queue_desc rt2800pci_queue_tx = { 1203static const struct data_queue_desc rt2800pci_queue_tx = {
1199 .entry_num = 64, 1204 .entry_num = 64,
1200 .data_size = AGGREGATION_SIZE, 1205 .data_size = AGGREGATION_SIZE,
1201 .desc_size = TXD_DESC_SIZE, 1206 .desc_size = TXD_DESC_SIZE,
1202 .priv_size = sizeof(struct queue_entry_priv_pci), 1207 .priv_size = sizeof(struct queue_entry_priv_mmio),
1203}; 1208};
1204 1209
1205static const struct data_queue_desc rt2800pci_queue_bcn = { 1210static const struct data_queue_desc rt2800pci_queue_bcn = {
1206 .entry_num = 8, 1211 .entry_num = 8,
1207 .data_size = 0, /* No DMA required for beacons */ 1212 .data_size = 0, /* No DMA required for beacons */
1208 .desc_size = TXWI_DESC_SIZE, 1213 .desc_size = TXWI_DESC_SIZE,
1209 .priv_size = sizeof(struct queue_entry_priv_pci), 1214 .priv_size = sizeof(struct queue_entry_priv_mmio),
1210}; 1215};
1211 1216
1212static const struct rt2x00_ops rt2800pci_ops = { 1217static const struct rt2x00_ops rt2800pci_ops = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 00:21:52 -0500