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authorArnd Bergmann <arnd@arndb.de>2011-12-27 18:58:46 -0500
committerArnd Bergmann <arnd@arndb.de>2011-12-27 18:58:46 -0500
commitae852749438df6cb2c3ea0a015863010ecd3be0d (patch)
treed21f312d04fc14fae2f9aa3473f1424ad10d2647
parent4eb821999086417ab42a15174b51497122fc406e (diff)
parent8a44930a11de8d66f92145fd2d2464ab4fba696b (diff)
Merge branch 'samsung/cleanup' into next/cleanup2
* samsung/cleanup: ARM: S3C64XX: Modified according to SPI consolidation work ARM: S5PV210: Modified files for SPI consolidation work ARM: S5P64X0: Modified files for SPI consolidation work ARM: S5PC100: Modified files for SPI consolidation work ARM: S3C64XX: Modified files for SPI consolidation work ARM: SAMSUNG: Consolidation of SPI platform devices to plat-samsung ARM: SAMSUNG: Remove SPI bus clocks from platform data ARM: S5PV210: Add SPI clkdev support ARM: S5P64X0: Add SPI clkdev support ARM: S5PC100: Add SPI clkdev support ARM: S3C64XX: Add SPI clkdev support spi/s3c64xx: Use bus clocks created using clkdev mmc: sdhci-s3c: Use generic clock names for sdhci bus clock options ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names ARM: SAMSUNG: Remove SDHCI bus clocks from platform data
Diffstat
-rw-r--r--arch/arm/mach-exynos/Makefile1
-rw-r--r--arch/arm/mach-exynos/clock.c88
-rw-r--r--arch/arm/mach-exynos/setup-sdhci.c22
-rw-r--r--arch/arm/mach-s3c2416/Makefile1
-rw-r--r--arch/arm/mach-s3c2416/clock.c68
-rw-r--r--arch/arm/mach-s3c2416/setup-sdhci.c24
-rw-r--r--arch/arm/mach-s3c64xx/Kconfig8
-rw-r--r--arch/arm/mach-s3c64xx/Makefile3
-rw-r--r--arch/arm/mach-s3c64xx/clock.c206
-rw-r--r--arch/arm/mach-s3c64xx/dev-spi.c180
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/map.h2
-rw-r--r--arch/arm/mach-s3c64xx/setup-sdhci.c24
-rw-r--r--arch/arm/mach-s3c64xx/setup-spi.c45
-rw-r--r--arch/arm/mach-s5p64x0/Kconfig7
-rw-r--r--arch/arm/mach-s5p64x0/Makefile2
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c61
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c49
-rw-r--r--arch/arm/mach-s5p64x0/dev-spi.c224
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h2
-rw-r--r--arch/arm/mach-s5p64x0/setup-spi.c55
-rw-r--r--arch/arm/mach-s5pc100/Kconfig5
-rw-r--r--arch/arm/mach-s5pc100/Makefile3
-rw-r--r--arch/arm/mach-s5pc100/clock.c254
-rw-r--r--arch/arm/mach-s5pc100/dev-spi.c227
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h3
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci.c23
-rw-r--r--arch/arm/mach-s5pc100/setup-spi.c65
-rw-r--r--arch/arm/mach-s5pv210/Kconfig5
-rw-r--r--arch/arm/mach-s5pv210/Makefile3
-rw-r--r--arch/arm/mach-s5pv210/clock.c217
-rw-r--r--arch/arm/mach-s5pv210/dev-spi.c175
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h2
-rw-r--r--arch/arm/mach-s5pv210/setup-sdhci.c22
-rw-r--r--arch/arm/mach-s5pv210/setup-spi.c51
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c16
-rw-r--r--arch/arm/plat-samsung/Kconfig16
-rw-r--r--arch/arm/plat-samsung/devs.c127
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h8
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h24
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h31
-rw-r--r--drivers/mmc/host/sdhci-s3c.c7
-rw-r--r--drivers/spi/spi-s3c64xx.c14
42 files changed, 985 insertions, 1385 deletions
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8d85ae635ac2..57e529620804 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -58,6 +58,5 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
58obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o 58obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
59obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o 59obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
60obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o 60obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
61obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
62obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 61obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
63obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o 62obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 7dee8694486a..5d8d4831e244 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -1156,42 +1156,6 @@ static struct clksrc_clk clksrcs[] = {
1156 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, 1156 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1157 }, { 1157 }, {
1158 .clk = { 1158 .clk = {
1159 .name = "sclk_mmc",
1160 .devname = "s3c-sdhci.0",
1161 .parent = &clk_dout_mmc0.clk,
1162 .enable = exynos4_clksrc_mask_fsys_ctrl,
1163 .ctrlbit = (1 << 0),
1164 },
1165 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1166 }, {
1167 .clk = {
1168 .name = "sclk_mmc",
1169 .devname = "s3c-sdhci.1",
1170 .parent = &clk_dout_mmc1.clk,
1171 .enable = exynos4_clksrc_mask_fsys_ctrl,
1172 .ctrlbit = (1 << 4),
1173 },
1174 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1175 }, {
1176 .clk = {
1177 .name = "sclk_mmc",
1178 .devname = "s3c-sdhci.2",
1179 .parent = &clk_dout_mmc2.clk,
1180 .enable = exynos4_clksrc_mask_fsys_ctrl,
1181 .ctrlbit = (1 << 8),
1182 },
1183 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1184 }, {
1185 .clk = {
1186 .name = "sclk_mmc",
1187 .devname = "s3c-sdhci.3",
1188 .parent = &clk_dout_mmc3.clk,
1189 .enable = exynos4_clksrc_mask_fsys_ctrl,
1190 .ctrlbit = (1 << 12),
1191 },
1192 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1193 }, {
1194 .clk = {
1195 .name = "sclk_dwmmc", 1159 .name = "sclk_dwmmc",
1196 .parent = &clk_dout_mmc4.clk, 1160 .parent = &clk_dout_mmc4.clk,
1197 .enable = exynos4_clksrc_mask_fsys_ctrl, 1161 .enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1249,6 +1213,50 @@ static struct clksrc_clk clk_sclk_uart3 = {
1249 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, 1213 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1250}; 1214};
1251 1215
1216static struct clksrc_clk clk_sclk_mmc0 = {
1217 .clk = {
1218 .name = "sclk_mmc",
1219 .devname = "s3c-sdhci.0",
1220 .parent = &clk_dout_mmc0.clk,
1221 .enable = exynos4_clksrc_mask_fsys_ctrl,
1222 .ctrlbit = (1 << 0),
1223 },
1224 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1225};
1226
1227static struct clksrc_clk clk_sclk_mmc1 = {
1228 .clk = {
1229 .name = "sclk_mmc",
1230 .devname = "s3c-sdhci.1",
1231 .parent = &clk_dout_mmc1.clk,
1232 .enable = exynos4_clksrc_mask_fsys_ctrl,
1233 .ctrlbit = (1 << 4),
1234 },
1235 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1236};
1237
1238static struct clksrc_clk clk_sclk_mmc2 = {
1239 .clk = {
1240 .name = "sclk_mmc",
1241 .devname = "s3c-sdhci.2",
1242 .parent = &clk_dout_mmc2.clk,
1243 .enable = exynos4_clksrc_mask_fsys_ctrl,
1244 .ctrlbit = (1 << 8),
1245 },
1246 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1247};
1248
1249static struct clksrc_clk clk_sclk_mmc3 = {
1250 .clk = {
1251 .name = "sclk_mmc",
1252 .devname = "s3c-sdhci.3",
1253 .parent = &clk_dout_mmc3.clk,
1254 .enable = exynos4_clksrc_mask_fsys_ctrl,
1255 .ctrlbit = (1 << 12),
1256 },
1257 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1258};
1259
1252/* Clock initialization code */ 1260/* Clock initialization code */
1253static struct clksrc_clk *sysclks[] = { 1261static struct clksrc_clk *sysclks[] = {
1254 &clk_mout_apll, 1262 &clk_mout_apll,
@@ -1293,6 +1301,10 @@ static struct clksrc_clk *clksrc_cdev[] = {
1293 &clk_sclk_uart1, 1301 &clk_sclk_uart1,
1294 &clk_sclk_uart2, 1302 &clk_sclk_uart2,
1295 &clk_sclk_uart3, 1303 &clk_sclk_uart3,
1304 &clk_sclk_mmc0,
1305 &clk_sclk_mmc1,
1306 &clk_sclk_mmc2,
1307 &clk_sclk_mmc3,
1296}; 1308};
1297 1309
1298static struct clk_lookup exynos4_clk_lookup[] = { 1310static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1300,6 +1312,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
1300 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), 1312 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1301 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), 1313 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1302 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), 1314 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1315 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1316 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1317 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1318 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1303 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0), 1319 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1304 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1), 1320 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1305}; 1321};
diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
deleted file mode 100644
index 92937b410906..000000000000
--- a/arch/arm/mach-exynos/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-exynos4/setup-sdhci.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14
15/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
16
17char *exynos4_hsmmc_clksrcs[4] = {
18 [0] = NULL,
19 [1] = NULL,
20 [2] = "sclk_mmc", /* mmc_bus */
21 [3] = NULL,
22};
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 7b805b279caf..ca0cd227f873 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM) += pm.o
15#obj-$(CONFIG_S3C2416_DMA) += dma.o 15#obj-$(CONFIG_S3C2416_DMA) += dma.o
16 16
17# Device setup 17# Device setup
18obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
19obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 18obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
20 19
21# Machine support 20# Machine support
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index afbbe8bc21d1..59f54d1d7f8b 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -90,39 +90,38 @@ static struct clksrc_clk hsmmc_div[] = {
90 }, 90 },
91}; 91};
92 92
93static struct clksrc_clk hsmmc_mux[] = { 93static struct clksrc_clk hsmmc_mux0 = {
94 [0] = { 94 .clk = {
95 .clk = { 95 .name = "hsmmc-if",
96 .name = "hsmmc-if", 96 .devname = "s3c-sdhci.0",
97 .devname = "s3c-sdhci.0", 97 .ctrlbit = (1 << 6),
98 .ctrlbit = (1 << 6), 98 .enable = s3c2443_clkcon_enable_s,
99 .enable = s3c2443_clkcon_enable_s,
100 },
101 .sources = &(struct clksrc_sources) {
102 .nr_sources = 2,
103 .sources = (struct clk *[]) {
104 [0] = &hsmmc_div[0].clk,
105 [1] = NULL, /* to fix */
106 },
107 },
108 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
109 }, 99 },
110 [1] = { 100 .sources = &(struct clksrc_sources) {
111 .clk = { 101 .nr_sources = 2,
112 .name = "hsmmc-if", 102 .sources = (struct clk * []) {
113 .devname = "s3c-sdhci.1", 103 [0] = &hsmmc_div[0].clk,
114 .ctrlbit = (1 << 12), 104 [1] = NULL, /* to fix */
115 .enable = s3c2443_clkcon_enable_s,
116 }, 105 },
117 .sources = &(struct clksrc_sources) { 106 },
118 .nr_sources = 2, 107 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
119 .sources = (struct clk *[]) { 108};
120 [0] = &hsmmc_div[1].clk, 109
121 [1] = NULL, /* to fix */ 110static struct clksrc_clk hsmmc_mux1 = {
122 }, 111 .clk = {
112 .name = "hsmmc-if",
113 .devname = "s3c-sdhci.1",
114 .ctrlbit = (1 << 12),
115 .enable = s3c2443_clkcon_enable_s,
116 },
117 .sources = &(struct clksrc_sources) {
118 .nr_sources = 2,
119 .sources = (struct clk * []) {
120 [0] = &hsmmc_div[1].clk,
121 [1] = NULL, /* to fix */
123 }, 122 },
124 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
125 }, 123 },
124 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
126}; 125};
127 126
128static struct clk hsmmc0_clk = { 127static struct clk hsmmc0_clk = {
@@ -144,8 +143,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
144 &hsspi_mux, 143 &hsspi_mux,
145 &hsmmc_div[0], 144 &hsmmc_div[0],
146 &hsmmc_div[1], 145 &hsmmc_div[1],
147 &hsmmc_mux[0], 146 &hsmmc_mux0,
148 &hsmmc_mux[1], 147 &hsmmc_mux1,
148};
149
150static struct clk_lookup s3c2416_clk_lookup[] = {
151 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
152 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
153 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
149}; 154};
150 155
151void __init s3c2416_init_clocks(int xtal) 156void __init s3c2416_init_clocks(int xtal)
@@ -167,6 +172,7 @@ void __init s3c2416_init_clocks(int xtal)
167 s3c_register_clksrc(clksrcs[ptr], 1); 172 s3c_register_clksrc(clksrcs[ptr], 1);
168 173
169 s3c24xx_register_clock(&hsmmc0_clk); 174 s3c24xx_register_clock(&hsmmc0_clk);
175 clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
170 176
171 s3c_pwmclk_init(); 177 s3c_pwmclk_init();
172 178
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
deleted file mode 100644
index cee53955eb02..000000000000
--- a/arch/arm/mach-s3c2416/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
2 *
3 * Copyright 2010 Promwad Innovation Company
4 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
5 *
6 * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * Based on mach-s3c64xx/setup-sdhci.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16
17/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
18
19char *s3c2416_hsmmc_clksrcs[4] = {
20 [0] = "hsmmc",
21 [1] = "hsmmc",
22 [2] = "hsmmc-if",
23 /* [3] = "48m", - note not successfully used yet */
24};
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 5552e048c2be..90b34ab75b53 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -77,6 +77,11 @@ config S3C64XX_SETUP_SDHCI_GPIO
77 help 77 help
78 Common setup code for S3C64XX SDHCI GPIO configurations 78 Common setup code for S3C64XX SDHCI GPIO configurations
79 79
80config S3C64XX_SETUP_SPI
81 bool
82 help
83 Common setup code for SPI GPIO configurations
84
80# S36400 Macchine support 85# S36400 Macchine support
81 86
82config MACH_SMDK6400 87config MACH_SMDK6400
@@ -276,6 +281,7 @@ config MACH_WLF_CRAGG_6410
276 select S3C64XX_SETUP_IDE 281 select S3C64XX_SETUP_IDE
277 select S3C64XX_SETUP_FB_24BPP 282 select S3C64XX_SETUP_FB_24BPP
278 select S3C64XX_SETUP_KEYPAD 283 select S3C64XX_SETUP_KEYPAD
284 select S3C64XX_SETUP_SPI
279 select SAMSUNG_DEV_ADC 285 select SAMSUNG_DEV_ADC
280 select SAMSUNG_DEV_KEYPAD 286 select SAMSUNG_DEV_KEYPAD
281 select S3C_DEV_USB_HOST 287 select S3C_DEV_USB_HOST
@@ -286,7 +292,7 @@ config MACH_WLF_CRAGG_6410
286 select S3C_DEV_I2C1 292 select S3C_DEV_I2C1
287 select S3C_DEV_WDT 293 select S3C_DEV_WDT
288 select S3C_DEV_RTC 294 select S3C_DEV_RTC
289 select S3C64XX_DEV_SPI 295 select S3C64XX_DEV_SPI0
290 select S3C24XX_GPIO_EXTRA128 296 select S3C24XX_GPIO_EXTRA128
291 select I2C 297 select I2C
292 help 298 help
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index cfc0b9941808..d7d9bb5dfb72 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -32,9 +32,9 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
32obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o 32obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
33obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o 33obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
34obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o 34obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
35obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
36obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o 35obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
37obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 36obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
37obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o
38 38
39# PM 39# PM
40 40
@@ -60,4 +60,3 @@ obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
60 60
61obj-y += dev-uart.o 61obj-y += dev-uart.o
62obj-y += dev-audio.o 62obj-y += dev-audio.o
63obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 2addd988141c..0187cde3a5dc 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
184 .enable = s3c64xx_pclk_ctrl, 184 .enable = s3c64xx_pclk_ctrl,
185 .ctrlbit = S3C_CLKCON_PCLK_SPI1, 185 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
186 }, { 186 }, {
187 .name = "spi_48m",
188 .devname = "s3c64xx-spi.0",
189 .parent = &clk_48m,
190 .enable = s3c64xx_sclk_ctrl,
191 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
192 }, {
193 .name = "spi_48m",
194 .devname = "s3c64xx-spi.1",
195 .parent = &clk_48m,
196 .enable = s3c64xx_sclk_ctrl,
197 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
198 }, {
199 .name = "48m", 187 .name = "48m",
200 .devname = "s3c-sdhci.0", 188 .devname = "s3c-sdhci.0",
201 .parent = &clk_48m, 189 .parent = &clk_48m,
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
226 }, 214 },
227}; 215};
228 216
217static struct clk clk_48m_spi0 = {
218 .name = "spi_48m",
219 .devname = "s3c64xx-spi.0",
220 .parent = &clk_48m,
221 .enable = s3c64xx_sclk_ctrl,
222 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
223};
224
225static struct clk clk_48m_spi1 = {
226 .name = "spi_48m",
227 .devname = "s3c64xx-spi.1",
228 .parent = &clk_48m,
229 .enable = s3c64xx_sclk_ctrl,
230 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
231};
232
229static struct clk init_clocks[] = { 233static struct clk init_clocks[] = {
230 { 234 {
231 .name = "lcd", 235 .name = "lcd",
@@ -243,24 +247,6 @@ static struct clk init_clocks[] = {
243 .enable = s3c64xx_hclk_ctrl, 247 .enable = s3c64xx_hclk_ctrl,
244 .ctrlbit = S3C_CLKCON_HCLK_UHOST, 248 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
245 }, { 249 }, {
246 .name = "hsmmc",
247 .devname = "s3c-sdhci.0",
248 .parent = &clk_h,
249 .enable = s3c64xx_hclk_ctrl,
250 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
251 }, {
252 .name = "hsmmc",
253 .devname = "s3c-sdhci.1",
254 .parent = &clk_h,
255 .enable = s3c64xx_hclk_ctrl,
256 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
257 }, {
258 .name = "hsmmc",
259 .devname = "s3c-sdhci.2",
260 .parent = &clk_h,
261 .enable = s3c64xx_hclk_ctrl,
262 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
263 }, {
264 .name = "otg", 250 .name = "otg",
265 .parent = &clk_h, 251 .parent = &clk_h,
266 .enable = s3c64xx_hclk_ctrl, 252 .enable = s3c64xx_hclk_ctrl,
@@ -310,6 +296,29 @@ static struct clk init_clocks[] = {
310 } 296 }
311}; 297};
312 298
299static struct clk clk_hsmmc0 = {
300 .name = "hsmmc",
301 .devname = "s3c-sdhci.0",
302 .parent = &clk_h,
303 .enable = s3c64xx_hclk_ctrl,
304 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
305};
306
307static struct clk clk_hsmmc1 = {
308 .name = "hsmmc",
309 .devname = "s3c-sdhci.1",
310 .parent = &clk_h,
311 .enable = s3c64xx_hclk_ctrl,
312 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
313};
314
315static struct clk clk_hsmmc2 = {
316 .name = "hsmmc",
317 .devname = "s3c-sdhci.2",
318 .parent = &clk_h,
319 .enable = s3c64xx_hclk_ctrl,
320 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
321};
313 322
314static struct clk clk_fout_apll = { 323static struct clk clk_fout_apll = {
315 .name = "fout_apll", 324 .name = "fout_apll",
@@ -578,36 +587,6 @@ static struct clksrc_sources clkset_camif = {
578static struct clksrc_clk clksrcs[] = { 587static struct clksrc_clk clksrcs[] = {
579 { 588 {
580 .clk = { 589 .clk = {
581 .name = "mmc_bus",
582 .devname = "s3c-sdhci.0",
583 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
584 .enable = s3c64xx_sclk_ctrl,
585 },
586 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
587 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
588 .sources = &clkset_spi_mmc,
589 }, {
590 .clk = {
591 .name = "mmc_bus",
592 .devname = "s3c-sdhci.1",
593 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
594 .enable = s3c64xx_sclk_ctrl,
595 },
596 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
597 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
598 .sources = &clkset_spi_mmc,
599 }, {
600 .clk = {
601 .name = "mmc_bus",
602 .devname = "s3c-sdhci.2",
603 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
604 .enable = s3c64xx_sclk_ctrl,
605 },
606 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
607 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
608 .sources = &clkset_spi_mmc,
609 }, {
610 .clk = {
611 .name = "usb-bus-host", 590 .name = "usb-bus-host",
612 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 591 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
613 .enable = s3c64xx_sclk_ctrl, 592 .enable = s3c64xx_sclk_ctrl,
@@ -617,25 +596,6 @@ static struct clksrc_clk clksrcs[] = {
617 .sources = &clkset_uhost, 596 .sources = &clkset_uhost,
618 }, { 597 }, {
619 .clk = { 598 .clk = {
620 .name = "spi-bus",
621 .devname = "s3c64xx-spi.0",
622 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
623 .enable = s3c64xx_sclk_ctrl,
624 },
625 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
626 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
627 .sources = &clkset_spi_mmc,
628 }, {
629 .clk = {
630 .name = "spi-bus",
631 .devname = "s3c64xx-spi.1",
632 .enable = s3c64xx_sclk_ctrl,
633 },
634 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
635 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
636 .sources = &clkset_spi_mmc,
637 }, {
638 .clk = {
639 .name = "audio-bus", 599 .name = "audio-bus",
640 .devname = "samsung-i2s.0", 600 .devname = "samsung-i2s.0",
641 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 601 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
@@ -697,6 +657,66 @@ static struct clksrc_clk clk_sclk_uclk = {
697 .sources = &clkset_uart, 657 .sources = &clkset_uart,
698}; 658};
699 659
660static struct clksrc_clk clk_sclk_mmc0 = {
661 .clk = {
662 .name = "mmc_bus",
663 .devname = "s3c-sdhci.0",
664 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
665 .enable = s3c64xx_sclk_ctrl,
666 },
667 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
668 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
669 .sources = &clkset_spi_mmc,
670};
671
672static struct clksrc_clk clk_sclk_mmc1 = {
673 .clk = {
674 .name = "mmc_bus",
675 .devname = "s3c-sdhci.1",
676 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
677 .enable = s3c64xx_sclk_ctrl,
678 },
679 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
680 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
681 .sources = &clkset_spi_mmc,
682};
683
684static struct clksrc_clk clk_sclk_mmc2 = {
685 .clk = {
686 .name = "mmc_bus",
687 .devname = "s3c-sdhci.2",
688 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
689 .enable = s3c64xx_sclk_ctrl,
690 },
691 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
692 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
693 .sources = &clkset_spi_mmc,
694};
695
696static struct clksrc_clk clk_sclk_spi0 = {
697 .clk = {
698 .name = "spi-bus",
699 .devname = "s3c64xx-spi.0",
700 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
701 .enable = s3c64xx_sclk_ctrl,
702 },
703 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
704 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
705 .sources = &clkset_spi_mmc,
706};
707
708static struct clksrc_clk clk_sclk_spi1 = {
709 .clk = {
710 .name = "spi-bus",
711 .devname = "s3c64xx-spi.1",
712 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
713 .enable = s3c64xx_sclk_ctrl,
714 },
715 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
716 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
717 .sources = &clkset_spi_mmc,
718};
719
700/* Clock initialisation code */ 720/* Clock initialisation code */
701 721
702static struct clksrc_clk *init_parents[] = { 722static struct clksrc_clk *init_parents[] = {
@@ -707,11 +727,35 @@ static struct clksrc_clk *init_parents[] = {
707 727
708static struct clksrc_clk *clksrc_cdev[] = { 728static struct clksrc_clk *clksrc_cdev[] = {
709 &clk_sclk_uclk, 729 &clk_sclk_uclk,
730 &clk_sclk_mmc0,
731 &clk_sclk_mmc1,
732 &clk_sclk_mmc2,
733 &clk_sclk_spi0,
734 &clk_sclk_spi1,
735};
736
737static struct clk *clk_cdev[] = {
738 &clk_hsmmc0,
739 &clk_hsmmc1,
740 &clk_hsmmc2,
741 &clk_48m_spi0,
742 &clk_48m_spi1,
710}; 743};
711 744
712static struct clk_lookup s3c64xx_clk_lookup[] = { 745static struct clk_lookup s3c64xx_clk_lookup[] = {
713 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 746 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
714 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 747 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
748 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
749 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
750 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
751 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
752 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
753 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
754 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
755 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
756 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
757 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
758 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
715}; 759};
716 760
717#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 761#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -834,6 +878,10 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
834 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 878 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
835 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 879 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
836 880
881 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
882 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
883 s3c_disable_clocks(clk_cdev[cnt], 1);
884
837 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); 885 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
838 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 886 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
839 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) 887 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
deleted file mode 100644
index 3341fd118723..000000000000
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/* linux/arch/arm/plat-s3c64xx/dev-spi.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/export.h>
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/spi-clocks.h>
21#include <mach/irqs.h>
22
23#include <plat/s3c64xx-spi.h>
24#include <plat/gpio-cfg.h>
25#include <plat/devs.h>
26
27static char *spi_src_clks[] = {
28 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
29 [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
30 [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
31};
32
33/* SPI Controller platform_devices */
34
35/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
36 * The emulated CS is toggled by board specific mechanism, as it can
37 * be either some immediate GPIO or some signal out of some other
38 * chip in between ... or some yet another way.
39 * We simply do not assume anything about CS.
40 */
41static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
42{
43 unsigned int base;
44
45 switch (pdev->id) {
46 case 0:
47 base = S3C64XX_GPC(0);
48 break;
49
50 case 1:
51 base = S3C64XX_GPC(4);
52 break;
53
54 default:
55 dev_err(&pdev->dev, "Invalid SPI Controller number!");
56 return -EINVAL;
57 }
58
59 s3c_gpio_cfgall_range(base, 3,
60 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
61
62 return 0;
63}
64
65static struct resource s3c64xx_spi0_resource[] = {
66 [0] = {
67 .start = S3C64XX_PA_SPI0,
68 .end = S3C64XX_PA_SPI0 + 0x100 - 1,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = DMACH_SPI0_TX,
73 .end = DMACH_SPI0_TX,
74 .flags = IORESOURCE_DMA,
75 },
76 [2] = {
77 .start = DMACH_SPI0_RX,
78 .end = DMACH_SPI0_RX,
79 .flags = IORESOURCE_DMA,
80 },
81 [3] = {
82 .start = IRQ_SPI0,
83 .end = IRQ_SPI0,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
89 .cfg_gpio = s3c64xx_spi_cfg_gpio,
90 .fifo_lvl_mask = 0x7f,
91 .rx_lvl_offset = 13,
92 .tx_st_done = 21,
93};
94
95static u64 spi_dmamask = DMA_BIT_MASK(32);
96
97struct platform_device s3c64xx_device_spi0 = {
98 .name = "s3c64xx-spi",
99 .id = 0,
100 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
101 .resource = s3c64xx_spi0_resource,
102 .dev = {
103 .dma_mask = &spi_dmamask,
104 .coherent_dma_mask = DMA_BIT_MASK(32),
105 .platform_data = &s3c64xx_spi0_pdata,
106 },
107};
108EXPORT_SYMBOL(s3c64xx_device_spi0);
109
110static struct resource s3c64xx_spi1_resource[] = {
111 [0] = {
112 .start = S3C64XX_PA_SPI1,
113 .end = S3C64XX_PA_SPI1 + 0x100 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = DMACH_SPI1_TX,
118 .end = DMACH_SPI1_TX,
119 .flags = IORESOURCE_DMA,
120 },
121 [2] = {
122 .start = DMACH_SPI1_RX,
123 .end = DMACH_SPI1_RX,
124 .flags = IORESOURCE_DMA,
125 },
126 [3] = {
127 .start = IRQ_SPI1,
128 .end = IRQ_SPI1,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
134 .cfg_gpio = s3c64xx_spi_cfg_gpio,
135 .fifo_lvl_mask = 0x7f,
136 .rx_lvl_offset = 13,
137 .tx_st_done = 21,
138};
139
140struct platform_device s3c64xx_device_spi1 = {
141 .name = "s3c64xx-spi",
142 .id = 1,
143 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
144 .resource = s3c64xx_spi1_resource,
145 .dev = {
146 .dma_mask = &spi_dmamask,
147 .coherent_dma_mask = DMA_BIT_MASK(32),
148 .platform_data = &s3c64xx_spi1_pdata,
149 },
150};
151EXPORT_SYMBOL(s3c64xx_device_spi1);
152
153void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
154{
155 struct s3c64xx_spi_info *pd;
156
157 /* Reject invalid configuration */
158 if (!num_cs || src_clk_nr < 0
159 || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
160 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
161 return;
162 }
163
164 switch (cntrlr) {
165 case 0:
166 pd = &s3c64xx_spi0_pdata;
167 break;
168 case 1:
169 pd = &s3c64xx_spi1_pdata;
170 break;
171 default:
172 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
173 __func__, cntrlr);
174 return;
175 }
176
177 pd->num_cs = num_cs;
178 pd->src_clk_nr = src_clk_nr;
179 pd->src_clk_name = spi_src_clks[src_clk_nr];
180}
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 23a1d71e4d53..8e2097bb208a 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -115,6 +115,8 @@
115#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG 115#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
116#define S3C_PA_RTC S3C64XX_PA_RTC 116#define S3C_PA_RTC S3C64XX_PA_RTC
117#define S3C_PA_WDT S3C64XX_PA_WATCHDOG 117#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
118#define S3C_PA_SPI0 S3C64XX_PA_SPI0
119#define S3C_PA_SPI1 S3C64XX_PA_SPI1
118 120
119#define SAMSUNG_PA_ADC S3C64XX_PA_ADC 121#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
120#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON 122#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
deleted file mode 100644
index c75a71b21165..000000000000
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/types.h>
16
17/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
18
19char *s3c64xx_hsmmc_clksrcs[4] = {
20 [0] = "hsmmc",
21 [1] = "hsmmc",
22 [2] = "mmc_bus",
23 /* [3] = "48m", - note not successfully used yet */
24};
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
new file mode 100644
index 000000000000..d9592ad7a825
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -0,0 +1,45 @@
1/* linux/arch/arm/mach-s3c64xx/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .tx_st_done = 21,
22};
23
24int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28 return 0;
29}
30#endif
31
32#ifdef CONFIG_S3C64XX_DEV_SPI1
33struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
34 .fifo_lvl_mask = 0x7f,
35 .rx_lvl_offset = 13,
36 .tx_st_done = 21,
37};
38
39int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
40{
41 s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
42 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
43 return 0;
44}
45#endif
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 18690c5f99e6..dd8c85ef6dab 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -36,6 +36,11 @@ config S5P64X0_SETUP_I2C1
36 help 36 help
37 Common setup code for i2c bus 1. 37 Common setup code for i2c bus 1.
38 38
39config S5P64X0_SETUP_SPI
40 bool
41 help
42 Common setup code for SPI GPIO configurations
43
39# machine support 44# machine support
40 45
41config MACH_SMDK6440 46config MACH_SMDK6440
@@ -45,7 +50,6 @@ config MACH_SMDK6440
45 select S3C_DEV_I2C1 50 select S3C_DEV_I2C1
46 select S3C_DEV_RTC 51 select S3C_DEV_RTC
47 select S3C_DEV_WDT 52 select S3C_DEV_WDT
48 select S3C64XX_DEV_SPI
49 select SAMSUNG_DEV_ADC 53 select SAMSUNG_DEV_ADC
50 select SAMSUNG_DEV_BACKLIGHT 54 select SAMSUNG_DEV_BACKLIGHT
51 select SAMSUNG_DEV_PWM 55 select SAMSUNG_DEV_PWM
@@ -62,7 +66,6 @@ config MACH_SMDK6450
62 select S3C_DEV_I2C1 66 select S3C_DEV_I2C1
63 select S3C_DEV_RTC 67 select S3C_DEV_RTC
64 select S3C_DEV_WDT 68 select S3C_DEV_WDT
65 select S3C64XX_DEV_SPI
66 select SAMSUNG_DEV_ADC 69 select SAMSUNG_DEV_ADC
67 select SAMSUNG_DEV_BACKLIGHT 70 select SAMSUNG_DEV_BACKLIGHT
68 select SAMSUNG_DEV_PWM 71 select SAMSUNG_DEV_PWM
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index a1324d8dc4e0..a7d7a499d99e 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
26# device support 26# device support
27 27
28obj-y += dev-audio.o 28obj-y += dev-audio.o
29obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
30 29
31obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o 30obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
32obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o 31obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
32obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index bfb1917ad0da..73c7cc9ef0dd 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -268,18 +268,6 @@ static struct clk init_clocks_off[] = {
268 .enable = s5p64x0_pclk_ctrl, 268 .enable = s5p64x0_pclk_ctrl,
269 .ctrlbit = (1 << 31), 269 .ctrlbit = (1 << 31),
270 }, { 270 }, {
271 .name = "sclk_spi_48",
272 .devname = "s3c64xx-spi.0",
273 .parent = &clk_48m,
274 .enable = s5p64x0_sclk_ctrl,
275 .ctrlbit = (1 << 22),
276 }, {
277 .name = "sclk_spi_48",
278 .devname = "s3c64xx-spi.1",
279 .parent = &clk_48m,
280 .enable = s5p64x0_sclk_ctrl,
281 .ctrlbit = (1 << 23),
282 }, {
283 .name = "mmc_48m", 271 .name = "mmc_48m",
284 .devname = "s3c-sdhci.0", 272 .devname = "s3c-sdhci.0",
285 .parent = &clk_48m, 273 .parent = &clk_48m,
@@ -421,26 +409,6 @@ static struct clksrc_clk clksrcs[] = {
421 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 409 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
422 }, { 410 }, {
423 .clk = { 411 .clk = {
424 .name = "sclk_spi",
425 .devname = "s3c64xx-spi.0",
426 .ctrlbit = (1 << 20),
427 .enable = s5p64x0_sclk_ctrl,
428 },
429 .sources = &clkset_group1,
430 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
431 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
432 }, {
433 .clk = {
434 .name = "sclk_spi",
435 .devname = "s3c64xx-spi.1",
436 .ctrlbit = (1 << 21),
437 .enable = s5p64x0_sclk_ctrl,
438 },
439 .sources = &clkset_group1,
440 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
441 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
442 }, {
443 .clk = {
444 .name = "sclk_post", 412 .name = "sclk_post",
445 .ctrlbit = (1 << 10), 413 .ctrlbit = (1 << 10),
446 .enable = s5p64x0_sclk_ctrl, 414 .enable = s5p64x0_sclk_ctrl,
@@ -489,6 +457,30 @@ static struct clksrc_clk clk_sclk_uclk = {
489 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, 457 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
490}; 458};
491 459
460static struct clksrc_clk clk_sclk_spi0 = {
461 .clk = {
462 .name = "sclk_spi",
463 .devname = "s3c64xx-spi.0",
464 .ctrlbit = (1 << 20),
465 .enable = s5p64x0_sclk_ctrl,
466 },
467 .sources = &clkset_group1,
468 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
469 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
470};
471
472static struct clksrc_clk clk_sclk_spi1 = {
473 .clk = {
474 .name = "sclk_spi",
475 .devname = "s3c64xx-spi.1",
476 .ctrlbit = (1 << 21),
477 .enable = s5p64x0_sclk_ctrl,
478 },
479 .sources = &clkset_group1,
480 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
481 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
482};
483
492/* Clock initialization code */ 484/* Clock initialization code */
493static struct clksrc_clk *sysclks[] = { 485static struct clksrc_clk *sysclks[] = {
494 &clk_mout_apll, 486 &clk_mout_apll,
@@ -509,11 +501,16 @@ static struct clk dummy_apb_pclk = {
509 501
510static struct clksrc_clk *clksrc_cdev[] = { 502static struct clksrc_clk *clksrc_cdev[] = {
511 &clk_sclk_uclk, 503 &clk_sclk_uclk,
504 &clk_sclk_spi0,
505 &clk_sclk_spi1,
512}; 506};
513 507
514static struct clk_lookup s5p6440_clk_lookup[] = { 508static struct clk_lookup s5p6440_clk_lookup[] = {
515 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 509 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
516 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 510 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
511 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
512 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
513 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
517}; 514};
518 515
519void __init_or_cpufreq s5p6440_setup_clocks(void) 516void __init_or_cpufreq s5p6440_setup_clocks(void)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index d132638c7b23..50f90cbf7798 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -443,26 +443,6 @@ static struct clksrc_clk clksrcs[] = {
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, 443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, { 444 }, {
445 .clk = { 445 .clk = {
446 .name = "sclk_spi",
447 .devname = "s3c64xx-spi.0",
448 .ctrlbit = (1 << 20),
449 .enable = s5p64x0_sclk_ctrl,
450 },
451 .sources = &clkset_group2,
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
454 }, {
455 .clk = {
456 .name = "sclk_spi",
457 .devname = "s3c64xx-spi.1",
458 .ctrlbit = (1 << 21),
459 .enable = s5p64x0_sclk_ctrl,
460 },
461 .sources = &clkset_group2,
462 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
463 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
464 }, {
465 .clk = {
466 .name = "sclk_fimc", 446 .name = "sclk_fimc",
467 .ctrlbit = (1 << 10), 447 .ctrlbit = (1 << 10),
468 .enable = s5p64x0_sclk_ctrl, 448 .enable = s5p64x0_sclk_ctrl,
@@ -538,13 +518,42 @@ static struct clksrc_clk clk_sclk_uclk = {
538 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, 518 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
539}; 519};
540 520
521static struct clksrc_clk clk_sclk_spi0 = {
522 .clk = {
523 .name = "sclk_spi",
524 .devname = "s3c64xx-spi.0",
525 .ctrlbit = (1 << 20),
526 .enable = s5p64x0_sclk_ctrl,
527 },
528 .sources = &clkset_group2,
529 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
530 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
531};
532
533static struct clksrc_clk clk_sclk_spi1 = {
534 .clk = {
535 .name = "sclk_spi",
536 .devname = "s3c64xx-spi.1",
537 .ctrlbit = (1 << 21),
538 .enable = s5p64x0_sclk_ctrl,
539 },
540 .sources = &clkset_group2,
541 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
542 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
543};
544
541static struct clksrc_clk *clksrc_cdev[] = { 545static struct clksrc_clk *clksrc_cdev[] = {
542 &clk_sclk_uclk, 546 &clk_sclk_uclk,
547 &clk_sclk_spi0,
548 &clk_sclk_spi1,
543}; 549};
544 550
545static struct clk_lookup s5p6450_clk_lookup[] = { 551static struct clk_lookup s5p6450_clk_lookup[] = {
546 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), 552 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
547 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 553 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
554 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
555 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
556 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
548}; 557};
549 558
550/* Clock initialization code */ 559/* Clock initialization code */
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
deleted file mode 100644
index 1fd9c79c7dbc..000000000000
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ /dev/null
@@ -1,224 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/dev-spi.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/irqs.h>
21#include <mach/regs-clock.h>
22#include <mach/spi-clocks.h>
23
24#include <plat/cpu.h>
25#include <plat/s3c64xx-spi.h>
26#include <plat/gpio-cfg.h>
27
28static char *s5p64x0_spi_src_clks[] = {
29 [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
30 [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
31};
32
33/* SPI Controller platform_devices */
34
35/* Since we emulate multi-cs capability, we do not touch the CS.
36 * The emulated CS is toggled by board specific mechanism, as it can
37 * be either some immediate GPIO or some signal out of some other
38 * chip in between ... or some yet another way.
39 * We simply do not assume anything about CS.
40 */
41static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
42{
43 unsigned int base;
44
45 switch (pdev->id) {
46 case 0:
47 base = S5P6440_GPC(0);
48 break;
49
50 case 1:
51 base = S5P6440_GPC(4);
52 break;
53
54 default:
55 dev_err(&pdev->dev, "Invalid SPI Controller number!");
56 return -EINVAL;
57 }
58
59 s3c_gpio_cfgall_range(base, 3,
60 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
61
62 return 0;
63}
64
65static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
66{
67 unsigned int base;
68
69 switch (pdev->id) {
70 case 0:
71 base = S5P6450_GPC(0);
72 break;
73
74 case 1:
75 base = S5P6450_GPC(4);
76 break;
77
78 default:
79 dev_err(&pdev->dev, "Invalid SPI Controller number!");
80 return -EINVAL;
81 }
82
83 s3c_gpio_cfgall_range(base, 3,
84 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
85
86 return 0;
87}
88
89static struct resource s5p64x0_spi0_resource[] = {
90 [0] = {
91 .start = S5P64X0_PA_SPI0,
92 .end = S5P64X0_PA_SPI0 + 0x100 - 1,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = DMACH_SPI0_TX,
97 .end = DMACH_SPI0_TX,
98 .flags = IORESOURCE_DMA,
99 },
100 [2] = {
101 .start = DMACH_SPI0_RX,
102 .end = DMACH_SPI0_RX,
103 .flags = IORESOURCE_DMA,
104 },
105 [3] = {
106 .start = IRQ_SPI0,
107 .end = IRQ_SPI0,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
113 .cfg_gpio = s5p6440_spi_cfg_gpio,
114 .fifo_lvl_mask = 0x1ff,
115 .rx_lvl_offset = 15,
116 .tx_st_done = 25,
117};
118
119static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
120 .cfg_gpio = s5p6450_spi_cfg_gpio,
121 .fifo_lvl_mask = 0x1ff,
122 .rx_lvl_offset = 15,
123 .tx_st_done = 25,
124};
125
126static u64 spi_dmamask = DMA_BIT_MASK(32);
127
128struct platform_device s5p64x0_device_spi0 = {
129 .name = "s3c64xx-spi",
130 .id = 0,
131 .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
132 .resource = s5p64x0_spi0_resource,
133 .dev = {
134 .dma_mask = &spi_dmamask,
135 .coherent_dma_mask = DMA_BIT_MASK(32),
136 },
137};
138
139static struct resource s5p64x0_spi1_resource[] = {
140 [0] = {
141 .start = S5P64X0_PA_SPI1,
142 .end = S5P64X0_PA_SPI1 + 0x100 - 1,
143 .flags = IORESOURCE_MEM,
144 },
145 [1] = {
146 .start = DMACH_SPI1_TX,
147 .end = DMACH_SPI1_TX,
148 .flags = IORESOURCE_DMA,
149 },
150 [2] = {
151 .start = DMACH_SPI1_RX,
152 .end = DMACH_SPI1_RX,
153 .flags = IORESOURCE_DMA,
154 },
155 [3] = {
156 .start = IRQ_SPI1,
157 .end = IRQ_SPI1,
158 .flags = IORESOURCE_IRQ,
159 },
160};
161
162static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
163 .cfg_gpio = s5p6440_spi_cfg_gpio,
164 .fifo_lvl_mask = 0x7f,
165 .rx_lvl_offset = 15,
166 .tx_st_done = 25,
167};
168
169static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
170 .cfg_gpio = s5p6450_spi_cfg_gpio,
171 .fifo_lvl_mask = 0x7f,
172 .rx_lvl_offset = 15,
173 .tx_st_done = 25,
174};
175
176struct platform_device s5p64x0_device_spi1 = {
177 .name = "s3c64xx-spi",
178 .id = 1,
179 .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
180 .resource = s5p64x0_spi1_resource,
181 .dev = {
182 .dma_mask = &spi_dmamask,
183 .coherent_dma_mask = DMA_BIT_MASK(32),
184 },
185};
186
187void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
188{
189 struct s3c64xx_spi_info *pd;
190
191 /* Reject invalid configuration */
192 if (!num_cs || src_clk_nr < 0
193 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
194 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
195 return;
196 }
197
198 switch (cntrlr) {
199 case 0:
200 if (soc_is_s5p6450())
201 pd = &s5p6450_spi0_pdata;
202 else
203 pd = &s5p6440_spi0_pdata;
204
205 s5p64x0_device_spi0.dev.platform_data = pd;
206 break;
207 case 1:
208 if (soc_is_s5p6450())
209 pd = &s5p6450_spi1_pdata;
210 else
211 pd = &s5p6440_spi1_pdata;
212
213 s5p64x0_device_spi1.dev.platform_data = pd;
214 break;
215 default:
216 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
217 __func__, cntrlr);
218 return;
219 }
220
221 pd->num_cs = num_cs;
222 pd->src_clk_nr = src_clk_nr;
223 pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
224}
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 4d3ac8a3709d..0c0175dbfa34 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -67,6 +67,8 @@
67#define S3C_PA_RTC S5P64X0_PA_RTC 67#define S3C_PA_RTC S5P64X0_PA_RTC
68#define S3C_PA_WDT S5P64X0_PA_WDT 68#define S3C_PA_WDT S5P64X0_PA_WDT
69#define S3C_PA_FB S5P64X0_PA_FB 69#define S3C_PA_FB S5P64X0_PA_FB
70#define S3C_PA_SPI0 S5P64X0_PA_SPI0
71#define S3C_PA_SPI1 S5P64X0_PA_SPI1
70 72
71#define S5P_PA_CHIPID S5P64X0_PA_CHIPID 73#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
72#define S5P_PA_SROMC S5P64X0_PA_SROMC 74#define S5P_PA_SROMC S5P64X0_PA_SROMC
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
new file mode 100644
index 000000000000..e9b841240352
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -0,0 +1,55 @@
1/* linux/arch/arm/mach-s5p64x0/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/cpu.h>
17#include <plat/s3c64xx-spi.h>
18
19#ifdef CONFIG_S3C64XX_DEV_SPI0
20struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
21 .fifo_lvl_mask = 0x1ff,
22 .rx_lvl_offset = 15,
23 .tx_st_done = 25,
24};
25
26int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
27{
28 if (soc_is_s5p6450())
29 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
30 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
31 else
32 s3c_gpio_cfgall_range(S5P6440_GPC(0), 3,
33 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
34 return 0;
35}
36#endif
37
38#ifdef CONFIG_S3C64XX_DEV_SPI1
39struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
40 .fifo_lvl_mask = 0x7f,
41 .rx_lvl_offset = 15,
42 .tx_st_done = 25,
43};
44
45int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
46{
47 if (soc_is_s5p6450())
48 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
49 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
50 else
51 s3c_gpio_cfgall_range(S5P6440_GPC(4), 3,
52 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
53 return 0;
54}
55#endif
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index e538a4c67e9c..75a26eaf2633 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -45,6 +45,11 @@ config S5PC100_SETUP_SDHCI_GPIO
45 help 45 help
46 Common setup code for SDHCI gpio. 46 Common setup code for SDHCI gpio.
47 47
48config S5PC100_SETUP_SPI
49 bool
50 help
51 Common setup code for SPI GPIO configurations.
52
48config MACH_SMDKC100 53config MACH_SMDKC100
49 bool "SMDKC100" 54 bool "SMDKC100"
50 select CPU_S5PC100 55 select CPU_S5PC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index a5e6e608b498..291e246c0ec0 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -21,12 +21,11 @@ obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
21obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o 21obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
22obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o 22obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
23obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o 23obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
24obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
25obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 24obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
25obj-$(CONFIG_S5PC100_SETUP_SPI) += setup-spi.o
26 26
27# device support 27# device support
28obj-y += dev-audio.o 28obj-y += dev-audio.o
29obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
30 29
31# machine support 30# machine support
32 31
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 9d644ece2604..eba721b551fc 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -426,24 +426,6 @@ static struct clk init_clocks_off[] = {
426 .enable = s5pc100_d0_2_ctrl, 426 .enable = s5pc100_d0_2_ctrl,
427 .ctrlbit = (1 << 1), 427 .ctrlbit = (1 << 1),
428 }, { 428 }, {
429 .name = "hsmmc",
430 .devname = "s3c-sdhci.2",
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
433 .ctrlbit = (1 << 7),
434 }, {
435 .name = "hsmmc",
436 .devname = "s3c-sdhci.1",
437 .parent = &clk_div_d1_bus.clk,
438 .enable = s5pc100_d1_0_ctrl,
439 .ctrlbit = (1 << 6),
440 }, {
441 .name = "hsmmc",
442 .devname = "s3c-sdhci.0",
443 .parent = &clk_div_d1_bus.clk,
444 .enable = s5pc100_d1_0_ctrl,
445 .ctrlbit = (1 << 5),
446 }, {
447 .name = "modemif", 429 .name = "modemif",
448 .parent = &clk_div_d1_bus.clk, 430 .parent = &clk_div_d1_bus.clk,
449 .enable = s5pc100_d1_0_ctrl, 431 .enable = s5pc100_d1_0_ctrl,
@@ -673,24 +655,6 @@ static struct clk init_clocks_off[] = {
673 .enable = s5pc100_d1_5_ctrl, 655 .enable = s5pc100_d1_5_ctrl,
674 .ctrlbit = (1 << 8), 656 .ctrlbit = (1 << 8),
675 }, { 657 }, {
676 .name = "spi_48m",
677 .devname = "s3c64xx-spi.0",
678 .parent = &clk_mout_48m.clk,
679 .enable = s5pc100_sclk0_ctrl,
680 .ctrlbit = (1 << 7),
681 }, {
682 .name = "spi_48m",
683 .devname = "s3c64xx-spi.1",
684 .parent = &clk_mout_48m.clk,
685 .enable = s5pc100_sclk0_ctrl,
686 .ctrlbit = (1 << 8),
687 }, {
688 .name = "spi_48m",
689 .devname = "s3c64xx-spi.2",
690 .parent = &clk_mout_48m.clk,
691 .enable = s5pc100_sclk0_ctrl,
692 .ctrlbit = (1 << 9),
693 }, {
694 .name = "mmc_48m", 658 .name = "mmc_48m",
695 .devname = "s3c-sdhci.0", 659 .devname = "s3c-sdhci.0",
696 .parent = &clk_mout_48m.clk, 660 .parent = &clk_mout_48m.clk,
@@ -711,6 +675,54 @@ static struct clk init_clocks_off[] = {
711 }, 675 },
712}; 676};
713 677
678static struct clk clk_hsmmc2 = {
679 .name = "hsmmc",
680 .devname = "s3c-sdhci.2",
681 .parent = &clk_div_d1_bus.clk,
682 .enable = s5pc100_d1_0_ctrl,
683 .ctrlbit = (1 << 7),
684};
685
686static struct clk clk_hsmmc1 = {
687 .name = "hsmmc",
688 .devname = "s3c-sdhci.1",
689 .parent = &clk_div_d1_bus.clk,
690 .enable = s5pc100_d1_0_ctrl,
691 .ctrlbit = (1 << 6),
692};
693
694static struct clk clk_hsmmc0 = {
695 .name = "hsmmc",
696 .devname = "s3c-sdhci.0",
697 .parent = &clk_div_d1_bus.clk,
698 .enable = s5pc100_d1_0_ctrl,
699 .ctrlbit = (1 << 5),
700};
701
702static struct clk clk_48m_spi0 = {
703 .name = "spi_48m",
704 .devname = "s3c64xx-spi.0",
705 .parent = &clk_mout_48m.clk,
706 .enable = s5pc100_sclk0_ctrl,
707 .ctrlbit = (1 << 7),
708};
709
710static struct clk clk_48m_spi1 = {
711 .name = "spi_48m",
712 .devname = "s3c64xx-spi.1",
713 .parent = &clk_mout_48m.clk,
714 .enable = s5pc100_sclk0_ctrl,
715 .ctrlbit = (1 << 8),
716};
717
718static struct clk clk_48m_spi2 = {
719 .name = "spi_48m",
720 .devname = "s3c64xx-spi.2",
721 .parent = &clk_mout_48m.clk,
722 .enable = s5pc100_sclk0_ctrl,
723 .ctrlbit = (1 << 9),
724};
725
714static struct clk clk_vclk54m = { 726static struct clk clk_vclk54m = {
715 .name = "vclk_54m", 727 .name = "vclk_54m",
716 .rate = 54000000, 728 .rate = 54000000,
@@ -929,39 +941,6 @@ static struct clksrc_clk clk_sclk_spdif = {
929static struct clksrc_clk clksrcs[] = { 941static struct clksrc_clk clksrcs[] = {
930 { 942 {
931 .clk = { 943 .clk = {
932 .name = "sclk_spi",
933 .devname = "s3c64xx-spi.0",
934 .ctrlbit = (1 << 4),
935 .enable = s5pc100_sclk0_ctrl,
936
937 },
938 .sources = &clk_src_group1,
939 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
940 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
941 }, {
942 .clk = {
943 .name = "sclk_spi",
944 .devname = "s3c64xx-spi.1",
945 .ctrlbit = (1 << 5),
946 .enable = s5pc100_sclk0_ctrl,
947
948 },
949 .sources = &clk_src_group1,
950 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
951 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
952 }, {
953 .clk = {
954 .name = "sclk_spi",
955 .devname = "s3c64xx-spi.2",
956 .ctrlbit = (1 << 6),
957 .enable = s5pc100_sclk0_ctrl,
958
959 },
960 .sources = &clk_src_group1,
961 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
962 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
963 }, {
964 .clk = {
965 .name = "sclk_mixer", 944 .name = "sclk_mixer",
966 .ctrlbit = (1 << 6), 945 .ctrlbit = (1 << 6),
967 .enable = s5pc100_sclk0_ctrl, 946 .enable = s5pc100_sclk0_ctrl,
@@ -1014,39 +993,6 @@ static struct clksrc_clk clksrcs[] = {
1014 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, 993 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1015 }, { 994 }, {
1016 .clk = { 995 .clk = {
1017 .name = "sclk_mmc",
1018 .devname = "s3c-sdhci.0",
1019 .ctrlbit = (1 << 12),
1020 .enable = s5pc100_sclk1_ctrl,
1021
1022 },
1023 .sources = &clk_src_mmc0,
1024 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1025 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1026 }, {
1027 .clk = {
1028 .name = "sclk_mmc",
1029 .devname = "s3c-sdhci.1",
1030 .ctrlbit = (1 << 13),
1031 .enable = s5pc100_sclk1_ctrl,
1032
1033 },
1034 .sources = &clk_src_mmc12,
1035 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1036 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1037 }, {
1038 .clk = {
1039 .name = "sclk_mmc",
1040 .devname = "s3c-sdhci.2",
1041 .ctrlbit = (1 << 14),
1042 .enable = s5pc100_sclk1_ctrl,
1043
1044 },
1045 .sources = &clk_src_mmc12,
1046 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1047 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1048 }, {
1049 .clk = {
1050 .name = "sclk_irda", 996 .name = "sclk_irda",
1051 .ctrlbit = (1 << 10), 997 .ctrlbit = (1 << 10),
1052 .enable = s5pc100_sclk0_ctrl, 998 .enable = s5pc100_sclk0_ctrl,
@@ -1099,6 +1045,78 @@ static struct clksrc_clk clk_sclk_uart = {
1099 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, 1045 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1100}; 1046};
1101 1047
1048static struct clksrc_clk clk_sclk_mmc0 = {
1049 .clk = {
1050 .name = "sclk_mmc",
1051 .devname = "s3c-sdhci.0",
1052 .ctrlbit = (1 << 12),
1053 .enable = s5pc100_sclk1_ctrl,
1054 },
1055 .sources = &clk_src_mmc0,
1056 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1057 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1058};
1059
1060static struct clksrc_clk clk_sclk_mmc1 = {
1061 .clk = {
1062 .name = "sclk_mmc",
1063 .devname = "s3c-sdhci.1",
1064 .ctrlbit = (1 << 13),
1065 .enable = s5pc100_sclk1_ctrl,
1066 },
1067 .sources = &clk_src_mmc12,
1068 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1069 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1070};
1071
1072static struct clksrc_clk clk_sclk_mmc2 = {
1073 .clk = {
1074 .name = "sclk_mmc",
1075 .devname = "s3c-sdhci.2",
1076 .ctrlbit = (1 << 14),
1077 .enable = s5pc100_sclk1_ctrl,
1078 },
1079 .sources = &clk_src_mmc12,
1080 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1081 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1082};
1083
1084static struct clksrc_clk clk_sclk_spi0 = {
1085 .clk = {
1086 .name = "sclk_spi",
1087 .devname = "s3c64xx-spi.0",
1088 .ctrlbit = (1 << 4),
1089 .enable = s5pc100_sclk0_ctrl,
1090 },
1091 .sources = &clk_src_group1,
1092 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1093 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1094};
1095
1096static struct clksrc_clk clk_sclk_spi1 = {
1097 .clk = {
1098 .name = "sclk_spi",
1099 .devname = "s3c64xx-spi.1",
1100 .ctrlbit = (1 << 5),
1101 .enable = s5pc100_sclk0_ctrl,
1102 },
1103 .sources = &clk_src_group1,
1104 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1105 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1106};
1107
1108static struct clksrc_clk clk_sclk_spi2 = {
1109 .clk = {
1110 .name = "sclk_spi",
1111 .devname = "s3c64xx-spi.2",
1112 .ctrlbit = (1 << 6),
1113 .enable = s5pc100_sclk0_ctrl,
1114 },
1115 .sources = &clk_src_group1,
1116 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1117 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1118};
1119
1102/* Clock initialisation code */ 1120/* Clock initialisation code */
1103static struct clksrc_clk *sysclks[] = { 1121static struct clksrc_clk *sysclks[] = {
1104 &clk_mout_apll, 1122 &clk_mout_apll,
@@ -1128,8 +1146,23 @@ static struct clksrc_clk *sysclks[] = {
1128 &clk_sclk_spdif, 1146 &clk_sclk_spdif,
1129}; 1147};
1130 1148
1149static struct clk *clk_cdev[] = {
1150 &clk_hsmmc0,
1151 &clk_hsmmc1,
1152 &clk_hsmmc2,
1153 &clk_48m_spi0,
1154 &clk_48m_spi1,
1155 &clk_48m_spi2,
1156};
1157
1131static struct clksrc_clk *clksrc_cdev[] = { 1158static struct clksrc_clk *clksrc_cdev[] = {
1132 &clk_sclk_uart, 1159 &clk_sclk_uart,
1160 &clk_sclk_mmc0,
1161 &clk_sclk_mmc1,
1162 &clk_sclk_mmc2,
1163 &clk_sclk_spi0,
1164 &clk_sclk_spi1,
1165 &clk_sclk_spi2,
1133}; 1166};
1134 1167
1135void __init_or_cpufreq s5pc100_setup_clocks(void) 1168void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1274,6 +1307,19 @@ static struct clk *clks[] __initdata = {
1274static struct clk_lookup s5pc100_clk_lookup[] = { 1307static struct clk_lookup s5pc100_clk_lookup[] = {
1275 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 1308 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1276 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), 1309 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1310 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1311 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1312 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1313 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1314 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1315 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1316 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1317 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
1318 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1319 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
1320 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1321 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
1322 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1277}; 1323};
1278 1324
1279void __init s5pc100_register_clocks(void) 1325void __init s5pc100_register_clocks(void)
@@ -1294,6 +1340,10 @@ void __init s5pc100_register_clocks(void)
1294 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1340 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1295 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup)); 1341 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1296 1342
1343 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1344 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1345 s3c_disable_clocks(clk_cdev[ptr], 1);
1346
1297 s3c24xx_register_clock(&dummy_apb_pclk); 1347 s3c24xx_register_clock(&dummy_apb_pclk);
1298 1348
1299 s3c_pwmclk_init(); 1349 s3c_pwmclk_init();
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
deleted file mode 100644
index e5d6c4dceb56..000000000000
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ /dev/null
@@ -1,227 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/spi-clocks.h>
18#include <mach/irqs.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22#include <plat/irqs.h>
23
24static char *spi_src_clks[] = {
25 [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
26 [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
27 [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
28};
29
30/* SPI Controller platform_devices */
31
32/* Since we emulate multi-cs capability, we do not touch the CS.
33 * The emulated CS is toggled by board specific mechanism, as it can
34 * be either some immediate GPIO or some signal out of some other
35 * chip in between ... or some yet another way.
36 * We simply do not assume anything about CS.
37 */
38static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
39{
40 switch (pdev->id) {
41 case 0:
42 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
43 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
44 break;
45
46 case 1:
47 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
48 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
49 break;
50
51 case 2:
52 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
53 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
54 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
55 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
56 break;
57
58 default:
59 dev_err(&pdev->dev, "Invalid SPI Controller number!");
60 return -EINVAL;
61 }
62
63 return 0;
64}
65
66static struct resource s5pc100_spi0_resource[] = {
67 [0] = {
68 .start = S5PC100_PA_SPI0,
69 .end = S5PC100_PA_SPI0 + 0x100 - 1,
70 .flags = IORESOURCE_MEM,
71 },
72 [1] = {
73 .start = DMACH_SPI0_TX,
74 .end = DMACH_SPI0_TX,
75 .flags = IORESOURCE_DMA,
76 },
77 [2] = {
78 .start = DMACH_SPI0_RX,
79 .end = DMACH_SPI0_RX,
80 .flags = IORESOURCE_DMA,
81 },
82 [3] = {
83 .start = IRQ_SPI0,
84 .end = IRQ_SPI0,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
90 .cfg_gpio = s5pc100_spi_cfg_gpio,
91 .fifo_lvl_mask = 0x7f,
92 .rx_lvl_offset = 13,
93 .high_speed = 1,
94 .tx_st_done = 21,
95};
96
97static u64 spi_dmamask = DMA_BIT_MASK(32);
98
99struct platform_device s5pc100_device_spi0 = {
100 .name = "s3c64xx-spi",
101 .id = 0,
102 .num_resources = ARRAY_SIZE(s5pc100_spi0_resource),
103 .resource = s5pc100_spi0_resource,
104 .dev = {
105 .dma_mask = &spi_dmamask,
106 .coherent_dma_mask = DMA_BIT_MASK(32),
107 .platform_data = &s5pc100_spi0_pdata,
108 },
109};
110
111static struct resource s5pc100_spi1_resource[] = {
112 [0] = {
113 .start = S5PC100_PA_SPI1,
114 .end = S5PC100_PA_SPI1 + 0x100 - 1,
115 .flags = IORESOURCE_MEM,
116 },
117 [1] = {
118 .start = DMACH_SPI1_TX,
119 .end = DMACH_SPI1_TX,
120 .flags = IORESOURCE_DMA,
121 },
122 [2] = {
123 .start = DMACH_SPI1_RX,
124 .end = DMACH_SPI1_RX,
125 .flags = IORESOURCE_DMA,
126 },
127 [3] = {
128 .start = IRQ_SPI1,
129 .end = IRQ_SPI1,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
134static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
135 .cfg_gpio = s5pc100_spi_cfg_gpio,
136 .fifo_lvl_mask = 0x7f,
137 .rx_lvl_offset = 13,
138 .high_speed = 1,
139 .tx_st_done = 21,
140};
141
142struct platform_device s5pc100_device_spi1 = {
143 .name = "s3c64xx-spi",
144 .id = 1,
145 .num_resources = ARRAY_SIZE(s5pc100_spi1_resource),
146 .resource = s5pc100_spi1_resource,
147 .dev = {
148 .dma_mask = &spi_dmamask,
149 .coherent_dma_mask = DMA_BIT_MASK(32),
150 .platform_data = &s5pc100_spi1_pdata,
151 },
152};
153
154static struct resource s5pc100_spi2_resource[] = {
155 [0] = {
156 .start = S5PC100_PA_SPI2,
157 .end = S5PC100_PA_SPI2 + 0x100 - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = DMACH_SPI2_TX,
162 .end = DMACH_SPI2_TX,
163 .flags = IORESOURCE_DMA,
164 },
165 [2] = {
166 .start = DMACH_SPI2_RX,
167 .end = DMACH_SPI2_RX,
168 .flags = IORESOURCE_DMA,
169 },
170 [3] = {
171 .start = IRQ_SPI2,
172 .end = IRQ_SPI2,
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
178 .cfg_gpio = s5pc100_spi_cfg_gpio,
179 .fifo_lvl_mask = 0x7f,
180 .rx_lvl_offset = 13,
181 .high_speed = 1,
182 .tx_st_done = 21,
183};
184
185struct platform_device s5pc100_device_spi2 = {
186 .name = "s3c64xx-spi",
187 .id = 2,
188 .num_resources = ARRAY_SIZE(s5pc100_spi2_resource),
189 .resource = s5pc100_spi2_resource,
190 .dev = {
191 .dma_mask = &spi_dmamask,
192 .coherent_dma_mask = DMA_BIT_MASK(32),
193 .platform_data = &s5pc100_spi2_pdata,
194 },
195};
196
197void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
198{
199 struct s3c64xx_spi_info *pd;
200
201 /* Reject invalid configuration */
202 if (!num_cs || src_clk_nr < 0
203 || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
204 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
205 return;
206 }
207
208 switch (cntrlr) {
209 case 0:
210 pd = &s5pc100_spi0_pdata;
211 break;
212 case 1:
213 pd = &s5pc100_spi1_pdata;
214 break;
215 case 2:
216 pd = &s5pc100_spi2_pdata;
217 break;
218 default:
219 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
220 __func__, cntrlr);
221 return;
222 }
223
224 pd->num_cs = num_cs;
225 pd->src_clk_nr = src_clk_nr;
226 pd->src_clk_name = spi_src_clks[src_clk_nr];
227}
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index ccbe6b767f7d..54bc4f82e17a 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -100,6 +100,9 @@
100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG 100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY 101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
102#define S3C_PA_WDT S5PC100_PA_WATCHDOG 102#define S3C_PA_WDT S5PC100_PA_WATCHDOG
103#define S3C_PA_SPI0 S5PC100_PA_SPI0
104#define S3C_PA_SPI1 S5PC100_PA_SPI1
105#define S3C_PA_SPI2 S5PC100_PA_SPI2
103 106
104#define S5P_PA_CHIPID S5PC100_PA_CHIPID 107#define S5P_PA_CHIPID S5PC100_PA_CHIPID
105#define S5P_PA_FIMC0 S5PC100_PA_FIMC0 108#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
deleted file mode 100644
index 6418c6e8a7b7..000000000000
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
2 *
3 * Copyright 2008 Samsung Electronics
4 *
5 * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
6 *
7 * Based on mach-s3c6410/setup-sdhci.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/types.h>
15
16/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
17
18char *s5pc100_hsmmc_clksrcs[4] = {
19 [0] = "hsmmc", /* HCLK */
20 /* [1] = "hsmmc", - duplicate HCLK entry */
21 [2] = "sclk_mmc", /* mmc_bus */
22 /* [3] = "48m", - note not successfully used yet */
23};
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
new file mode 100644
index 000000000000..431a6f747caa
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -0,0 +1,65 @@
1/* linux/arch/arm/mach-s5pc100/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
19 .fifo_lvl_mask = 0x7f,
20 .rx_lvl_offset = 13,
21 .high_speed = 1,
22 .tx_st_done = 21,
23};
24
25int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
26{
27 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
28 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
29 return 0;
30}
31#endif
32
33#ifdef CONFIG_S3C64XX_DEV_SPI1
34struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
35 .fifo_lvl_mask = 0x7f,
36 .rx_lvl_offset = 13,
37 .high_speed = 1,
38 .tx_st_done = 21,
39};
40
41int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
42{
43 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
44 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
45 return 0;
46}
47#endif
48
49#ifdef CONFIG_S3C64XX_DEV_SPI2
50struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
51 .fifo_lvl_mask = 0x7f,
52 .rx_lvl_offset = 13,
53 .high_speed = 1,
54 .tx_st_done = 21,
55};
56
57int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
58{
59 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
60 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
61 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
62 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
63 return 0;
64}
65#endif
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 646057ab2e4c..2cdc42e838b8 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -60,6 +60,11 @@ config S5PV210_SETUP_FIMC
60 help 60 help
61 Common setup code for the camera interfaces. 61 Common setup code for the camera interfaces.
62 62
63config S5PV210_SETUP_SPI
64 bool
65 help
66 Common setup code for SPI GPIO configurations.
67
63menu "S5PC110 Machines" 68menu "S5PC110 Machines"
64 69
65config MACH_AQUILA 70config MACH_AQUILA
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 009fbe53df96..471df5d2d25c 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_MACH_TORBRECK) += mach-torbreck.o
27# device support 27# device support
28 28
29obj-y += dev-audio.o 29obj-y += dev-audio.o
30obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
31 30
32obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o 31obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
33obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o 32obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o
@@ -35,5 +34,5 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
35obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o 34obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
36obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o 35obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
37obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o 36obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o
38obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o
39obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 37obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
38obj-$(CONFIG_S5PV210_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 43a045d354ec..cead51321b29 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -399,30 +399,6 @@ static struct clk init_clocks_off[] = {
399 .enable = s5pv210_clk_ip1_ctrl, 399 .enable = s5pv210_clk_ip1_ctrl,
400 .ctrlbit = (1<<25), 400 .ctrlbit = (1<<25),
401 }, { 401 }, {
402 .name = "hsmmc",
403 .devname = "s3c-sdhci.0",
404 .parent = &clk_hclk_psys.clk,
405 .enable = s5pv210_clk_ip2_ctrl,
406 .ctrlbit = (1<<16),
407 }, {
408 .name = "hsmmc",
409 .devname = "s3c-sdhci.1",
410 .parent = &clk_hclk_psys.clk,
411 .enable = s5pv210_clk_ip2_ctrl,
412 .ctrlbit = (1<<17),
413 }, {
414 .name = "hsmmc",
415 .devname = "s3c-sdhci.2",
416 .parent = &clk_hclk_psys.clk,
417 .enable = s5pv210_clk_ip2_ctrl,
418 .ctrlbit = (1<<18),
419 }, {
420 .name = "hsmmc",
421 .devname = "s3c-sdhci.3",
422 .parent = &clk_hclk_psys.clk,
423 .enable = s5pv210_clk_ip2_ctrl,
424 .ctrlbit = (1<<19),
425 }, {
426 .name = "systimer", 402 .name = "systimer",
427 .parent = &clk_pclk_psys.clk, 403 .parent = &clk_pclk_psys.clk,
428 .enable = s5pv210_clk_ip3_ctrl, 404 .enable = s5pv210_clk_ip3_ctrl,
@@ -559,6 +535,38 @@ static struct clk init_clocks[] = {
559 }, 535 },
560}; 536};
561 537
538static struct clk clk_hsmmc0 = {
539 .name = "hsmmc",
540 .devname = "s3c-sdhci.0",
541 .parent = &clk_hclk_psys.clk,
542 .enable = s5pv210_clk_ip2_ctrl,
543 .ctrlbit = (1<<16),
544};
545
546static struct clk clk_hsmmc1 = {
547 .name = "hsmmc",
548 .devname = "s3c-sdhci.1",
549 .parent = &clk_hclk_psys.clk,
550 .enable = s5pv210_clk_ip2_ctrl,
551 .ctrlbit = (1<<17),
552};
553
554static struct clk clk_hsmmc2 = {
555 .name = "hsmmc",
556 .devname = "s3c-sdhci.2",
557 .parent = &clk_hclk_psys.clk,
558 .enable = s5pv210_clk_ip2_ctrl,
559 .ctrlbit = (1<<18),
560};
561
562static struct clk clk_hsmmc3 = {
563 .name = "hsmmc",
564 .devname = "s3c-sdhci.3",
565 .parent = &clk_hclk_psys.clk,
566 .enable = s5pv210_clk_ip2_ctrl,
567 .ctrlbit = (1<<19),
568};
569
562static struct clk *clkset_uart_list[] = { 570static struct clk *clkset_uart_list[] = {
563 [6] = &clk_mout_mpll.clk, 571 [6] = &clk_mout_mpll.clk,
564 [7] = &clk_mout_epll.clk, 572 [7] = &clk_mout_epll.clk,
@@ -866,46 +874,6 @@ static struct clksrc_clk clksrcs[] = {
866 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, 874 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
867 }, { 875 }, {
868 .clk = { 876 .clk = {
869 .name = "sclk_mmc",
870 .devname = "s3c-sdhci.0",
871 .enable = s5pv210_clk_mask0_ctrl,
872 .ctrlbit = (1 << 8),
873 },
874 .sources = &clkset_group2,
875 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
876 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
877 }, {
878 .clk = {
879 .name = "sclk_mmc",
880 .devname = "s3c-sdhci.1",
881 .enable = s5pv210_clk_mask0_ctrl,
882 .ctrlbit = (1 << 9),
883 },
884 .sources = &clkset_group2,
885 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
886 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
887 }, {
888 .clk = {
889 .name = "sclk_mmc",
890 .devname = "s3c-sdhci.2",
891 .enable = s5pv210_clk_mask0_ctrl,
892 .ctrlbit = (1 << 10),
893 },
894 .sources = &clkset_group2,
895 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
896 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
897 }, {
898 .clk = {
899 .name = "sclk_mmc",
900 .devname = "s3c-sdhci.3",
901 .enable = s5pv210_clk_mask0_ctrl,
902 .ctrlbit = (1 << 11),
903 },
904 .sources = &clkset_group2,
905 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
906 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
907 }, {
908 .clk = {
909 .name = "sclk_mfc", 877 .name = "sclk_mfc",
910 .devname = "s5p-mfc", 878 .devname = "s5p-mfc",
911 .enable = s5pv210_clk_ip0_ctrl, 879 .enable = s5pv210_clk_ip0_ctrl,
@@ -943,26 +911,6 @@ static struct clksrc_clk clksrcs[] = {
943 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, 911 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
944 }, { 912 }, {
945 .clk = { 913 .clk = {
946 .name = "sclk_spi",
947 .devname = "s3c64xx-spi.0",
948 .enable = s5pv210_clk_mask0_ctrl,
949 .ctrlbit = (1 << 16),
950 },
951 .sources = &clkset_group2,
952 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
953 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
954 }, {
955 .clk = {
956 .name = "sclk_spi",
957 .devname = "s3c64xx-spi.1",
958 .enable = s5pv210_clk_mask0_ctrl,
959 .ctrlbit = (1 << 17),
960 },
961 .sources = &clkset_group2,
962 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
963 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
964 }, {
965 .clk = {
966 .name = "sclk_pwi", 914 .name = "sclk_pwi",
967 .enable = s5pv210_clk_mask0_ctrl, 915 .enable = s5pv210_clk_mask0_ctrl,
968 .ctrlbit = (1 << 29), 916 .ctrlbit = (1 << 29),
@@ -1030,11 +978,97 @@ static struct clksrc_clk clk_sclk_uart3 = {
1030 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, 978 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
1031}; 979};
1032 980
981static struct clksrc_clk clk_sclk_mmc0 = {
982 .clk = {
983 .name = "sclk_mmc",
984 .devname = "s3c-sdhci.0",
985 .enable = s5pv210_clk_mask0_ctrl,
986 .ctrlbit = (1 << 8),
987 },
988 .sources = &clkset_group2,
989 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
990 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
991};
992
993static struct clksrc_clk clk_sclk_mmc1 = {
994 .clk = {
995 .name = "sclk_mmc",
996 .devname = "s3c-sdhci.1",
997 .enable = s5pv210_clk_mask0_ctrl,
998 .ctrlbit = (1 << 9),
999 },
1000 .sources = &clkset_group2,
1001 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1002 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1003};
1004
1005static struct clksrc_clk clk_sclk_mmc2 = {
1006 .clk = {
1007 .name = "sclk_mmc",
1008 .devname = "s3c-sdhci.2",
1009 .enable = s5pv210_clk_mask0_ctrl,
1010 .ctrlbit = (1 << 10),
1011 },
1012 .sources = &clkset_group2,
1013 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1014 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1015};
1016
1017static struct clksrc_clk clk_sclk_mmc3 = {
1018 .clk = {
1019 .name = "sclk_mmc",
1020 .devname = "s3c-sdhci.3",
1021 .enable = s5pv210_clk_mask0_ctrl,
1022 .ctrlbit = (1 << 11),
1023 },
1024 .sources = &clkset_group2,
1025 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1026 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1027};
1028
1029static struct clksrc_clk clk_sclk_spi0 = {
1030 .clk = {
1031 .name = "sclk_spi",
1032 .devname = "s3c64xx-spi.0",
1033 .enable = s5pv210_clk_mask0_ctrl,
1034 .ctrlbit = (1 << 16),
1035 },
1036 .sources = &clkset_group2,
1037 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
1038 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
1039 };
1040
1041static struct clksrc_clk clk_sclk_spi1 = {
1042 .clk = {
1043 .name = "sclk_spi",
1044 .devname = "s3c64xx-spi.1",
1045 .enable = s5pv210_clk_mask0_ctrl,
1046 .ctrlbit = (1 << 17),
1047 },
1048 .sources = &clkset_group2,
1049 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
1050 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1051 };
1052
1053
1033static struct clksrc_clk *clksrc_cdev[] = { 1054static struct clksrc_clk *clksrc_cdev[] = {
1034 &clk_sclk_uart0, 1055 &clk_sclk_uart0,
1035 &clk_sclk_uart1, 1056 &clk_sclk_uart1,
1036 &clk_sclk_uart2, 1057 &clk_sclk_uart2,
1037 &clk_sclk_uart3, 1058 &clk_sclk_uart3,
1059 &clk_sclk_mmc0,
1060 &clk_sclk_mmc1,
1061 &clk_sclk_mmc2,
1062 &clk_sclk_mmc3,
1063 &clk_sclk_spi0,
1064 &clk_sclk_spi1,
1065};
1066
1067static struct clk *clk_cdev[] = {
1068 &clk_hsmmc0,
1069 &clk_hsmmc1,
1070 &clk_hsmmc2,
1071 &clk_hsmmc3,
1038}; 1072};
1039 1073
1040/* Clock initialisation code */ 1074/* Clock initialisation code */
@@ -1282,6 +1316,17 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
1282 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), 1316 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1283 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), 1317 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1284 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), 1318 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1319 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1320 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1321 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1322 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1323 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1324 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1325 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1326 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1327 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1328 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
1329 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
1285}; 1330};
1286 1331
1287void __init s5pv210_register_clocks(void) 1332void __init s5pv210_register_clocks(void)
@@ -1306,6 +1351,10 @@ void __init s5pv210_register_clocks(void)
1306 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1351 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1307 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); 1352 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1308 1353
1354 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1355 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1356 s3c_disable_clocks(clk_cdev[ptr], 1);
1357
1309 s3c24xx_register_clock(&dummy_apb_pclk); 1358 s3c24xx_register_clock(&dummy_apb_pclk);
1310 s3c_pwmclk_init(); 1359 s3c_pwmclk_init();
1311} 1360}
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
deleted file mode 100644
index eaf9a7bff7a0..000000000000
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ /dev/null
@@ -1,175 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23static char *spi_src_clks[] = {
24 [S5PV210_SPI_SRCCLK_PCLK] = "pclk",
25 [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi",
26};
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
37{
38 unsigned int base;
39
40 switch (pdev->id) {
41 case 0:
42 base = S5PV210_GPB(0);
43 break;
44
45 case 1:
46 base = S5PV210_GPB(4);
47 break;
48
49 default:
50 dev_err(&pdev->dev, "Invalid SPI Controller number!");
51 return -EINVAL;
52 }
53
54 s3c_gpio_cfgall_range(base, 3,
55 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
56
57 return 0;
58}
59
60static struct resource s5pv210_spi0_resource[] = {
61 [0] = {
62 .start = S5PV210_PA_SPI0,
63 .end = S5PV210_PA_SPI0 + 0x100 - 1,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = DMACH_SPI0_TX,
68 .end = DMACH_SPI0_TX,
69 .flags = IORESOURCE_DMA,
70 },
71 [2] = {
72 .start = DMACH_SPI0_RX,
73 .end = DMACH_SPI0_RX,
74 .flags = IORESOURCE_DMA,
75 },
76 [3] = {
77 .start = IRQ_SPI0,
78 .end = IRQ_SPI0,
79 .flags = IORESOURCE_IRQ,
80 },
81};
82
83static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
84 .cfg_gpio = s5pv210_spi_cfg_gpio,
85 .fifo_lvl_mask = 0x1ff,
86 .rx_lvl_offset = 15,
87 .high_speed = 1,
88 .tx_st_done = 25,
89};
90
91static u64 spi_dmamask = DMA_BIT_MASK(32);
92
93struct platform_device s5pv210_device_spi0 = {
94 .name = "s3c64xx-spi",
95 .id = 0,
96 .num_resources = ARRAY_SIZE(s5pv210_spi0_resource),
97 .resource = s5pv210_spi0_resource,
98 .dev = {
99 .dma_mask = &spi_dmamask,
100 .coherent_dma_mask = DMA_BIT_MASK(32),
101 .platform_data = &s5pv210_spi0_pdata,
102 },
103};
104
105static struct resource s5pv210_spi1_resource[] = {
106 [0] = {
107 .start = S5PV210_PA_SPI1,
108 .end = S5PV210_PA_SPI1 + 0x100 - 1,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = DMACH_SPI1_TX,
113 .end = DMACH_SPI1_TX,
114 .flags = IORESOURCE_DMA,
115 },
116 [2] = {
117 .start = DMACH_SPI1_RX,
118 .end = DMACH_SPI1_RX,
119 .flags = IORESOURCE_DMA,
120 },
121 [3] = {
122 .start = IRQ_SPI1,
123 .end = IRQ_SPI1,
124 .flags = IORESOURCE_IRQ,
125 },
126};
127
128static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
129 .cfg_gpio = s5pv210_spi_cfg_gpio,
130 .fifo_lvl_mask = 0x7f,
131 .rx_lvl_offset = 15,
132 .high_speed = 1,
133 .tx_st_done = 25,
134};
135
136struct platform_device s5pv210_device_spi1 = {
137 .name = "s3c64xx-spi",
138 .id = 1,
139 .num_resources = ARRAY_SIZE(s5pv210_spi1_resource),
140 .resource = s5pv210_spi1_resource,
141 .dev = {
142 .dma_mask = &spi_dmamask,
143 .coherent_dma_mask = DMA_BIT_MASK(32),
144 .platform_data = &s5pv210_spi1_pdata,
145 },
146};
147
148void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
149{
150 struct s3c64xx_spi_info *pd;
151
152 /* Reject invalid configuration */
153 if (!num_cs || src_clk_nr < 0
154 || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) {
155 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
156 return;
157 }
158
159 switch (cntrlr) {
160 case 0:
161 pd = &s5pv210_spi0_pdata;
162 break;
163 case 1:
164 pd = &s5pv210_spi1_pdata;
165 break;
166 default:
167 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
168 __func__, cntrlr);
169 return;
170 }
171
172 pd->num_cs = num_cs;
173 pd->src_clk_nr = src_clk_nr;
174 pd->src_clk_name = spi_src_clks[src_clk_nr];
175}
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 7ff609f1568b..89c34b8f73bf 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -109,6 +109,8 @@
109#define S3C_PA_RTC S5PV210_PA_RTC 109#define S3C_PA_RTC S5PV210_PA_RTC
110#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG 110#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
111#define S3C_PA_WDT S5PV210_PA_WATCHDOG 111#define S3C_PA_WDT S5PV210_PA_WATCHDOG
112#define S3C_PA_SPI0 S5PV210_PA_SPI0
113#define S3C_PA_SPI1 S5PV210_PA_SPI1
112 114
113#define S5P_PA_CHIPID S5PV210_PA_CHIPID 115#define S5P_PA_CHIPID S5PV210_PA_CHIPID
114#define S5P_PA_FIMC0 S5PV210_PA_FIMC0 116#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
deleted file mode 100644
index 6b8ccc4d35fd..000000000000
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/* linux/arch/arm/mach-s5pv210/setup-sdhci.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/types.h>
14
15/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
16
17char *s5pv210_hsmmc_clksrcs[4] = {
18 [0] = "hsmmc", /* HCLK */
19 /* [1] = "hsmmc", - duplicate HCLK entry */
20 [2] = "sclk_mmc", /* mmc_bus */
21 /* [3] = NULL, - reserved */
22};
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
new file mode 100644
index 000000000000..f43c5048a37d
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -0,0 +1,51 @@
1/* linux/arch/arm/mach-s5pv210/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <linux/platform_device.h>
13
14#include <plat/gpio-cfg.h>
15#include <plat/s3c64xx-spi.h>
16
17#ifdef CONFIG_S3C64XX_DEV_SPI0
18struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
19 .fifo_lvl_mask = 0x1ff,
20 .rx_lvl_offset = 15,
21 .high_speed = 1,
22 .tx_st_done = 25,
23};
24
25int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
26{
27 s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
28 s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
29 s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,
30 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
31 return 0;
32}
33#endif
34
35#ifdef CONFIG_S3C64XX_DEV_SPI1
36struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
37 .fifo_lvl_mask = 0x7f,
38 .rx_lvl_offset = 15,
39 .high_speed = 1,
40 .tx_st_done = 25,
41};
42
43int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
44{
45 s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
46 s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
47 s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,
48 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
49 return 0;
50}
51#endif
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 4eab2cca2d92..95e68190d593 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -427,12 +427,6 @@ static struct clk init_clocks[] = {
427 .enable = s3c2443_clkcon_enable_h, 427 .enable = s3c2443_clkcon_enable_h,
428 .ctrlbit = S3C2443_HCLKCON_DMA5, 428 .ctrlbit = S3C2443_HCLKCON_DMA5,
429 }, { 429 }, {
430 .name = "hsmmc",
431 .devname = "s3c-sdhci.1",
432 .parent = &clk_h,
433 .enable = s3c2443_clkcon_enable_h,
434 .ctrlbit = S3C2443_HCLKCON_HSMMC,
435 }, {
436 .name = "gpio", 430 .name = "gpio",
437 .parent = &clk_p, 431 .parent = &clk_p,
438 .enable = s3c2443_clkcon_enable_p, 432 .enable = s3c2443_clkcon_enable_p,
@@ -514,6 +508,14 @@ static struct clk init_clocks[] = {
514 } 508 }
515}; 509};
516 510
511static struct clk hsmmc1_clk = {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.1",
514 .parent = &clk_h,
515 .enable = s3c2443_clkcon_enable_h,
516 .ctrlbit = S3C2443_HCLKCON_HSMMC,
517};
518
517static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) 519static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
518{ 520{
519 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; 521 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
@@ -579,6 +581,7 @@ static struct clk *clks[] __initdata = {
579 &clk_epll, 581 &clk_epll,
580 &clk_usb_bus, 582 &clk_usb_bus,
581 &clk_armdiv, 583 &clk_armdiv,
584 &hsmmc1_clk,
582}; 585};
583 586
584static struct clksrc_clk *clksrcs[] __initdata = { 587static struct clksrc_clk *clksrcs[] __initdata = {
@@ -595,6 +598,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
595 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), 598 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
596 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 599 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
597 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), 600 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
601 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
598}; 602};
599 603
600void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 604void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 313eb26cfa62..160eea15a6ef 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -226,11 +226,23 @@ config SAMSUNG_DEV_IDE
226 help 226 help
227 Compile in platform device definitions for IDE 227 Compile in platform device definitions for IDE
228 228
229config S3C64XX_DEV_SPI 229config S3C64XX_DEV_SPI0
230 bool 230 bool
231 help 231 help
232 Compile in platform device definitions for S3C64XX's type 232 Compile in platform device definitions for S3C64XX's type
233 SPI controllers. 233 SPI controller 0
234
235config S3C64XX_DEV_SPI1
236 bool
237 help
238 Compile in platform device definitions for S3C64XX's type
239 SPI controller 1
240
241config S3C64XX_DEV_SPI2
242 bool
243 help
244 Compile in platform device definitions for S3C64XX's type
245 SPI controller 2
234 246
235config SAMSUNG_DEV_TS 247config SAMSUNG_DEV_TS
236 bool 248 bool
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 4ca8b571f971..de0d88d6a0f1 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -61,6 +61,7 @@
61#include <plat/regs-iic.h> 61#include <plat/regs-iic.h>
62#include <plat/regs-serial.h> 62#include <plat/regs-serial.h>
63#include <plat/regs-spi.h> 63#include <plat/regs-spi.h>
64#include <plat/s3c64xx-spi.h>
64 65
65static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); 66static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
66 67
@@ -1461,3 +1462,129 @@ struct platform_device s3c_device_wdt = {
1461 .resource = s3c_wdt_resource, 1462 .resource = s3c_wdt_resource,
1462}; 1463};
1463#endif /* CONFIG_S3C_DEV_WDT */ 1464#endif /* CONFIG_S3C_DEV_WDT */
1465
1466#ifdef CONFIG_S3C64XX_DEV_SPI0
1467static struct resource s3c64xx_spi0_resource[] = {
1468 [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
1469 [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
1470 [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
1471 [3] = DEFINE_RES_IRQ(IRQ_SPI0),
1472};
1473
1474struct platform_device s3c64xx_device_spi0 = {
1475 .name = "s3c64xx-spi",
1476 .id = 0,
1477 .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
1478 .resource = s3c64xx_spi0_resource,
1479 .dev = {
1480 .dma_mask = &samsung_device_dma_mask,
1481 .coherent_dma_mask = DMA_BIT_MASK(32),
1482 },
1483};
1484
1485void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
1486 int src_clk_nr, int num_cs)
1487{
1488 if (!pd) {
1489 pr_err("%s:Need to pass platform data\n", __func__);
1490 return;
1491 }
1492
1493 /* Reject invalid configuration */
1494 if (!num_cs || src_clk_nr < 0) {
1495 pr_err("%s: Invalid SPI configuration\n", __func__);
1496 return;
1497 }
1498
1499 pd->num_cs = num_cs;
1500 pd->src_clk_nr = src_clk_nr;
1501 if (!pd->cfg_gpio)
1502 pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
1503
1504 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
1505}
1506#endif /* CONFIG_S3C64XX_DEV_SPI0 */
1507
1508#ifdef CONFIG_S3C64XX_DEV_SPI1
1509static struct resource s3c64xx_spi1_resource[] = {
1510 [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
1511 [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
1512 [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
1513 [3] = DEFINE_RES_IRQ(IRQ_SPI1),
1514};
1515
1516struct platform_device s3c64xx_device_spi1 = {
1517 .name = "s3c64xx-spi",
1518 .id = 1,
1519 .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
1520 .resource = s3c64xx_spi1_resource,
1521 .dev = {
1522 .dma_mask = &samsung_device_dma_mask,
1523 .coherent_dma_mask = DMA_BIT_MASK(32),
1524 },
1525};
1526
1527void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
1528 int src_clk_nr, int num_cs)
1529{
1530 if (!pd) {
1531 pr_err("%s:Need to pass platform data\n", __func__);
1532 return;
1533 }
1534
1535 /* Reject invalid configuration */
1536 if (!num_cs || src_clk_nr < 0) {
1537 pr_err("%s: Invalid SPI configuration\n", __func__);
1538 return;
1539 }
1540
1541 pd->num_cs = num_cs;
1542 pd->src_clk_nr = src_clk_nr;
1543 if (!pd->cfg_gpio)
1544 pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
1545
1546 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
1547}
1548#endif /* CONFIG_S3C64XX_DEV_SPI1 */
1549
1550#ifdef CONFIG_S3C64XX_DEV_SPI2
1551static struct resource s3c64xx_spi2_resource[] = {
1552 [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
1553 [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
1554 [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
1555 [3] = DEFINE_RES_IRQ(IRQ_SPI2),
1556};
1557
1558struct platform_device s3c64xx_device_spi2 = {
1559 .name = "s3c64xx-spi",
1560 .id = 2,
1561 .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
1562 .resource = s3c64xx_spi2_resource,
1563 .dev = {
1564 .dma_mask = &samsung_device_dma_mask,
1565 .coherent_dma_mask = DMA_BIT_MASK(32),
1566 },
1567};
1568
1569void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
1570 int src_clk_nr, int num_cs)
1571{
1572 if (!pd) {
1573 pr_err("%s:Need to pass platform data\n", __func__);
1574 return;
1575 }
1576
1577 /* Reject invalid configuration */
1578 if (!num_cs || src_clk_nr < 0) {
1579 pr_err("%s: Invalid SPI configuration\n", __func__);
1580 return;
1581 }
1582
1583 pd->num_cs = num_cs;
1584 pd->src_clk_nr = src_clk_nr;
1585 if (!pd->cfg_gpio)
1586 pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
1587
1588 s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
1589}
1590#endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index ab633c9c2aec..83b1e31696d9 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -39,6 +39,7 @@ extern struct platform_device s3c64xx_device_pcm0;
39extern struct platform_device s3c64xx_device_pcm1; 39extern struct platform_device s3c64xx_device_pcm1;
40extern struct platform_device s3c64xx_device_spi0; 40extern struct platform_device s3c64xx_device_spi0;
41extern struct platform_device s3c64xx_device_spi1; 41extern struct platform_device s3c64xx_device_spi1;
42extern struct platform_device s3c64xx_device_spi2;
42 43
43extern struct platform_device s3c_device_adc; 44extern struct platform_device s3c_device_adc;
44extern struct platform_device s3c_device_cfcon; 45extern struct platform_device s3c_device_cfcon;
@@ -98,8 +99,6 @@ extern struct platform_device s5p6450_device_iis1;
98extern struct platform_device s5p6450_device_iis2; 99extern struct platform_device s5p6450_device_iis2;
99extern struct platform_device s5p6450_device_pcm0; 100extern struct platform_device s5p6450_device_pcm0;
100 101
101extern struct platform_device s5p64x0_device_spi0;
102extern struct platform_device s5p64x0_device_spi1;
103 102
104extern struct platform_device s5pc100_device_ac97; 103extern struct platform_device s5pc100_device_ac97;
105extern struct platform_device s5pc100_device_iis0; 104extern struct platform_device s5pc100_device_iis0;
@@ -108,9 +107,6 @@ extern struct platform_device s5pc100_device_iis2;
108extern struct platform_device s5pc100_device_pcm0; 107extern struct platform_device s5pc100_device_pcm0;
109extern struct platform_device s5pc100_device_pcm1; 108extern struct platform_device s5pc100_device_pcm1;
110extern struct platform_device s5pc100_device_spdif; 109extern struct platform_device s5pc100_device_spdif;
111extern struct platform_device s5pc100_device_spi0;
112extern struct platform_device s5pc100_device_spi1;
113extern struct platform_device s5pc100_device_spi2;
114 110
115extern struct platform_device s5pv210_device_ac97; 111extern struct platform_device s5pv210_device_ac97;
116extern struct platform_device s5pv210_device_iis0; 112extern struct platform_device s5pv210_device_iis0;
@@ -120,8 +116,6 @@ extern struct platform_device s5pv210_device_pcm0;
120extern struct platform_device s5pv210_device_pcm1; 116extern struct platform_device s5pv210_device_pcm1;
121extern struct platform_device s5pv210_device_pcm2; 117extern struct platform_device s5pv210_device_pcm2;
122extern struct platform_device s5pv210_device_spdif; 118extern struct platform_device s5pv210_device_spdif;
123extern struct platform_device s5pv210_device_spi0;
124extern struct platform_device s5pv210_device_spi1;
125 119
126extern struct platform_device exynos4_device_ac97; 120extern struct platform_device exynos4_device_ac97;
127extern struct platform_device exynos4_device_ahci; 121extern struct platform_device exynos4_device_ahci;
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4c16fa3621bb..aea68b60ef98 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -31,7 +31,6 @@ struct s3c64xx_spi_csinfo {
31/** 31/**
32 * struct s3c64xx_spi_info - SPI Controller defining structure 32 * struct s3c64xx_spi_info - SPI Controller defining structure
33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. 33 * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
34 * @src_clk_name: Platform name of the corresponding clock.
35 * @clk_from_cmu: If the SPI clock/prescalar control block is present 34 * @clk_from_cmu: If the SPI clock/prescalar control block is present
36 * by the platform's clock-management-unit and not in SPI controller. 35 * by the platform's clock-management-unit and not in SPI controller.
37 * @num_cs: Number of CS this controller emulates. 36 * @num_cs: Number of CS this controller emulates.
@@ -43,7 +42,6 @@ struct s3c64xx_spi_csinfo {
43 */ 42 */
44struct s3c64xx_spi_info { 43struct s3c64xx_spi_info {
45 int src_clk_nr; 44 int src_clk_nr;
46 char *src_clk_name;
47 bool clk_from_cmu; 45 bool clk_from_cmu;
48 46
49 int num_cs; 47 int num_cs;
@@ -58,18 +56,28 @@ struct s3c64xx_spi_info {
58}; 56};
59 57
60/** 58/**
61 * s3c64xx_spi_set_info - SPI Controller configure callback by the board 59 * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
62 * initialization code. 60 * initialization code.
63 * @cntrlr: SPI controller number the configuration is for. 61 * @pd: SPI platform data to set.
64 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. 62 * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
65 * @num_cs: Number of elements in the 'cs' array. 63 * @num_cs: Number of elements in the 'cs' array.
66 * 64 *
67 * Call this from machine init code for each SPI Controller that 65 * Call this from machine init code for each SPI Controller that
68 * has some chips attached to it. 66 * has some chips attached to it.
69 */ 67 */
70extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 68extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
71extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 69 int src_clk_nr, int num_cs);
72extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 70extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
73extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 71 int src_clk_nr, int num_cs);
72extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
73 int src_clk_nr, int num_cs);
74 74
75/* defined by architecture to configure gpio */
76extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
77extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
78extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
79
80extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
81extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
82extern struct s3c64xx_spi_info s3c64xx_spi2_pdata;
75#endif /* __S3C64XX_PLAT_SPI_H */ 83#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index e7b3c752e919..dcff7dd1ae8a 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -66,8 +66,6 @@ struct s3c_sdhci_platdata {
66 enum cd_types cd_type; 66 enum cd_types cd_type;
67 enum clk_types clk_type; 67 enum clk_types clk_type;
68 68
69 char **clocks; /* set of clock sources */
70
71 int ext_cd_gpio; 69 int ext_cd_gpio;
72 bool ext_cd_gpio_invert; 70 bool ext_cd_gpio_invert;
73 int (*ext_cd_init)(void (*notify_func)(struct platform_device *, 71 int (*ext_cd_init)(void (*notify_func)(struct platform_device *,
@@ -129,12 +127,9 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
129/* S3C2416 SDHCI setup */ 127/* S3C2416 SDHCI setup */
130 128
131#ifdef CONFIG_S3C2416_SETUP_SDHCI 129#ifdef CONFIG_S3C2416_SETUP_SDHCI
132extern char *s3c2416_hsmmc_clksrcs[4];
133
134static inline void s3c2416_default_sdhci0(void) 130static inline void s3c2416_default_sdhci0(void)
135{ 131{
136#ifdef CONFIG_S3C_DEV_HSMMC 132#ifdef CONFIG_S3C_DEV_HSMMC
137 s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
138 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; 133 s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
139#endif /* CONFIG_S3C_DEV_HSMMC */ 134#endif /* CONFIG_S3C_DEV_HSMMC */
140} 135}
@@ -142,7 +137,6 @@ static inline void s3c2416_default_sdhci0(void)
142static inline void s3c2416_default_sdhci1(void) 137static inline void s3c2416_default_sdhci1(void)
143{ 138{
144#ifdef CONFIG_S3C_DEV_HSMMC1 139#ifdef CONFIG_S3C_DEV_HSMMC1
145 s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
146 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; 140 s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
147#endif /* CONFIG_S3C_DEV_HSMMC1 */ 141#endif /* CONFIG_S3C_DEV_HSMMC1 */
148} 142}
@@ -155,12 +149,9 @@ static inline void s3c2416_default_sdhci1(void) { }
155/* S3C64XX SDHCI setup */ 149/* S3C64XX SDHCI setup */
156 150
157#ifdef CONFIG_S3C64XX_SETUP_SDHCI 151#ifdef CONFIG_S3C64XX_SETUP_SDHCI
158extern char *s3c64xx_hsmmc_clksrcs[4];
159
160static inline void s3c6400_default_sdhci0(void) 152static inline void s3c6400_default_sdhci0(void)
161{ 153{
162#ifdef CONFIG_S3C_DEV_HSMMC 154#ifdef CONFIG_S3C_DEV_HSMMC
163 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
164 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 155 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
165#endif 156#endif
166} 157}
@@ -168,7 +159,6 @@ static inline void s3c6400_default_sdhci0(void)
168static inline void s3c6400_default_sdhci1(void) 159static inline void s3c6400_default_sdhci1(void)
169{ 160{
170#ifdef CONFIG_S3C_DEV_HSMMC1 161#ifdef CONFIG_S3C_DEV_HSMMC1
171 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
172 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 162 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
173#endif 163#endif
174} 164}
@@ -176,7 +166,6 @@ static inline void s3c6400_default_sdhci1(void)
176static inline void s3c6400_default_sdhci2(void) 166static inline void s3c6400_default_sdhci2(void)
177{ 167{
178#ifdef CONFIG_S3C_DEV_HSMMC2 168#ifdef CONFIG_S3C_DEV_HSMMC2
179 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
180 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 169 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
181#endif 170#endif
182} 171}
@@ -184,7 +173,6 @@ static inline void s3c6400_default_sdhci2(void)
184static inline void s3c6410_default_sdhci0(void) 173static inline void s3c6410_default_sdhci0(void)
185{ 174{
186#ifdef CONFIG_S3C_DEV_HSMMC 175#ifdef CONFIG_S3C_DEV_HSMMC
187 s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
188 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; 176 s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
189#endif 177#endif
190} 178}
@@ -192,7 +180,6 @@ static inline void s3c6410_default_sdhci0(void)
192static inline void s3c6410_default_sdhci1(void) 180static inline void s3c6410_default_sdhci1(void)
193{ 181{
194#ifdef CONFIG_S3C_DEV_HSMMC1 182#ifdef CONFIG_S3C_DEV_HSMMC1
195 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
196 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; 183 s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
197#endif 184#endif
198} 185}
@@ -200,7 +187,6 @@ static inline void s3c6410_default_sdhci1(void)
200static inline void s3c6410_default_sdhci2(void) 187static inline void s3c6410_default_sdhci2(void)
201{ 188{
202#ifdef CONFIG_S3C_DEV_HSMMC2 189#ifdef CONFIG_S3C_DEV_HSMMC2
203 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs;
204 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; 190 s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
205#endif 191#endif
206} 192}
@@ -218,12 +204,9 @@ static inline void s3c6400_default_sdhci2(void) { }
218/* S5PC100 SDHCI setup */ 204/* S5PC100 SDHCI setup */
219 205
220#ifdef CONFIG_S5PC100_SETUP_SDHCI 206#ifdef CONFIG_S5PC100_SETUP_SDHCI
221extern char *s5pc100_hsmmc_clksrcs[4];
222
223static inline void s5pc100_default_sdhci0(void) 207static inline void s5pc100_default_sdhci0(void)
224{ 208{
225#ifdef CONFIG_S3C_DEV_HSMMC 209#ifdef CONFIG_S3C_DEV_HSMMC
226 s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
227 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; 210 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
228#endif 211#endif
229} 212}
@@ -231,7 +214,6 @@ static inline void s5pc100_default_sdhci0(void)
231static inline void s5pc100_default_sdhci1(void) 214static inline void s5pc100_default_sdhci1(void)
232{ 215{
233#ifdef CONFIG_S3C_DEV_HSMMC1 216#ifdef CONFIG_S3C_DEV_HSMMC1
234 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
235 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; 217 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
236#endif 218#endif
237} 219}
@@ -239,7 +221,6 @@ static inline void s5pc100_default_sdhci1(void)
239static inline void s5pc100_default_sdhci2(void) 221static inline void s5pc100_default_sdhci2(void)
240{ 222{
241#ifdef CONFIG_S3C_DEV_HSMMC2 223#ifdef CONFIG_S3C_DEV_HSMMC2
242 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
243 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; 224 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
244#endif 225#endif
245} 226}
@@ -254,12 +235,9 @@ static inline void s5pc100_default_sdhci2(void) { }
254/* S5PV210 SDHCI setup */ 235/* S5PV210 SDHCI setup */
255 236
256#ifdef CONFIG_S5PV210_SETUP_SDHCI 237#ifdef CONFIG_S5PV210_SETUP_SDHCI
257extern char *s5pv210_hsmmc_clksrcs[4];
258
259static inline void s5pv210_default_sdhci0(void) 238static inline void s5pv210_default_sdhci0(void)
260{ 239{
261#ifdef CONFIG_S3C_DEV_HSMMC 240#ifdef CONFIG_S3C_DEV_HSMMC
262 s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
263 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; 241 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio;
264#endif 242#endif
265} 243}
@@ -267,7 +245,6 @@ static inline void s5pv210_default_sdhci0(void)
267static inline void s5pv210_default_sdhci1(void) 245static inline void s5pv210_default_sdhci1(void)
268{ 246{
269#ifdef CONFIG_S3C_DEV_HSMMC1 247#ifdef CONFIG_S3C_DEV_HSMMC1
270 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
271 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; 248 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio;
272#endif 249#endif
273} 250}
@@ -275,7 +252,6 @@ static inline void s5pv210_default_sdhci1(void)
275static inline void s5pv210_default_sdhci2(void) 252static inline void s5pv210_default_sdhci2(void)
276{ 253{
277#ifdef CONFIG_S3C_DEV_HSMMC2 254#ifdef CONFIG_S3C_DEV_HSMMC2
278 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
279 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; 255 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio;
280#endif 256#endif
281} 257}
@@ -283,7 +259,6 @@ static inline void s5pv210_default_sdhci2(void)
283static inline void s5pv210_default_sdhci3(void) 259static inline void s5pv210_default_sdhci3(void)
284{ 260{
285#ifdef CONFIG_S3C_DEV_HSMMC3 261#ifdef CONFIG_S3C_DEV_HSMMC3
286 s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
287 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; 262 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
288#endif 263#endif
289} 264}
@@ -298,12 +273,9 @@ static inline void s5pv210_default_sdhci3(void) { }
298 273
299/* EXYNOS4 SDHCI setup */ 274/* EXYNOS4 SDHCI setup */
300#ifdef CONFIG_EXYNOS4_SETUP_SDHCI 275#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
301extern char *exynos4_hsmmc_clksrcs[4];
302
303static inline void exynos4_default_sdhci0(void) 276static inline void exynos4_default_sdhci0(void)
304{ 277{
305#ifdef CONFIG_S3C_DEV_HSMMC 278#ifdef CONFIG_S3C_DEV_HSMMC
306 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
307 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; 279 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
308#endif 280#endif
309} 281}
@@ -311,7 +283,6 @@ static inline void exynos4_default_sdhci0(void)
311static inline void exynos4_default_sdhci1(void) 283static inline void exynos4_default_sdhci1(void)
312{ 284{
313#ifdef CONFIG_S3C_DEV_HSMMC1 285#ifdef CONFIG_S3C_DEV_HSMMC1
314 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
315 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; 286 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
316#endif 287#endif
317} 288}
@@ -319,7 +290,6 @@ static inline void exynos4_default_sdhci1(void)
319static inline void exynos4_default_sdhci2(void) 290static inline void exynos4_default_sdhci2(void)
320{ 291{
321#ifdef CONFIG_S3C_DEV_HSMMC2 292#ifdef CONFIG_S3C_DEV_HSMMC2
322 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
323 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; 293 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
324#endif 294#endif
325} 295}
@@ -327,7 +297,6 @@ static inline void exynos4_default_sdhci2(void)
327static inline void exynos4_default_sdhci3(void) 297static inline void exynos4_default_sdhci3(void)
328{ 298{
329#ifdef CONFIG_S3C_DEV_HSMMC3 299#ifdef CONFIG_S3C_DEV_HSMMC3
330 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
331 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; 300 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
332#endif 301#endif
333} 302}
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index cb60c4197e0a..6b3f3664edeb 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -435,14 +435,11 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
435 435
436 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { 436 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
437 struct clk *clk; 437 struct clk *clk;
438 char *name = pdata->clocks[ptr]; 438 char name[14];
439
440 if (name == NULL)
441 continue;
442 439
440 snprintf(name, 14, "mmc_busclk.%d", ptr);
443 clk = clk_get(dev, name); 441 clk = clk_get(dev, name);
444 if (IS_ERR(clk)) { 442 if (IS_ERR(clk)) {
445 dev_err(dev, "failed to get clock %s\n", name);
446 continue; 443 continue;
447 } 444 }
448 445
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 019a7163572f..dcf7e1006426 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -971,6 +971,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
971 struct s3c64xx_spi_info *sci; 971 struct s3c64xx_spi_info *sci;
972 struct spi_master *master; 972 struct spi_master *master;
973 int ret; 973 int ret;
974 char clk_name[16];
974 975
975 if (pdev->id < 0) { 976 if (pdev->id < 0) {
976 dev_err(&pdev->dev, 977 dev_err(&pdev->dev,
@@ -984,11 +985,6 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
984 } 985 }
985 986
986 sci = pdev->dev.platform_data; 987 sci = pdev->dev.platform_data;
987 if (!sci->src_clk_name) {
988 dev_err(&pdev->dev,
989 "Board init must call s3c64xx_spi_set_info()\n");
990 return -EINVAL;
991 }
992 988
993 /* Check for availability of necessary resource */ 989 /* Check for availability of necessary resource */
994 990
@@ -1073,17 +1069,17 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev)
1073 goto err4; 1069 goto err4;
1074 } 1070 }
1075 1071
1076 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name); 1072 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1073 sdd->src_clk = clk_get(&pdev->dev, clk_name);
1077 if (IS_ERR(sdd->src_clk)) { 1074 if (IS_ERR(sdd->src_clk)) {
1078 dev_err(&pdev->dev, 1075 dev_err(&pdev->dev,
1079 "Unable to acquire clock '%s'\n", sci->src_clk_name); 1076 "Unable to acquire clock '%s'\n", clk_name);
1080 ret = PTR_ERR(sdd->src_clk); 1077 ret = PTR_ERR(sdd->src_clk);
1081 goto err5; 1078 goto err5;
1082 } 1079 }
1083 1080
1084 if (clk_enable(sdd->src_clk)) { 1081 if (clk_enable(sdd->src_clk)) {
1085 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", 1082 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1086 sci->src_clk_name);
1087 ret = -EBUSY; 1083 ret = -EBUSY;
1088 goto err6; 1084 goto err6;
1089 } 1085 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 02:23:46 -0500