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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-21 15:47:53 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-21 15:47:53 -0400
commit8e95a53ba4b060e2d0d46575059ae96ea91a80fd (patch)
treec5e2cacf18475cb3f3b8fdfaa6223d24c37849e1
parentcd975ae0ce13e4cbb21f13ae1222bdb6a8996ba0 (diff)
parent672552adb3197c5db3acc8800c7917bcff180461 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lliubbo/blackfin
Pull blackfin changes from Bob Liu: "The biggest change was added an new processor(bf60x series). Bf60x series processor of blackfin can up to 1GHz with Hardware Support for HD Video Analytics, it use the same blackfin ISA but with some changes on system buses, interrupt controller and peripheral devices. Added dir arch/blackfin/mach-bf609/ and did some changes to the framework made linux working fine on the reference board bf609-ezkit now." * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lliubbo/blackfin: (41 commits) blackfin: fix build after add bf60x mach/pm.h blackfin: twi: include linux/i2c.h blackfin: bf60x: add head file for crc controller blackfin: bf60x: twi: work around temporary anomaly 0501001 blackfin: twi: Move TWI MMR access macro to twi head file blackfin: twi: Move TWI peripheral pin request array to platform data blackfin: bf60x: anomaly: Add a temporary anomaly 0501001 blackfin: bf60x: Rename the DDR controller macro blackfin: mach-bf609: pm: cleanup bfin_deepsleep blackfin: bf60x: cleanup get clock code blackfin: bf60x: pm: Add a debug option to calculate kernel wakeup time. blackfin: bf60x: add wakeup source select blackfin: bf60x: make clock changeable in kernel menuconfig blackfin:mach-bf609: fix norflash for bf609-ezkit blackfin: mach-bf609: add can_wakeup to ethernet device blackfin: remove redundant CONFIG_BF60x macro blackfin: rotary: Add pm_wakeup flag to platform data structure. bfin_gpio: fix bf548-ezkit kernel fail to boot bfin_dma: fix initcall return error in proc_dma_init() Blackfin: delete fork func ...
Diffstat
-rw-r--r--arch/blackfin/ADI_BSD.txt41
-rw-r--r--arch/blackfin/Clear_BSD.txt33
-rw-r--r--arch/blackfin/Kconfig184
-rw-r--r--arch/blackfin/Kconfig.debug7
-rw-r--r--arch/blackfin/Makefile2
-rw-r--r--arch/blackfin/configs/BF561-EZKIT-SMP_defconfig4
-rw-r--r--arch/blackfin/configs/BF609-EZKIT_defconfig155
-rw-r--r--arch/blackfin/include/asm/bfin-global.h5
-rw-r--r--arch/blackfin/include/asm/bfin6xx_spi.h258
-rw-r--r--arch/blackfin/include/asm/bfin_crc.h139
-rw-r--r--arch/blackfin/include/asm/bfin_dma.h84
-rw-r--r--arch/blackfin/include/asm/bfin_pfmon.h2
-rw-r--r--arch/blackfin/include/asm/bfin_ppi.h128
-rw-r--r--arch/blackfin/include/asm/bfin_rotary.h1
-rw-r--r--arch/blackfin/include/asm/bfin_serial.h182
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h1
-rw-r--r--arch/blackfin/include/asm/bfin_sport3.h107
-rw-r--r--arch/blackfin/include/asm/bfin_twi.h142
-rw-r--r--arch/blackfin/include/asm/blackfin.h8
-rw-r--r--arch/blackfin/include/asm/clkdev.h14
-rw-r--r--arch/blackfin/include/asm/clocks.h23
-rw-r--r--arch/blackfin/include/asm/cplb.h4
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h6
-rw-r--r--arch/blackfin/include/asm/dma.h137
-rw-r--r--arch/blackfin/include/asm/dpmc.h656
-rw-r--r--arch/blackfin/include/asm/fixed_code.h30
-rw-r--r--arch/blackfin/include/asm/gpio.h44
-rw-r--r--arch/blackfin/include/asm/gptimers.h104
-rw-r--r--arch/blackfin/include/asm/irqflags.h6
-rw-r--r--arch/blackfin/include/asm/page.h5
-rw-r--r--arch/blackfin/include/asm/pda.h2
-rw-r--r--arch/blackfin/include/asm/pm.h31
-rw-r--r--arch/blackfin/include/asm/unistd.h2
-rw-r--r--arch/blackfin/kernel/bfin_dma.c146
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c28
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c4
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbmgr.c6
-rw-r--r--arch/blackfin/kernel/debug-mmrs.c9
-rw-r--r--arch/blackfin/kernel/entry.S10
-rw-r--r--arch/blackfin/kernel/gptimers.c85
-rw-r--r--arch/blackfin/kernel/process.c8
-rw-r--r--arch/blackfin/kernel/reboot.c6
-rw-r--r--arch/blackfin/kernel/setup.c132
-rw-r--r--arch/blackfin/kernel/shadow_console.c6
-rw-r--r--arch/blackfin/kernel/time-ts.c27
-rw-r--r--arch/blackfin/lib/divsi3.S2
-rw-r--r--arch/blackfin/lib/memchr.S2
-rw-r--r--arch/blackfin/lib/memcmp.S2
-rw-r--r--arch/blackfin/lib/memcpy.S2
-rw-r--r--arch/blackfin/lib/memmove.S2
-rw-r--r--arch/blackfin/lib/memset.S2
-rw-r--r--arch/blackfin/lib/modsi3.S2
-rw-r--r--arch/blackfin/lib/muldi3.S2
-rw-r--r--arch/blackfin/lib/smulsi3_highpart.S2
-rw-r--r--arch/blackfin/lib/strcmp.S2
-rw-r--r--arch/blackfin/lib/strcpy.S2
-rw-r--r--arch/blackfin/lib/strncmp.S2
-rw-r--r--arch/blackfin/lib/strncpy.S2
-rw-r--r--arch/blackfin/lib/udivsi3.S2
-rw-r--r--arch/blackfin/lib/umodsi3.S2
-rw-r--r--arch/blackfin/lib/umulsi3_highpart.S2
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c5
-rw-r--r--arch/blackfin/mach-bf518/boards/tcm-bf518.c5
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h3
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF512.h2
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF514.h2
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF516.h2
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF518.h2
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF512.h73
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF514.h2
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF516.h2
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF518.h2
-rw-r--r--arch/blackfin/mach-bf527/boards/ad7160eval.c6
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c5
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c5
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c6
-rw-r--r--arch/blackfin/mach-bf527/boards/tll6527m.c5
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h3
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF522.h73
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF525.h2
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF527.h2
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h3
-rw-r--r--arch/blackfin/mach-bf533/include/mach/defBF532.h2
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537e.c5
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537u.c5
-rw-r--r--arch/blackfin/mach-bf537/boards/dnp5370.c5
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c5
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c66
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c5
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h3
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h71
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF537.h2
-rw-r--r--arch/blackfin/mach-bf538/boards/ezkit.c8
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h3
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF538.h78
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h2
-rw-r--r--arch/blackfin/mach-bf548/boards/cm_bf548.c10
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c11
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h3
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF542.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF544.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF548.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF549.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h111
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h3
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h2
-rw-r--r--arch/blackfin/mach-bf609/Kconfig56
-rw-r--r--arch/blackfin/mach-bf609/Makefile6
-rw-r--r--arch/blackfin/mach-bf609/boards/Kconfig12
-rw-r--r--arch/blackfin/mach-bf609/boards/Makefile5
-rw-r--r--arch/blackfin/mach-bf609/boards/ezkit.c1340
-rw-r--r--arch/blackfin/mach-bf609/clock.c390
-rw-r--r--arch/blackfin/mach-bf609/dma.c202
-rw-r--r--arch/blackfin/mach-bf609/hibernate.S65
-rw-r--r--arch/blackfin/mach-bf609/include/mach/anomaly.h130
-rw-r--r--arch/blackfin/mach-bf609/include/mach/bf609.h93
-rw-r--r--arch/blackfin/mach-bf609/include/mach/bfin_serial.h17
-rw-r--r--arch/blackfin/mach-bf609/include/mach/blackfin.h25
-rw-r--r--arch/blackfin/mach-bf609/include/mach/cdefBF609.h15
-rw-r--r--arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h3252
-rw-r--r--arch/blackfin/mach-bf609/include/mach/defBF609.h15
-rw-r--r--arch/blackfin/mach-bf609/include/mach/defBF60x_base.h3587
-rw-r--r--arch/blackfin/mach-bf609/include/mach/dma.h116
-rw-r--r--arch/blackfin/mach-bf609/include/mach/gpio.h171
-rw-r--r--arch/blackfin/mach-bf609/include/mach/irq.h318
-rw-r--r--arch/blackfin/mach-bf609/include/mach/mem_map.h86
-rw-r--r--arch/blackfin/mach-bf609/include/mach/pll.h1
-rw-r--r--arch/blackfin/mach-bf609/include/mach/pm.h21
-rw-r--r--arch/blackfin/mach-bf609/include/mach/portmux.h347
-rw-r--r--arch/blackfin/mach-bf609/pm.c362
-rw-r--r--arch/blackfin/mach-common/Makefile5
-rw-r--r--arch/blackfin/mach-common/clock.h27
-rw-r--r--arch/blackfin/mach-common/clocks-init.c153
-rw-r--r--arch/blackfin/mach-common/cpufreq.c46
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S606
-rw-r--r--arch/blackfin/mach-common/entry.S5
-rw-r--r--arch/blackfin/mach-common/head.S2
-rw-r--r--arch/blackfin/mach-common/ints-priority.c423
-rw-r--r--arch/blackfin/mach-common/pm.c62
-rw-r--r--arch/blackfin/mm/init.c14
-rw-r--r--arch/blackfin/mm/sram-alloc.c36
142 files changed, 14357 insertions, 1320 deletions
diff --git a/arch/blackfin/ADI_BSD.txt b/arch/blackfin/ADI_BSD.txt
deleted file mode 100644
index 501d0b645943..000000000000
--- a/arch/blackfin/ADI_BSD.txt
+++ /dev/null
@@ -1,41 +0,0 @@
1This BSD-Style License applies to a few files in ./arch/blackfin directory,
2and is included here, so people understand which code they can use outside
3the Linux kernel, in non-GPL based projects.
4
5Using the files released under the "ADI BSD" license, must comply with
6these license terms.
7
8--------------------------------------------------------------------------
9
10Copyright Analog Devices, Inc.
11
12All rights reserved.
13
14Redistribution and use in source and binary forms, with or without
15modification, are permitted provided that the following conditions
16are met:
17 - Redistributions of source code must retain the above copyright
18 notice, this list of conditions and the following disclaimer.
19 - Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in
21 the documentation and/or other materials provided with the
22 distribution.
23 - Neither the name of Analog Devices, Inc. nor the names of its
24 contributors may be used to endorse or promote products derived
25 from this software without specific prior written permission.
26 - The use of this software may or may not infringe the patent rights
27 of one or more patent holders. This license does not release you
28 from the requirement that you obtain separate licenses from these
29 patent holders to use this software.
30
31THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
32IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
33MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
34IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
35INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF
37SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
38BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
39WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
40OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
41ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
diff --git a/arch/blackfin/Clear_BSD.txt b/arch/blackfin/Clear_BSD.txt
new file mode 100644
index 000000000000..bfa4b378a368
--- /dev/null
+++ b/arch/blackfin/Clear_BSD.txt
@@ -0,0 +1,33 @@
1The Clear BSD license:
2
3Copyright (c) 2012, Analog Devices, Inc. All rights reserved.
4
5Redistribution and use in source and binary forms, with or without
6modification, are permitted (subject to the limitations in the
7disclaimer below) provided that the following conditions are met:
8
9* Redistributions of source code must retain the above copyright
10 notice, this list of conditions and the following disclaimer.
11
12* Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the
15 distribution.
16
17* Neither the name of Analog Devices, Inc. nor the names of its
18 contributors may be used to endorse or promote products derived
19 from this software without specific prior written permission.
20
21NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 373a6902d8fa..383e7ecda923 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -226,6 +226,12 @@ config BF561
226 help 226 help
227 BF561 Processor Support. 227 BF561 Processor Support.
228 228
229config BF609
230 bool "BF609"
231 select CLKDEV_LOOKUP
232 help
233 BF609 Processor Support.
234
229endchoice 235endchoice
230 236
231config SMP 237config SMP
@@ -251,27 +257,27 @@ config HOTPLUG_CPU
251 257
252config BF_REV_MIN 258config BF_REV_MIN
253 int 259 int
254 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) 260 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
255 default 2 if (BF537 || BF536 || BF534) 261 default 2 if (BF537 || BF536 || BF534)
256 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) 262 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
257 default 4 if (BF538 || BF539) 263 default 4 if (BF538 || BF539)
258 264
259config BF_REV_MAX 265config BF_REV_MAX
260 int 266 int
261 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) 267 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
262 default 3 if (BF537 || BF536 || BF534 || BF54xM) 268 default 3 if (BF537 || BF536 || BF534 || BF54xM)
263 default 5 if (BF561 || BF538 || BF539) 269 default 5 if (BF561 || BF538 || BF539)
264 default 6 if (BF533 || BF532 || BF531) 270 default 6 if (BF533 || BF532 || BF531)
265 271
266choice 272choice
267 prompt "Silicon Rev" 273 prompt "Silicon Rev"
268 default BF_REV_0_0 if (BF51x || BF52x) 274 default BF_REV_0_0 if (BF51x || BF52x || BF60x)
269 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) 275 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
270 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) 276 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
271 277
272config BF_REV_0_0 278config BF_REV_0_0
273 bool "0.0" 279 bool "0.0"
274 depends on (BF51x || BF52x || (BF54x && !BF54xM)) 280 depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
275 281
276config BF_REV_0_1 282config BF_REV_0_1
277 bool "0.1" 283 bool "0.1"
@@ -350,6 +356,7 @@ source "arch/blackfin/mach-bf561/Kconfig"
350source "arch/blackfin/mach-bf537/Kconfig" 356source "arch/blackfin/mach-bf537/Kconfig"
351source "arch/blackfin/mach-bf538/Kconfig" 357source "arch/blackfin/mach-bf538/Kconfig"
352source "arch/blackfin/mach-bf548/Kconfig" 358source "arch/blackfin/mach-bf548/Kconfig"
359source "arch/blackfin/mach-bf609/Kconfig"
353 360
354menu "Board customizations" 361menu "Board customizations"
355 362
@@ -379,6 +386,12 @@ config BOOT_LOAD
379 memory region is used to capture NULL pointer references as well 386 memory region is used to capture NULL pointer references as well
380 as some core kernel functions. 387 as some core kernel functions.
381 388
389config PHY_RAM_BASE_ADDRESS
390 hex "Physical RAM Base"
391 default 0x0
392 help
393 set BF609 FPGA physical SRAM base address
394
382config ROM_BASE 395config ROM_BASE
383 hex "Kernel ROM Base" 396 hex "Kernel ROM Base"
384 depends on ROMKERNEL 397 depends on ROMKERNEL
@@ -422,7 +435,7 @@ config BFIN_KERNEL_CLOCK
422 435
423config PLL_BYPASS 436config PLL_BYPASS
424 bool "Bypass PLL" 437 bool "Bypass PLL"
425 depends on BFIN_KERNEL_CLOCK 438 depends on BFIN_KERNEL_CLOCK && (!BF60x)
426 default n 439 default n
427 440
428config CLKIN_HALF 441config CLKIN_HALF
@@ -441,7 +454,7 @@ config VCO_MULT
441 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) 454 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
442 default "22" if BFIN533_BLUETECHNIX_CM 455 default "22" if BFIN533_BLUETECHNIX_CM
443 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 456 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
444 default "20" if BFIN561_EZKIT 457 default "20" if (BFIN561_EZKIT || BF609)
445 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) 458 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
446 default "25" if BFIN527_AD7160EVAL 459 default "25" if BFIN527_AD7160EVAL
447 help 460 help
@@ -473,12 +486,45 @@ config SCLK_DIV
473 int "System Clock Divider" 486 int "System Clock Divider"
474 depends on BFIN_KERNEL_CLOCK 487 depends on BFIN_KERNEL_CLOCK
475 range 1 15 488 range 1 15
476 default 5 489 default 4
477 help 490 help
478 This sets the frequency of the system clock (including SDRAM or DDR). 491 This sets the frequency of the system clock (including SDRAM or DDR) on
492 !BF60x else it set the clock for system buses and provides the
493 source from which SCLK0 and SCLK1 are derived.
479 This can be between 1 and 15 494 This can be between 1 and 15
480 System Clock = (PLL frequency) / (this setting) 495 System Clock = (PLL frequency) / (this setting)
481 496
497config SCLK0_DIV
498 int "System Clock0 Divider"
499 depends on BFIN_KERNEL_CLOCK && BF60x
500 range 1 15
501 default 1
502 help
503 This sets the frequency of the system clock0 for PVP and all other
504 peripherals not clocked by SCLK1.
505 This can be between 1 and 15
506 System Clock0 = (System Clock) / (this setting)
507
508config SCLK1_DIV
509 int "System Clock1 Divider"
510 depends on BFIN_KERNEL_CLOCK && BF60x
511 range 1 15
512 default 1
513 help
514 This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
515 This can be between 1 and 15
516 System Clock1 = (System Clock) / (this setting)
517
518config DCLK_DIV
519 int "DDR Clock Divider"
520 depends on BFIN_KERNEL_CLOCK && BF60x
521 range 1 15
522 default 2
523 help
524 This sets the frequency of the DDR memory.
525 This can be between 1 and 15
526 DDR Clock = (PLL frequency) / (this setting)
527
482choice 528choice
483 prompt "DDR SDRAM Chip Type" 529 prompt "DDR SDRAM Chip Type"
484 depends on BFIN_KERNEL_CLOCK 530 depends on BFIN_KERNEL_CLOCK
@@ -494,7 +540,7 @@ endchoice
494 540
495choice 541choice
496 prompt "DDR/SDRAM Timing" 542 prompt "DDR/SDRAM Timing"
497 depends on BFIN_KERNEL_CLOCK 543 depends on BFIN_KERNEL_CLOCK && !BF60x
498 default BFIN_KERNEL_CLOCK_MEMINIT_CALC 544 default BFIN_KERNEL_CLOCK_MEMINIT_CALC
499 help 545 help
500 This option allows you to specify Blackfin SDRAM/DDR Timing parameters 546 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
@@ -576,6 +622,7 @@ config MAX_VCO_HZ
576 default 600000000 if BF548 622 default 600000000 if BF548
577 default 533333333 if BF549 623 default 533333333 if BF549
578 default 600000000 if BF561 624 default 600000000 if BF561
625 default 800000000 if BF609
579 626
580config MIN_VCO_HZ 627config MIN_VCO_HZ
581 int 628 int
@@ -583,6 +630,7 @@ config MIN_VCO_HZ
583 630
584config MAX_SCLK_HZ 631config MAX_SCLK_HZ
585 int 632 int
633 default 200000000 if BF609
586 default 133333333 634 default 133333333
587 635
588config MIN_SCLK_HZ 636config MIN_SCLK_HZ
@@ -1051,7 +1099,7 @@ endchoice
1051config BFIN_L2_DCACHEABLE 1099config BFIN_L2_DCACHEABLE
1052 bool "Enable DCACHE for L2 SRAM" 1100 bool "Enable DCACHE for L2 SRAM"
1053 depends on BFIN_DCACHE 1101 depends on BFIN_DCACHE
1054 depends on (BF54x || BF561) && !SMP 1102 depends on (BF54x || BF561 || BF60x) && !SMP
1055 default n 1103 default n
1056choice 1104choice
1057 prompt "L2 SRAM DCACHE policy" 1105 prompt "L2 SRAM DCACHE policy"
@@ -1077,6 +1125,7 @@ config MPU
1077comment "Asynchronous Memory Configuration" 1125comment "Asynchronous Memory Configuration"
1078 1126
1079menu "EBIU_AMGCTL Global Control" 1127menu "EBIU_AMGCTL Global Control"
1128 depends on !BF60x
1080config C_AMCKEN 1129config C_AMCKEN
1081 bool "Enable CLKOUT" 1130 bool "Enable CLKOUT"
1082 default y 1131 default y
@@ -1127,6 +1176,7 @@ endchoice
1127endmenu 1176endmenu
1128 1177
1129menu "EBIU_AMBCTL Control" 1178menu "EBIU_AMBCTL Control"
1179 depends on !BF60x
1130config BANK_0 1180config BANK_0
1131 hex "Bank 0 (AMBCTL0.L)" 1181 hex "Bank 0 (AMBCTL0.L)"
1132 default 0x7BB0 1182 default 0x7BB0
@@ -1206,7 +1256,7 @@ config ARCH_SUSPEND_POSSIBLE
1206 1256
1207choice 1257choice
1208 prompt "Standby Power Saving Mode" 1258 prompt "Standby Power Saving Mode"
1209 depends on PM 1259 depends on PM && !BF60x
1210 default PM_BFIN_SLEEP_DEEPER 1260 default PM_BFIN_SLEEP_DEEPER
1211config PM_BFIN_SLEEP_DEEPER 1261config PM_BFIN_SLEEP_DEEPER
1212 bool "Sleep Deeper" 1262 bool "Sleep Deeper"
@@ -1261,6 +1311,118 @@ config PM_BFIN_WAKE_GP
1261 On ADSP-BF549 this option enables the the same functionality on the 1311 On ADSP-BF549 this option enables the the same functionality on the
1262 /MRXON pin also PH7. 1312 /MRXON pin also PH7.
1263 1313
1314config PM_BFIN_WAKE_PA15
1315 bool "Allow Wake-Up from PA15"
1316 depends on PM && BF60x
1317 default n
1318 help
1319 Enable PA15 Wake-Up
1320
1321config PM_BFIN_WAKE_PA15_POL
1322 int "Wake-up priority"
1323 depends on PM_BFIN_WAKE_PA15
1324 default 0
1325 help
1326 Wake-Up priority 0(low) 1(high)
1327
1328config PM_BFIN_WAKE_PB15
1329 bool "Allow Wake-Up from PB15"
1330 depends on PM && BF60x
1331 default n
1332 help
1333 Enable PB15 Wake-Up
1334
1335config PM_BFIN_WAKE_PB15_POL
1336 int "Wake-up priority"
1337 depends on PM_BFIN_WAKE_PB15
1338 default 0
1339 help
1340 Wake-Up priority 0(low) 1(high)
1341
1342config PM_BFIN_WAKE_PC15
1343 bool "Allow Wake-Up from PC15"
1344 depends on PM && BF60x
1345 default n
1346 help
1347 Enable PC15 Wake-Up
1348
1349config PM_BFIN_WAKE_PC15_POL
1350 int "Wake-up priority"
1351 depends on PM_BFIN_WAKE_PC15
1352 default 0
1353 help
1354 Wake-Up priority 0(low) 1(high)
1355
1356config PM_BFIN_WAKE_PD06
1357 bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
1358 depends on PM && BF60x
1359 default n
1360 help
1361 Enable PD06(ETH0_PHYINT) Wake-up
1362
1363config PM_BFIN_WAKE_PD06_POL
1364 int "Wake-up priority"
1365 depends on PM_BFIN_WAKE_PD06
1366 default 0
1367 help
1368 Wake-Up priority 0(low) 1(high)
1369
1370config PM_BFIN_WAKE_PE12
1371 bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
1372 depends on PM && BF60x
1373 default n
1374 help
1375 Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
1376
1377config PM_BFIN_WAKE_PE12_POL
1378 int "Wake-up priority"
1379 depends on PM_BFIN_WAKE_PE12
1380 default 0
1381 help
1382 Wake-Up priority 0(low) 1(high)
1383
1384config PM_BFIN_WAKE_PG04
1385 bool "Allow Wake-Up from PG04(CAN0_RX)"
1386 depends on PM && BF60x
1387 default n
1388 help
1389 Enable PG04(CAN0_RX) Wake-up
1390
1391config PM_BFIN_WAKE_PG04_POL
1392 int "Wake-up priority"
1393 depends on PM_BFIN_WAKE_PG04
1394 default 0
1395 help
1396 Wake-Up priority 0(low) 1(high)
1397
1398config PM_BFIN_WAKE_PG13
1399 bool "Allow Wake-Up from PG13"
1400 depends on PM && BF60x
1401 default n
1402 help
1403 Enable PG13 Wake-Up
1404
1405config PM_BFIN_WAKE_PG13_POL
1406 int "Wake-up priority"
1407 depends on PM_BFIN_WAKE_PG13
1408 default 0
1409 help
1410 Wake-Up priority 0(low) 1(high)
1411
1412config PM_BFIN_WAKE_USB
1413 bool "Allow Wake-Up from (USB)"
1414 depends on PM && BF60x
1415 default n
1416 help
1417 Enable (USB) Wake-up
1418
1419config PM_BFIN_WAKE_USB_POL
1420 int "Wake-up priority"
1421 depends on PM_BFIN_WAKE_USB
1422 default 0
1423 help
1424 Wake-Up priority 0(low) 1(high)
1425
1264endmenu 1426endmenu
1265 1427
1266menu "CPU Frequency scaling" 1428menu "CPU Frequency scaling"
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index e2a3d4c8ab9a..79594694ee90 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -253,4 +253,11 @@ config BFIN_PSEUDODBG_INSNS
253 253
254 Most people should say N here. 254 Most people should say N here.
255 255
256config BFIN_PM_WAKEUP_TIME_BENCH
257 bool "Display the total time for kernel to resume from power saving mode"
258 default n
259 help
260 Display the total time when kernel resumes normal from standby or
261 suspend to mem mode.
262
256endmenu 263endmenu
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 46f42b2066e5..74fdf679da01 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -54,6 +54,7 @@ machine-$(CONFIG_BF548M) := bf548
54machine-$(CONFIG_BF549) := bf548 54machine-$(CONFIG_BF549) := bf548
55machine-$(CONFIG_BF549M) := bf548 55machine-$(CONFIG_BF549M) := bf548
56machine-$(CONFIG_BF561) := bf561 56machine-$(CONFIG_BF561) := bf561
57machine-$(CONFIG_BF609) := bf609
57MACHINE := $(machine-y) 58MACHINE := $(machine-y)
58export MACHINE 59export MACHINE
59 60
@@ -86,6 +87,7 @@ cpu-$(CONFIG_BF548M) := bf548m
86cpu-$(CONFIG_BF549) := bf549 87cpu-$(CONFIG_BF549) := bf549
87cpu-$(CONFIG_BF549M) := bf549m 88cpu-$(CONFIG_BF549M) := bf549m
88cpu-$(CONFIG_BF561) := bf561 89cpu-$(CONFIG_BF561) := bf561
90cpu-$(CONFIG_BF609) := bf609
89 91
90rev-$(CONFIG_BF_REV_0_0) := 0.0 92rev-$(CONFIG_BF_REV_0_0) := 0.0
91rev-$(CONFIG_BF_REV_0_1) := 0.1 93rev-$(CONFIG_BF_REV_0_1) := 0.1
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
index 680730eeaf23..e2a2fa5935ce 100644
--- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
@@ -21,14 +21,12 @@ CONFIG_MODULE_UNLOAD=y
21# CONFIG_IOSCHED_CFQ is not set 21# CONFIG_IOSCHED_CFQ is not set
22CONFIG_PREEMPT_VOLUNTARY=y 22CONFIG_PREEMPT_VOLUNTARY=y
23CONFIG_BF561=y 23CONFIG_BF561=y
24CONFIG_SMP=y
24CONFIG_IRQ_TIMER0=10 25CONFIG_IRQ_TIMER0=10
25CONFIG_CLKIN_HZ=30000000 26CONFIG_CLKIN_HZ=30000000
26CONFIG_HIGH_RES_TIMERS=y 27CONFIG_HIGH_RES_TIMERS=y
27CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 28CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
28CONFIG_BFIN_GPTIMERS=m 29CONFIG_BFIN_GPTIMERS=m
29CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
30CONFIG_BFIN_L2_DCACHEABLE=y
31CONFIG_BFIN_L2_WRITETHROUGH=y
32CONFIG_C_CDPRIO=y 30CONFIG_C_CDPRIO=y
33CONFIG_BANK_3=0xAAC2 31CONFIG_BANK_3=0xAAC2
34CONFIG_BINFMT_FLAT=y 32CONFIG_BINFMT_FLAT=y
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig
new file mode 100644
index 000000000000..be9526bee4fb
--- /dev/null
+++ b/arch/blackfin/configs/BF609-EZKIT_defconfig
@@ -0,0 +1,155 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=14
6CONFIG_BLK_DEV_INITRD=y
7CONFIG_EXPERT=y
8# CONFIG_ELF_CORE is not set
9# CONFIG_FUTEX is not set
10# CONFIG_SIGNALFD is not set
11# CONFIG_TIMERFD is not set
12# CONFIG_EVENTFD is not set
13# CONFIG_AIO is not set
14CONFIG_SLAB=y
15CONFIG_MMAP_ALLOW_UNINITIALIZED=y
16CONFIG_MODULES=y
17CONFIG_MODULE_UNLOAD=y
18# CONFIG_LBDAF is not set
19# CONFIG_BLK_DEV_BSG is not set
20# CONFIG_IOSCHED_DEADLINE is not set
21# CONFIG_IOSCHED_CFQ is not set
22CONFIG_PREEMPT_VOLUNTARY=y
23CONFIG_BF609=y
24CONFIG_PINT1_ASSIGN=0x01010000
25CONFIG_PINT2_ASSIGN=0x07000101
26CONFIG_PINT3_ASSIGN=0x02020303
27CONFIG_HIGH_RES_TIMERS=y
28CONFIG_IP_CHECKSUM_L1=y
29CONFIG_SYSCALL_TAB_L1=y
30CONFIG_CPLB_SWITCH_TAB_L1=y
31# CONFIG_APP_STACK_L1 is not set
32# CONFIG_BFIN_INS_LOWOVERHEAD is not set
33CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
34CONFIG_BINFMT_FLAT=y
35CONFIG_BINFMT_ZFLAT=y
36CONFIG_PM_BFIN_WAKE_PE12=y
37CONFIG_PM_BFIN_WAKE_PE12_POL=1
38CONFIG_CPU_FREQ=y
39CONFIG_CPU_FREQ_GOV_POWERSAVE=y
40CONFIG_CPU_FREQ_GOV_ONDEMAND=y
41CONFIG_NET=y
42CONFIG_PACKET=y
43CONFIG_UNIX=y
44CONFIG_INET=y
45CONFIG_IP_PNP=y
46CONFIG_IP_PNP_DHCP=y
47CONFIG_IP_PNP_BOOTP=y
48CONFIG_IP_PNP_RARP=y
49# CONFIG_IPV6 is not set
50CONFIG_NETFILTER=y
51CONFIG_CAN=y
52CONFIG_CAN_BFIN=y
53CONFIG_IRDA=y
54CONFIG_IRTTY_SIR=y
55# CONFIG_WIRELESS is not set
56CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
57CONFIG_FW_LOADER=m
58CONFIG_MTD=y
59CONFIG_MTD_CMDLINE_PARTS=y
60CONFIG_MTD_CHAR=y
61CONFIG_MTD_BLOCK=y
62CONFIG_MTD_CFI=y
63CONFIG_MTD_CFI_INTELEXT=y
64CONFIG_MTD_CFI_STAA=y
65CONFIG_MTD_COMPLEX_MAPPINGS=y
66CONFIG_MTD_PHYSMAP=y
67CONFIG_MTD_M25P80=y
68CONFIG_MTD_UBI=m
69CONFIG_SCSI=y
70CONFIG_BLK_DEV_SD=y
71CONFIG_NETDEVICES=y
72# CONFIG_NET_VENDOR_BROADCOM is not set
73# CONFIG_NET_VENDOR_CHELSIO is not set
74# CONFIG_NET_VENDOR_INTEL is not set
75# CONFIG_NET_VENDOR_MARVELL is not set
76# CONFIG_NET_VENDOR_MICREL is not set
77# CONFIG_NET_VENDOR_MICROCHIP is not set
78# CONFIG_NET_VENDOR_NATSEMI is not set
79# CONFIG_NET_VENDOR_SEEQ is not set
80# CONFIG_NET_VENDOR_SMSC is not set
81CONFIG_STMMAC_ETH=y
82CONFIG_STMMAC_IEEE1588=y
83# CONFIG_WLAN is not set
84# CONFIG_INPUT_MOUSEDEV is not set
85CONFIG_INPUT_EVDEV=y
86# CONFIG_INPUT_KEYBOARD is not set
87# CONFIG_INPUT_MOUSE is not set
88CONFIG_INPUT_MISC=y
89CONFIG_INPUT_BFIN_ROTARY=y
90# CONFIG_SERIO is not set
91# CONFIG_LEGACY_PTYS is not set
92CONFIG_BFIN_SIMPLE_TIMER=m
93CONFIG_BFIN_LINKPORT=y
94# CONFIG_DEVKMEM is not set
95CONFIG_SERIAL_BFIN=y
96CONFIG_SERIAL_BFIN_CONSOLE=y
97CONFIG_SERIAL_BFIN_UART0=y
98# CONFIG_HW_RANDOM is not set
99CONFIG_I2C=y
100CONFIG_I2C_CHARDEV=y
101CONFIG_I2C_BLACKFIN_TWI=y
102CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
103CONFIG_SPI=y
104CONFIG_SPI_BFIN6XX=y
105CONFIG_GPIOLIB=y
106CONFIG_GPIO_SYSFS=y
107# CONFIG_HWMON is not set
108CONFIG_WATCHDOG=y
109CONFIG_BFIN_WDT=y
110CONFIG_SOUND=m
111CONFIG_SND=m
112CONFIG_SND_MIXER_OSS=m
113CONFIG_SND_PCM_OSS=m
114# CONFIG_SND_DRIVERS is not set
115# CONFIG_SND_SPI is not set
116# CONFIG_SND_USB is not set
117CONFIG_SND_SOC=m
118CONFIG_SND_BF6XX_I2S=m
119CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61=m
120CONFIG_SND_SOC_ALL_CODECS=m
121CONFIG_USB=y
122CONFIG_USB_MUSB_HDRC=y
123CONFIG_USB_MUSB_BLACKFIN=m
124CONFIG_USB_STORAGE=y
125CONFIG_USB_GADGET=y
126CONFIG_USB_GADGET_MUSB_HDRC=y
127CONFIG_USB_ZERO=y
128CONFIG_MMC=y
129CONFIG_SDH_BFIN=y
130# CONFIG_IOMMU_SUPPORT is not set
131CONFIG_EXT2_FS=y
132# CONFIG_DNOTIFY is not set
133CONFIG_MSDOS_FS=y
134CONFIG_VFAT_FS=y
135CONFIG_JFFS2_FS=m
136CONFIG_UBIFS_FS=m
137CONFIG_NFS_FS=m
138CONFIG_NFS_V3=y
139CONFIG_NLS_CODEPAGE_437=y
140CONFIG_NLS_ISO8859_1=y
141CONFIG_DEBUG_FS=y
142CONFIG_DEBUG_SHIRQ=y
143CONFIG_DETECT_HUNG_TASK=y
144CONFIG_DEBUG_INFO=y
145CONFIG_FRAME_POINTER=y
146# CONFIG_FTRACE is not set
147CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
148CONFIG_EARLY_PRINTK=y
149CONFIG_CPLB_INFO=y
150CONFIG_BFIN_PSEUDODBG_INSNS=y
151CONFIG_CRYPTO_HMAC=y
152CONFIG_CRYPTO_MD4=y
153CONFIG_CRYPTO_MD5=y
154CONFIG_CRYPTO_ARC4=y
155# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 17bcbf60bcae..608be5e6d25c 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -35,6 +35,11 @@ extern void bfin_setup_cpudata(unsigned int cpu);
35 35
36extern unsigned long get_cclk(void); 36extern unsigned long get_cclk(void);
37extern unsigned long get_sclk(void); 37extern unsigned long get_sclk(void);
38#ifdef CONFIG_BF60x
39extern unsigned long get_sclk0(void);
40extern unsigned long get_sclk1(void);
41extern unsigned long get_dclk(void);
42#endif
38extern unsigned long sclk_to_usecs(unsigned long sclk); 43extern unsigned long sclk_to_usecs(unsigned long sclk);
39extern unsigned long usecs_to_sclk(unsigned long usecs); 44extern unsigned long usecs_to_sclk(unsigned long usecs);
40 45
diff --git a/arch/blackfin/include/asm/bfin6xx_spi.h b/arch/blackfin/include/asm/bfin6xx_spi.h
new file mode 100644
index 000000000000..89370b653dcd
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin6xx_spi.h
@@ -0,0 +1,258 @@
1/*
2 * Analog Devices SPI3 controller driver
3 *
4 * Copyright (c) 2011 Analog Devices Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef _SPI_CHANNEL_H_
21#define _SPI_CHANNEL_H_
22
23#include <linux/types.h>
24
25/* SPI_CONTROL */
26#define SPI_CTL_EN 0x00000001 /* Enable */
27#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */
28#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */
29#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */
30#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */
31#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */
32#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */
33#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */
34#define SPI_CTL_EMISO 0x00000100 /* Enable MISO */
35#define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */
36#define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */
37#define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */
38#define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */
39#define SPI_CTL_LSBF 0x00001000 /* LSB First */
40#define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */
41#define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */
42#define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */
43#define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */
44#define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */
45#define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
46#define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
47#define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */
48#define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */
49#define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */
50#define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */
51#define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */
52#define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */
53/* SPI_RX_CONTROL */
54#define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */
55#define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */
56#define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */
57#define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */
58#define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */
59#define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */
60#define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */
61#define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */
62#define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */
63#define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */
64#define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */
65#define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */
66#define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */
67#define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */
68#define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */
69#define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */
70#define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */
71#define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */
72#define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */
73#define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */
74#define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */
75#define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */
76/* SPI_TX_CONTROL */
77#define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */
78#define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */
79#define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */
80#define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */
81#define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */
82#define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */
83#define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */
84#define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */
85#define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */
86#define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */
87#define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */
88#define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */
89#define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */
90#define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */
91#define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */
92#define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */
93#define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */
94#define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */
95#define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */
96#define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */
97#define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */
98#define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */
99/* SPI_CLOCK */
100#define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */
101/* SPI_DELAY */
102#define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */
103#define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */
104#define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */
105/* SPI_SSEL */
106#define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */
107#define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */
108#define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */
109#define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */
110#define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */
111#define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */
112#define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */
113#define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */
114#define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */
115#define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */
116#define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */
117#define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */
118#define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */
119#define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */
120/* SPI_RWC */
121#define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */
122/* SPI_RWCR */
123#define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */
124/* SPI_TWC */
125#define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */
126/* SPI_TWCR */
127#define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */
128/* SPI_IMASK */
129#define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
130#define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
131#define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
132#define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
133#define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
134#define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
135#define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */
136#define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */
137#define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */
138#define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
139/* SPI_IMASKCL */
140#define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
141#define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
142#define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
143#define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
144#define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
145#define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
146#define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */
147#define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */
148#define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */
149#define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
150/* SPI_IMASKST */
151#define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
152#define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
153#define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
154#define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
155#define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
156#define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
157#define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */
158#define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */
159#define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */
160#define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
161/* SPI_STATUS */
162#define SPI_STAT_SPIF 0x00000001 /* SPI Finished */
163#define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */
164#define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */
165#define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */
166#define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */
167#define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */
168#define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */
169#define SPI_STAT_RS 0x00000100 /* Receive Start Indication */
170#define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */
171#define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */
172#define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */
173#define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */
174#define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */
175#define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */
176#define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */
177#define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */
178#define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */
179#define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */
180#define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */
181#define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */
182#define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */
183#define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */
184#define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */
185#define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */
186#define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */
187#define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */
188/* SPI_ILAT */
189#define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
190#define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
191#define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */
192#define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */
193#define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */
194#define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */
195#define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */
196#define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */
197#define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */
198#define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */
199/* SPI_ILATCL */
200#define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
201#define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
202#define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */
203#define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */
204#define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */
205#define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */
206#define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */
207#define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */
208#define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */
209#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */
210
211/*
212 * bfin spi3 registers layout
213 */
214struct bfin_spi_regs {
215 u32 revid;
216 u32 control;
217 u32 rx_control;
218 u32 tx_control;
219 u32 clock;
220 u32 delay;
221 u32 ssel;
222 u32 rwc;
223 u32 rwcr;
224 u32 twc;
225 u32 twcr;
226 u32 reserved0;
227 u32 emask;
228 u32 emaskcl;
229 u32 emaskst;
230 u32 reserved1;
231 u32 status;
232 u32 elat;
233 u32 elatcl;
234 u32 reserved2;
235 u32 rfifo;
236 u32 reserved3;
237 u32 tfifo;
238};
239
240#define MAX_CTRL_CS 8 /* cs in spi controller */
241
242/* device.platform_data for SSP controller devices */
243struct bfin6xx_spi_master {
244 u16 num_chipselect;
245 u16 pin_req[7];
246};
247
248/* spi_board_info.controller_data for SPI slave devices,
249 * copied to spi_device.platform_data ... mostly for dma tuning
250 */
251struct bfin6xx_spi_chip {
252 u32 control;
253 u16 cs_chg_udelay; /* Some devices require 16-bit delays */
254 u32 tx_dummy_val; /* tx value for rx only transfer */
255 bool enable_dma;
256};
257
258#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h
new file mode 100644
index 000000000000..3deb4452ceed
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_crc.h
@@ -0,0 +1,139 @@
1/*
2 * bfin_crc.h - interface to Blackfin CRC controllers
3 *
4 * Copyright 2012 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_CRC_H__
10#define __BFIN_CRC_H__
11
12/* Function driver which use hardware crc must initialize the structure */
13struct crc_info {
14 /* Input data address */
15 unsigned char *in_addr;
16 /* Output data address */
17 unsigned char *out_addr;
18 /* Input or output bytes */
19 unsigned long datasize;
20 union {
21 /* CRC to compare with that of input buffer */
22 unsigned long crc_compare;
23 /* Value to compare with input data */
24 unsigned long val_verify;
25 /* Value to fill */
26 unsigned long val_fill;
27 };
28 /* Value to program the 32b CRC Polynomial */
29 unsigned long crc_poly;
30 union {
31 /* CRC calculated from the input data */
32 unsigned long crc_result;
33 /* First failed position to verify input data */
34 unsigned long pos_verify;
35 };
36 /* CRC mirror flags */
37 unsigned int bitmirr:1;
38 unsigned int bytmirr:1;
39 unsigned int w16swp:1;
40 unsigned int fdsel:1;
41 unsigned int rsltmirr:1;
42 unsigned int polymirr:1;
43 unsigned int cmpmirr:1;
44};
45
46/* Userspace interface */
47#define CRC_IOC_MAGIC 'C'
48#define CRC_IOC_CALC_CRC _IOWR('C', 0x01, unsigned int)
49#define CRC_IOC_MEMCPY_CRC _IOWR('C', 0x02, unsigned int)
50#define CRC_IOC_VERIFY_VAL _IOWR('C', 0x03, unsigned int)
51#define CRC_IOC_FILL_VAL _IOWR('C', 0x04, unsigned int)
52
53
54#ifdef __KERNEL__
55
56#include <linux/types.h>
57#include <linux/spinlock.h>
58#include <linux/miscdevice.h>
59
60struct crc_register {
61 u32 control;
62 u32 datacnt;
63 u32 datacntrld;
64 u32 __pad_1[2];
65 u32 compare;
66 u32 fillval;
67 u32 datafifo;
68 u32 intren;
69 u32 intrenset;
70 u32 intrenclr;
71 u32 poly;
72 u32 __pad_2[4];
73 u32 status;
74 u32 datacntcap;
75 u32 __pad_3;
76 u32 result;
77 u32 curresult;
78 u32 __pad_4[3];
79 u32 revid;
80};
81
82struct bfin_crc {
83 struct miscdevice mdev;
84 struct list_head list;
85 int irq;
86 int dma_ch_src;
87 int dma_ch_dest;
88 volatile struct crc_register *regs;
89 struct crc_info *info;
90 struct mutex mutex;
91 struct completion c;
92 unsigned short opmode;
93 char name[20];
94};
95
96/* CRC_STATUS Masks */
97#define CMPERR 0x00000002 /* Compare error */
98#define DCNTEXP 0x00000010 /* datacnt register expired */
99#define IBR 0x00010000 /* Input buffer ready */
100#define OBR 0x00020000 /* Output buffer ready */
101#define IRR 0x00040000 /* Immediate result readt */
102#define LUTDONE 0x00080000 /* Look-up table generation done */
103#define FSTAT 0x00700000 /* FIFO status */
104#define MAX_FIFO 4 /* Max fifo size */
105
106/* CRC_CONTROL Masks */
107#define BLKEN 0x00000001 /* Block enable */
108#define OPMODE 0x000000F0 /* Operation mode */
109#define OPMODE_OFFSET 4 /* Operation mode mask offset*/
110#define MODE_DMACPY_CRC 1 /* MTM CRC compute and compare */
111#define MODE_DATA_FILL 2 /* MTM data fill */
112#define MODE_CALC_CRC 3 /* MSM CRC compute and compare */
113#define MODE_DATA_VERIFY 4 /* MSM data verify */
114#define AUTOCLRZ 0x00000100 /* Auto clear to zero */
115#define AUTOCLRF 0x00000200 /* Auto clear to one */
116#define OBRSTALL 0x00001000 /* Stall on output buffer ready */
117#define IRRSTALL 0x00002000 /* Stall on immediate result ready */
118#define BITMIRR 0x00010000 /* Mirror bits within each byte of 32-bit input data */
119#define BITMIRR_OFFSET 16 /* Mirror bits offset */
120#define BYTMIRR 0x00020000 /* Mirror bytes of 32-bit input data */
121#define BYTMIRR_OFFSET 17 /* Mirror bytes offset */
122#define W16SWP 0x00040000 /* Mirror uppper and lower 16-bit word of 32-bit input data */
123#define W16SWP_OFFSET 18 /* Mirror 16-bit word offset */
124#define FDSEL 0x00080000 /* FIFO is written after input data is mirrored */
125#define FDSEL_OFFSET 19 /* Mirror FIFO offset */
126#define RSLTMIRR 0x00100000 /* CRC result registers are mirrored. */
127#define RSLTMIRR_OFFSET 20 /* Mirror CRC result offset. */
128#define POLYMIRR 0x00200000 /* CRC poly register is mirrored. */
129#define POLYMIRR_OFFSET 21 /* Mirror CRC poly offset. */
130#define CMPMIRR 0x00400000 /* CRC compare register is mirrored. */
131#define CMPMIRR_OFFSET 22 /* Mirror CRC compare offset. */
132
133/* CRC_INTREN Masks */
134#define CMPERRI 0x02 /* CRC_ERROR_INTR */
135#define DCNTEXPI 0x10 /* CRC_STATUS_INTR */
136
137#endif
138
139#endif
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
index d51120744148..6319f4e49083 100644
--- a/arch/blackfin/include/asm/bfin_dma.h
+++ b/arch/blackfin/include/asm/bfin_dma.h
@@ -15,12 +15,55 @@
15#define DMAEN 0x0001 /* DMA Channel Enable */ 15#define DMAEN 0x0001 /* DMA Channel Enable */
16#define WNR 0x0002 /* Channel Direction (W/R*) */ 16#define WNR 0x0002 /* Channel Direction (W/R*) */
17#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ 17#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
18#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
19
20#ifdef CONFIG_BF60x
21
22#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
23#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
24#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
25#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
26#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
27#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
28#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
29#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
30#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
31#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
32#define DI_EN_X 0x00100000 /* Data Interrupt Enable in X count */
33#define DI_EN_Y 0x00200000 /* Data Interrupt Enable in Y count */
34#define DI_EN_P 0x00300000 /* Data Interrupt Enable in Peripheral */
35#define DI_EN DI_EN_X /* Data Interrupt Enable */
36#define NDSIZE_0 0x00000000 /* Next Descriptor Size = 1 */
37#define NDSIZE_1 0x00010000 /* Next Descriptor Size = 2 */
38#define NDSIZE_2 0x00020000 /* Next Descriptor Size = 3 */
39#define NDSIZE_3 0x00030000 /* Next Descriptor Size = 4 */
40#define NDSIZE_4 0x00040000 /* Next Descriptor Size = 5 */
41#define NDSIZE_5 0x00050000 /* Next Descriptor Size = 6 */
42#define NDSIZE_6 0x00060000 /* Next Descriptor Size = 7 */
43#define NDSIZE 0x00070000 /* Next Descriptor Size */
44#define NDSIZE_OFFSET 16 /* Next Descriptor Size Offset */
45#define DMAFLOW_LIST 0x00004000 /* Descriptor List Mode */
46#define DMAFLOW_LARGE DMAFLOW_LIST
47#define DMAFLOW_ARRAY 0x00005000 /* Descriptor Array Mode */
48#define DMAFLOW_LIST_DEMAND 0x00006000 /* Descriptor Demand List Mode */
49#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Descriptor Demand Array Mode */
50#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Running Indicator (DFETCH) */
51#define DMA_RUN 0x00000200 /* DMA Channel Running Indicator */
52#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Running Indicator (WAIT TRIG) */
53#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Running Indicator (WAIT ACK) */
54
55#else
56
57#define PSIZE_16 0x0000 /* Transfer Word Size = 16 */
58#define PSIZE_32 0x0000 /* Transfer Word Size = 32 */
18#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ 59#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
19#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ 60#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
20#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ 61#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
21#define RESTART 0x0020 /* DMA Buffer Clear */ 62#define RESTART 0x0020 /* DMA Buffer Clear */
22#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ 63#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
23#define DI_EN 0x0080 /* Data Interrupt Enable */ 64#define DI_EN 0x0080 /* Data Interrupt Enable */
65#define DI_EN_X 0x00C0 /* Data Interrupt Enable in X count*/
66#define DI_EN_Y 0x0080 /* Data Interrupt Enable in Y count*/
24#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ 67#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
25#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ 68#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
26#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ 69#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
@@ -32,18 +75,26 @@
32#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ 75#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
33#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ 76#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
34#define NDSIZE 0x0f00 /* Next Descriptor Size */ 77#define NDSIZE 0x0f00 /* Next Descriptor Size */
35#define DMAFLOW 0x7000 /* Flow Control */ 78#define NDSIZE_OFFSET 8 /* Next Descriptor Size Offset */
36#define DMAFLOW_STOP 0x0000 /* Stop Mode */
37#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
38#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ 79#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
39#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ 80#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
40#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ 81#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
82#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
83#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
84
85#endif
86#define DMAFLOW 0x7000 /* Flow Control */
87#define DMAFLOW_STOP 0x0000 /* Stop Mode */
88#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
41 89
42/* DMA_IRQ_STATUS Masks */ 90/* DMA_IRQ_STATUS Masks */
43#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ 91#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
44#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ 92#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
45#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ 93#ifdef CONFIG_BF60x
46#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ 94#define DMA_PIRQ 0x0004 /* DMA Peripheral Error Interrupt Status */
95#else
96#define DMA_PIRQ 0
97#endif
47 98
48/* 99/*
49 * All Blackfin system MMRs are padded to 32bits even if the register 100 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -57,6 +108,26 @@
57struct bfin_dma_regs { 108struct bfin_dma_regs {
58 u32 next_desc_ptr; 109 u32 next_desc_ptr;
59 u32 start_addr; 110 u32 start_addr;
111#ifdef CONFIG_BF60x
112 u32 cfg;
113 u32 x_count;
114 u32 x_modify;
115 u32 y_count;
116 u32 y_modify;
117 u32 pad1;
118 u32 pad2;
119 u32 curr_desc_ptr;
120 u32 prev_desc_ptr;
121 u32 curr_addr;
122 u32 irq_status;
123 u32 curr_x_count;
124 u32 curr_y_count;
125 u32 pad3;
126 u32 bw_limit_count;
127 u32 curr_bw_limit_count;
128 u32 bw_monitor_count;
129 u32 curr_bw_monitor_count;
130#else
60 __BFP(config); 131 __BFP(config);
61 u32 __pad0; 132 u32 __pad0;
62 __BFP(x_count); 133 __BFP(x_count);
@@ -71,8 +142,10 @@ struct bfin_dma_regs {
71 u32 __pad1; 142 u32 __pad1;
72 __BFP(curr_y_count); 143 __BFP(curr_y_count);
73 u32 __pad2; 144 u32 __pad2;
145#endif
74}; 146};
75 147
148#ifndef CONFIG_BF60x
76/* 149/*
77 * bfin handshake mdma registers layout 150 * bfin handshake mdma registers layout
78 */ 151 */
@@ -85,6 +158,7 @@ struct bfin_hmdma_regs {
85 __BFP(ecount); 158 __BFP(ecount);
86 __BFP(bcount); 159 __BFP(bcount);
87}; 160};
161#endif
88 162
89#undef __BFP 163#undef __BFP
90 164
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
index accd47e2db40..bf52e1f32257 100644
--- a/arch/blackfin/include/asm/bfin_pfmon.h
+++ b/arch/blackfin/include/asm/bfin_pfmon.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright 2005-2011 Analog Devices Inc. 4 * Copyright 2005-2011 Analog Devices Inc.
5 * 5 *
6 * Licensed under the ADI BSD license or GPL-2 (or later). 6 * Licensed under the Clear BSD license or GPL-2 (or later).
7 */ 7 */
8 8
9#ifndef __ASM_BFIN_PFMON_H__ 9#ifndef __ASM_BFIN_PFMON_H__
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h
index 3be05faa2c65..a4e872e16e75 100644
--- a/arch/blackfin/include/asm/bfin_ppi.h
+++ b/arch/blackfin/include/asm/bfin_ppi.h
@@ -10,6 +10,7 @@
10#define __ASM_BFIN_PPI_H__ 10#define __ASM_BFIN_PPI_H__
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13#include <asm/blackfin.h>
13 14
14/* 15/*
15 * All Blackfin system MMRs are padded to 32bits even if the register 16 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -48,6 +49,133 @@ struct bfin_eppi_regs {
48 u32 clip; 49 u32 clip;
49}; 50};
50 51
52/*
53 * bfin eppi3 registers layout
54 */
55struct bfin_eppi3_regs {
56 u32 stat;
57 u32 hcnt;
58 u32 hdly;
59 u32 vcnt;
60 u32 vdly;
61 u32 frame;
62 u32 line;
63 u32 clkdiv;
64 u32 ctl;
65 u32 fs1_wlhb;
66 u32 fs1_paspl;
67 u32 fs2_wlvb;
68 u32 fs2_palpf;
69 u32 imsk;
70 u32 oddclip;
71 u32 evenclip;
72 u32 fs1_dly;
73 u32 fs2_dly;
74 u32 ctl2;
75};
76
51#undef __BFP 77#undef __BFP
52 78
79#ifdef EPPI0_CTL2
80#define EPPI_STAT_CFIFOERR 0x00000001 /* Chroma FIFO Error */
81#define EPPI_STAT_YFIFOERR 0x00000002 /* Luma FIFO Error */
82#define EPPI_STAT_LTERROVR 0x00000004 /* Line Track Overflow */
83#define EPPI_STAT_LTERRUNDR 0x00000008 /* Line Track Underflow */
84#define EPPI_STAT_FTERROVR 0x00000010 /* Frame Track Overflow */
85#define EPPI_STAT_FTERRUNDR 0x00000020 /* Frame Track Underflow */
86#define EPPI_STAT_ERRNCOR 0x00000040 /* Preamble Error Not Corrected */
87#define EPPI_STAT_PXPERR 0x00000080 /* PxP Ready Error */
88#define EPPI_STAT_ERRDET 0x00004000 /* Preamble Error Detected */
89#define EPPI_STAT_FLD 0x00008000 /* Current Field Received by EPPI */
90
91#define EPPI_HCNT_VALUE 0x0000FFFF /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
92
93#define EPPI_HDLY_VALUE 0x0000FFFF /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
94
95#define EPPI_VCNT_VALUE 0x0000FFFF /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
96
97#define EPPI_VDLY_VALUE 0x0000FFFF /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
98
99#define EPPI_FRAME_VALUE 0x0000FFFF /* Holds the number of lines expected per frame of data */
100
101#define EPPI_LINE_VALUE 0x0000FFFF /* Holds the number of samples expected per line */
102
103#define EPPI_CLKDIV_VALUE 0x0000FFFF /* Internal clock divider */
104
105#define EPPI_CTL_EN 0x00000001 /* PPI Enable */
106#define EPPI_CTL_DIR 0x00000002 /* PPI Direction */
107#define EPPI_CTL_XFRTYPE 0x0000000C /* PPI Operating Mode */
108#define EPPI_CTL_ACTIVE656 0x00000000 /* XFRTYPE: ITU656 Active Video Only Mode */
109#define EPPI_CTL_ENTIRE656 0x00000004 /* XFRTYPE: ITU656 Entire Field Mode */
110#define EPPI_CTL_VERT656 0x00000008 /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
111#define EPPI_CTL_NON656 0x0000000C /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
112#define EPPI_CTL_FSCFG 0x00000030 /* Frame Sync Configuration */
113#define EPPI_CTL_SYNC0 0x00000000 /* FSCFG: Sync Mode 0 */
114#define EPPI_CTL_SYNC1 0x00000010 /* FSCFG: Sync Mode 1 */
115#define EPPI_CTL_SYNC2 0x00000020 /* FSCFG: Sync Mode 2 */
116#define EPPI_CTL_SYNC3 0x00000030 /* FSCFG: Sync Mode 3 */
117#define EPPI_CTL_FLDSEL 0x00000040 /* Field Select/Trigger */
118#define EPPI_CTL_ITUTYPE 0x00000080 /* ITU Interlace or Progressive */
119#define EPPI_CTL_BLANKGEN 0x00000100 /* ITU Output Mode with Internal Blanking Generation */
120#define EPPI_CTL_ICLKGEN 0x00000200 /* Internal Clock Generation */
121#define EPPI_CTL_IFSGEN 0x00000400 /* Internal Frame Sync Generation */
122#define EPPI_CTL_SIGNEXT 0x00000800 /* Sign Extension */
123#define EPPI_CTL_POLC 0x00003000 /* Frame Sync and Data Driving and Sampling Edges */
124#define EPPI_CTL_POLC0 0x00000000 /* POLC: Clock/Sync polarity mode 0 */
125#define EPPI_CTL_POLC1 0x00001000 /* POLC: Clock/Sync polarity mode 1 */
126#define EPPI_CTL_POLC2 0x00002000 /* POLC: Clock/Sync polarity mode 2 */
127#define EPPI_CTL_POLC3 0x00003000 /* POLC: Clock/Sync polarity mode 3 */
128#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
129#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
130#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
131#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
132#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
133#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
134#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
135#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
136#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
137#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
138#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
139#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
140#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
141#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
142#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
143#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
144#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
145#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
146#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
147#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
148#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
149#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
150#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
151#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
152#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
153#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
154#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
155
156#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
157#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
158#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
159#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
160
161#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
162#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
163
164#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
165#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
166#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
167#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
168#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
169#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
170#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
171#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
172
173#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
174#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
175
176#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
177#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
178
179#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
180#endif
53#endif 181#endif
diff --git a/arch/blackfin/include/asm/bfin_rotary.h b/arch/blackfin/include/asm/bfin_rotary.h
index 0b6910bdc57f..8895a750c70c 100644
--- a/arch/blackfin/include/asm/bfin_rotary.h
+++ b/arch/blackfin/include/asm/bfin_rotary.h
@@ -39,6 +39,7 @@ struct bfin_rotary_platform_data {
39 unsigned int rotary_rel_code; 39 unsigned int rotary_rel_code;
40 unsigned short debounce; /* 0..17 */ 40 unsigned short debounce; /* 0..17 */
41 unsigned short mode; 41 unsigned short mode;
42 unsigned short pm_wakeup;
42}; 43};
43 44
44/* CNT_CONFIG bitmasks */ 45/* CNT_CONFIG bitmasks */
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
index 68bcc3d119b6..8597158010b5 100644
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -18,7 +18,7 @@
18 defined(CONFIG_BFIN_UART1_CTSRTS) || \ 18 defined(CONFIG_BFIN_UART1_CTSRTS) || \
19 defined(CONFIG_BFIN_UART2_CTSRTS) || \ 19 defined(CONFIG_BFIN_UART2_CTSRTS) || \
20 defined(CONFIG_BFIN_UART3_CTSRTS) 20 defined(CONFIG_BFIN_UART3_CTSRTS)
21# ifdef BFIN_UART_BF54X_STYLE 21# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
22# define CONFIG_SERIAL_BFIN_HARD_CTSRTS 22# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
23# else 23# else
24# define CONFIG_SERIAL_BFIN_CTSRTS 24# define CONFIG_SERIAL_BFIN_CTSRTS
@@ -58,14 +58,69 @@ struct bfin_serial_port {
58#endif 58#endif
59}; 59};
60 60
61#ifdef BFIN_UART_BF60X_STYLE
62
63/* UART_CTL Masks */
64#define UCEN 0x1 /* Enable UARTx Clocks */
65#define LOOP_ENA 0x2 /* Loopback Mode Enable */
66#define UMOD_MDB 0x10 /* Enable MDB Mode */
67#define UMOD_IRDA 0x20 /* Enable IrDA Mode */
68#define UMOD_MASK 0x30 /* Uart Mode Mask */
69#define WLS(x) (((x-5) & 0x03) << 8) /* Word Length Select */
70#define WLS_MASK 0x300 /* Word length Select Mask */
71#define WLS_OFFSET 8 /* Word length Select Offset */
72#define STB 0x1000 /* Stop Bits */
73#define STBH 0x2000 /* Half Stop Bits */
74#define PEN 0x4000 /* Parity Enable */
75#define EPS 0x8000 /* Even Parity Select */
76#define STP 0x10000 /* Stick Parity */
77#define FPE 0x20000 /* Force Parity Error On Transmit */
78#define FFE 0x40000 /* Force Framing Error On Transmit */
79#define SB 0x80000 /* Set Break */
80#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
81#define FCPOL 0x400000 /* Flow Control Pin Polarity */
82#define RPOLC 0x800000 /* IrDA RX Polarity Change */
83#define TPOLC 0x1000000 /* IrDA TX Polarity Change */
84#define MRTS 0x2000000 /* Manual Request To Send */
85#define XOFF 0x4000000 /* Transmitter Off */
86#define ARTS 0x8000000 /* Automatic Request To Send */
87#define ACTS 0x10000000 /* Automatic Clear To Send */
88#define RFIT 0x20000000 /* Receive FIFO IRQ Threshold */
89#define RFRT 0x40000000 /* Receive FIFO RTS Threshold */
90
91/* UART_STAT Masks */
92#define DR 0x01 /* Data Ready */
93#define OE 0x02 /* Overrun Error */
94#define PE 0x04 /* Parity Error */
95#define FE 0x08 /* Framing Error */
96#define BI 0x10 /* Break Interrupt */
97#define THRE 0x20 /* THR Empty */
98#define TEMT 0x80 /* TSR and UART_THR Empty */
99#define TFI 0x100 /* Transmission Finished Indicator */
100
101#define ASTKY 0x200 /* Address Sticky */
102#define ADDR 0x400 /* Address bit status */
103#define RO 0x800 /* Reception Ongoing */
104#define SCTS 0x1000 /* Sticky CTS */
105#define CTS 0x10000 /* Clear To Send */
106#define RFCS 0x20000 /* Receive FIFO Count Status */
107
108/* UART_CLOCK Masks */
109#define EDBO 0x80000000 /* Enable Devide by One */
110
111#else /* BFIN_UART_BF60X_STYLE */
112
61/* UART_LCR Masks */ 113/* UART_LCR Masks */
62#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 114#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
115#define WLS_MASK 0x03 /* Word length Select Mask */
116#define WLS_OFFSET 0 /* Word length Select Offset */
63#define STB 0x04 /* Stop Bits */ 117#define STB 0x04 /* Stop Bits */
64#define PEN 0x08 /* Parity Enable */ 118#define PEN 0x08 /* Parity Enable */
65#define EPS 0x10 /* Even Parity Select */ 119#define EPS 0x10 /* Even Parity Select */
66#define STP 0x20 /* Stick Parity */ 120#define STP 0x20 /* Stick Parity */
67#define SB 0x40 /* Set Break */ 121#define SB 0x40 /* Set Break */
68#define DLAB 0x80 /* Divisor Latch Access */ 122#define DLAB 0x80 /* Divisor Latch Access */
123#define LCR_MASK (SB | STP | EPS | PEN | STB | WLS_MASK)
69 124
70/* UART_LSR Masks */ 125/* UART_LSR Masks */
71#define DR 0x01 /* Data Ready */ 126#define DR 0x01 /* Data Ready */
@@ -77,15 +132,6 @@ struct bfin_serial_port {
77#define TEMT 0x40 /* TSR and UART_THR Empty */ 132#define TEMT 0x40 /* TSR and UART_THR Empty */
78#define TFI 0x80 /* Transmission Finished Indicator */ 133#define TFI 0x80 /* Transmission Finished Indicator */
79 134
80/* UART_IER Masks */
81#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
82#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
83#define ELSI 0x04 /* Enable RX Status Interrupt */
84#define EDSSI 0x08 /* Enable Modem Status Interrupt */
85#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
86#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
87#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
88
89/* UART_MCR Masks */ 135/* UART_MCR Masks */
90#define XOFF 0x01 /* Transmitter Off */ 136#define XOFF 0x01 /* Transmitter Off */
91#define MRTS 0x02 /* Manual Request To Send */ 137#define MRTS 0x02 /* Manual Request To Send */
@@ -103,13 +149,36 @@ struct bfin_serial_port {
103 149
104/* UART_GCTL Masks */ 150/* UART_GCTL Masks */
105#define UCEN 0x01 /* Enable UARTx Clocks */ 151#define UCEN 0x01 /* Enable UARTx Clocks */
106#define IREN 0x02 /* Enable IrDA Mode */ 152#define UMOD_IRDA 0x02 /* Enable IrDA Mode */
153#define UMOD_MASK 0x02 /* Uart Mode Mask */
107#define TPOLC 0x04 /* IrDA TX Polarity Change */ 154#define TPOLC 0x04 /* IrDA TX Polarity Change */
108#define RPOLC 0x08 /* IrDA RX Polarity Change */ 155#define RPOLC 0x08 /* IrDA RX Polarity Change */
109#define FPE 0x10 /* Force Parity Error On Transmit */ 156#define FPE 0x10 /* Force Parity Error On Transmit */
110#define FFE 0x20 /* Force Framing Error On Transmit */ 157#define FFE 0x20 /* Force Framing Error On Transmit */
111 158
112#ifdef BFIN_UART_BF54X_STYLE 159#endif /* BFIN_UART_BF60X_STYLE */
160
161/* UART_IER Masks */
162#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
163#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
164#define ELSI 0x04 /* Enable RX Status Interrupt */
165#define EDSSI 0x08 /* Enable Modem Status Interrupt */
166#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
167#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
168#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
169
170#if defined(BFIN_UART_BF60X_STYLE)
171# define OFFSET_REDIV 0x00 /* Version ID Register */
172# define OFFSET_CTL 0x04 /* Control Register */
173# define OFFSET_STAT 0x08 /* Status Register */
174# define OFFSET_SCR 0x0C /* SCR Scratch Register */
175# define OFFSET_CLK 0x10 /* Clock Rate Register */
176# define OFFSET_IER 0x14 /* Interrupt Enable Register */
177# define OFFSET_IER_SET 0x18 /* Set Interrupt Enable Register */
178# define OFFSET_IER_CLEAR 0x1C /* Clear Interrupt Enable Register */
179# define OFFSET_RBR 0x20 /* Receive Buffer register */
180# define OFFSET_THR 0x24 /* Transmit Holding register */
181#elif defined(BFIN_UART_BF54X_STYLE)
113# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */ 182# define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
114# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */ 183# define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
115# define OFFSET_GCTL 0x08 /* Global Control Register */ 184# define OFFSET_GCTL 0x08 /* Global Control Register */
@@ -145,7 +214,23 @@ struct bfin_serial_port {
145 */ 214 */
146#define __BFP(m) u16 m; u16 __pad_##m 215#define __BFP(m) u16 m; u16 __pad_##m
147struct bfin_uart_regs { 216struct bfin_uart_regs {
148#ifdef BFIN_UART_BF54X_STYLE 217#if defined(BFIN_UART_BF60X_STYLE)
218 u32 revid;
219 u32 ctl;
220 u32 stat;
221 u32 scr;
222 u32 clk;
223 u32 ier;
224 u32 ier_set;
225 u32 ier_clear;
226 u32 rbr;
227 u32 thr;
228 u32 taip;
229 u32 tsr;
230 u32 rsr;
231 u32 txdiv;
232 u32 rxdiv;
233#elif defined(BFIN_UART_BF54X_STYLE)
149 __BFP(dll); 234 __BFP(dll);
150 __BFP(dlh); 235 __BFP(dlh);
151 __BFP(gctl); 236 __BFP(gctl);
@@ -182,13 +267,70 @@ struct bfin_uart_regs {
182}; 267};
183#undef __BFP 268#undef __BFP
184 269
270#define port_membase(uart) (((struct bfin_serial_port *)(uart))->port.membase)
271
272/*
185#ifndef port_membase 273#ifndef port_membase
186# define port_membase(p) 0 274# define port_membase(p) 0
187#endif 275#endif
276*/
277#ifdef BFIN_UART_BF60X_STYLE
278
279#define UART_GET_CHAR(p) bfin_read32(port_membase(p) + OFFSET_RBR)
280#define UART_GET_CLK(p) bfin_read32(port_membase(p) + OFFSET_CLK)
281#define UART_GET_CTL(p) bfin_read32(port_membase(p) + OFFSET_CTL)
282#define UART_GET_GCTL(p) UART_GET_CTL(p)
283#define UART_GET_LCR(p) UART_GET_CTL(p)
284#define UART_GET_MCR(p) UART_GET_CTL(p)
285#if ANOMALY_05001001
286#define UART_GET_STAT(p) \
287({ \
288 u32 __ret; \
289 unsigned long flags; \
290 flags = hard_local_irq_save(); \
291 __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \
292 hard_local_irq_restore(flags); \
293 __ret; \
294})
295#else
296#define UART_GET_STAT(p) bfin_read32(port_membase(p) + OFFSET_STAT)
297#endif
298#define UART_GET_MSR(p) UART_GET_STAT(p)
299
300#define UART_PUT_CHAR(p, v) bfin_write32(port_membase(p) + OFFSET_THR, v)
301#define UART_PUT_CLK(p, v) bfin_write32(port_membase(p) + OFFSET_CLK, v)
302#define UART_PUT_CTL(p, v) bfin_write32(port_membase(p) + OFFSET_CTL, v)
303#define UART_PUT_GCTL(p, v) UART_PUT_CTL(p, v)
304#define UART_PUT_LCR(p, v) UART_PUT_CTL(p, v)
305#define UART_PUT_MCR(p, v) UART_PUT_CTL(p, v)
306#define UART_PUT_STAT(p, v) bfin_write32(port_membase(p) + OFFSET_STAT, v)
307
308#define UART_CLEAR_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
309#define UART_GET_IER(p) bfin_read32(port_membase(p) + OFFSET_IER)
310#define UART_SET_IER(p, v) bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
311
312#define UART_CLEAR_DLAB(p) /* MMRs not muxed on BF60x */
313#define UART_SET_DLAB(p) /* MMRs not muxed on BF60x */
314
315#define UART_CLEAR_LSR(p) UART_PUT_STAT(p, -1)
316#define UART_GET_LSR(p) UART_GET_STAT(p)
317#define UART_PUT_LSR(p, v) UART_PUT_STAT(p, v)
318
319/* This handles hard CTS/RTS */
320#define BFIN_UART_CTSRTS_HARD
321#define UART_CLEAR_SCTS(p) UART_PUT_STAT(p, SCTS)
322#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
323#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
324#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
325#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
326#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
327
328#else /* BFIN_UART_BF60X_STYLE */
188 329
189#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR) 330#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
190#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL) 331#define UART_GET_DLL(p) bfin_read16(port_membase(p) + OFFSET_DLL)
191#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH) 332#define UART_GET_DLH(p) bfin_read16(port_membase(p) + OFFSET_DLH)
333#define UART_GET_CLK(p) ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
192#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL) 334#define UART_GET_GCTL(p) bfin_read16(port_membase(p) + OFFSET_GCTL)
193#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR) 335#define UART_GET_LCR(p) bfin_read16(port_membase(p) + OFFSET_LCR)
194#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR) 336#define UART_GET_MCR(p) bfin_read16(port_membase(p) + OFFSET_MCR)
@@ -197,6 +339,11 @@ struct bfin_uart_regs {
197#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v) 339#define UART_PUT_CHAR(p, v) bfin_write16(port_membase(p) + OFFSET_THR, v)
198#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v) 340#define UART_PUT_DLL(p, v) bfin_write16(port_membase(p) + OFFSET_DLL, v)
199#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v) 341#define UART_PUT_DLH(p, v) bfin_write16(port_membase(p) + OFFSET_DLH, v)
342#define UART_PUT_CLK(p, v) do \
343{\
344UART_PUT_DLL(p, v & 0xFF); \
345UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
346
200#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v) 347#define UART_PUT_GCTL(p, v) bfin_write16(port_membase(p) + OFFSET_GCTL, v)
201#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v) 348#define UART_PUT_LCR(p, v) bfin_write16(port_membase(p) + OFFSET_LCR, v)
202#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v) 349#define UART_PUT_MCR(p, v) bfin_write16(port_membase(p) + OFFSET_MCR, v)
@@ -233,12 +380,17 @@ struct bfin_uart_regs {
233#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0) 380#define UART_CLEAR_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
234#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0) 381#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
235 382
383#define get_lsr_cache(uart) (((struct bfin_serial_port *)(uart))->lsr)
384#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
385
386/*
236#ifndef put_lsr_cache 387#ifndef put_lsr_cache
237# define put_lsr_cache(p, v) 388# define put_lsr_cache(p, v)
238#endif 389#endif
239#ifndef get_lsr_cache 390#ifndef get_lsr_cache
240# define get_lsr_cache(p) 0 391# define get_lsr_cache(p) 0
241#endif 392#endif
393*/
242 394
243/* The hardware clears the LSR bits upon read, so we need to cache 395/* The hardware clears the LSR bits upon read, so we need to cache
244 * some of the more fun bits in software so they don't get lost 396 * some of the more fun bits in software so they don't get lost
@@ -267,7 +419,9 @@ static inline void UART_PUT_LSR(void *p, uint16_t val)
267#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v) 419#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
268#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0) 420#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
269 421
270#endif 422#endif /* BFIN_UART_BF54X_STYLE */
423
424#endif /* BFIN_UART_BF60X_STYLE */
271 425
272#ifndef BFIN_UART_TX_FIFO_SIZE 426#ifndef BFIN_UART_TX_FIFO_SIZE
273# define BFIN_UART_TX_FIFO_SIZE 2 427# define BFIN_UART_TX_FIFO_SIZE 2
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index 0afcfbd54a82..f8907ea6b5b6 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -24,6 +24,7 @@
24struct sport_config { 24struct sport_config {
25 /* TDM (multichannels), I2S or other mode */ 25 /* TDM (multichannels), I2S or other mode */
26 unsigned int mode:3; 26 unsigned int mode:3;
27 unsigned int polled; /* use poll instead of irq when set */
27 28
28 /* if TDM mode is selected, channels must be set */ 29 /* if TDM mode is selected, channels must be set */
29 int channels; /* Must be in 8 units */ 30 int channels; /* Must be in 8 units */
diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h
new file mode 100644
index 000000000000..03c00220d69b
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_sport3.h
@@ -0,0 +1,107 @@
1/*
2 * bfin_sport - Analog Devices BF6XX SPORT registers
3 *
4 * Copyright (c) 2012 Analog Devices Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef _BFIN_SPORT3_H_
21#define _BFIN_SPORT3_H_
22
23#include <linux/types.h>
24
25#define SPORT_CTL_SPENPRI 0x00000001 /* Enable Primary Channel */
26#define SPORT_CTL_DTYPE 0x00000006 /* Data type select */
27#define SPORT_CTL_RJUSTIFY_ZFILL 0x00000000 /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
28#define SPORT_CTL_RJUSTIFY_SFILL 0x00000002 /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
29#define SPORT_CTL_USE_U_LAW 0x00000004 /* DTYPE: MCM mode: Compand using u-law */
30#define SPORT_CTL_USE_A_LAW 0x00000006 /* DTYPE: MCM mode: Compand using A-law */
31#define SPORT_CTL_LSBF 0x00000008 /* Serial bit endian select */
32#define SPORT_CTL_SLEN 0x000001F0 /* Serial Word length select */
33#define SPORT_CTL_PACK 0x00000200 /* 16-bit to 32-bit packing enable */
34#define SPORT_CTL_ICLK 0x00000400 /* Internal Clock Select */
35#define SPORT_CTL_OPMODE 0x00000800 /* Operation mode */
36#define SPORT_CTL_CKRE 0x00001000 /* Clock rising edge select */
37#define SPORT_CTL_FSR 0x00002000 /* Frame Sync required */
38#define SPORT_CTL_IFS 0x00004000 /* Internal Frame Sync select */
39#define SPORT_CTL_DIFS 0x00008000 /* Data-independent frame sync select */
40#define SPORT_CTL_LFS 0x00010000 /* Active low frame sync select */
41#define SPORT_CTL_LAFS 0x00020000 /* Late Transmit frame select */
42#define SPORT_CTL_RJUST 0x00040000 /* Right Justified mode select */
43#define SPORT_CTL_FSED 0x00080000 /* External frame sync edge select */
44#define SPORT_CTL_TFIEN 0x00100000 /* Transmit finish interrrupt enable select */
45#define SPORT_CTL_GCLKEN 0x00200000 /* Gated clock mode select */
46#define SPORT_CTL_SPENSEC 0x01000000 /* Enable secondary channel */
47#define SPORT_CTL_SPTRAN 0x02000000 /* Data direction control */
48#define SPORT_CTL_DERRSEC 0x04000000 /* Secondary channel error status */
49#define SPORT_CTL_DXSSEC 0x18000000 /* Secondary channel data buffer status */
50#define SPORT_CTL_SEC_EMPTY 0x00000000 /* DXSSEC: Empty */
51#define SPORT_CTL_SEC_PART_FULL 0x10000000 /* DXSSEC: Partially full */
52#define SPORT_CTL_SEC_FULL 0x18000000 /* DXSSEC: Full */
53#define SPORT_CTL_DERRPRI 0x20000000 /* Primary channel error status */
54#define SPORT_CTL_DXSPRI 0xC0000000 /* Primary channel data buffer status */
55#define SPORT_CTL_PRM_EMPTY 0x00000000 /* DXSPRI: Empty */
56#define SPORT_CTL_PRM_PART_FULL 0x80000000 /* DXSPRI: Partially full */
57#define SPORT_CTL_PRM_FULL 0xC0000000 /* DXSPRI: Full */
58
59#define SPORT_DIV_CLKDIV 0x0000FFFF /* Clock divisor */
60#define SPORT_DIV_FSDIV 0xFFFF0000 /* Frame sync divisor */
61
62#define SPORT_MCTL_MCE 0x00000001 /* Multichannel enable */
63#define SPORT_MCTL_MCPDE 0x00000004 /* Multichannel data packing select */
64#define SPORT_MCTL_MFD 0x000000F0 /* Multichannel frame delay */
65#define SPORT_MCTL_WSIZE 0x00007F00 /* Number of multichannel slots */
66#define SPORT_MCTL_WOFFSET 0x03FF0000 /* Window offset size */
67
68#define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */
69#define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
70
71#define SPORT_ERR_DERRPMSK 0x00000001 /* Primary channel data error interrupt enable */
72#define SPORT_ERR_DERRSMSK 0x00000002 /* Secondary channel data error interrupt enable */
73#define SPORT_ERR_FSERRMSK 0x00000004 /* Frame sync error interrupt enable */
74#define SPORT_ERR_DERRPSTAT 0x00000010 /* Primary channel data error status */
75#define SPORT_ERR_DERRSSTAT 0x00000020 /* Secondary channel data error status */
76#define SPORT_ERR_FSERRSTAT 0x00000040 /* Frame sync error status */
77
78#define SPORT_MSTAT_CURCHAN 0x000003FF /* Channel which is being serviced in the multichannel operation */
79
80#define SPORT_CTL2_FSMUXSEL 0x00000001 /* Frame Sync MUX Select */
81#define SPORT_CTL2_CKMUXSEL 0x00000002 /* Clock MUX Select */
82#define SPORT_CTL2_LBSEL 0x00000004 /* Loopback Select */
83
84struct sport_register {
85 u32 spctl;
86 u32 div;
87 u32 spmctl;
88 u32 spcs0;
89 u32 spcs1;
90 u32 spcs2;
91 u32 spcs3;
92 u32 spcnt;
93 u32 sperrctl;
94 u32 spmstat;
95 u32 spctl2;
96 u32 txa;
97 u32 rxa;
98 u32 txb;
99 u32 rxb;
100 u32 revid;
101};
102
103struct bfin_snd_platform_data {
104 const unsigned short *pin_req;
105};
106
107#endif
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
index e767d649dfc4..2f3339a47626 100644
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -10,6 +10,7 @@
10#define __ASM_BFIN_TWI_H__ 10#define __ASM_BFIN_TWI_H__
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/i2c.h>
13 14
14/* 15/*
15 * All Blackfin system MMRs are padded to 32bits even if the register 16 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -42,4 +43,145 @@ struct bfin_twi_regs {
42 43
43#undef __BFP 44#undef __BFP
44 45
46struct bfin_twi_iface {
47 int irq;
48 spinlock_t lock;
49 char read_write;
50 u8 command;
51 u8 *transPtr;
52 int readNum;
53 int writeNum;
54 int cur_mode;
55 int manual_stop;
56 int result;
57 struct i2c_adapter adap;
58 struct completion complete;
59 struct i2c_msg *pmsg;
60 int msg_num;
61 int cur_msg;
62 u16 saved_clkdiv;
63 u16 saved_control;
64 struct bfin_twi_regs *regs_base;
65};
66
67#define DEFINE_TWI_REG(reg_name, reg) \
68static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
69 { return iface->regs_base->reg; } \
70static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
71 { iface->regs_base->reg = v; }
72
73DEFINE_TWI_REG(CLKDIV, clkdiv)
74DEFINE_TWI_REG(CONTROL, control)
75DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
76DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
77DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
78DEFINE_TWI_REG(MASTER_CTL, master_ctl)
79DEFINE_TWI_REG(MASTER_STAT, master_stat)
80DEFINE_TWI_REG(MASTER_ADDR, master_addr)
81DEFINE_TWI_REG(INT_STAT, int_stat)
82DEFINE_TWI_REG(INT_MASK, int_mask)
83DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
84DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
85DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
86DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
87#if !ANOMALY_05001001
88DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
89DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
90#else
91static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
92{
93 u16 ret;
94 unsigned long flags;
95
96 flags = hard_local_irq_save();
97 ret = iface->regs_base->rcv_data8;
98 hard_local_irq_restore(flags);
99
100 return ret;
101}
102
103static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
104{
105 u16 ret;
106 unsigned long flags;
107
108 flags = hard_local_irq_save();
109 ret = iface->regs_base->rcv_data16;
110 hard_local_irq_restore(flags);
111
112 return ret;
113}
114#endif
115
116
117/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
118/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
119#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
120#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
121
122/* TWI_PRESCALE Masks */
123#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
124#define TWI_ENA 0x0080 /* TWI Enable */
125#define SCCB 0x0200 /* SCCB Compatibility Enable */
126
127/* TWI_SLAVE_CTL Masks */
128#define SEN 0x0001 /* Slave Enable */
129#define SADD_LEN 0x0002 /* Slave Address Length */
130#define STDVAL 0x0004 /* Slave Transmit Data Valid */
131#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
132#define GEN 0x0010 /* General Call Address Matching Enabled */
133
134/* TWI_SLAVE_STAT Masks */
135#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
136#define GCALL 0x0002 /* General Call Indicator */
137
138/* TWI_MASTER_CTL Masks */
139#define MEN 0x0001 /* Master Mode Enable */
140#define MADD_LEN 0x0002 /* Master Address Length */
141#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
142#define FAST 0x0008 /* Use Fast Mode Timing Specs */
143#define STOP 0x0010 /* Issue Stop Condition */
144#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
145#define DCNT 0x3FC0 /* Data Bytes To Transfer */
146#define SDAOVR 0x4000 /* Serial Data Override */
147#define SCLOVR 0x8000 /* Serial Clock Override */
148
149/* TWI_MASTER_STAT Masks */
150#define MPROG 0x0001 /* Master Transfer In Progress */
151#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
152#define ANAK 0x0004 /* Address Not Acknowledged */
153#define DNAK 0x0008 /* Data Not Acknowledged */
154#define BUFRDERR 0x0010 /* Buffer Read Error */
155#define BUFWRERR 0x0020 /* Buffer Write Error */
156#define SDASEN 0x0040 /* Serial Data Sense */
157#define SCLSEN 0x0080 /* Serial Clock Sense */
158#define BUSBUSY 0x0100 /* Bus Busy Indicator */
159
160/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
161#define SINIT 0x0001 /* Slave Transfer Initiated */
162#define SCOMP 0x0002 /* Slave Transfer Complete */
163#define SERR 0x0004 /* Slave Transfer Error */
164#define SOVF 0x0008 /* Slave Overflow */
165#define MCOMP 0x0010 /* Master Transfer Complete */
166#define MERR 0x0020 /* Master Transfer Error */
167#define XMTSERV 0x0040 /* Transmit FIFO Service */
168#define RCVSERV 0x0080 /* Receive FIFO Service */
169
170/* TWI_FIFO_CTRL Masks */
171#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
172#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
173#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
174#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
175
176/* TWI_FIFO_STAT Masks */
177#define XMTSTAT 0x0003 /* Transmit FIFO Status */
178#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
179#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
180#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
181
182#define RCVSTAT 0x000C /* Receive FIFO Status */
183#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
184#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
185#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
186
45#endif 187#endif
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index 7be5368c0512..f111f366d758 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -63,20 +63,16 @@ static inline void CSYNC(void)
63 63
64#if ANOMALY_05000312 || ANOMALY_05000244 64#if ANOMALY_05000312 || ANOMALY_05000244
65#define SSYNC(scratch) \ 65#define SSYNC(scratch) \
66do { \
67 cli scratch; \ 66 cli scratch; \
68 nop; nop; nop; \ 67 nop; nop; nop; \
69 SSYNC; \ 68 SSYNC; \
70 sti scratch; \ 69 sti scratch;
71} while (0)
72 70
73#define CSYNC(scratch) \ 71#define CSYNC(scratch) \
74do { \
75 cli scratch; \ 72 cli scratch; \
76 nop; nop; nop; \ 73 nop; nop; nop; \
77 CSYNC; \ 74 CSYNC; \
78 sti scratch; \ 75 sti scratch;
79} while (0)
80 76
81#else 77#else
82#define SSYNC(scratch) SSYNC; 78#define SSYNC(scratch) SSYNC;
diff --git a/arch/blackfin/include/asm/clkdev.h b/arch/blackfin/include/asm/clkdev.h
new file mode 100644
index 000000000000..9053beda8c50
--- /dev/null
+++ b/arch/blackfin/include/asm/clkdev.h
@@ -0,0 +1,14 @@
1#ifndef __ASM_CLKDEV__H_
2#define __ASM_CLKDEV__H_
3
4#include <linux/slab.h>
5
6static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
7{
8 return kzalloc(size, GFP_KERNEL);
9}
10
11#define __clk_put(clk)
12#define __clk_get(clk) ({ 1; })
13
14#endif
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
index 6f0b61852f58..9b3c85b3c288 100644
--- a/arch/blackfin/include/asm/clocks.h
+++ b/arch/blackfin/include/asm/clocks.h
@@ -48,4 +48,27 @@
48# define CONFIG_VCO_MULT 0 48# define CONFIG_VCO_MULT 0
49#endif 49#endif
50 50
51#include <linux/clk.h>
52
53struct clk_ops {
54 unsigned long (*get_rate)(struct clk *clk);
55 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
56 int (*set_rate)(struct clk *clk, unsigned long rate);
57 int (*enable)(struct clk *clk);
58 int (*disable)(struct clk *clk);
59};
60
61struct clk {
62 struct clk *parent;
63 const char *name;
64 unsigned long rate;
65 spinlock_t lock;
66 u32 flags;
67 const struct clk_ops *ops;
68 void __iomem *reg;
69 u32 mask;
70 u32 shift;
71};
72
73int clk_init(void);
51#endif 74#endif
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index fda96261ed62..5c37f620c4b3 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -62,6 +62,10 @@
62#define SIZE_4K 0x00001000 /* 4K */ 62#define SIZE_4K 0x00001000 /* 4K */
63#define SIZE_1M 0x00100000 /* 1M */ 63#define SIZE_1M 0x00100000 /* 1M */
64#define SIZE_4M 0x00400000 /* 4M */ 64#define SIZE_4M 0x00400000 /* 4M */
65#define SIZE_16K 0x00004000 /* 16K */
66#define SIZE_64K 0x00010000 /* 64K */
67#define SIZE_16M 0x01000000 /* 16M */
68#define SIZE_64M 0x04000000 /* 64M */
65 69
66#define MAX_CPLBS 16 70#define MAX_CPLBS 16
67 71
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 823679011457..fe0ca03a1cb2 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright 2005-2008 Analog Devices Inc. 4 * Copyright 2005-2008 Analog Devices Inc.
5 * 5 *
6 * Licensed under the ADI BSD license or GPL-2 (or later). 6 * Licensed under the Clear BSD license or GPL-2 (or later).
7 */ 7 */
8 8
9#ifndef _DEF_LPBLACKFIN_H 9#ifndef _DEF_LPBLACKFIN_H
@@ -622,6 +622,10 @@ do { \
622#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ 622#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
623#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ 623#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
624#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ 624#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
625#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
626#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
627#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
628#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
625#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not 629#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
626 * mapped to L1 630 * mapped to L1
627 */ 631 */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index dac0c97242bb..40e9c2bbc6e3 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -22,12 +22,22 @@
22#define DATA_SIZE_8 0 22#define DATA_SIZE_8 0
23#define DATA_SIZE_16 1 23#define DATA_SIZE_16 1
24#define DATA_SIZE_32 2 24#define DATA_SIZE_32 2
25#ifdef CONFIG_BF60x
26#define DATA_SIZE_64 3
27#endif
25 28
26#define DMA_FLOW_STOP 0 29#define DMA_FLOW_STOP 0
27#define DMA_FLOW_AUTO 1 30#define DMA_FLOW_AUTO 1
31#ifdef CONFIG_BF60x
32#define DMA_FLOW_LIST 4
33#define DMA_FLOW_ARRAY 5
34#define DMA_FLOW_LIST_DEMAND 6
35#define DMA_FLOW_ARRAY_DEMAND 7
36#else
28#define DMA_FLOW_ARRAY 4 37#define DMA_FLOW_ARRAY 4
29#define DMA_FLOW_SMALL 6 38#define DMA_FLOW_SMALL 6
30#define DMA_FLOW_LARGE 7 39#define DMA_FLOW_LARGE 7
40#endif
31 41
32#define DIMENSION_LINEAR 0 42#define DIMENSION_LINEAR 0
33#define DIMENSION_2D 1 43#define DIMENSION_2D 1
@@ -36,26 +46,80 @@
36#define DIR_WRITE 1 46#define DIR_WRITE 1
37 47
38#define INTR_DISABLE 0 48#define INTR_DISABLE 0
49#ifdef CONFIG_BF60x
50#define INTR_ON_PERI 1
51#endif
39#define INTR_ON_BUF 2 52#define INTR_ON_BUF 2
40#define INTR_ON_ROW 3 53#define INTR_ON_ROW 3
41 54
42#define DMA_NOSYNC_KEEP_DMA_BUF 0 55#define DMA_NOSYNC_KEEP_DMA_BUF 0
43#define DMA_SYNC_RESTART 1 56#define DMA_SYNC_RESTART 1
44 57
58#ifdef DMA_MMR_SIZE_32
59#define DMA_MMR_SIZE_TYPE long
60#define DMA_MMR_READ bfin_read32
61#define DMA_MMR_WRITE bfin_write32
62#else
63#define DMA_MMR_SIZE_TYPE short
64#define DMA_MMR_READ bfin_read16
65#define DMA_MMR_WRITE bfin_write16
66#endif
67
68struct dma_desc_array {
69 unsigned long start_addr;
70 unsigned DMA_MMR_SIZE_TYPE cfg;
71 unsigned DMA_MMR_SIZE_TYPE x_count;
72 DMA_MMR_SIZE_TYPE x_modify;
73} __attribute__((packed));
74
45struct dmasg { 75struct dmasg {
46 void *next_desc_addr; 76 void *next_desc_addr;
47 unsigned long start_addr; 77 unsigned long start_addr;
48 unsigned short cfg; 78 unsigned DMA_MMR_SIZE_TYPE cfg;
49 unsigned short x_count; 79 unsigned DMA_MMR_SIZE_TYPE x_count;
50 short x_modify; 80 DMA_MMR_SIZE_TYPE x_modify;
51 unsigned short y_count; 81 unsigned DMA_MMR_SIZE_TYPE y_count;
52 short y_modify; 82 DMA_MMR_SIZE_TYPE y_modify;
53} __attribute__((packed)); 83} __attribute__((packed));
54 84
55struct dma_register { 85struct dma_register {
56 void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ 86 void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
57 unsigned long start_addr; /* DMA Start address register */ 87 unsigned long start_addr; /* DMA Start address register */
88#ifdef CONFIG_BF60x
89 unsigned long cfg; /* DMA Configuration register */
58 90
91 unsigned long x_count; /* DMA x_count register */
92
93 long x_modify; /* DMA x_modify register */
94
95 unsigned long y_count; /* DMA y_count register */
96
97 long y_modify; /* DMA y_modify register */
98
99 unsigned long reserved;
100 unsigned long reserved2;
101
102 void *curr_desc_ptr; /* DMA Current Descriptor Pointer
103 register */
104 void *prev_desc_ptr; /* DMA previous initial Descriptor Pointer
105 register */
106 unsigned long curr_addr_ptr; /* DMA Current Address Pointer
107 register */
108 unsigned long irq_status; /* DMA irq status register */
109
110 unsigned long curr_x_count; /* DMA Current x-count register */
111
112 unsigned long curr_y_count; /* DMA Current y-count register */
113
114 unsigned long reserved3;
115
116 unsigned long bw_limit_count; /* DMA band width limit count register */
117 unsigned long curr_bw_limit_count; /* DMA Current band width limit
118 count register */
119 unsigned long bw_monitor_count; /* DMA band width limit count register */
120 unsigned long curr_bw_monitor_count; /* DMA Current band width limit
121 count register */
122#else
59 unsigned short cfg; /* DMA Configuration register */ 123 unsigned short cfg; /* DMA Configuration register */
60 unsigned short dummy1; /* DMA Configuration register */ 124 unsigned short dummy1; /* DMA Configuration register */
61 125
@@ -92,6 +156,7 @@ struct dma_register {
92 unsigned short dummy9; 156 unsigned short dummy9;
93 157
94 unsigned long reserved3; 158 unsigned long reserved3;
159#endif
95 160
96}; 161};
97 162
@@ -131,23 +196,23 @@ static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
131{ 196{
132 dma_ch[channel].regs->curr_desc_ptr = addr; 197 dma_ch[channel].regs->curr_desc_ptr = addr;
133} 198}
134static inline void set_dma_x_count(unsigned int channel, unsigned short x_count) 199static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
135{ 200{
136 dma_ch[channel].regs->x_count = x_count; 201 dma_ch[channel].regs->x_count = x_count;
137} 202}
138static inline void set_dma_y_count(unsigned int channel, unsigned short y_count) 203static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
139{ 204{
140 dma_ch[channel].regs->y_count = y_count; 205 dma_ch[channel].regs->y_count = y_count;
141} 206}
142static inline void set_dma_x_modify(unsigned int channel, short x_modify) 207static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
143{ 208{
144 dma_ch[channel].regs->x_modify = x_modify; 209 dma_ch[channel].regs->x_modify = x_modify;
145} 210}
146static inline void set_dma_y_modify(unsigned int channel, short y_modify) 211static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
147{ 212{
148 dma_ch[channel].regs->y_modify = y_modify; 213 dma_ch[channel].regs->y_modify = y_modify;
149} 214}
150static inline void set_dma_config(unsigned int channel, unsigned short config) 215static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
151{ 216{
152 dma_ch[channel].regs->cfg = config; 217 dma_ch[channel].regs->cfg = config;
153} 218}
@@ -156,23 +221,55 @@ static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
156 dma_ch[channel].regs->curr_addr_ptr = addr; 221 dma_ch[channel].regs->curr_addr_ptr = addr;
157} 222}
158 223
159static inline unsigned short 224#ifdef CONFIG_BF60x
225static inline unsigned long
226set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
227 char dma_mode, char mem_width, char syncmode, char peri_width)
228{
229 unsigned long config = 0;
230
231 switch (intr_mode) {
232 case INTR_ON_BUF:
233 if (dma_mode == DIMENSION_2D)
234 config = DI_EN_Y;
235 else
236 config = DI_EN_X;
237 break;
238 case INTR_ON_ROW:
239 config = DI_EN_X;
240 break;
241 case INTR_ON_PERI:
242 config = DI_EN_P;
243 break;
244 };
245
246 return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
247 (flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
248}
249#endif
250
251static inline unsigned DMA_MMR_SIZE_TYPE
160set_bfin_dma_config(char direction, char flow_mode, 252set_bfin_dma_config(char direction, char flow_mode,
161 char intr_mode, char dma_mode, char width, char syncmode) 253 char intr_mode, char dma_mode, char mem_width, char syncmode)
162{ 254{
163 return (direction << 1) | (width << 2) | (dma_mode << 4) | 255#ifdef CONFIG_BF60x
256 return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
257 mem_width, syncmode, mem_width);
258#else
259 return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
164 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5); 260 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
261#endif
165} 262}
166 263
167static inline unsigned short get_dma_curr_irqstat(unsigned int channel) 264static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
168{ 265{
169 return dma_ch[channel].regs->irq_status; 266 return dma_ch[channel].regs->irq_status;
170} 267}
171static inline unsigned short get_dma_curr_xcount(unsigned int channel) 268static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
172{ 269{
173 return dma_ch[channel].regs->curr_x_count; 270 return dma_ch[channel].regs->curr_x_count;
174} 271}
175static inline unsigned short get_dma_curr_ycount(unsigned int channel) 272static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
176{ 273{
177 return dma_ch[channel].regs->curr_y_count; 274 return dma_ch[channel].regs->curr_y_count;
178} 275}
@@ -184,7 +281,7 @@ static inline void *get_dma_curr_desc_ptr(unsigned int channel)
184{ 281{
185 return dma_ch[channel].regs->curr_desc_ptr; 282 return dma_ch[channel].regs->curr_desc_ptr;
186} 283}
187static inline unsigned short get_dma_config(unsigned int channel) 284static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
188{ 285{
189 return dma_ch[channel].regs->cfg; 286 return dma_ch[channel].regs->cfg;
190} 287}
@@ -203,8 +300,8 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize
203 300
204 dma_ch[channel].regs->next_desc_ptr = sg; 301 dma_ch[channel].regs->next_desc_ptr = sg;
205 dma_ch[channel].regs->cfg = 302 dma_ch[channel].regs->cfg =
206 (dma_ch[channel].regs->cfg & ~(0xf << 8)) | 303 (dma_ch[channel].regs->cfg & ~NDSIZE) |
207 ((ndsize & 0xf) << 8); 304 ((ndsize << NDSIZE_OFFSET) & NDSIZE);
208} 305}
209 306
210static inline int dma_channel_active(unsigned int channel) 307static inline int dma_channel_active(unsigned int channel)
@@ -239,7 +336,7 @@ static inline void dma_enable_irq(unsigned int channel)
239} 336}
240static inline void clear_dma_irqstat(unsigned int channel) 337static inline void clear_dma_irqstat(unsigned int channel)
241{ 338{
242 dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR; 339 dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
243} 340}
244 341
245void *dma_memcpy(void *dest, const void *src, size_t count); 342void *dma_memcpy(void *dest, const void *src, size_t count);
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index c4ec959dad78..e91eae8330a6 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -9,6 +9,651 @@
9#ifndef _BLACKFIN_DPMC_H_ 9#ifndef _BLACKFIN_DPMC_H_
10#define _BLACKFIN_DPMC_H_ 10#define _BLACKFIN_DPMC_H_
11 11
12#ifdef __ASSEMBLY__
13#define PM_REG0 R7
14#define PM_REG1 R6
15#define PM_REG2 R5
16#define PM_REG3 R4
17#define PM_REG4 R3
18#define PM_REG5 R2
19#define PM_REG6 R1
20#define PM_REG7 R0
21#define PM_REG8 P5
22#define PM_REG9 P4
23#define PM_REG10 P3
24#define PM_REG11 P2
25#define PM_REG12 P1
26#define PM_REG13 P0
27
28#define PM_REGSET0 R7:7
29#define PM_REGSET1 R7:6
30#define PM_REGSET2 R7:5
31#define PM_REGSET3 R7:4
32#define PM_REGSET4 R7:3
33#define PM_REGSET5 R7:2
34#define PM_REGSET6 R7:1
35#define PM_REGSET7 R7:0
36#define PM_REGSET8 R7:0, P5:5
37#define PM_REGSET9 R7:0, P5:4
38#define PM_REGSET10 R7:0, P5:3
39#define PM_REGSET11 R7:0, P5:2
40#define PM_REGSET12 R7:0, P5:1
41#define PM_REGSET13 R7:0, P5:0
42
43#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
44#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
45#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
46#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
47#define PM_PUSH(n, x) PM_REG##n = [FP++];
48#define PM_POP(n, x) [FP--] = PM_REG##n;
49#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
50#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
51#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
52#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
53#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
54#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
55
56 .macro bfin_init_pm_bench_cycles
57#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
58 R4 = 0;
59 CYCLES = R4;
60 CYCLES2 = R4;
61 R4 = SYSCFG;
62 BITSET(R4, 1);
63 SYSCFG = R4;
64#endif
65 .endm
66
67 .macro bfin_cpu_reg_save
68 /*
69 * Save the core regs early so we can blow them away when
70 * saving/restoring MMR states
71 */
72 [--sp] = (R7:0, P5:0);
73 [--sp] = fp;
74 [--sp] = usp;
75
76 [--sp] = i0;
77 [--sp] = i1;
78 [--sp] = i2;
79 [--sp] = i3;
80
81 [--sp] = m0;
82 [--sp] = m1;
83 [--sp] = m2;
84 [--sp] = m3;
85
86 [--sp] = l0;
87 [--sp] = l1;
88 [--sp] = l2;
89 [--sp] = l3;
90
91 [--sp] = b0;
92 [--sp] = b1;
93 [--sp] = b2;
94 [--sp] = b3;
95 [--sp] = a0.x;
96 [--sp] = a0.w;
97 [--sp] = a1.x;
98 [--sp] = a1.w;
99
100 [--sp] = LC0;
101 [--sp] = LC1;
102 [--sp] = LT0;
103 [--sp] = LT1;
104 [--sp] = LB0;
105 [--sp] = LB1;
106
107 /* We can't push RETI directly as that'll change IPEND[4] */
108 r7 = RETI;
109 [--sp] = RETS;
110 [--sp] = ASTAT;
111#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
112 [--sp] = CYCLES;
113 [--sp] = CYCLES2;
114#endif
115 [--sp] = SYSCFG;
116 [--sp] = RETX;
117 [--sp] = SEQSTAT;
118 [--sp] = r7;
119
120 /* Save first func arg in M3 */
121 M3 = R0;
122 .endm
123
124 .macro bfin_cpu_reg_restore
125 /* Restore Core Registers */
126 RETI = [sp++];
127 SEQSTAT = [sp++];
128 RETX = [sp++];
129 SYSCFG = [sp++];
130#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
131 CYCLES2 = [sp++];
132 CYCLES = [sp++];
133#endif
134 ASTAT = [sp++];
135 RETS = [sp++];
136
137 LB1 = [sp++];
138 LB0 = [sp++];
139 LT1 = [sp++];
140 LT0 = [sp++];
141 LC1 = [sp++];
142 LC0 = [sp++];
143
144 a1.w = [sp++];
145 a1.x = [sp++];
146 a0.w = [sp++];
147 a0.x = [sp++];
148 b3 = [sp++];
149 b2 = [sp++];
150 b1 = [sp++];
151 b0 = [sp++];
152
153 l3 = [sp++];
154 l2 = [sp++];
155 l1 = [sp++];
156 l0 = [sp++];
157
158 m3 = [sp++];
159 m2 = [sp++];
160 m1 = [sp++];
161 m0 = [sp++];
162
163 i3 = [sp++];
164 i2 = [sp++];
165 i1 = [sp++];
166 i0 = [sp++];
167
168 usp = [sp++];
169 fp = [sp++];
170 (R7:0, P5:0) = [sp++];
171
172 .endm
173
174 .macro bfin_sys_mmr_save
175 /* Save system MMRs */
176 FP.H = hi(SYSMMR_BASE);
177 FP.L = lo(SYSMMR_BASE);
178#ifdef SIC_IMASK0
179 PM_SYS_PUSH(0, SIC_IMASK0)
180 PM_SYS_PUSH(1, SIC_IMASK1)
181# ifdef SIC_IMASK2
182 PM_SYS_PUSH(2, SIC_IMASK2)
183# endif
184#else
185# ifdef SIC_IMASK
186 PM_SYS_PUSH(0, SIC_IMASK)
187# endif
188#endif
189
190#ifdef SIC_IAR0
191 PM_SYS_PUSH(3, SIC_IAR0)
192 PM_SYS_PUSH(4, SIC_IAR1)
193 PM_SYS_PUSH(5, SIC_IAR2)
194#endif
195#ifdef SIC_IAR3
196 PM_SYS_PUSH(6, SIC_IAR3)
197#endif
198#ifdef SIC_IAR4
199 PM_SYS_PUSH(7, SIC_IAR4)
200 PM_SYS_PUSH(8, SIC_IAR5)
201 PM_SYS_PUSH(9, SIC_IAR6)
202#endif
203#ifdef SIC_IAR7
204 PM_SYS_PUSH(10, SIC_IAR7)
205#endif
206#ifdef SIC_IAR8
207 PM_SYS_PUSH(11, SIC_IAR8)
208 PM_SYS_PUSH(12, SIC_IAR9)
209 PM_SYS_PUSH(13, SIC_IAR10)
210#endif
211 PM_PUSH_SYNC(13)
212#ifdef SIC_IAR11
213 PM_SYS_PUSH(0, SIC_IAR11)
214#endif
215
216#ifdef SIC_IWR
217 PM_SYS_PUSH(1, SIC_IWR)
218#endif
219#ifdef SIC_IWR0
220 PM_SYS_PUSH(1, SIC_IWR0)
221#endif
222#ifdef SIC_IWR1
223 PM_SYS_PUSH(2, SIC_IWR1)
224#endif
225#ifdef SIC_IWR2
226 PM_SYS_PUSH(3, SIC_IWR2)
227#endif
228
229#ifdef PINT0_ASSIGN
230 PM_SYS_PUSH(4, PINT0_MASK_SET)
231 PM_SYS_PUSH(5, PINT1_MASK_SET)
232 PM_SYS_PUSH(6, PINT2_MASK_SET)
233 PM_SYS_PUSH(7, PINT3_MASK_SET)
234 PM_SYS_PUSH(8, PINT0_ASSIGN)
235 PM_SYS_PUSH(9, PINT1_ASSIGN)
236 PM_SYS_PUSH(10, PINT2_ASSIGN)
237 PM_SYS_PUSH(11, PINT3_ASSIGN)
238 PM_SYS_PUSH(12, PINT0_INVERT_SET)
239 PM_SYS_PUSH(13, PINT1_INVERT_SET)
240 PM_PUSH_SYNC(13)
241 PM_SYS_PUSH(0, PINT2_INVERT_SET)
242 PM_SYS_PUSH(1, PINT3_INVERT_SET)
243 PM_SYS_PUSH(2, PINT0_EDGE_SET)
244 PM_SYS_PUSH(3, PINT1_EDGE_SET)
245 PM_SYS_PUSH(4, PINT2_EDGE_SET)
246 PM_SYS_PUSH(5, PINT3_EDGE_SET)
247#endif
248
249#ifdef SYSCR
250 PM_SYS_PUSH16(6, SYSCR)
251#endif
252
253#ifdef EBIU_AMGCTL
254 PM_SYS_PUSH16(7, EBIU_AMGCTL)
255 PM_SYS_PUSH(8, EBIU_AMBCTL0)
256 PM_SYS_PUSH(9, EBIU_AMBCTL1)
257#endif
258#ifdef EBIU_FCTL
259 PM_SYS_PUSH(10, EBIU_MBSCTL)
260 PM_SYS_PUSH(11, EBIU_MODE)
261 PM_SYS_PUSH(12, EBIU_FCTL)
262 PM_PUSH_SYNC(12)
263#else
264 PM_PUSH_SYNC(9)
265#endif
266 .endm
267
268
269 .macro bfin_sys_mmr_restore
270/* Restore System MMRs */
271 FP.H = hi(SYSMMR_BASE);
272 FP.L = lo(SYSMMR_BASE);
273
274#ifdef EBIU_FCTL
275 PM_POP_SYNC(12)
276 PM_SYS_POP(12, EBIU_FCTL)
277 PM_SYS_POP(11, EBIU_MODE)
278 PM_SYS_POP(10, EBIU_MBSCTL)
279#else
280 PM_POP_SYNC(9)
281#endif
282
283#ifdef EBIU_AMBCTL
284 PM_SYS_POP(9, EBIU_AMBCTL1)
285 PM_SYS_POP(8, EBIU_AMBCTL0)
286 PM_SYS_POP16(7, EBIU_AMGCTL)
287#endif
288
289#ifdef SYSCR
290 PM_SYS_POP16(6, SYSCR)
291#endif
292
293#ifdef PINT0_ASSIGN
294 PM_SYS_POP(5, PINT3_EDGE_SET)
295 PM_SYS_POP(4, PINT2_EDGE_SET)
296 PM_SYS_POP(3, PINT1_EDGE_SET)
297 PM_SYS_POP(2, PINT0_EDGE_SET)
298 PM_SYS_POP(1, PINT3_INVERT_SET)
299 PM_SYS_POP(0, PINT2_INVERT_SET)
300 PM_POP_SYNC(13)
301 PM_SYS_POP(13, PINT1_INVERT_SET)
302 PM_SYS_POP(12, PINT0_INVERT_SET)
303 PM_SYS_POP(11, PINT3_ASSIGN)
304 PM_SYS_POP(10, PINT2_ASSIGN)
305 PM_SYS_POP(9, PINT1_ASSIGN)
306 PM_SYS_POP(8, PINT0_ASSIGN)
307 PM_SYS_POP(7, PINT3_MASK_SET)
308 PM_SYS_POP(6, PINT2_MASK_SET)
309 PM_SYS_POP(5, PINT1_MASK_SET)
310 PM_SYS_POP(4, PINT0_MASK_SET)
311#endif
312
313#ifdef SIC_IWR2
314 PM_SYS_POP(3, SIC_IWR2)
315#endif
316#ifdef SIC_IWR1
317 PM_SYS_POP(2, SIC_IWR1)
318#endif
319#ifdef SIC_IWR0
320 PM_SYS_POP(1, SIC_IWR0)
321#endif
322#ifdef SIC_IWR
323 PM_SYS_POP(1, SIC_IWR)
324#endif
325
326#ifdef SIC_IAR11
327 PM_SYS_POP(0, SIC_IAR11)
328#endif
329 PM_POP_SYNC(13)
330#ifdef SIC_IAR8
331 PM_SYS_POP(13, SIC_IAR10)
332 PM_SYS_POP(12, SIC_IAR9)
333 PM_SYS_POP(11, SIC_IAR8)
334#endif
335#ifdef SIC_IAR7
336 PM_SYS_POP(10, SIC_IAR7)
337#endif
338#ifdef SIC_IAR6
339 PM_SYS_POP(9, SIC_IAR6)
340 PM_SYS_POP(8, SIC_IAR5)
341 PM_SYS_POP(7, SIC_IAR4)
342#endif
343#ifdef SIC_IAR3
344 PM_SYS_POP(6, SIC_IAR3)
345#endif
346#ifdef SIC_IAR0
347 PM_SYS_POP(5, SIC_IAR2)
348 PM_SYS_POP(4, SIC_IAR1)
349 PM_SYS_POP(3, SIC_IAR0)
350#endif
351#ifdef SIC_IMASK0
352# ifdef SIC_IMASK2
353 PM_SYS_POP(2, SIC_IMASK2)
354# endif
355 PM_SYS_POP(1, SIC_IMASK1)
356 PM_SYS_POP(0, SIC_IMASK0)
357#else
358# ifdef SIC_IMASK
359 PM_SYS_POP(0, SIC_IMASK)
360# endif
361#endif
362 .endm
363
364 .macro bfin_core_mmr_save
365 /* Save Core MMRs */
366 I0.H = hi(COREMMR_BASE);
367 I0.L = lo(COREMMR_BASE);
368 I1 = I0;
369 I2 = I0;
370 I3 = I0;
371 B0 = I0;
372 B1 = I0;
373 B2 = I0;
374 B3 = I0;
375 I1.L = lo(DCPLB_ADDR0);
376 I2.L = lo(DCPLB_DATA0);
377 I3.L = lo(ICPLB_ADDR0);
378 B0.L = lo(ICPLB_DATA0);
379 B1.L = lo(EVT2);
380 B2.L = lo(IMASK);
381 B3.L = lo(TCNTL);
382
383 /* Event Vectors */
384 FP = B1;
385 PM_PUSH(0, EVT2)
386 PM_PUSH(1, EVT3)
387 FP += 4; /* EVT4 */
388 PM_PUSH(2, EVT5)
389 PM_PUSH(3, EVT6)
390 PM_PUSH(4, EVT7)
391 PM_PUSH(5, EVT8)
392 PM_PUSH_SYNC(5)
393
394 PM_PUSH(0, EVT9)
395 PM_PUSH(1, EVT10)
396 PM_PUSH(2, EVT11)
397 PM_PUSH(3, EVT12)
398 PM_PUSH(4, EVT13)
399 PM_PUSH(5, EVT14)
400 PM_PUSH(6, EVT15)
401
402 /* CEC */
403 FP = B2;
404 PM_PUSH(7, IMASK)
405 FP += 4; /* IPEND */
406 PM_PUSH(8, ILAT)
407 PM_PUSH(9, IPRIO)
408
409 /* Core Timer */
410 FP = B3;
411 PM_PUSH(10, TCNTL)
412 PM_PUSH(11, TPERIOD)
413 PM_PUSH(12, TSCALE)
414 PM_PUSH(13, TCOUNT)
415 PM_PUSH_SYNC(13)
416
417 /* Misc non-contiguous registers */
418 FP = I0;
419 PM_CORE_PUSH(0, DMEM_CONTROL);
420 PM_CORE_PUSH(1, IMEM_CONTROL);
421 PM_CORE_PUSH(2, TBUFCTL);
422 PM_PUSH_SYNC(2)
423
424 /* DCPLB Addr */
425 FP = I1;
426 PM_PUSH(0, DCPLB_ADDR0)
427 PM_PUSH(1, DCPLB_ADDR1)
428 PM_PUSH(2, DCPLB_ADDR2)
429 PM_PUSH(3, DCPLB_ADDR3)
430 PM_PUSH(4, DCPLB_ADDR4)
431 PM_PUSH(5, DCPLB_ADDR5)
432 PM_PUSH(6, DCPLB_ADDR6)
433 PM_PUSH(7, DCPLB_ADDR7)
434 PM_PUSH(8, DCPLB_ADDR8)
435 PM_PUSH(9, DCPLB_ADDR9)
436 PM_PUSH(10, DCPLB_ADDR10)
437 PM_PUSH(11, DCPLB_ADDR11)
438 PM_PUSH(12, DCPLB_ADDR12)
439 PM_PUSH(13, DCPLB_ADDR13)
440 PM_PUSH_SYNC(13)
441 PM_PUSH(0, DCPLB_ADDR14)
442 PM_PUSH(1, DCPLB_ADDR15)
443
444 /* DCPLB Data */
445 FP = I2;
446 PM_PUSH(2, DCPLB_DATA0)
447 PM_PUSH(3, DCPLB_DATA1)
448 PM_PUSH(4, DCPLB_DATA2)
449 PM_PUSH(5, DCPLB_DATA3)
450 PM_PUSH(6, DCPLB_DATA4)
451 PM_PUSH(7, DCPLB_DATA5)
452 PM_PUSH(8, DCPLB_DATA6)
453 PM_PUSH(9, DCPLB_DATA7)
454 PM_PUSH(10, DCPLB_DATA8)
455 PM_PUSH(11, DCPLB_DATA9)
456 PM_PUSH(12, DCPLB_DATA10)
457 PM_PUSH(13, DCPLB_DATA11)
458 PM_PUSH_SYNC(13)
459 PM_PUSH(0, DCPLB_DATA12)
460 PM_PUSH(1, DCPLB_DATA13)
461 PM_PUSH(2, DCPLB_DATA14)
462 PM_PUSH(3, DCPLB_DATA15)
463
464 /* ICPLB Addr */
465 FP = I3;
466 PM_PUSH(4, ICPLB_ADDR0)
467 PM_PUSH(5, ICPLB_ADDR1)
468 PM_PUSH(6, ICPLB_ADDR2)
469 PM_PUSH(7, ICPLB_ADDR3)
470 PM_PUSH(8, ICPLB_ADDR4)
471 PM_PUSH(9, ICPLB_ADDR5)
472 PM_PUSH(10, ICPLB_ADDR6)
473 PM_PUSH(11, ICPLB_ADDR7)
474 PM_PUSH(12, ICPLB_ADDR8)
475 PM_PUSH(13, ICPLB_ADDR9)
476 PM_PUSH_SYNC(13)
477 PM_PUSH(0, ICPLB_ADDR10)
478 PM_PUSH(1, ICPLB_ADDR11)
479 PM_PUSH(2, ICPLB_ADDR12)
480 PM_PUSH(3, ICPLB_ADDR13)
481 PM_PUSH(4, ICPLB_ADDR14)
482 PM_PUSH(5, ICPLB_ADDR15)
483
484 /* ICPLB Data */
485 FP = B0;
486 PM_PUSH(6, ICPLB_DATA0)
487 PM_PUSH(7, ICPLB_DATA1)
488 PM_PUSH(8, ICPLB_DATA2)
489 PM_PUSH(9, ICPLB_DATA3)
490 PM_PUSH(10, ICPLB_DATA4)
491 PM_PUSH(11, ICPLB_DATA5)
492 PM_PUSH(12, ICPLB_DATA6)
493 PM_PUSH(13, ICPLB_DATA7)
494 PM_PUSH_SYNC(13)
495 PM_PUSH(0, ICPLB_DATA8)
496 PM_PUSH(1, ICPLB_DATA9)
497 PM_PUSH(2, ICPLB_DATA10)
498 PM_PUSH(3, ICPLB_DATA11)
499 PM_PUSH(4, ICPLB_DATA12)
500 PM_PUSH(5, ICPLB_DATA13)
501 PM_PUSH(6, ICPLB_DATA14)
502 PM_PUSH(7, ICPLB_DATA15)
503 PM_PUSH_SYNC(7)
504 .endm
505
506 .macro bfin_core_mmr_restore
507 /* Restore Core MMRs */
508 I0.H = hi(COREMMR_BASE);
509 I0.L = lo(COREMMR_BASE);
510 I1 = I0;
511 I2 = I0;
512 I3 = I0;
513 B0 = I0;
514 B1 = I0;
515 B2 = I0;
516 B3 = I0;
517 I1.L = lo(DCPLB_ADDR15);
518 I2.L = lo(DCPLB_DATA15);
519 I3.L = lo(ICPLB_ADDR15);
520 B0.L = lo(ICPLB_DATA15);
521 B1.L = lo(EVT15);
522 B2.L = lo(IPRIO);
523 B3.L = lo(TCOUNT);
524
525 /* ICPLB Data */
526 FP = B0;
527 PM_POP_SYNC(7)
528 PM_POP(7, ICPLB_DATA15)
529 PM_POP(6, ICPLB_DATA14)
530 PM_POP(5, ICPLB_DATA13)
531 PM_POP(4, ICPLB_DATA12)
532 PM_POP(3, ICPLB_DATA11)
533 PM_POP(2, ICPLB_DATA10)
534 PM_POP(1, ICPLB_DATA9)
535 PM_POP(0, ICPLB_DATA8)
536 PM_POP_SYNC(13)
537 PM_POP(13, ICPLB_DATA7)
538 PM_POP(12, ICPLB_DATA6)
539 PM_POP(11, ICPLB_DATA5)
540 PM_POP(10, ICPLB_DATA4)
541 PM_POP(9, ICPLB_DATA3)
542 PM_POP(8, ICPLB_DATA2)
543 PM_POP(7, ICPLB_DATA1)
544 PM_POP(6, ICPLB_DATA0)
545
546 /* ICPLB Addr */
547 FP = I3;
548 PM_POP(5, ICPLB_ADDR15)
549 PM_POP(4, ICPLB_ADDR14)
550 PM_POP(3, ICPLB_ADDR13)
551 PM_POP(2, ICPLB_ADDR12)
552 PM_POP(1, ICPLB_ADDR11)
553 PM_POP(0, ICPLB_ADDR10)
554 PM_POP_SYNC(13)
555 PM_POP(13, ICPLB_ADDR9)
556 PM_POP(12, ICPLB_ADDR8)
557 PM_POP(11, ICPLB_ADDR7)
558 PM_POP(10, ICPLB_ADDR6)
559 PM_POP(9, ICPLB_ADDR5)
560 PM_POP(8, ICPLB_ADDR4)
561 PM_POP(7, ICPLB_ADDR3)
562 PM_POP(6, ICPLB_ADDR2)
563 PM_POP(5, ICPLB_ADDR1)
564 PM_POP(4, ICPLB_ADDR0)
565
566 /* DCPLB Data */
567 FP = I2;
568 PM_POP(3, DCPLB_DATA15)
569 PM_POP(2, DCPLB_DATA14)
570 PM_POP(1, DCPLB_DATA13)
571 PM_POP(0, DCPLB_DATA12)
572 PM_POP_SYNC(13)
573 PM_POP(13, DCPLB_DATA11)
574 PM_POP(12, DCPLB_DATA10)
575 PM_POP(11, DCPLB_DATA9)
576 PM_POP(10, DCPLB_DATA8)
577 PM_POP(9, DCPLB_DATA7)
578 PM_POP(8, DCPLB_DATA6)
579 PM_POP(7, DCPLB_DATA5)
580 PM_POP(6, DCPLB_DATA4)
581 PM_POP(5, DCPLB_DATA3)
582 PM_POP(4, DCPLB_DATA2)
583 PM_POP(3, DCPLB_DATA1)
584 PM_POP(2, DCPLB_DATA0)
585
586 /* DCPLB Addr */
587 FP = I1;
588 PM_POP(1, DCPLB_ADDR15)
589 PM_POP(0, DCPLB_ADDR14)
590 PM_POP_SYNC(13)
591 PM_POP(13, DCPLB_ADDR13)
592 PM_POP(12, DCPLB_ADDR12)
593 PM_POP(11, DCPLB_ADDR11)
594 PM_POP(10, DCPLB_ADDR10)
595 PM_POP(9, DCPLB_ADDR9)
596 PM_POP(8, DCPLB_ADDR8)
597 PM_POP(7, DCPLB_ADDR7)
598 PM_POP(6, DCPLB_ADDR6)
599 PM_POP(5, DCPLB_ADDR5)
600 PM_POP(4, DCPLB_ADDR4)
601 PM_POP(3, DCPLB_ADDR3)
602 PM_POP(2, DCPLB_ADDR2)
603 PM_POP(1, DCPLB_ADDR1)
604 PM_POP(0, DCPLB_ADDR0)
605
606
607 /* Misc non-contiguous registers */
608
609 /* icache & dcache will enable later
610 drop IMEM_CONTROL, DMEM_CONTROL pop
611 */
612 FP = I0;
613 PM_POP_SYNC(2)
614 PM_CORE_POP(2, TBUFCTL)
615 PM_CORE_POP(1, IMEM_CONTROL)
616 PM_CORE_POP(0, DMEM_CONTROL)
617
618 /* Core Timer */
619 FP = B3;
620 R0 = 0x1;
621 [FP - 0xC] = R0;
622
623 PM_POP_SYNC(13)
624 FP = B3;
625 PM_POP(13, TCOUNT)
626 PM_POP(12, TSCALE)
627 PM_POP(11, TPERIOD)
628 PM_POP(10, TCNTL)
629
630 /* CEC */
631 FP = B2;
632 PM_POP(9, IPRIO)
633 PM_POP(8, ILAT)
634 FP += -4; /* IPEND */
635 PM_POP(7, IMASK)
636
637 /* Event Vectors */
638 FP = B1;
639 PM_POP(6, EVT15)
640 PM_POP(5, EVT14)
641 PM_POP(4, EVT13)
642 PM_POP(3, EVT12)
643 PM_POP(2, EVT11)
644 PM_POP(1, EVT10)
645 PM_POP(0, EVT9)
646 PM_POP_SYNC(5)
647 PM_POP(5, EVT8)
648 PM_POP(4, EVT7)
649 PM_POP(3, EVT6)
650 PM_POP(2, EVT5)
651 FP += -4; /* EVT4 */
652 PM_POP(1, EVT3)
653 PM_POP(0, EVT2)
654 .endm
655#endif
656
12#include <mach/pll.h> 657#include <mach/pll.h>
13 658
14/* PLL_CTL Masks */ 659/* PLL_CTL Masks */
@@ -98,6 +743,16 @@
98#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 743#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
99#endif 744#endif
100 745
746#ifdef CONFIG_BF60x
747#define PA15WE 0x00000001 /* Allow Wake-Up from PA15 */
748#define PB15WE 0x00000002 /* Allow Wake-Up from PB15 */
749#define PC15WE 0x00000004 /* Allow Wake-Up from PC15 */
750#define PD06WE 0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */
751#define PE12WE 0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */
752#define PG04WE 0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */
753#define PG13WE 0x00000040 /* Allow Wake-Up from PG13 */
754#define USBWE 0x00000080 /* Allow Wake-Up from (USB) */
755#else
101#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 756#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
102#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ 757#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
103#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ 758#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
@@ -113,6 +768,7 @@
113#else 768#else
114#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */ 769#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
115#endif 770#endif
771#endif
116 772
117#ifndef __ASSEMBLY__ 773#ifndef __ASSEMBLY__
118 774
diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h
index 73fe53e7fd24..5395088b2d0e 100644
--- a/arch/blackfin/include/asm/fixed_code.h
+++ b/arch/blackfin/include/asm/fixed_code.h
@@ -29,24 +29,28 @@ extern void sigreturn_stub(void);
29#endif 29#endif
30#endif 30#endif
31 31
32#define FIXED_CODE_START 0x400 32#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
33#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0
34#endif
35
36#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
33 37
34#define SIGRETURN_STUB 0x400 38#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
35 39
36#define ATOMIC_SEQS_START 0x410 40#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
37 41
38#define ATOMIC_XCHG32 0x410 42#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
39#define ATOMIC_CAS32 0x420 43#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
40#define ATOMIC_ADD32 0x430 44#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
41#define ATOMIC_SUB32 0x440 45#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
42#define ATOMIC_IOR32 0x450 46#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
43#define ATOMIC_AND32 0x460 47#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
44#define ATOMIC_XOR32 0x470 48#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
45 49
46#define ATOMIC_SEQS_END 0x480 50#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
47 51
48#define SAFE_USER_INSTRUCTION 0x480 52#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
49 53
50#define FIXED_CODE_END 0x490 54#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
51 55
52#endif 56#endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 12d3571b5232..3d84d96f7c2c 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -26,6 +26,7 @@
26#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
27 27
28#include <linux/compiler.h> 28#include <linux/compiler.h>
29#include <linux/gpio.h>
29 30
30/*********************************************************** 31/***********************************************************
31* 32*
@@ -244,6 +245,49 @@ static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
244 return -EINVAL; 245 return -EINVAL;
245} 246}
246 247
248static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
249{
250 int err;
251
252 err = bfin_gpio_request(gpio, label);
253 if (err)
254 return err;
255
256 if (flags & GPIOF_DIR_IN)
257 err = bfin_gpio_direction_input(gpio);
258 else
259 err = bfin_gpio_direction_output(gpio,
260 (flags & GPIOF_INIT_HIGH) ? 1 : 0);
261
262 if (err)
263 bfin_gpio_free(gpio);
264
265 return err;
266}
267
268static inline int gpio_request_array(const struct gpio *array, size_t num)
269{
270 int i, err;
271
272 for (i = 0; i < num; i++, array++) {
273 err = gpio_request_one(array->gpio, array->flags, array->label);
274 if (err)
275 goto err_free;
276 }
277 return 0;
278
279err_free:
280 while (i--)
281 bfin_gpio_free((--array)->gpio);
282 return err;
283}
284
285static inline void gpio_free_array(const struct gpio *array, size_t num)
286{
287 while (num--)
288 bfin_gpio_free((array++)->gpio);
289}
290
247static inline int __gpio_get_value(unsigned gpio) 291static inline int __gpio_get_value(unsigned gpio)
248{ 292{
249 return bfin_gpio_get_value(gpio); 293 return bfin_gpio_get_value(gpio);
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index 38bddcb190c8..381e3d621a4c 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -44,6 +44,13 @@
44# define TIMER_GROUP2 1 44# define TIMER_GROUP2 1
45#endif 45#endif
46/* 46/*
47 * BF609: 8 timers:
48 */
49#if defined(CONFIG_BF60x)
50# define MAX_BLACKFIN_GPTIMERS 8
51# define TIMER0_GROUP_REG TIMER_RUN
52#endif
53/*
47 * All others: 3 timers: 54 * All others: 3 timers:
48 */ 55 */
49#define TIMER_GROUP1 0 56#define TIMER_GROUP1 0
@@ -104,6 +111,72 @@
104# define FS2_TIMER_BIT TIMER1bit 111# define FS2_TIMER_BIT TIMER1bit
105#endif 112#endif
106 113
114#ifdef CONFIG_BF60x
115/*
116 * Timer Configuration Register Bits
117 */
118#define TIMER_EMU_RUN 0x8000
119#define TIMER_BPER_EN 0x4000
120#define TIMER_BWID_EN 0x2000
121#define TIMER_BDLY_EN 0x1000
122#define TIMER_OUT_DIS 0x0800
123#define TIMER_TIN_SEL 0x0400
124#define TIMER_CLK_SEL 0x0300
125#define TIMER_CLK_SCLK 0x0000
126#define TIMER_CLK_ALT_CLK0 0x0100
127#define TIMER_CLK_ALT_CLK1 0x0300
128#define TIMER_PULSE_HI 0x0080
129#define TIMER_SLAVE_TRIG 0x0040
130#define TIMER_IRQ_MODE 0x0030
131#define TIMER_IRQ_ACT_EDGE 0x0000
132#define TIMER_IRQ_DLY 0x0010
133#define TIMER_IRQ_WID_DLY 0x0020
134#define TIMER_IRQ_PER 0x0030
135#define TIMER_MODE 0x000f
136#define TIMER_MODE_WDOG_P 0x0008
137#define TIMER_MODE_WDOG_W 0x0009
138#define TIMER_MODE_PWM_CONT 0x000c
139#define TIMER_MODE_PWM 0x000d
140#define TIMER_MODE_WDTH 0x000a
141#define TIMER_MODE_WDTH_D 0x000b
142#define TIMER_MODE_EXT_CLK 0x000e
143#define TIMER_MODE_PININT 0x000f
144
145/*
146 * Timer Status Register Bits
147 */
148#define TIMER_STATUS_TIMIL0 0x0001
149#define TIMER_STATUS_TIMIL1 0x0002
150#define TIMER_STATUS_TIMIL2 0x0004
151#define TIMER_STATUS_TIMIL3 0x0008
152#define TIMER_STATUS_TIMIL4 0x0010
153#define TIMER_STATUS_TIMIL5 0x0020
154#define TIMER_STATUS_TIMIL6 0x0040
155#define TIMER_STATUS_TIMIL7 0x0080
156
157#define TIMER_STATUS_TOVF0 0x0001 /* timer 0 overflow error */
158#define TIMER_STATUS_TOVF1 0x0002
159#define TIMER_STATUS_TOVF2 0x0004
160#define TIMER_STATUS_TOVF3 0x0008
161#define TIMER_STATUS_TOVF4 0x0010
162#define TIMER_STATUS_TOVF5 0x0020
163#define TIMER_STATUS_TOVF6 0x0040
164#define TIMER_STATUS_TOVF7 0x0080
165
166/*
167 * Timer Slave Enable Status : write 1 to clear
168 */
169#define TIMER_STATUS_TRUN0 0x0001
170#define TIMER_STATUS_TRUN1 0x0002
171#define TIMER_STATUS_TRUN2 0x0004
172#define TIMER_STATUS_TRUN3 0x0008
173#define TIMER_STATUS_TRUN4 0x0010
174#define TIMER_STATUS_TRUN5 0x0020
175#define TIMER_STATUS_TRUN6 0x0040
176#define TIMER_STATUS_TRUN7 0x0080
177
178#else
179
107/* 180/*
108 * Timer Configuration Register Bits 181 * Timer Configuration Register Bits
109 */ 182 */
@@ -170,12 +243,18 @@
170#define TIMER_STATUS_TRUN10 0x4000 243#define TIMER_STATUS_TRUN10 0x4000
171#define TIMER_STATUS_TRUN11 0x8000 244#define TIMER_STATUS_TRUN11 0x8000
172 245
246#endif
247
173/* The actual gptimer API */ 248/* The actual gptimer API */
174 249
175void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); 250void set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
176uint32_t get_gptimer_pwidth(unsigned int timer_id); 251uint32_t get_gptimer_pwidth(unsigned int timer_id);
177void set_gptimer_period(unsigned int timer_id, uint32_t period); 252void set_gptimer_period(unsigned int timer_id, uint32_t period);
178uint32_t get_gptimer_period(unsigned int timer_id); 253uint32_t get_gptimer_period(unsigned int timer_id);
254#ifdef CONFIG_BF60x
255void set_gptimer_delay(unsigned int timer_id, uint32_t delay);
256uint32_t get_gptimer_delay(unsigned int timer_id);
257#endif
179uint32_t get_gptimer_count(unsigned int timer_id); 258uint32_t get_gptimer_count(unsigned int timer_id);
180int get_gptimer_intr(unsigned int timer_id); 259int get_gptimer_intr(unsigned int timer_id);
181void clear_gptimer_intr(unsigned int timer_id); 260void clear_gptimer_intr(unsigned int timer_id);
@@ -217,16 +296,41 @@ struct bfin_gptimer_regs {
217 u32 counter; 296 u32 counter;
218 u32 period; 297 u32 period;
219 u32 width; 298 u32 width;
299#ifdef CONFIG_BF60x
300 u32 delay;
301#endif
220}; 302};
221 303
222/* 304/*
223 * bfin group timer registers layout 305 * bfin group timer registers layout
224 */ 306 */
307#ifndef CONFIG_BF60x
225struct bfin_gptimer_group_regs { 308struct bfin_gptimer_group_regs {
226 __BFP(enable); 309 __BFP(enable);
227 __BFP(disable); 310 __BFP(disable);
228 u32 status; 311 u32 status;
229}; 312};
313#else
314struct bfin_gptimer_group_regs {
315 __BFP(run);
316 __BFP(enable);
317 __BFP(disable);
318 __BFP(stop_cfg);
319 __BFP(stop_cfg_set);
320 __BFP(stop_cfg_clr);
321 __BFP(data_imsk);
322 __BFP(stat_imsk);
323 __BFP(tr_msk);
324 __BFP(tr_ie);
325 __BFP(data_ilat);
326 __BFP(stat_ilat);
327 __BFP(err_status);
328 __BFP(bcast_per);
329 __BFP(bcast_wid);
330 __BFP(bcast_dly);
331
332};
333#endif
230 334
231#undef __BFP 335#undef __BFP
232 336
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 43eb4749de3d..07aff230a812 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -67,7 +67,11 @@ static inline notrace unsigned long __hard_local_irq_save(void)
67 67
68static inline notrace int hard_irqs_disabled_flags(unsigned long flags) 68static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
69{ 69{
70#ifdef CONFIG_BF60x
71 return (flags & IMASK_IVG11) == 0;
72#else
70 return (flags & ~0x3f) == 0; 73 return (flags & ~0x3f) == 0;
74#endif
71} 75}
72 76
73static inline notrace int hard_irqs_disabled(void) 77static inline notrace int hard_irqs_disabled(void)
@@ -224,7 +228,7 @@ static inline notrace void hard_local_irq_restore(unsigned long flags)
224 * Direct interface to linux/irqflags.h. 228 * Direct interface to linux/irqflags.h.
225 */ 229 */
226#define arch_local_save_flags() hard_local_save_flags() 230#define arch_local_save_flags() hard_local_save_flags()
227#define arch_local_irq_save(flags) __hard_local_irq_save() 231#define arch_local_irq_save() __hard_local_irq_save()
228#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags) 232#define arch_local_irq_restore(flags) __hard_local_irq_restore(flags)
229#define arch_local_irq_enable() __hard_local_irq_enable() 233#define arch_local_irq_enable() __hard_local_irq_enable()
230#define arch_local_irq_disable() __hard_local_irq_disable() 234#define arch_local_irq_disable() __hard_local_irq_disable()
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
index 7202404966f6..b93474d5be75 100644
--- a/arch/blackfin/include/asm/page.h
+++ b/arch/blackfin/include/asm/page.h
@@ -7,14 +7,15 @@
7#ifndef _BLACKFIN_PAGE_H 7#ifndef _BLACKFIN_PAGE_H
8#define _BLACKFIN_PAGE_H 8#define _BLACKFIN_PAGE_H
9 9
10#include <asm-generic/page.h> 10#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
11#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) 11#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
12 12
13#define VM_DATA_DEFAULT_FLAGS \ 13#define VM_DATA_DEFAULT_FLAGS \
14 (VM_READ | VM_WRITE | \ 14 (VM_READ | VM_WRITE | \
15 ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \ 15 ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
16 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) 16 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
17 17
18#include <asm-generic/page.h>
18#include <asm-generic/memory_model.h> 19#include <asm-generic/memory_model.h>
19#include <asm-generic/getorder.h> 20#include <asm-generic/getorder.h>
20 21
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
index 28c2498c9c98..68d6f6618f2a 100644
--- a/arch/blackfin/include/asm/pda.h
+++ b/arch/blackfin/include/asm/pda.h
@@ -13,7 +13,9 @@
13#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
14 14
15struct blackfin_pda { /* Per-processor Data Area */ 15struct blackfin_pda { /* Per-processor Data Area */
16#ifdef CONFIG_SMP
16 struct blackfin_pda *next; 17 struct blackfin_pda *next;
18#endif
17 19
18 unsigned long syscfg; 20 unsigned long syscfg;
19#ifdef CONFIG_SMP 21#ifdef CONFIG_SMP
diff --git a/arch/blackfin/include/asm/pm.h b/arch/blackfin/include/asm/pm.h
new file mode 100644
index 000000000000..f72239bf3638
--- /dev/null
+++ b/arch/blackfin/include/asm/pm.h
@@ -0,0 +1,31 @@
1/*
2 * Blackfin bf609 power management
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2
7 */
8
9#ifndef __PM_H__
10#define __PM_H__
11
12#include <linux/suspend.h>
13
14struct bfin_cpu_pm_fns {
15 void (*save)(unsigned long *);
16 void (*restore)(unsigned long *);
17 int (*valid)(suspend_state_t state);
18 void (*enter)(suspend_state_t state);
19 int (*prepare)(void);
20 void (*finish)(void);
21};
22
23extern struct bfin_cpu_pm_fns *bfin_cpu_pm;
24
25# ifdef CONFIG_BFIN_COREB
26void bfin_coreb_start(void);
27void bfin_coreb_stop(void);
28void bfin_coreb_reset(void);
29# endif
30
31#endif
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 75ec9df5318b..3287222cba34 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -11,7 +11,7 @@
11 */ 11 */
12#define __NR_restart_syscall 0 12#define __NR_restart_syscall 0
13#define __NR_exit 1 13#define __NR_exit 1
14#define __NR_fork 2 14 /* 2 __NR_fork not supported on nommu */
15#define __NR_read 3 15#define __NR_read 3
16#define __NR_write 4 16#define __NR_write 4
17#define __NR_open 5 17#define __NR_open 5
diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c
index 40c2ed61258e..c166939ffb2b 100644
--- a/arch/blackfin/kernel/bfin_dma.c
+++ b/arch/blackfin/kernel/bfin_dma.c
@@ -45,9 +45,15 @@ static int __init blackfin_dma_init(void)
45 atomic_set(&dma_ch[i].chan_status, 0); 45 atomic_set(&dma_ch[i].chan_status, 0);
46 dma_ch[i].regs = dma_io_base_addr[i]; 46 dma_ch[i].regs = dma_io_base_addr[i];
47 } 47 }
48#ifdef CH_MEM_STREAM3_SRC
49 /* Mark MEMDMA Channel 3 as requested since we're using it internally */
50 request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
51 request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
52#else
48 /* Mark MEMDMA Channel 0 as requested since we're using it internally */ 53 /* Mark MEMDMA Channel 0 as requested since we're using it internally */
49 request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); 54 request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
50 request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy"); 55 request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
56#endif
51 57
52#if defined(CONFIG_DEB_DMA_URGENT) 58#if defined(CONFIG_DEB_DMA_URGENT)
53 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() 59 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
@@ -84,7 +90,8 @@ static const struct file_operations proc_dma_operations = {
84 90
85static int __init proc_dma_init(void) 91static int __init proc_dma_init(void)
86{ 92{
87 return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL; 93 proc_create("dma", 0, NULL, &proc_dma_operations);
94 return 0;
88} 95}
89late_initcall(proc_dma_init); 96late_initcall(proc_dma_init);
90#endif 97#endif
@@ -204,6 +211,7 @@ EXPORT_SYMBOL(free_dma);
204# ifndef MAX_DMA_SUSPEND_CHANNELS 211# ifndef MAX_DMA_SUSPEND_CHANNELS
205# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS 212# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
206# endif 213# endif
214# ifndef CONFIG_BF60x
207int blackfin_dma_suspend(void) 215int blackfin_dma_suspend(void)
208{ 216{
209 int i; 217 int i;
@@ -213,7 +221,6 @@ int blackfin_dma_suspend(void)
213 printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); 221 printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
214 return -EBUSY; 222 return -EBUSY;
215 } 223 }
216
217 if (i < MAX_DMA_SUSPEND_CHANNELS) 224 if (i < MAX_DMA_SUSPEND_CHANNELS)
218 dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; 225 dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
219 } 226 }
@@ -230,7 +237,6 @@ void blackfin_dma_resume(void)
230 237
231 for (i = 0; i < MAX_DMA_CHANNELS; ++i) { 238 for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
232 dma_ch[i].regs->cfg = 0; 239 dma_ch[i].regs->cfg = 0;
233
234 if (i < MAX_DMA_SUSPEND_CHANNELS) 240 if (i < MAX_DMA_SUSPEND_CHANNELS)
235 dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map; 241 dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
236 } 242 }
@@ -238,6 +244,16 @@ void blackfin_dma_resume(void)
238 bfin_write_DMAC_TC_PER(0x0111); 244 bfin_write_DMAC_TC_PER(0x0111);
239#endif 245#endif
240} 246}
247# else
248int blackfin_dma_suspend(void)
249{
250 return 0;
251}
252
253void blackfin_dma_resume(void)
254{
255}
256#endif
241#endif 257#endif
242 258
243/** 259/**
@@ -279,10 +295,10 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
279 src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR; 295 src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
280 } 296 }
281 297
282 if (!bfin_read16(&src_ch->cfg)) 298 if (!DMA_MMR_READ(&src_ch->cfg))
283 break; 299 break;
284 else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) { 300 else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
285 bfin_write16(&src_ch->cfg, 0); 301 DMA_MMR_WRITE(&src_ch->cfg, 0);
286 break; 302 break;
287 } 303 }
288 } 304 }
@@ -295,22 +311,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
295 311
296 /* Destination */ 312 /* Destination */
297 bfin_write32(&dst_ch->start_addr, dst); 313 bfin_write32(&dst_ch->start_addr, dst);
298 bfin_write16(&dst_ch->x_count, size >> 2); 314 DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
299 bfin_write16(&dst_ch->x_modify, 1 << 2); 315 DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
300 bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR); 316 DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
301 317
302 /* Source */ 318 /* Source */
303 bfin_write32(&src_ch->start_addr, src); 319 bfin_write32(&src_ch->start_addr, src);
304 bfin_write16(&src_ch->x_count, size >> 2); 320 DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
305 bfin_write16(&src_ch->x_modify, 1 << 2); 321 DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
306 bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR); 322 DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
307 323
308 /* Enable */ 324 /* Enable */
309 bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32); 325 DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
310 bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32); 326 DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
311 327
312 /* Since we are atomic now, don't use the workaround ssync */ 328 /* Since we are atomic now, don't use the workaround ssync */
313 __builtin_bfin_ssync(); 329 __builtin_bfin_ssync();
330
331#ifdef CONFIG_BF60x
332 /* Work around a possible MDMA anomaly. Running 2 MDMA channels to
333 * transfer DDR data to L1 SRAM may corrupt data.
334 * Should be reverted after this issue is root caused.
335 */
336 while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
337 continue;
338#endif
314} 339}
315 340
316void __init early_dma_memcpy_done(void) 341void __init early_dma_memcpy_done(void)
@@ -336,6 +361,42 @@ void __init early_dma_memcpy_done(void)
336 __builtin_bfin_ssync(); 361 __builtin_bfin_ssync();
337} 362}
338 363
364#ifdef CH_MEM_STREAM3_SRC
365#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
366#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
367#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
368#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
369#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
370#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
371#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
372#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
373#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
374#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
375#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
376#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
377#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
378#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
379#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
380#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
381#else
382#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
383#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
384#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
385#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
386#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
387#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
388#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
389#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
390#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
391#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
392#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
393#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
394#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
395#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
396#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
397#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
398#endif
399
339/** 400/**
340 * __dma_memcpy - program the MDMA registers 401 * __dma_memcpy - program the MDMA registers
341 * 402 *
@@ -358,8 +419,8 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
358 */ 419 */
359 __builtin_bfin_ssync(); 420 __builtin_bfin_ssync();
360 421
361 if (bfin_read_MDMA_S0_CONFIG()) 422 if (bfin_read_MDMA_S_CONFIG())
362 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) 423 while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
363 continue; 424 continue;
364 425
365 if (conf & DMA2D) { 426 if (conf & DMA2D) {
@@ -374,39 +435,42 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
374 u32 shift = abs(dmod) >> 1; 435 u32 shift = abs(dmod) >> 1;
375 size_t ycnt = cnt >> (16 - shift); 436 size_t ycnt = cnt >> (16 - shift);
376 cnt = 1 << (16 - shift); 437 cnt = 1 << (16 - shift);
377 bfin_write_MDMA_D0_Y_COUNT(ycnt); 438 bfin_write_MDMA_D_Y_COUNT(ycnt);
378 bfin_write_MDMA_S0_Y_COUNT(ycnt); 439 bfin_write_MDMA_S_Y_COUNT(ycnt);
379 bfin_write_MDMA_D0_Y_MODIFY(dmod); 440 bfin_write_MDMA_D_Y_MODIFY(dmod);
380 bfin_write_MDMA_S0_Y_MODIFY(smod); 441 bfin_write_MDMA_S_Y_MODIFY(smod);
381 } 442 }
382 443
383 bfin_write_MDMA_D0_START_ADDR(daddr); 444 bfin_write_MDMA_D_START_ADDR(daddr);
384 bfin_write_MDMA_D0_X_COUNT(cnt); 445 bfin_write_MDMA_D_X_COUNT(cnt);
385 bfin_write_MDMA_D0_X_MODIFY(dmod); 446 bfin_write_MDMA_D_X_MODIFY(dmod);
386 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 447 bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
387 448
388 bfin_write_MDMA_S0_START_ADDR(saddr); 449 bfin_write_MDMA_S_START_ADDR(saddr);
389 bfin_write_MDMA_S0_X_COUNT(cnt); 450 bfin_write_MDMA_S_X_COUNT(cnt);
390 bfin_write_MDMA_S0_X_MODIFY(smod); 451 bfin_write_MDMA_S_X_MODIFY(smod);
391 bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR); 452 bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
392 453
393 bfin_write_MDMA_S0_CONFIG(DMAEN | conf); 454 bfin_write_MDMA_S_CONFIG(DMAEN | conf);
394 bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf); 455 if (conf & DMA2D)
456 bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
457 else
458 bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
395 459
396 spin_unlock_irqrestore(&mdma_lock, flags); 460 spin_unlock_irqrestore(&mdma_lock, flags);
397 461
398 SSYNC(); 462 SSYNC();
399 463
400 while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) 464 while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
401 if (bfin_read_MDMA_S0_CONFIG()) 465 if (bfin_read_MDMA_S_CONFIG())
402 continue; 466 continue;
403 else 467 else
404 return; 468 return;
405 469
406 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 470 bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
407 471
408 bfin_write_MDMA_S0_CONFIG(0); 472 bfin_write_MDMA_S_CONFIG(0);
409 bfin_write_MDMA_D0_CONFIG(0); 473 bfin_write_MDMA_D_CONFIG(0);
410} 474}
411 475
412/** 476/**
@@ -448,8 +512,10 @@ static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
448 } 512 }
449 size >>= shift; 513 size >>= shift;
450 514
515#ifndef DMA_MMR_SIZE_32
451 if (size > 0x10000) 516 if (size > 0x10000)
452 conf |= DMA2D; 517 conf |= DMA2D;
518#endif
453 519
454 __dma_memcpy(dst, mod, src, mod, size, conf); 520 __dma_memcpy(dst, mod, src, mod, size, conf);
455 521
@@ -488,6 +554,9 @@ EXPORT_SYMBOL(dma_memcpy);
488 */ 554 */
489void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size) 555void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
490{ 556{
557#ifdef DMA_MMR_SIZE_32
558 _dma_memcpy(pdst, psrc, size);
559#else
491 size_t bulk, rest; 560 size_t bulk, rest;
492 561
493 bulk = size & ~0xffff; 562 bulk = size & ~0xffff;
@@ -495,6 +564,7 @@ void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
495 if (bulk) 564 if (bulk)
496 _dma_memcpy(pdst, psrc, bulk); 565 _dma_memcpy(pdst, psrc, bulk);
497 _dma_memcpy(pdst + bulk, psrc + bulk, rest); 566 _dma_memcpy(pdst + bulk, psrc + bulk, rest);
567#endif
498 return pdst; 568 return pdst;
499} 569}
500EXPORT_SYMBOL(dma_memcpy_nocache); 570EXPORT_SYMBOL(dma_memcpy_nocache);
@@ -514,14 +584,14 @@ void *safe_dma_memcpy(void *dst, const void *src, size_t size)
514} 584}
515EXPORT_SYMBOL(safe_dma_memcpy); 585EXPORT_SYMBOL(safe_dma_memcpy);
516 586
517static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len, 587static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
518 u16 size, u16 dma_size) 588 u16 size, u16 dma_size)
519{ 589{
520 blackfin_dcache_flush_range(buf, buf + len * size); 590 blackfin_dcache_flush_range(buf, buf + len * size);
521 __dma_memcpy(addr, 0, buf, size, len, dma_size); 591 __dma_memcpy(addr, 0, buf, size, len, dma_size);
522} 592}
523 593
524static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len, 594static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
525 u16 size, u16 dma_size) 595 u16 size, u16 dma_size)
526{ 596{
527 blackfin_dcache_invalidate_range(buf, buf + len * size); 597 blackfin_dcache_invalidate_range(buf, buf + len * size);
@@ -529,7 +599,7 @@ static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
529} 599}
530 600
531#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \ 601#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
532void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \ 602void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
533{ \ 603{ \
534 _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \ 604 _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
535} \ 605} \
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 02796b88443d..83139aaf3072 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -58,7 +58,7 @@ static struct gpio_port_t * const gpio_array[] = {
58 (struct gpio_port_t *) FIO0_FLAG_D, 58 (struct gpio_port_t *) FIO0_FLAG_D,
59 (struct gpio_port_t *) FIO1_FLAG_D, 59 (struct gpio_port_t *) FIO1_FLAG_D,
60 (struct gpio_port_t *) FIO2_FLAG_D, 60 (struct gpio_port_t *) FIO2_FLAG_D,
61#elif defined(CONFIG_BF54x) 61#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
62 (struct gpio_port_t *)PORTA_FER, 62 (struct gpio_port_t *)PORTA_FER,
63 (struct gpio_port_t *)PORTB_FER, 63 (struct gpio_port_t *)PORTB_FER,
64 (struct gpio_port_t *)PORTC_FER, 64 (struct gpio_port_t *)PORTC_FER,
@@ -66,9 +66,11 @@ static struct gpio_port_t * const gpio_array[] = {
66 (struct gpio_port_t *)PORTE_FER, 66 (struct gpio_port_t *)PORTE_FER,
67 (struct gpio_port_t *)PORTF_FER, 67 (struct gpio_port_t *)PORTF_FER,
68 (struct gpio_port_t *)PORTG_FER, 68 (struct gpio_port_t *)PORTG_FER,
69# if defined(CONFIG_BF54x)
69 (struct gpio_port_t *)PORTH_FER, 70 (struct gpio_port_t *)PORTH_FER,
70 (struct gpio_port_t *)PORTI_FER, 71 (struct gpio_port_t *)PORTI_FER,
71 (struct gpio_port_t *)PORTJ_FER, 72 (struct gpio_port_t *)PORTJ_FER,
73# endif
72#else 74#else
73# error no gpio arrays defined 75# error no gpio arrays defined
74#endif 76#endif
@@ -210,7 +212,7 @@ static void port_setup(unsigned gpio, unsigned short usage)
210 else 212 else
211 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); 213 *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
212 SSYNC(); 214 SSYNC();
213#elif defined(CONFIG_BF54x) 215#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
214 if (usage == GPIO_USAGE) 216 if (usage == GPIO_USAGE)
215 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); 217 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
216 else 218 else
@@ -299,7 +301,7 @@ static void portmux_setup(unsigned short per)
299 pmux |= (function << offset); 301 pmux |= (function << offset);
300 bfin_write_PORT_MUX(pmux); 302 bfin_write_PORT_MUX(pmux);
301} 303}
302#elif defined(CONFIG_BF54x) 304#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
303inline void portmux_setup(unsigned short per) 305inline void portmux_setup(unsigned short per)
304{ 306{
305 u16 ident = P_IDENT(per); 307 u16 ident = P_IDENT(per);
@@ -377,7 +379,7 @@ static int portmux_group_check(unsigned short per)
377} 379}
378#endif 380#endif
379 381
380#ifndef CONFIG_BF54x 382#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
381/*********************************************************** 383/***********************************************************
382* 384*
383* FUNCTIONS: Blackfin General Purpose Ports Access Functions 385* FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -680,7 +682,7 @@ void bfin_gpio_pm_hibernate_restore(void)
680 682
681 683
682#endif 684#endif
683#else /* CONFIG_BF54x */ 685#else /* CONFIG_BF54x || CONFIG_BF60x */
684#ifdef CONFIG_PM 686#ifdef CONFIG_PM
685 687
686int bfin_pm_standby_ctrl(unsigned ctrl) 688int bfin_pm_standby_ctrl(unsigned ctrl)
@@ -726,7 +728,7 @@ unsigned short get_gpio_dir(unsigned gpio)
726} 728}
727EXPORT_SYMBOL(get_gpio_dir); 729EXPORT_SYMBOL(get_gpio_dir);
728 730
729#endif /* CONFIG_BF54x */ 731#endif /* CONFIG_BF54x || CONFIG_BF60x */
730 732
731/*********************************************************** 733/***********************************************************
732* 734*
@@ -783,7 +785,7 @@ int peripheral_request(unsigned short per, const char *label)
783 * be requested and used by several drivers 785 * be requested and used by several drivers
784 */ 786 */
785 787
786#ifdef CONFIG_BF54x 788#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
787 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) { 789 if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
788#else 790#else
789 if (!(per & P_MAYSHARE)) { 791 if (!(per & P_MAYSHARE)) {
@@ -937,7 +939,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
937 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!" 939 printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
938 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio); 940 " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
939 } 941 }
940#ifndef CONFIG_BF54x 942#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
941 else { /* Reset POLAR setting when acquiring a gpio for the first time */ 943 else { /* Reset POLAR setting when acquiring a gpio for the first time */
942 set_gpio_polar(gpio, 0); 944 set_gpio_polar(gpio, 0);
943 } 945 }
@@ -1110,7 +1112,7 @@ void bfin_gpio_irq_free(unsigned gpio)
1110 1112
1111static inline void __bfin_gpio_direction_input(unsigned gpio) 1113static inline void __bfin_gpio_direction_input(unsigned gpio)
1112{ 1114{
1113#ifdef CONFIG_BF54x 1115#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1114 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio); 1116 gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
1115#else 1117#else
1116 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio); 1118 gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
@@ -1138,13 +1140,13 @@ EXPORT_SYMBOL(bfin_gpio_direction_input);
1138 1140
1139void bfin_gpio_irq_prepare(unsigned gpio) 1141void bfin_gpio_irq_prepare(unsigned gpio)
1140{ 1142{
1141#ifdef CONFIG_BF54x 1143#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1142 unsigned long flags; 1144 unsigned long flags;
1143#endif 1145#endif
1144 1146
1145 port_setup(gpio, GPIO_USAGE); 1147 port_setup(gpio, GPIO_USAGE);
1146 1148
1147#ifdef CONFIG_BF54x 1149#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1148 flags = hard_local_irq_save(); 1150 flags = hard_local_irq_save();
1149 __bfin_gpio_direction_input(gpio); 1151 __bfin_gpio_direction_input(gpio);
1150 hard_local_irq_restore(flags); 1152 hard_local_irq_restore(flags);
@@ -1173,7 +1175,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
1173 1175
1174 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); 1176 gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
1175 gpio_set_value(gpio, value); 1177 gpio_set_value(gpio, value);
1176#ifdef CONFIG_BF54x 1178#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1177 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio); 1179 gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
1178#else 1180#else
1179 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio); 1181 gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
@@ -1188,7 +1190,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_output);
1188 1190
1189int bfin_gpio_get_value(unsigned gpio) 1191int bfin_gpio_get_value(unsigned gpio)
1190{ 1192{
1191#ifdef CONFIG_BF54x 1193#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
1192 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio))); 1194 return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
1193#else 1195#else
1194 unsigned long flags; 1196 unsigned long flags;
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 886e00014d75..3e366dc2d6e1 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -139,7 +139,7 @@ void __init generate_cplb_tables_all(void)
139 dcplb_bounds[i_d].eaddr = BOOT_ROM_START; 139 dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
140 dcplb_bounds[i_d++].data = 0; 140 dcplb_bounds[i_d++].data = 0;
141 /* BootROM -- largest one should be less than 1 meg. */ 141 /* BootROM -- largest one should be less than 1 meg. */
142 dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); 142 dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
143 dcplb_bounds[i_d++].data = SDRAM_DGENERIC; 143 dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
144 if (L2_LENGTH) { 144 if (L2_LENGTH) {
145 /* Addressing hole up to L2 SRAM. */ 145 /* Addressing hole up to L2 SRAM. */
@@ -178,7 +178,7 @@ void __init generate_cplb_tables_all(void)
178 icplb_bounds[i_i].eaddr = BOOT_ROM_START; 178 icplb_bounds[i_i].eaddr = BOOT_ROM_START;
179 icplb_bounds[i_i++].data = 0; 179 icplb_bounds[i_i++].data = 0;
180 /* BootROM -- largest one should be less than 1 meg. */ 180 /* BootROM -- largest one should be less than 1 meg. */
181 icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024); 181 icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
182 icplb_bounds[i_i++].data = SDRAM_IGENERIC; 182 icplb_bounds[i_i++].data = SDRAM_IGENERIC;
183 183
184 if (L2_LENGTH) { 184 if (L2_LENGTH) {
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
index 5b88861d6183..e854f9066cbd 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
@@ -179,6 +179,12 @@ MGR_ATTR static int dcplb_miss(int cpu)
179 addr = addr1; 179 addr = addr1;
180 } 180 }
181 181
182#ifdef CONFIG_BF60x
183 if ((addr >= ASYNC_BANK0_BASE)
184 && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
185 d_data |= PAGE_SIZE_64MB;
186#endif
187
182 /* Pick entry to evict */ 188 /* Pick entry to evict */
183 idx = evict_one_dcplb(cpu); 189 idx = evict_one_dcplb(cpu);
184 190
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
index 92f664826281..01232a13470d 100644
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -105,6 +105,7 @@ DEFINE_SYSREG(seqstat, , );
105DEFINE_SYSREG(syscfg, , CSYNC()); 105DEFINE_SYSREG(syscfg, , CSYNC());
106#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr) 106#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
107 107
108#ifndef CONFIG_BF60x
108/* 109/*
109 * CAN 110 * CAN
110 */ 111 */
@@ -223,8 +224,10 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm
223 __DMA(CURR_DESC_PTR, curr_desc_ptr); 224 __DMA(CURR_DESC_PTR, curr_desc_ptr);
224 __DMA(CURR_ADDR, curr_addr); 225 __DMA(CURR_ADDR, curr_addr);
225 __DMA(IRQ_STATUS, irq_status); 226 __DMA(IRQ_STATUS, irq_status);
227#ifndef CONFIG_BF60x
226 if (strcmp(pfx, "IMDMA") != 0) 228 if (strcmp(pfx, "IMDMA") != 0)
227 __DMA(PERIPHERAL_MAP, peripheral_map); 229 __DMA(PERIPHERAL_MAP, peripheral_map);
230#endif
228 __DMA(CURR_X_COUNT, curr_x_count); 231 __DMA(CURR_X_COUNT, curr_x_count);
229 __DMA(CURR_Y_COUNT, curr_y_count); 232 __DMA(CURR_Y_COUNT, curr_y_count);
230} 233}
@@ -568,7 +571,7 @@ bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
568#endif 571#endif
569} 572}
570#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num) 573#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
571 574#endif /* CONFIG_BF60x */
572/* 575/*
573 * The actual debugfs generation 576 * The actual debugfs generation
574 */ 577 */
@@ -740,7 +743,7 @@ static int __init bfin_debug_mmrs_init(void)
740 D32(WPDACNT0); 743 D32(WPDACNT0);
741 D32(WPDACNT1); 744 D32(WPDACNT1);
742 D32(WPSTAT); 745 D32(WPSTAT);
743 746#ifndef CONFIG_BF60x
744 /* System MMRs */ 747 /* System MMRs */
745#ifdef ATAPI_CONTROL 748#ifdef ATAPI_CONTROL
746 parent = debugfs_create_dir("atapi", top); 749 parent = debugfs_create_dir("atapi", top);
@@ -1873,7 +1876,7 @@ static int __init bfin_debug_mmrs_init(void)
1873 1876
1874 } 1877 }
1875#endif /* BF54x */ 1878#endif /* BF54x */
1876 1879#endif /* CONFIG_BF60x */
1877 debug_mmrs_dentry = top; 1880 debug_mmrs_dentry = top;
1878 1881
1879 return 0; 1882 return 0;
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S
index 686478f5f66b..f33792cc1a0d 100644
--- a/arch/blackfin/kernel/entry.S
+++ b/arch/blackfin/kernel/entry.S
@@ -64,16 +64,6 @@ ENTRY(_ret_from_fork)
64 jump (p0); 64 jump (p0);
65ENDPROC(_ret_from_fork) 65ENDPROC(_ret_from_fork)
66 66
67ENTRY(_sys_fork)
68 r0 = -EINVAL;
69#if (ANOMALY_05000371)
70 nop;
71 nop;
72 nop;
73#endif
74 rts;
75ENDPROC(_sys_fork)
76
77ENTRY(_sys_vfork) 67ENTRY(_sys_vfork)
78 r0 = sp; 68 r0 = sp;
79 r0 += 24; 69 r0 += 24;
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
index 06459f4bf43a..d776773d3869 100644
--- a/arch/blackfin/kernel/gptimers.c
+++ b/arch/blackfin/kernel/gptimers.c
@@ -23,7 +23,11 @@
23 printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__); 23 printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__);
24#endif 24#endif
25 25
26#define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1) 26#ifndef CONFIG_BF60x
27# define BFIN_TIMER_NUM_GROUP (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
28#else
29# define BFIN_TIMER_NUM_GROUP 1
30#endif
27 31
28static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] = 32static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
29{ 33{
@@ -158,6 +162,74 @@ uint32_t get_gptimer_count(unsigned int timer_id)
158} 162}
159EXPORT_SYMBOL(get_gptimer_count); 163EXPORT_SYMBOL(get_gptimer_count);
160 164
165#ifdef CONFIG_BF60x
166void set_gptimer_delay(unsigned int timer_id, uint32_t delay)
167{
168 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
169 bfin_write(&timer_regs[timer_id]->delay, delay);
170 SSYNC();
171}
172EXPORT_SYMBOL(set_gptimer_delay);
173
174uint32_t get_gptimer_delay(unsigned int timer_id)
175{
176 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
177 return bfin_read(&timer_regs[timer_id]->delay);
178}
179EXPORT_SYMBOL(get_gptimer_delay);
180#endif
181
182#ifdef CONFIG_BF60x
183int get_gptimer_intr(unsigned int timer_id)
184{
185 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
186 return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]);
187}
188EXPORT_SYMBOL(get_gptimer_intr);
189
190void clear_gptimer_intr(unsigned int timer_id)
191{
192 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
193 bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]);
194}
195EXPORT_SYMBOL(clear_gptimer_intr);
196
197int get_gptimer_over(unsigned int timer_id)
198{
199 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
200 return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]);
201}
202EXPORT_SYMBOL(get_gptimer_over);
203
204void clear_gptimer_over(unsigned int timer_id)
205{
206 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
207 bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]);
208}
209EXPORT_SYMBOL(clear_gptimer_over);
210
211int get_gptimer_run(unsigned int timer_id)
212{
213 tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
214 return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]);
215}
216EXPORT_SYMBOL(get_gptimer_run);
217
218uint32_t get_gptimer_status(unsigned int group)
219{
220 tassert(group < BFIN_TIMER_NUM_GROUP);
221 return bfin_read(&group_regs[group]->data_ilat);
222}
223EXPORT_SYMBOL(get_gptimer_status);
224
225void set_gptimer_status(unsigned int group, uint32_t value)
226{
227 tassert(group < BFIN_TIMER_NUM_GROUP);
228 bfin_write(&group_regs[group]->data_ilat, value);
229 SSYNC();
230}
231EXPORT_SYMBOL(set_gptimer_status);
232#else
161uint32_t get_gptimer_status(unsigned int group) 233uint32_t get_gptimer_status(unsigned int group)
162{ 234{
163 tassert(group < BFIN_TIMER_NUM_GROUP); 235 tassert(group < BFIN_TIMER_NUM_GROUP);
@@ -212,6 +284,7 @@ int get_gptimer_run(unsigned int timer_id)
212 return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]); 284 return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
213} 285}
214EXPORT_SYMBOL(get_gptimer_run); 286EXPORT_SYMBOL(get_gptimer_run);
287#endif
215 288
216void set_gptimer_config(unsigned int timer_id, uint16_t config) 289void set_gptimer_config(unsigned int timer_id, uint16_t config)
217{ 290{
@@ -231,6 +304,12 @@ EXPORT_SYMBOL(get_gptimer_config);
231void enable_gptimers(uint16_t mask) 304void enable_gptimers(uint16_t mask)
232{ 305{
233 int i; 306 int i;
307#ifdef CONFIG_BF60x
308 uint16_t imask;
309 imask = bfin_read16(TIMER_DATA_IMSK);
310 imask &= ~mask;
311 bfin_write16(TIMER_DATA_IMSK, imask);
312#endif
234 tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0); 313 tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
235 for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) { 314 for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
236 bfin_write(&group_regs[i]->enable, mask & 0xFF); 315 bfin_write(&group_regs[i]->enable, mask & 0xFF);
@@ -253,12 +332,16 @@ static void _disable_gptimers(uint16_t mask)
253 332
254void disable_gptimers(uint16_t mask) 333void disable_gptimers(uint16_t mask)
255{ 334{
335#ifndef CONFIG_BF60x
256 int i; 336 int i;
257 _disable_gptimers(mask); 337 _disable_gptimers(mask);
258 for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i) 338 for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
259 if (mask & (1 << i)) 339 if (mask & (1 << i))
260 bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]); 340 bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
261 SSYNC(); 341 SSYNC();
342#else
343 _disable_gptimers(mask);
344#endif
262} 345}
263EXPORT_SYMBOL(disable_gptimers); 346EXPORT_SYMBOL(disable_gptimers);
264 347
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index c0f4fe287eb6..2e3994b20169 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -95,7 +95,9 @@ void cpu_idle(void)
95 idle(); 95 idle();
96 rcu_idle_exit(); 96 rcu_idle_exit();
97 tick_nohz_idle_exit(); 97 tick_nohz_idle_exit();
98 schedule_preempt_disabled(); 98 preempt_enable_no_resched();
99 schedule();
100 preempt_disable();
99 } 101 }
100} 102}
101 103
@@ -329,12 +331,16 @@ int in_mem_const(unsigned long addr, unsigned long size,
329{ 331{
330 return in_mem_const_off(addr, size, 0, const_addr, const_size); 332 return in_mem_const_off(addr, size, 0, const_addr, const_size);
331} 333}
334#ifdef CONFIG_BF60x
335#define ASYNC_ENABLED(bnum, bctlnum) 1
336#else
332#define ASYNC_ENABLED(bnum, bctlnum) \ 337#define ASYNC_ENABLED(bnum, bctlnum) \
333({ \ 338({ \
334 (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \ 339 (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
335 bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \ 340 bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
336 1; \ 341 1; \
337}) 342})
343#endif
338/* 344/*
339 * We can't read EBIU banks that aren't enabled or we end up hanging 345 * We can't read EBIU banks that aren't enabled or we end up hanging
340 * on the access to the async space. Make sure we validate accesses 346 * on the access to the async space. Make sure we validate accesses
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index b0434f89e8de..5272e6eefd92 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -22,6 +22,7 @@
22__attribute__ ((__l1_text__, __noreturn__)) 22__attribute__ ((__l1_text__, __noreturn__))
23static void bfin_reset(void) 23static void bfin_reset(void)
24{ 24{
25#ifndef CONFIG_BF60x
25 if (!ANOMALY_05000353 && !ANOMALY_05000386) 26 if (!ANOMALY_05000353 && !ANOMALY_05000386)
26 bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20)); 27 bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
27 28
@@ -57,7 +58,6 @@ static void bfin_reset(void)
57 if (__SILICON_REVISION__ < 1 && bfin_revid() < 1) 58 if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
58 bfin_read_SWRST(); 59 bfin_read_SWRST();
59#endif 60#endif
60
61 /* Wait for the SWRST write to complete. Cannot rely on SSYNC 61 /* Wait for the SWRST write to complete. Cannot rely on SSYNC
62 * though as the System state is all reset now. 62 * though as the System state is all reset now.
63 */ 63 */
@@ -72,6 +72,10 @@ static void bfin_reset(void)
72 while (1) 72 while (1)
73 /* Issue core reset */ 73 /* Issue core reset */
74 asm("raise 1"); 74 asm("raise 1");
75#else
76 while (1)
77 bfin_write_RCU0_CTL(0x1);
78#endif
75} 79}
76 80
77__attribute__((weak)) 81__attribute__((weak))
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 2ad747e909fb..ada8f0fc71e4 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -25,12 +25,16 @@
25#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
26#include <asm/blackfin.h> 26#include <asm/blackfin.h>
27#include <asm/cplbinit.h> 27#include <asm/cplbinit.h>
28#include <asm/clocks.h>
28#include <asm/div64.h> 29#include <asm/div64.h>
29#include <asm/cpu.h> 30#include <asm/cpu.h>
30#include <asm/fixed_code.h> 31#include <asm/fixed_code.h>
31#include <asm/early_printk.h> 32#include <asm/early_printk.h>
32#include <asm/irq_handler.h> 33#include <asm/irq_handler.h>
33#include <asm/pda.h> 34#include <asm/pda.h>
35#ifdef CONFIG_BF60x
36#include <mach/pm.h>
37#endif
34 38
35u16 _bfin_swrst; 39u16 _bfin_swrst;
36EXPORT_SYMBOL(_bfin_swrst); 40EXPORT_SYMBOL(_bfin_swrst);
@@ -550,7 +554,6 @@ static __init void memory_setup(void)
550{ 554{
551#ifdef CONFIG_MTD_UCLINUX 555#ifdef CONFIG_MTD_UCLINUX
552 unsigned long mtd_phys = 0; 556 unsigned long mtd_phys = 0;
553 unsigned long n;
554#endif 557#endif
555 unsigned long max_mem; 558 unsigned long max_mem;
556 559
@@ -594,9 +597,9 @@ static __init void memory_setup(void)
594 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8))); 597 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
595 598
596# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS) 599# if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
597 n = ext2_image_size((void *)(mtd_phys + 0x400)); 600 if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
598 if (n) 601 mtd_size =
599 mtd_size = PAGE_ALIGN(n * 1024); 602 PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
600# endif 603# endif
601 604
602# if defined(CONFIG_CRAMFS) 605# if defined(CONFIG_CRAMFS)
@@ -612,7 +615,8 @@ static __init void memory_setup(void)
612 615
613 /* ROM_FS is XIP, so if we found it, we need to limit memory */ 616 /* ROM_FS is XIP, so if we found it, we need to limit memory */
614 if (memory_end > max_mem) { 617 if (memory_end > max_mem) {
615 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); 618 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
619 (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
616 memory_end = max_mem; 620 memory_end = max_mem;
617 } 621 }
618 } 622 }
@@ -642,7 +646,8 @@ static __init void memory_setup(void)
642 * doesn't exist, or we don't need to - then dont. 646 * doesn't exist, or we don't need to - then dont.
643 */ 647 */
644 if (memory_end > max_mem) { 648 if (memory_end > max_mem) {
645 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20); 649 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
650 (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
646 memory_end = max_mem; 651 memory_end = max_mem;
647 } 652 }
648 653
@@ -661,8 +666,8 @@ static __init void memory_setup(void)
661 init_mm.end_data = (unsigned long)_edata; 666 init_mm.end_data = (unsigned long)_edata;
662 init_mm.brk = (unsigned long)0; 667 init_mm.brk = (unsigned long)0;
663 668
664 printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20); 669 printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
665 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20); 670 printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
666 671
667 printk(KERN_INFO "Memory map:\n" 672 printk(KERN_INFO "Memory map:\n"
668 " fixedcode = 0x%p-0x%p\n" 673 " fixedcode = 0x%p-0x%p\n"
@@ -705,7 +710,7 @@ void __init find_min_max_pfn(void)
705 int i; 710 int i;
706 711
707 max_pfn = 0; 712 max_pfn = 0;
708 min_low_pfn = memory_end; 713 min_low_pfn = PFN_DOWN(memory_end);
709 714
710 for (i = 0; i < bfin_memmap.nr_map; i++) { 715 for (i = 0; i < bfin_memmap.nr_map; i++) {
711 unsigned long start, end; 716 unsigned long start, end;
@@ -748,8 +753,7 @@ static __init void setup_bootmem_allocator(void)
748 /* pfn of the first usable page frame after kernel image*/ 753 /* pfn of the first usable page frame after kernel image*/
749 if (min_low_pfn < memory_start >> PAGE_SHIFT) 754 if (min_low_pfn < memory_start >> PAGE_SHIFT)
750 min_low_pfn = memory_start >> PAGE_SHIFT; 755 min_low_pfn = memory_start >> PAGE_SHIFT;
751 756 start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
752 start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
753 end_pfn = memory_end >> PAGE_SHIFT; 757 end_pfn = memory_end >> PAGE_SHIFT;
754 758
755 /* 759 /*
@@ -794,8 +798,8 @@ static __init void setup_bootmem_allocator(void)
794 } 798 }
795 799
796 /* reserve memory before memory_start, including bootmap */ 800 /* reserve memory before memory_start, including bootmap */
797 reserve_bootmem(PAGE_OFFSET, 801 reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
798 memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET, 802 memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
799 BOOTMEM_DEFAULT); 803 BOOTMEM_DEFAULT);
800} 804}
801 805
@@ -844,13 +848,40 @@ static inline int __init get_mem_size(void)
844 break; 848 break;
845 } 849 }
846 switch (ddrctl & 0x30000) { 850 switch (ddrctl & 0x30000) {
847 case DEVWD_4: ret *= 2; 851 case DEVWD_4:
848 case DEVWD_8: ret *= 2; 852 ret *= 2;
849 case DEVWD_16: break; 853 case DEVWD_8:
854 ret *= 2;
855 case DEVWD_16:
856 break;
850 } 857 }
851 if ((ddrctl & 0xc000) == 0x4000) 858 if ((ddrctl & 0xc000) == 0x4000)
852 ret *= 2; 859 ret *= 2;
853 return ret; 860 return ret;
861#elif defined(CONFIG_BF60x)
862 u32 ddrctl = bfin_read_DMC0_CFG();
863 int ret;
864 switch (ddrctl & 0xf00) {
865 case DEVSZ_64:
866 ret = 64 / 8;
867 break;
868 case DEVSZ_128:
869 ret = 128 / 8;
870 break;
871 case DEVSZ_256:
872 ret = 256 / 8;
873 break;
874 case DEVSZ_512:
875 ret = 512 / 8;
876 break;
877 case DEVSZ_1G:
878 ret = 1024 / 8;
879 break;
880 case DEVSZ_2G:
881 ret = 2048 / 8;
882 break;
883 }
884 return ret;
854#endif 885#endif
855 BUG(); 886 BUG();
856} 887}
@@ -860,6 +891,22 @@ void __init native_machine_early_platform_add_devices(void)
860{ 891{
861} 892}
862 893
894#ifdef CONFIG_BF60x
895static inline u_long bfin_get_clk(char *name)
896{
897 struct clk *clk;
898 u_long clk_rate;
899
900 clk = clk_get(NULL, name);
901 if (IS_ERR(clk))
902 return 0;
903
904 clk_rate = clk_get_rate(clk);
905 clk_put(clk);
906 return clk_rate;
907}
908#endif
909
863void __init setup_arch(char **cmdline_p) 910void __init setup_arch(char **cmdline_p)
864{ 911{
865 u32 mmr; 912 u32 mmr;
@@ -870,6 +917,7 @@ void __init setup_arch(char **cmdline_p)
870 enable_shadow_console(); 917 enable_shadow_console();
871 918
872 /* Check to make sure we are running on the right processor */ 919 /* Check to make sure we are running on the right processor */
920 mmr = bfin_cpuid();
873 if (unlikely(CPUID != bfin_cpuid())) 921 if (unlikely(CPUID != bfin_cpuid()))
874 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n", 922 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
875 CPU, bfin_cpuid(), bfin_revid()); 923 CPU, bfin_cpuid(), bfin_revid());
@@ -890,6 +938,10 @@ void __init setup_arch(char **cmdline_p)
890 938
891 memset(&bfin_memmap, 0, sizeof(bfin_memmap)); 939 memset(&bfin_memmap, 0, sizeof(bfin_memmap));
892 940
941#ifdef CONFIG_BF60x
942 /* Should init clock device before parse command early */
943 clk_init();
944#endif
893 /* If the user does not specify things on the command line, use 945 /* If the user does not specify things on the command line, use
894 * what the bootloader set things up as 946 * what the bootloader set things up as
895 */ 947 */
@@ -904,6 +956,7 @@ void __init setup_arch(char **cmdline_p)
904 956
905 memory_setup(); 957 memory_setup();
906 958
959#ifndef CONFIG_BF60x
907 /* Initialize Async memory banks */ 960 /* Initialize Async memory banks */
908 bfin_write_EBIU_AMBCTL0(AMBCTL0VAL); 961 bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
909 bfin_write_EBIU_AMBCTL1(AMBCTL1VAL); 962 bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
@@ -913,6 +966,7 @@ void __init setup_arch(char **cmdline_p)
913 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL); 966 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
914 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL); 967 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
915#endif 968#endif
969#endif
916#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL 970#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
917 bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15); 971 bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
918 bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15); 972 bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
@@ -938,7 +992,7 @@ void __init setup_arch(char **cmdline_p)
938 printk(KERN_INFO "Hardware Trace %s and %sabled\n", 992 printk(KERN_INFO "Hardware Trace %s and %sabled\n",
939 (mmr & 0x1) ? "active" : "off", 993 (mmr & 0x1) ? "active" : "off",
940 (mmr & 0x2) ? "en" : "dis"); 994 (mmr & 0x2) ? "en" : "dis");
941 995#ifndef CONFIG_BF60x
942 mmr = bfin_read_SYSCR(); 996 mmr = bfin_read_SYSCR();
943 printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF); 997 printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
944 998
@@ -980,7 +1034,7 @@ void __init setup_arch(char **cmdline_p)
980 printk(KERN_INFO "Recovering from Watchdog event\n"); 1034 printk(KERN_INFO "Recovering from Watchdog event\n");
981 else if (_bfin_swrst & RESET_SOFTWARE) 1035 else if (_bfin_swrst & RESET_SOFTWARE)
982 printk(KERN_NOTICE "Reset caused by Software reset\n"); 1036 printk(KERN_NOTICE "Reset caused by Software reset\n");
983 1037#endif
984 printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n"); 1038 printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
985 if (bfin_compiled_revid() == 0xffff) 1039 if (bfin_compiled_revid() == 0xffff)
986 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid()); 1040 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
@@ -1008,8 +1062,13 @@ void __init setup_arch(char **cmdline_p)
1008 1062
1009 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); 1063 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
1010 1064
1065#ifdef CONFIG_BF60x
1066 printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
1067 cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
1068#else
1011 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", 1069 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
1012 cclk / 1000000, sclk / 1000000); 1070 cclk / 1000000, sclk / 1000000);
1071#endif
1013 1072
1014 setup_bootmem_allocator(); 1073 setup_bootmem_allocator();
1015 1074
@@ -1060,10 +1119,12 @@ subsys_initcall(topology_init);
1060 1119
1061/* Get the input clock frequency */ 1120/* Get the input clock frequency */
1062static u_long cached_clkin_hz = CONFIG_CLKIN_HZ; 1121static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
1122#ifndef CONFIG_BF60x
1063static u_long get_clkin_hz(void) 1123static u_long get_clkin_hz(void)
1064{ 1124{
1065 return cached_clkin_hz; 1125 return cached_clkin_hz;
1066} 1126}
1127#endif
1067static int __init early_init_clkin_hz(char *buf) 1128static int __init early_init_clkin_hz(char *buf)
1068{ 1129{
1069 cached_clkin_hz = simple_strtoul(buf, NULL, 0); 1130 cached_clkin_hz = simple_strtoul(buf, NULL, 0);
@@ -1075,6 +1136,7 @@ static int __init early_init_clkin_hz(char *buf)
1075} 1136}
1076early_param("clkin_hz=", early_init_clkin_hz); 1137early_param("clkin_hz=", early_init_clkin_hz);
1077 1138
1139#ifndef CONFIG_BF60x
1078/* Get the voltage input multiplier */ 1140/* Get the voltage input multiplier */
1079static u_long get_vco(void) 1141static u_long get_vco(void)
1080{ 1142{
@@ -1097,10 +1159,14 @@ static u_long get_vco(void)
1097 cached_vco *= msel; 1159 cached_vco *= msel;
1098 return cached_vco; 1160 return cached_vco;
1099} 1161}
1162#endif
1100 1163
1101/* Get the Core clock */ 1164/* Get the Core clock */
1102u_long get_cclk(void) 1165u_long get_cclk(void)
1103{ 1166{
1167#ifdef CONFIG_BF60x
1168 return bfin_get_clk("CCLK");
1169#else
1104 static u_long cached_cclk_pll_div, cached_cclk; 1170 static u_long cached_cclk_pll_div, cached_cclk;
1105 u_long csel, ssel; 1171 u_long csel, ssel;
1106 1172
@@ -1120,12 +1186,39 @@ u_long get_cclk(void)
1120 else 1186 else
1121 cached_cclk = get_vco() >> csel; 1187 cached_cclk = get_vco() >> csel;
1122 return cached_cclk; 1188 return cached_cclk;
1189#endif
1123} 1190}
1124EXPORT_SYMBOL(get_cclk); 1191EXPORT_SYMBOL(get_cclk);
1125 1192
1126/* Get the System clock */ 1193#ifdef CONFIG_BF60x
1194/* Get the bf60x clock of SCLK0 domain */
1195u_long get_sclk0(void)
1196{
1197 return bfin_get_clk("SCLK0");
1198}
1199EXPORT_SYMBOL(get_sclk0);
1200
1201/* Get the bf60x clock of SCLK1 domain */
1202u_long get_sclk1(void)
1203{
1204 return bfin_get_clk("SCLK1");
1205}
1206EXPORT_SYMBOL(get_sclk1);
1207
1208/* Get the bf60x DRAM clock */
1209u_long get_dclk(void)
1210{
1211 return bfin_get_clk("DCLK");
1212}
1213EXPORT_SYMBOL(get_dclk);
1214#endif
1215
1216/* Get the default system clock */
1127u_long get_sclk(void) 1217u_long get_sclk(void)
1128{ 1218{
1219#ifdef CONFIG_BF60x
1220 return get_sclk0();
1221#else
1129 static u_long cached_sclk; 1222 static u_long cached_sclk;
1130 u_long ssel; 1223 u_long ssel;
1131 1224
@@ -1146,6 +1239,7 @@ u_long get_sclk(void)
1146 1239
1147 cached_sclk = get_vco() / ssel; 1240 cached_sclk = get_vco() / ssel;
1148 return cached_sclk; 1241 return cached_sclk;
1242#endif
1149} 1243}
1150EXPORT_SYMBOL(get_sclk); 1244EXPORT_SYMBOL(get_sclk);
1151 1245
diff --git a/arch/blackfin/kernel/shadow_console.c b/arch/blackfin/kernel/shadow_console.c
index 557e9fef406a..aeb8343eeb03 100644
--- a/arch/blackfin/kernel/shadow_console.c
+++ b/arch/blackfin/kernel/shadow_console.c
@@ -15,9 +15,9 @@
15#include <asm/irq_handler.h> 15#include <asm/irq_handler.h>
16#include <asm/early_printk.h> 16#include <asm/early_printk.h>
17 17
18#define SHADOW_CONSOLE_START (0x500) 18#define SHADOW_CONSOLE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
19#define SHADOW_CONSOLE_END (0x1000) 19#define SHADOW_CONSOLE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
20#define SHADOW_CONSOLE_MAGIC_LOC (0x4F0) 20#define SHADOW_CONSOLE_MAGIC_LOC (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
21#define SHADOW_CONSOLE_MAGIC (0xDEADBEEF) 21#define SHADOW_CONSOLE_MAGIC (0xDEADBEEF)
22 22
23static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START; 23static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
index d98f2d69b0c4..f608f02f29a3 100644
--- a/arch/blackfin/kernel/time-ts.c
+++ b/arch/blackfin/kernel/time-ts.c
@@ -66,8 +66,14 @@ void __init setup_gptimer0(void)
66{ 66{
67 disable_gptimers(TIMER0bit); 67 disable_gptimers(TIMER0bit);
68 68
69#ifdef CONFIG_BF60x
70 bfin_write16(TIMER_DATA_IMSK, 0);
71 set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
72 | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
73#else
69 set_gptimer_config(TIMER0_id, \ 74 set_gptimer_config(TIMER0_id, \
70 TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM); 75 TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
76#endif
71 set_gptimer_period(TIMER0_id, -1); 77 set_gptimer_period(TIMER0_id, -1);
72 set_gptimer_pwidth(TIMER0_id, -2); 78 set_gptimer_pwidth(TIMER0_id, -2);
73 SSYNC(); 79 SSYNC();
@@ -135,9 +141,15 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
135{ 141{
136 switch (mode) { 142 switch (mode) {
137 case CLOCK_EVT_MODE_PERIODIC: { 143 case CLOCK_EVT_MODE_PERIODIC: {
144#ifndef CONFIG_BF60x
138 set_gptimer_config(TIMER0_id, \ 145 set_gptimer_config(TIMER0_id, \
139 TIMER_OUT_DIS | TIMER_IRQ_ENA | \ 146 TIMER_OUT_DIS | TIMER_IRQ_ENA | \
140 TIMER_PERIOD_CNT | TIMER_MODE_PWM); 147 TIMER_PERIOD_CNT | TIMER_MODE_PWM);
148#else
149 set_gptimer_config(TIMER0_id, TIMER_OUT_DIS
150 | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
151#endif
152
141 set_gptimer_period(TIMER0_id, get_sclk() / HZ); 153 set_gptimer_period(TIMER0_id, get_sclk() / HZ);
142 set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1); 154 set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
143 enable_gptimers(TIMER0bit); 155 enable_gptimers(TIMER0bit);
@@ -145,8 +157,14 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
145 } 157 }
146 case CLOCK_EVT_MODE_ONESHOT: 158 case CLOCK_EVT_MODE_ONESHOT:
147 disable_gptimers(TIMER0bit); 159 disable_gptimers(TIMER0bit);
160#ifndef CONFIG_BF60x
148 set_gptimer_config(TIMER0_id, \ 161 set_gptimer_config(TIMER0_id, \
149 TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM); 162 TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
163#else
164 set_gptimer_config(TIMER0_id, TIMER_OUT_DIS | TIMER_MODE_PWM
165 | TIMER_PULSE_HI | TIMER_IRQ_WID_DLY);
166#endif
167
150 set_gptimer_period(TIMER0_id, 0); 168 set_gptimer_period(TIMER0_id, 0);
151 break; 169 break;
152 case CLOCK_EVT_MODE_UNUSED: 170 case CLOCK_EVT_MODE_UNUSED:
@@ -160,7 +178,7 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
160 178
161static void bfin_gptmr0_ack(void) 179static void bfin_gptmr0_ack(void)
162{ 180{
163 set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0); 181 clear_gptimer_intr(TIMER0_id);
164} 182}
165 183
166static void __init bfin_gptmr0_init(void) 184static void __init bfin_gptmr0_init(void)
@@ -197,7 +215,7 @@ static struct clock_event_device clockevent_gptmr0 = {
197 .rating = 300, 215 .rating = 300,
198 .irq = IRQ_TIMER0, 216 .irq = IRQ_TIMER0,
199 .shift = 32, 217 .shift = 32,
200 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 218 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
201 .set_next_event = bfin_gptmr0_set_next_event, 219 .set_next_event = bfin_gptmr0_set_next_event,
202 .set_mode = bfin_gptmr0_set_mode, 220 .set_mode = bfin_gptmr0_set_mode,
203}; 221};
@@ -312,6 +330,11 @@ void bfin_coretmr_clockevent_init(void)
312#endif 330#endif
313 331
314 332
333#ifdef CONFIG_SMP
334 evt->broadcast = smp_timer_broadcast;
335#endif
336
337
315 evt->name = "bfin_core_timer"; 338 evt->name = "bfin_core_timer";
316 evt->rating = 350; 339 evt->rating = 350;
317 evt->irq = -1; 340 evt->irq = -1;
diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S
index f89c5a49c47b..ef2cd99efb89 100644
--- a/arch/blackfin/lib/divsi3.S
+++ b/arch/blackfin/lib/divsi3.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 * 5 *
6 * 16 / 32 bit signed division. 6 * 16 / 32 bit signed division.
7 * Special cases : 7 * Special cases :
diff --git a/arch/blackfin/lib/memchr.S b/arch/blackfin/lib/memchr.S
index 542e40f8775f..bcfc8a14c3f2 100644
--- a/arch/blackfin/lib/memchr.S
+++ b/arch/blackfin/lib/memchr.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
index ce5b9f1a8267..2e1c9477f2f7 100644
--- a/arch/blackfin/lib/memcmp.S
+++ b/arch/blackfin/lib/memcmp.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
index c31bf22aab19..53cb3698ab33 100644
--- a/arch/blackfin/lib/memcpy.S
+++ b/arch/blackfin/lib/memcpy.S
@@ -7,7 +7,7 @@
7 * 7 *
8 * Copyright 2004-2009 Analog Devices Inc. 8 * Copyright 2004-2009 Analog Devices Inc.
9 * 9 *
10 * Licensed under the ADI BSD license or the GPL-2 (or later) 10 * Licensed under the Clear BSD license or the GPL-2 (or later)
11 */ 11 */
12 12
13#include <linux/linkage.h> 13#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
index 4eca566237a4..e0b78208f1d6 100644
--- a/arch/blackfin/lib/memmove.S
+++ b/arch/blackfin/lib/memmove.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2009 Analog Devices Inc. 2 * Copyright 2005-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
index eab1bef3f5bf..cdcf9148ea20 100644
--- a/arch/blackfin/lib/memset.S
+++ b/arch/blackfin/lib/memset.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/modsi3.S b/arch/blackfin/lib/modsi3.S
index 8b0c7d4052af..f7026ce1fa0e 100644
--- a/arch/blackfin/lib/modsi3.S
+++ b/arch/blackfin/lib/modsi3.S
@@ -6,7 +6,7 @@
6 * 6 *
7 * Copyright 2004-2009 Analog Devices Inc. 7 * Copyright 2004-2009 Analog Devices Inc.
8 * 8 *
9 * Licensed under the ADI BSD license or the GPL-2 (or later) 9 * Licensed under the Clear BSD license or the GPL-2 (or later)
10 */ 10 */
11 11
12.global ___modsi3; 12.global ___modsi3;
diff --git a/arch/blackfin/lib/muldi3.S b/arch/blackfin/lib/muldi3.S
index 953a38a1d1d1..abf9b2a515b2 100644
--- a/arch/blackfin/lib/muldi3.S
+++ b/arch/blackfin/lib/muldi3.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008 Analog Devices Inc. 2 * Copyright 2008 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7.align 2 7.align 2
diff --git a/arch/blackfin/lib/smulsi3_highpart.S b/arch/blackfin/lib/smulsi3_highpart.S
index 99ee8c5de38b..e50d6c4ac2a5 100644
--- a/arch/blackfin/lib/smulsi3_highpart.S
+++ b/arch/blackfin/lib/smulsi3_highpart.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007 Analog Devices Inc. 2 * Copyright 2007 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7.align 2 7.align 2
diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S
index d7c1d158973b..9c8b9863713e 100644
--- a/arch/blackfin/lib/strcmp.S
+++ b/arch/blackfin/lib/strcmp.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2010 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S
index a6a0c6363806..9495aa77cc40 100644
--- a/arch/blackfin/lib/strcpy.S
+++ b/arch/blackfin/lib/strcpy.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2010 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S
index 6da37c34a847..3bfaedce893e 100644
--- a/arch/blackfin/lib/strncmp.S
+++ b/arch/blackfin/lib/strncmp.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2010 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S
index 2c07dddac995..92fd1823bbee 100644
--- a/arch/blackfin/lib/strncpy.S
+++ b/arch/blackfin/lib/strncpy.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2010 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S
index 97e904315ec6..748a6a2e8c17 100644
--- a/arch/blackfin/lib/udivsi3.S
+++ b/arch/blackfin/lib/udivsi3.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#include <linux/linkage.h> 7#include <linux/linkage.h>
diff --git a/arch/blackfin/lib/umodsi3.S b/arch/blackfin/lib/umodsi3.S
index 168eba7c64c8..3794c00d859d 100644
--- a/arch/blackfin/lib/umodsi3.S
+++ b/arch/blackfin/lib/umodsi3.S
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright 2004-2009 Analog Devices Inc. 4 * Copyright 2004-2009 Analog Devices Inc.
5 * 5 *
6 * Licensed under the ADI BSD license or the GPL-2 (or later) 6 * Licensed under the Clear BSD license or the GPL-2 (or later)
7 */ 7 */
8 8
9#ifdef CONFIG_ARITHMETIC_OPS_L1 9#ifdef CONFIG_ARITHMETIC_OPS_L1
diff --git a/arch/blackfin/lib/umulsi3_highpart.S b/arch/blackfin/lib/umulsi3_highpart.S
index 051824a6ed00..0dcace96e4e7 100644
--- a/arch/blackfin/lib/umulsi3_highpart.S
+++ b/arch/blackfin/lib/umulsi3_highpart.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007 Analog Devices Inc. 2 * Copyright 2007 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7.align 2 7.align 2
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index a17395727efa..f8047ca3b339 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -529,6 +529,8 @@ static struct platform_device bfin_i2s = {
529#endif 529#endif
530 530
531#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 531#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
532static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
533
532static struct resource bfin_twi0_resource[] = { 534static struct resource bfin_twi0_resource[] = {
533 [0] = { 535 [0] = {
534 .start = TWI0_REGBASE, 536 .start = TWI0_REGBASE,
@@ -547,6 +549,9 @@ static struct platform_device i2c_bfin_twi_device = {
547 .id = 0, 549 .id = 0,
548 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 550 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
549 .resource = bfin_twi0_resource, 551 .resource = bfin_twi0_resource,
552 .dev = {
553 .platform_data = &bfin_twi0_pins,
554 },
550}; 555};
551#endif 556#endif
552 557
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index 6eebee4e4217..0bedc737566b 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -455,6 +455,8 @@ static struct platform_device bfin_sir1_device = {
455#endif 455#endif
456 456
457#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 457#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
458static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
459
458static struct resource bfin_twi0_resource[] = { 460static struct resource bfin_twi0_resource[] = {
459 [0] = { 461 [0] = {
460 .start = TWI0_REGBASE, 462 .start = TWI0_REGBASE,
@@ -473,6 +475,9 @@ static struct platform_device i2c_bfin_twi_device = {
473 .id = 0, 475 .id = 0,
474 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 476 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
475 .resource = bfin_twi0_resource, 477 .resource = bfin_twi0_resource,
478 .dev = {
479 .platform_data = &bfin_twi0_pins,
480 },
476}; 481};
477#endif 482#endif
478 483
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 56383f7cbc07..845e6bc8d633 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -6,8 +6,7 @@
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2011 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the Clear BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 10 */
12 11
13/* This file should be up to date with: 12/* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
index bb79627f0929..1c03ad4bcb72 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2010 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF512_H 7#ifndef _CDEF_BF512_H
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
index dc988668203e..861221d1dcc9 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2010 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF514_H 7#ifndef _CDEF_BF514_H
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
index 142e45cbc253..cc9bf0d378c3 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2010 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF516_H 7#ifndef _CDEF_BF516_H
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
index e638197bf8b1..96a82fd62ef1 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2010 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF518_H 7#ifndef _CDEF_BF518_H
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index 729704078cd7..e6a017faad01 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2010 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF512_H 7#ifndef _DEF_BF512_H
@@ -1083,77 +1083,6 @@
1083#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 1083#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1084 1084
1085 1085
1086/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1087/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1088#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1089#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1090
1091/* TWI_PRESCALE Masks */
1092#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1093#define TWI_ENA 0x0080 /* TWI Enable */
1094#define SCCB 0x0200 /* SCCB Compatibility Enable */
1095
1096/* TWI_SLAVE_CTL Masks */
1097#define SEN 0x0001 /* Slave Enable */
1098#define SADD_LEN 0x0002 /* Slave Address Length */
1099#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1100#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1101#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1102
1103/* TWI_SLAVE_STAT Masks */
1104#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1105#define GCALL 0x0002 /* General Call Indicator */
1106
1107/* TWI_MASTER_CTL Masks */
1108#define MEN 0x0001 /* Master Mode Enable */
1109#define MADD_LEN 0x0002 /* Master Address Length */
1110#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1111#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1112#define STOP 0x0010 /* Issue Stop Condition */
1113#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1114#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1115#define SDAOVR 0x4000 /* Serial Data Override */
1116#define SCLOVR 0x8000 /* Serial Clock Override */
1117
1118/* TWI_MASTER_STAT Masks */
1119#define MPROG 0x0001 /* Master Transfer In Progress */
1120#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1121#define ANAK 0x0004 /* Address Not Acknowledged */
1122#define DNAK 0x0008 /* Data Not Acknowledged */
1123#define BUFRDERR 0x0010 /* Buffer Read Error */
1124#define BUFWRERR 0x0020 /* Buffer Write Error */
1125#define SDASEN 0x0040 /* Serial Data Sense */
1126#define SCLSEN 0x0080 /* Serial Clock Sense */
1127#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1128
1129/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1130#define SINIT 0x0001 /* Slave Transfer Initiated */
1131#define SCOMP 0x0002 /* Slave Transfer Complete */
1132#define SERR 0x0004 /* Slave Transfer Error */
1133#define SOVF 0x0008 /* Slave Overflow */
1134#define MCOMP 0x0010 /* Master Transfer Complete */
1135#define MERR 0x0020 /* Master Transfer Error */
1136#define XMTSERV 0x0040 /* Transmit FIFO Service */
1137#define RCVSERV 0x0080 /* Receive FIFO Service */
1138
1139/* TWI_FIFO_CTRL Masks */
1140#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1141#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1142#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1143#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1144
1145/* TWI_FIFO_STAT Masks */
1146#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1147#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1148#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1149#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1150
1151#define RCVSTAT 0x000C /* Receive FIFO Status */
1152#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1153#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1154#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1155
1156
1157/* ******************* PIN CONTROL REGISTER MASKS ************************/ 1086/* ******************* PIN CONTROL REGISTER MASKS ************************/
1158/* PORT_MUX Masks */ 1087/* PORT_MUX Masks */
1159#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ 1088#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
index cfab428e577c..97feaa629ed7 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF514_H 7#ifndef _DEF_BF514_H
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
index 22a3aa0d2629..7c79cb6a03b1 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF516_H 7#ifndef _DEF_BF516_H
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
index cb18270e55c2..12042ff13601 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF518_H 7#ifndef _DEF_BF518_H
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index fad7fea1b0bf..d58f50e5aa4b 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -569,6 +569,8 @@ static const struct ad7160_platform_data bfin_ad7160_ts_info = {
569#endif 569#endif
570 570
571#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 571#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
572static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
573
572static struct resource bfin_twi0_resource[] = { 574static struct resource bfin_twi0_resource[] = {
573 [0] = { 575 [0] = {
574 .start = TWI0_REGBASE, 576 .start = TWI0_REGBASE,
@@ -587,6 +589,9 @@ static struct platform_device i2c_bfin_twi_device = {
587 .id = 0, 589 .id = 0,
588 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 590 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
589 .resource = bfin_twi0_resource, 591 .resource = bfin_twi0_resource,
592 .dev = {
593 .platform_data = &bfin_twi0_pins,
594 },
590}; 595};
591#endif 596#endif
592 597
@@ -681,6 +686,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = {
681 .rotary_button_key = KEY_ENTER, 686 .rotary_button_key = KEY_ENTER,
682 .debounce = 10, /* 0..17 */ 687 .debounce = 10, /* 0..17 */
683 .mode = ROT_QUAD_ENC | ROT_DEBE, 688 .mode = ROT_QUAD_ENC | ROT_DEBE,
689 .pm_wakeup = 1,
684}; 690};
685 691
686static struct resource bfin_rotary_resources[] = { 692static struct resource bfin_rotary_resources[] = {
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 65b7fbd30e16..413d0132b66f 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -698,6 +698,8 @@ static struct platform_device bfin_sir1_device = {
698#endif 698#endif
699 699
700#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 700#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
701static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
702
701static struct resource bfin_twi0_resource[] = { 703static struct resource bfin_twi0_resource[] = {
702 [0] = { 704 [0] = {
703 .start = TWI0_REGBASE, 705 .start = TWI0_REGBASE,
@@ -716,6 +718,9 @@ static struct platform_device i2c_bfin_twi_device = {
716 .id = 0, 718 .id = 0,
717 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 719 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
718 .resource = bfin_twi0_resource, 720 .resource = bfin_twi0_resource,
721 .dev = {
722 .platform_data = &bfin_twi0_pins,
723 },
719}; 724};
720#endif 725#endif
721 726
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 17c6a24cc076..50bda79194e5 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -576,6 +576,8 @@ static struct platform_device bfin_sir1_device = {
576#endif 576#endif
577 577
578#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 578#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
579static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
580
579static struct resource bfin_twi0_resource[] = { 581static struct resource bfin_twi0_resource[] = {
580 [0] = { 582 [0] = {
581 .start = TWI0_REGBASE, 583 .start = TWI0_REGBASE,
@@ -594,6 +596,9 @@ static struct platform_device i2c_bfin_twi_device = {
594 .id = 0, 596 .id = 0,
595 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 597 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
596 .resource = bfin_twi0_resource, 598 .resource = bfin_twi0_resource,
599 .dev = {
600 .platform_data = &bfin_twi0_pins,
601 },
597}; 602};
598#endif 603#endif
599 604
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 2f9a2bd83ce4..af732eb3a687 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -869,6 +869,8 @@ static struct platform_device bfin_sir1_device = {
869#endif 869#endif
870 870
871#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 871#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
872static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
873
872static struct resource bfin_twi0_resource[] = { 874static struct resource bfin_twi0_resource[] = {
873 [0] = { 875 [0] = {
874 .start = TWI0_REGBASE, 876 .start = TWI0_REGBASE,
@@ -887,6 +889,9 @@ static struct platform_device i2c_bfin_twi_device = {
887 .id = 0, 889 .id = 0,
888 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 890 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
889 .resource = bfin_twi0_resource, 891 .resource = bfin_twi0_resource,
892 .dev = {
893 .platform_data = &bfin_twi0_pins,
894 },
890}; 895};
891#endif 896#endif
892 897
@@ -1105,6 +1110,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = {
1105 .rotary_button_key = KEY_ENTER, 1110 .rotary_button_key = KEY_ENTER,
1106 .debounce = 10, /* 0..17 */ 1111 .debounce = 10, /* 0..17 */
1107 .mode = ROT_QUAD_ENC | ROT_DEBE, 1112 .mode = ROT_QUAD_ENC | ROT_DEBE,
1113 .pm_wakeup = 1,
1108}; 1114};
1109 1115
1110static struct resource bfin_rotary_resources[] = { 1116static struct resource bfin_rotary_resources[] = {
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index d192c0ac941c..1509c5a8a3ff 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -656,6 +656,8 @@ static struct platform_device bfin_sir1_device = {
656#endif 656#endif
657 657
658#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 658#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
659static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
660
659static struct resource bfin_twi0_resource[] = { 661static struct resource bfin_twi0_resource[] = {
660 [0] = { 662 [0] = {
661 .start = TWI0_REGBASE, 663 .start = TWI0_REGBASE,
@@ -674,6 +676,9 @@ static struct platform_device i2c_bfin_twi_device = {
674 .id = 0, 676 .id = 0,
675 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 677 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
676 .resource = bfin_twi0_resource, 678 .resource = bfin_twi0_resource,
679 .dev = {
680 .platform_data = &bfin_twi0_pins,
681 },
677}; 682};
678#endif 683#endif
679 684
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 688470611e15..aa14110be4c4 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -6,8 +6,7 @@
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2011 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the Clear BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 10 */
12 11
13/* This file should be up to date with: 12/* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index 37d353a19722..e007017cf958 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007-2010 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF522_H 7#ifndef _DEF_BF522_H
@@ -1084,77 +1084,6 @@
1084#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 1084#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1085 1085
1086 1086
1087/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1088/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1089#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1090#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1091
1092/* TWI_PRESCALE Masks */
1093#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1094#define TWI_ENA 0x0080 /* TWI Enable */
1095#define SCCB 0x0200 /* SCCB Compatibility Enable */
1096
1097/* TWI_SLAVE_CTL Masks */
1098#define SEN 0x0001 /* Slave Enable */
1099#define SADD_LEN 0x0002 /* Slave Address Length */
1100#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1101#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1102#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1103
1104/* TWI_SLAVE_STAT Masks */
1105#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1106#define GCALL 0x0002 /* General Call Indicator */
1107
1108/* TWI_MASTER_CTL Masks */
1109#define MEN 0x0001 /* Master Mode Enable */
1110#define MADD_LEN 0x0002 /* Master Address Length */
1111#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1112#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1113#define STOP 0x0010 /* Issue Stop Condition */
1114#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1115#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1116#define SDAOVR 0x4000 /* Serial Data Override */
1117#define SCLOVR 0x8000 /* Serial Clock Override */
1118
1119/* TWI_MASTER_STAT Masks */
1120#define MPROG 0x0001 /* Master Transfer In Progress */
1121#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1122#define ANAK 0x0004 /* Address Not Acknowledged */
1123#define DNAK 0x0008 /* Data Not Acknowledged */
1124#define BUFRDERR 0x0010 /* Buffer Read Error */
1125#define BUFWRERR 0x0020 /* Buffer Write Error */
1126#define SDASEN 0x0040 /* Serial Data Sense */
1127#define SCLSEN 0x0080 /* Serial Clock Sense */
1128#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1129
1130/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1131#define SINIT 0x0001 /* Slave Transfer Initiated */
1132#define SCOMP 0x0002 /* Slave Transfer Complete */
1133#define SERR 0x0004 /* Slave Transfer Error */
1134#define SOVF 0x0008 /* Slave Overflow */
1135#define MCOMP 0x0010 /* Master Transfer Complete */
1136#define MERR 0x0020 /* Master Transfer Error */
1137#define XMTSERV 0x0040 /* Transmit FIFO Service */
1138#define RCVSERV 0x0080 /* Receive FIFO Service */
1139
1140/* TWI_FIFO_CTRL Masks */
1141#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1142#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1143#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1144#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1145
1146/* TWI_FIFO_STAT Masks */
1147#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1148#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1149#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1150#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1151
1152#define RCVSTAT 0x000C /* Receive FIFO Status */
1153#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1154#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1155#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1156
1157
1158/* Omit CAN masks from defBF534.h */ 1087/* Omit CAN masks from defBF534.h */
1159 1088
1160/* ******************* PIN CONTROL REGISTER MASKS ************************/ 1089/* ******************* PIN CONTROL REGISTER MASKS ************************/
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
index aab80bb1a683..71578d964d00 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007-2010 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF525_H 7#ifndef _DEF_BF525_H
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
index 05369a92fbc8..aeb84795b35e 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007-2010 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF527_H 7#ifndef _DEF_BF527_H
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 03f2b40912a3..3a8f73a669f0 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -6,8 +6,7 @@
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2011 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the Clear BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 10 */
12 11
13/* This file should be up to date with: 12/* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 2376d5393511..d438150b1025 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright 2005-2010 Analog Devices Inc. 4 * Copyright 2005-2010 Analog Devices Inc.
5 * 5 *
6 * Licensed under the ADI BSD license or the GPL-2 (or later) 6 * Licensed under the Clear BSD license or the GPL-2 (or later)
7 */ 7 */
8 8
9#ifndef _DEF_BF532_H 9#ifndef _DEF_BF532_H
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 27fd2c32ae9a..9408ab56d87f 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -486,6 +486,8 @@ static struct platform_device bfin_sir1_device = {
486#endif 486#endif
487 487
488#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 488#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
489static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
490
489static struct resource bfin_twi0_resource[] = { 491static struct resource bfin_twi0_resource[] = {
490 [0] = { 492 [0] = {
491 .start = TWI0_REGBASE, 493 .start = TWI0_REGBASE,
@@ -504,6 +506,9 @@ static struct platform_device i2c_bfin_twi_device = {
504 .id = 0, 506 .id = 0,
505 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 507 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
506 .resource = bfin_twi0_resource, 508 .resource = bfin_twi0_resource,
509 .dev = {
510 .platform_data = &bfin_twi0_pins,
511 },
507}; 512};
508#endif 513#endif
509 514
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index 3f3abad86ec3..0143d8bef909 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -451,6 +451,8 @@ static struct platform_device bfin_sir1_device = {
451#endif 451#endif
452 452
453#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 453#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
454static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
455
454static struct resource bfin_twi0_resource[] = { 456static struct resource bfin_twi0_resource[] = {
455 [0] = { 457 [0] = {
456 .start = TWI0_REGBASE, 458 .start = TWI0_REGBASE,
@@ -469,6 +471,9 @@ static struct platform_device i2c_bfin_twi_device = {
469 .id = 0, 471 .id = 0,
470 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 472 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
471 .resource = bfin_twi0_resource, 473 .resource = bfin_twi0_resource,
474 .dev = {
475 .platform_data = &bfin_twi0_pins,
476 },
472}; 477};
473#endif 478#endif
474 479
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
index 6f77bf708ec0..8bbf0a23fd49 100644
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -329,6 +329,8 @@ static struct platform_device bfin_uart1_device = {
329#endif 329#endif
330 330
331#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 331#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
332static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
333
332static struct resource bfin_twi0_resource[] = { 334static struct resource bfin_twi0_resource[] = {
333 [0] = { 335 [0] = {
334 .start = TWI0_REGBASE, 336 .start = TWI0_REGBASE,
@@ -347,6 +349,9 @@ static struct platform_device i2c_bfin_twi_device = {
347 .id = 0, 349 .id = 0,
348 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 350 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
349 .resource = bfin_twi0_resource, 351 .resource = bfin_twi0_resource,
352 .dev = {
353 .platform_data = &bfin_twi0_pins,
354 },
350}; 355};
351#endif 356#endif
352 357
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index d2d71282618f..a10f90e444bc 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -386,6 +386,8 @@ static struct platform_device bfin_sir1_device = {
386#endif 386#endif
387 387
388#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 388#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
389static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
390
389static struct resource bfin_twi0_resource[] = { 391static struct resource bfin_twi0_resource[] = {
390 [0] = { 392 [0] = {
391 .start = TWI0_REGBASE, 393 .start = TWI0_REGBASE,
@@ -404,6 +406,9 @@ static struct platform_device i2c_bfin_twi_device = {
404 .id = 0, 406 .id = 0,
405 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 407 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
406 .resource = bfin_twi0_resource, 408 .resource = bfin_twi0_resource,
409 .dev = {
410 .platform_data = &bfin_twi0_pins,
411 },
407}; 412};
408#endif 413#endif
409 414
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index f3562b0922af..c9d9473a5ab2 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -1790,6 +1790,8 @@ static struct platform_device bfin_sir1_device = {
1790#endif 1790#endif
1791 1791
1792#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 1792#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1793static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1794
1793static struct resource bfin_twi0_resource[] = { 1795static struct resource bfin_twi0_resource[] = {
1794 [0] = { 1796 [0] = {
1795 .start = TWI0_REGBASE, 1797 .start = TWI0_REGBASE,
@@ -1808,6 +1810,9 @@ static struct platform_device i2c_bfin_twi_device = {
1808 .id = 0, 1810 .id = 0,
1809 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 1811 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1810 .resource = bfin_twi0_resource, 1812 .resource = bfin_twi0_resource,
1813 .dev = {
1814 .platform_data = &bfin_twi0_pins,
1815 },
1811}; 1816};
1812#endif 1817#endif
1813 1818
@@ -2361,7 +2366,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
2361 }, 2366 },
2362#endif 2367#endif
2363}; 2368};
2364 2369#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) \
2370|| defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
2371unsigned short bfin_sport0_peripherals[] = {
2372 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
2373 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
2374};
2375#endif
2365#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 2376#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
2366#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 2377#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
2367static struct resource bfin_sport0_uart_resources[] = { 2378static struct resource bfin_sport0_uart_resources[] = {
@@ -2382,11 +2393,6 @@ static struct resource bfin_sport0_uart_resources[] = {
2382 }, 2393 },
2383}; 2394};
2384 2395
2385static unsigned short bfin_sport0_peripherals[] = {
2386 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
2387 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
2388};
2389
2390static struct platform_device bfin_sport0_uart_device = { 2396static struct platform_device bfin_sport0_uart_device = {
2391 .name = "bfin-sport-uart", 2397 .name = "bfin-sport-uart",
2392 .id = 0, 2398 .id = 0,
@@ -2432,7 +2438,49 @@ static struct platform_device bfin_sport1_uart_device = {
2432}; 2438};
2433#endif 2439#endif
2434#endif 2440#endif
2435 2441#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
2442static struct resource bfin_sport0_resources[] = {
2443 {
2444 .start = SPORT0_TCR1,
2445 .end = SPORT0_MRCS3+4,
2446 .flags = IORESOURCE_MEM,
2447 },
2448 {
2449 .start = IRQ_SPORT0_RX,
2450 .end = IRQ_SPORT0_RX+1,
2451 .flags = IORESOURCE_IRQ,
2452 },
2453 {
2454 .start = IRQ_SPORT0_TX,
2455 .end = IRQ_SPORT0_TX+1,
2456 .flags = IORESOURCE_IRQ,
2457 },
2458 {
2459 .start = IRQ_SPORT0_ERROR,
2460 .end = IRQ_SPORT0_ERROR,
2461 .flags = IORESOURCE_IRQ,
2462 },
2463 {
2464 .start = CH_SPORT0_TX,
2465 .end = CH_SPORT0_TX,
2466 .flags = IORESOURCE_DMA,
2467 },
2468 {
2469 .start = CH_SPORT0_RX,
2470 .end = CH_SPORT0_RX,
2471 .flags = IORESOURCE_DMA,
2472 },
2473};
2474static struct platform_device bfin_sport0_device = {
2475 .name = "bfin_sport_raw",
2476 .id = 0,
2477 .num_resources = ARRAY_SIZE(bfin_sport0_resources),
2478 .resource = bfin_sport0_resources,
2479 .dev = {
2480 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
2481 },
2482};
2483#endif
2436#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 2484#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
2437#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE 2485#define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
2438/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */ 2486/* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
@@ -2754,7 +2802,9 @@ static struct platform_device bf5xx_adau1701_device = {
2754static struct platform_device *stamp_devices[] __initdata = { 2802static struct platform_device *stamp_devices[] __initdata = {
2755 2803
2756 &bfin_dpmc, 2804 &bfin_dpmc,
2757 2805#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
2806 &bfin_sport0_device,
2807#endif
2758#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) 2808#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
2759 &bfin_pcmcia_cf_device, 2809 &bfin_pcmcia_cf_device,
2760#endif 2810#endif
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 3fb421823857..e285c3675286 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -453,6 +453,8 @@ static struct platform_device bfin_sir1_device = {
453#endif 453#endif
454 454
455#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 455#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
456static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
457
456static struct resource bfin_twi0_resource[] = { 458static struct resource bfin_twi0_resource[] = {
457 [0] = { 459 [0] = {
458 .start = TWI0_REGBASE, 460 .start = TWI0_REGBASE,
@@ -471,6 +473,9 @@ static struct platform_device i2c_bfin_twi_device = {
471 .id = 0, 473 .id = 0,
472 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 474 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
473 .resource = bfin_twi0_resource, 475 .resource = bfin_twi0_resource,
476 .dev = {
477 .platform_data = &bfin_twi0_pins,
478 },
474}; 479};
475#endif 480#endif
476 481
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 543cd3fb305e..df9212696397 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -6,8 +6,7 @@
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2011 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the Clear BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 10 */
12 11
13/* This file should be up to date with: 12/* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 4a031dde173f..ef6a98cdfd44 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2010 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF534_H 7#ifndef _DEF_BF534_H
@@ -1403,75 +1403,6 @@
1403#define ERR_DET 0x4000 /* Error Detected Indicator */ 1403#define ERR_DET 0x4000 /* Error Detected Indicator */
1404#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 1404#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1405 1405
1406/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1407/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1408#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1409#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1410
1411/* TWI_PRESCALE Masks */
1412#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1413#define TWI_ENA 0x0080 /* TWI Enable */
1414#define SCCB 0x0200 /* SCCB Compatibility Enable */
1415
1416/* TWI_SLAVE_CTL Masks */
1417#define SEN 0x0001 /* Slave Enable */
1418#define SADD_LEN 0x0002 /* Slave Address Length */
1419#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1420#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1421#define GEN 0x0010 /* General Call Address Matching Enabled */
1422
1423/* TWI_SLAVE_STAT Masks */
1424#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1425#define GCALL 0x0002 /* General Call Indicator */
1426
1427/* TWI_MASTER_CTL Masks */
1428#define MEN 0x0001 /* Master Mode Enable */
1429#define MADD_LEN 0x0002 /* Master Address Length */
1430#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1431#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1432#define STOP 0x0010 /* Issue Stop Condition */
1433#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1434#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1435#define SDAOVR 0x4000 /* Serial Data Override */
1436#define SCLOVR 0x8000 /* Serial Clock Override */
1437
1438/* TWI_MASTER_STAT Masks */
1439#define MPROG 0x0001 /* Master Transfer In Progress */
1440#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1441#define ANAK 0x0004 /* Address Not Acknowledged */
1442#define DNAK 0x0008 /* Data Not Acknowledged */
1443#define BUFRDERR 0x0010 /* Buffer Read Error */
1444#define BUFWRERR 0x0020 /* Buffer Write Error */
1445#define SDASEN 0x0040 /* Serial Data Sense */
1446#define SCLSEN 0x0080 /* Serial Clock Sense */
1447#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1448
1449/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1450#define SINIT 0x0001 /* Slave Transfer Initiated */
1451#define SCOMP 0x0002 /* Slave Transfer Complete */
1452#define SERR 0x0004 /* Slave Transfer Error */
1453#define SOVF 0x0008 /* Slave Overflow */
1454#define MCOMP 0x0010 /* Master Transfer Complete */
1455#define MERR 0x0020 /* Master Transfer Error */
1456#define XMTSERV 0x0040 /* Transmit FIFO Service */
1457#define RCVSERV 0x0080 /* Receive FIFO Service */
1458
1459/* TWI_FIFO_CTRL Masks */
1460#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1461#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1462#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1463#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1464
1465/* TWI_FIFO_STAT Masks */
1466#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1467#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1468#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1469#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1470
1471#define RCVSTAT 0x000C /* Receive FIFO Status */
1472#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1473#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1474#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1475 1406
1476/* ******************* PIN CONTROL REGISTER MASKS ************************/ 1407/* ******************* PIN CONTROL REGISTER MASKS ************************/
1477/* PORT_MUX Masks */ 1408/* PORT_MUX Masks */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
index 3d471d752684..e10332c9f660 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2010 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF537_H 7#ifndef _DEF_BF537_H
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 85038f54354d..a4fce0370c1d 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -718,6 +718,8 @@ static struct platform_device bf538_spi_master2 = {
718}; 718};
719 719
720#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 720#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
721static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
722
721static struct resource bfin_twi0_resource[] = { 723static struct resource bfin_twi0_resource[] = {
722 [0] = { 724 [0] = {
723 .start = TWI0_REGBASE, 725 .start = TWI0_REGBASE,
@@ -736,9 +738,13 @@ static struct platform_device i2c_bfin_twi0_device = {
736 .id = 0, 738 .id = 0,
737 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 739 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
738 .resource = bfin_twi0_resource, 740 .resource = bfin_twi0_resource,
741 .dev = {
742 .platform_data = &bfin_twi0_pins,
743 },
739}; 744};
740 745
741#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 746static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
747
742static struct resource bfin_twi1_resource[] = { 748static struct resource bfin_twi1_resource[] = {
743 [0] = { 749 [0] = {
744 .start = TWI1_REGBASE, 750 .start = TWI1_REGBASE,
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index b6ca99788710..318d922d11d4 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -6,8 +6,7 @@
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2011 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the Clear BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 10 */
12 11
13/* This file should be up to date with: 12/* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
index d27f81d6c4b1..876a77028001 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF538.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2010 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF538_H 7#ifndef _DEF_BF538_H
@@ -1746,80 +1746,4 @@
1746#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ 1746#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1747#define BGSTAT 0x00000020 /* Bus granted */ 1747#define BGSTAT 0x00000020 /* Bus granted */
1748 1748
1749
1750/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
1751/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1752#ifdef _MISRA_RULES
1753#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */
1754#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */
1755#else
1756#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1757#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1758#endif /* _MISRA_RULES */
1759
1760/* TWIx_PRESCALE Masks */
1761#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1762#define TWI_ENA 0x0080 /* TWI Enable */
1763#define SCCB 0x0200 /* SCCB Compatibility Enable */
1764
1765/* TWIx_SLAVE_CTRL Masks */
1766#define SEN 0x0001 /* Slave Enable */
1767#define SADD_LEN 0x0002 /* Slave Address Length */
1768#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1769#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1770#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1771
1772/* TWIx_SLAVE_STAT Masks */
1773#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1774#define GCALL 0x0002 /* General Call Indicator */
1775
1776/* TWIx_MASTER_CTRL Masks */
1777#define MEN 0x0001 /* Master Mode Enable */
1778#define MADD_LEN 0x0002 /* Master Address Length */
1779#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1780#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1781#define STOP 0x0010 /* Issue Stop Condition */
1782#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1783#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1784#define SDAOVR 0x4000 /* Serial Data Override */
1785#define SCLOVR 0x8000 /* Serial Clock Override */
1786
1787/* TWIx_MASTER_STAT Masks */
1788#define MPROG 0x0001 /* Master Transfer In Progress */
1789#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1790#define ANAK 0x0004 /* Address Not Acknowledged */
1791#define DNAK 0x0008 /* Data Not Acknowledged */
1792#define BUFRDERR 0x0010 /* Buffer Read Error */
1793#define BUFWRERR 0x0020 /* Buffer Write Error */
1794#define SDASEN 0x0040 /* Serial Data Sense */
1795#define SCLSEN 0x0080 /* Serial Clock Sense */
1796#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1797
1798/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
1799#define SINIT 0x0001 /* Slave Transfer Initiated */
1800#define SCOMP 0x0002 /* Slave Transfer Complete */
1801#define SERR 0x0004 /* Slave Transfer Error */
1802#define SOVF 0x0008 /* Slave Overflow */
1803#define MCOMP 0x0010 /* Master Transfer Complete */
1804#define MERR 0x0020 /* Master Transfer Error */
1805#define XMTSERV 0x0040 /* Transmit FIFO Service */
1806#define RCVSERV 0x0080 /* Receive FIFO Service */
1807
1808/* TWIx_FIFO_CTL Masks */
1809#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1810#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1811#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1812#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1813
1814/* TWIx_FIFO_STAT Masks */
1815#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1816#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1817#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1818#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1819
1820#define RCVSTAT 0x000C /* Receive FIFO Status */
1821#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1822#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1823#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1824
1825#endif 1749#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 8100bcd01a0d..199e871634b4 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2010 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF539_H 7#ifndef _DEF_BF539_H
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index 68af594db48e..e92543362f35 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -1007,6 +1007,8 @@ static struct platform_device bf54x_spi_master1 = {
1007#endif /* spi master and devices */ 1007#endif /* spi master and devices */
1008 1008
1009#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 1009#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1010static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1011
1010static struct resource bfin_twi0_resource[] = { 1012static struct resource bfin_twi0_resource[] = {
1011 [0] = { 1013 [0] = {
1012 .start = TWI0_REGBASE, 1014 .start = TWI0_REGBASE,
@@ -1025,9 +1027,14 @@ static struct platform_device i2c_bfin_twi0_device = {
1025 .id = 0, 1027 .id = 0,
1026 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 1028 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1027 .resource = bfin_twi0_resource, 1029 .resource = bfin_twi0_resource,
1030 .dev = {
1031 .platform_data = &bfin_twi0_pins,
1032 },
1028}; 1033};
1029 1034
1030#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 1035#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1036static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1037
1031static struct resource bfin_twi1_resource[] = { 1038static struct resource bfin_twi1_resource[] = {
1032 [0] = { 1039 [0] = {
1033 .start = TWI1_REGBASE, 1040 .start = TWI1_REGBASE,
@@ -1046,6 +1053,9 @@ static struct platform_device i2c_bfin_twi1_device = {
1046 .id = 1, 1053 .id = 1,
1047 .num_resources = ARRAY_SIZE(bfin_twi1_resource), 1054 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1048 .resource = bfin_twi1_resource, 1055 .resource = bfin_twi1_resource,
1056 .dev = {
1057 .platform_data = &bfin_twi1_pins,
1058 },
1049}; 1059};
1050#endif 1060#endif
1051#endif 1061#endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 4cadaf8d0b56..3bd75bae750d 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -165,6 +165,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = {
165 .rotary_button_key = KEY_ENTER, 165 .rotary_button_key = KEY_ENTER,
166 .debounce = 10, /* 0..17 */ 166 .debounce = 10, /* 0..17 */
167 .mode = ROT_QUAD_ENC | ROT_DEBE, 167 .mode = ROT_QUAD_ENC | ROT_DEBE,
168 .pm_wakeup = 1,
168}; 169};
169 170
170static struct resource bfin_rotary_resources[] = { 171static struct resource bfin_rotary_resources[] = {
@@ -1251,6 +1252,8 @@ static struct platform_device bfin_capture_device = {
1251#endif 1252#endif
1252 1253
1253#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) 1254#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1255static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1256
1254static struct resource bfin_twi0_resource[] = { 1257static struct resource bfin_twi0_resource[] = {
1255 [0] = { 1258 [0] = {
1256 .start = TWI0_REGBASE, 1259 .start = TWI0_REGBASE,
@@ -1269,9 +1272,14 @@ static struct platform_device i2c_bfin_twi0_device = {
1269 .id = 0, 1272 .id = 0,
1270 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 1273 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1271 .resource = bfin_twi0_resource, 1274 .resource = bfin_twi0_resource,
1275 .dev = {
1276 .platform_data = &bfin_twi0_pins,
1277 },
1272}; 1278};
1273 1279
1274#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 1280#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1281static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1282
1275static struct resource bfin_twi1_resource[] = { 1283static struct resource bfin_twi1_resource[] = {
1276 [0] = { 1284 [0] = {
1277 .start = TWI1_REGBASE, 1285 .start = TWI1_REGBASE,
@@ -1290,6 +1298,9 @@ static struct platform_device i2c_bfin_twi1_device = {
1290 .id = 1, 1298 .id = 1,
1291 .num_resources = ARRAY_SIZE(bfin_twi1_resource), 1299 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1292 .resource = bfin_twi1_resource, 1300 .resource = bfin_twi1_resource,
1301 .dev = {
1302 .platform_data = &bfin_twi1_pins,
1303 },
1293}; 1304};
1294#endif 1305#endif
1295#endif 1306#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index ac96ee83b00e..5b711d85b90b 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -6,8 +6,7 @@
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2011 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the Clear BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 10 */
12 11
13/* This file should be up to date with: 12/* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
index 629bf216e2b5..51161575a163 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007-2010 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF542_H 7#ifndef _DEF_BF542_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index bcccab36629c..329b2c58228b 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007-2010 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF544_H 7#ifndef _DEF_BF544_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 1fa41ec03f31..e18de212ba1a 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2010 Analog Devices Inc. 2 * Copyright 2008-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF547_H 7#ifndef _DEF_BF547_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index 3c7f1b69349e..27f29481e283 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007-2010 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF548_H 7#ifndef _DEF_BF548_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index 9a45cb6b30da..ac569fc12972 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007-2010 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF549_H 7#ifndef _DEF_BF549_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 0867c2bedb43..8f6e1925779d 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2007-2010 Analog Devices Inc. 2 * Copyright 2007-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF54X_H 7#ifndef _DEF_BF54X_H
@@ -2062,115 +2062,6 @@
2062#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ 2062#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
2063#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ 2063#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
2064 2064
2065/* ************************************************ */
2066/* The TWI bit masks fields are from the ADSP-BF538 */
2067/* and they have not been verified as the final */
2068/* ones for the Moab processors ... bz 1/19/2007 */
2069/* ************************************************ */
2070
2071/* Bit masks for TWIx_CONTROL */
2072
2073#define PRESCALE 0x7f /* Prescale Value */
2074#define TWI_ENA 0x80 /* TWI Enable */
2075#define SCCB 0x200 /* Serial Camera Control Bus */
2076
2077/* Bit maskes for TWIx_CLKDIV */
2078
2079#define CLKLOW 0xff /* Clock Low */
2080#define CLKHI 0xff00 /* Clock High */
2081
2082/* Bit maskes for TWIx_SLAVE_CTL */
2083
2084#define SEN 0x1 /* Slave Enable */
2085#define STDVAL 0x4 /* Slave Transmit Data Valid */
2086#define NAK 0x8 /* Not Acknowledge */
2087#define GEN 0x10 /* General Call Enable */
2088
2089/* Bit maskes for TWIx_SLAVE_ADDR */
2090
2091#define SADDR 0x7f /* Slave Mode Address */
2092
2093/* Bit maskes for TWIx_SLAVE_STAT */
2094
2095#define SDIR 0x1 /* Slave Transfer Direction */
2096#define GCALL 0x2 /* General Call */
2097
2098/* Bit maskes for TWIx_MASTER_CTL */
2099
2100#define MEN 0x1 /* Master Mode Enable */
2101#define MDIR 0x4 /* Master Transfer Direction */
2102#define FAST 0x8 /* Fast Mode */
2103#define STOP 0x10 /* Issue Stop Condition */
2104#define RSTART 0x20 /* Repeat Start */
2105#define DCNT 0x3fc0 /* Data Transfer Count */
2106#define SDAOVR 0x4000 /* Serial Data Override */
2107#define SCLOVR 0x8000 /* Serial Clock Override */
2108
2109/* Bit maskes for TWIx_MASTER_ADDR */
2110
2111#define MADDR 0x7f /* Master Mode Address */
2112
2113/* Bit maskes for TWIx_MASTER_STAT */
2114
2115#define MPROG 0x1 /* Master Transfer in Progress */
2116#define LOSTARB 0x2 /* Lost Arbitration */
2117#define ANAK 0x4 /* Address Not Acknowledged */
2118#define DNAK 0x8 /* Data Not Acknowledged */
2119#define BUFRDERR 0x10 /* Buffer Read Error */
2120#define BUFWRERR 0x20 /* Buffer Write Error */
2121#define SDASEN 0x40 /* Serial Data Sense */
2122#define SCLSEN 0x80 /* Serial Clock Sense */
2123#define BUSBUSY 0x100 /* Bus Busy */
2124
2125/* Bit maskes for TWIx_FIFO_CTL */
2126
2127#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
2128#define RCVFLUSH 0x2 /* Receive Buffer Flush */
2129#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
2130#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
2131
2132/* Bit maskes for TWIx_FIFO_STAT */
2133
2134#define XMTSTAT 0x3 /* Transmit FIFO Status */
2135#define RCVSTAT 0xc /* Receive FIFO Status */
2136
2137/* Bit maskes for TWIx_INT_MASK */
2138
2139#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
2140#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
2141#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
2142#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
2143#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
2144#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
2145#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
2146#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
2147
2148/* Bit maskes for TWIx_INT_STAT */
2149
2150#define SINIT 0x1 /* Slave Transfer Initiated */
2151#define SCOMP 0x2 /* Slave Transfer Complete */
2152#define SERR 0x4 /* Slave Transfer Error */
2153#define SOVF 0x8 /* Slave Overflow */
2154#define MCOMP 0x10 /* Master Transfer Complete */
2155#define MERR 0x20 /* Master Transfer Error */
2156#define XMTSERV 0x40 /* Transmit FIFO Service */
2157#define RCVSERV 0x80 /* Receive FIFO Service */
2158
2159/* Bit maskes for TWIx_XMT_DATA8 */
2160
2161#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
2162
2163/* Bit maskes for TWIx_XMT_DATA16 */
2164
2165#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
2166
2167/* Bit maskes for TWIx_RCV_DATA8 */
2168
2169#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
2170
2171/* Bit maskes for TWIx_RCV_DATA16 */
2172
2173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
2174 2065
2175/* ******************************************* */ 2066/* ******************************************* */
2176/* MULTI BIT MACRO ENUMERATIONS */ 2067/* MULTI BIT MACRO ENUMERATIONS */
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 836baeed303a..72476ff50335 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -6,8 +6,7 @@
6 * DO NOT EDIT THIS FILE 6 * DO NOT EDIT THIS FILE
7 * 7 *
8 * Copyright 2004-2011 Analog Devices Inc. 8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the ADI BSD license. 9 * Licensed under the Clear BSD license.
10 * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
11 */ 10 */
12 11
13/* This file should be up to date with: 12/* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 5f0ac5a77a37..9f21f768c63a 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2005-2010 Analog Devices Inc. 2 * Copyright 2005-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later) 4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _DEF_BF561_H 7#ifndef _DEF_BF561_H
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
new file mode 100644
index 000000000000..2cb727243778
--- /dev/null
+++ b/arch/blackfin/mach-bf609/Kconfig
@@ -0,0 +1,56 @@
1config BF60x
2 def_bool y
3 depends on (BF609)
4 select IRQ_PREFLOW_FASTEOI
5
6if (BF60x)
7
8source "arch/blackfin/mach-bf609/boards/Kconfig"
9
10menu "BF609 Specific Configuration"
11
12comment "Pin Interrupt to Port Assignment"
13menu "Assignment"
14
15config PINTx_REASSIGN
16 bool "Reprogram PINT Assignment"
17 default y
18 help
19 The interrupt assignment registers controls the pin-to-interrupt
20 assignment in a byte-wide manner. Each option allows you to select
21 a set of pins (High/Low Byte) of an specific Port being mapped
22 to one of the four PIN Interrupts IRQ_PINTx.
23
24 You shouldn't change any of these unless you know exactly what you're doing.
25 Please consult the Blackfin BF60x Processor Hardware Reference Manual.
26
27config PINT0_ASSIGN
28 hex "PINT0_ASSIGN"
29 depends on PINTx_REASSIGN
30 default 0x00000101
31config PINT1_ASSIGN
32 hex "PINT1_ASSIGN"
33 depends on PINTx_REASSIGN
34 default 0x00000101
35config PINT2_ASSIGN
36 hex "PINT2_ASSIGN"
37 depends on PINTx_REASSIGN
38 default 0x00000101
39config PINT3_ASSIGN
40 hex "PINT3_ASSIGN"
41 depends on PINTx_REASSIGN
42 default 0x00000101
43config PINT4_ASSIGN
44 hex "PINT3_ASSIGN"
45 depends on PINTx_REASSIGN
46 default 0x00000101
47config PINT5_ASSIGN
48 hex "PINT3_ASSIGN"
49 depends on PINTx_REASSIGN
50 default 0x00000101
51
52endmenu
53
54endmenu
55
56endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
new file mode 100644
index 000000000000..2a27f8174543
--- /dev/null
+++ b/arch/blackfin/mach-bf609/Makefile
@@ -0,0 +1,6 @@
1#
2# arch/blackfin/mach-bf609/Makefile
3#
4
5obj-y := dma.o clock.o
6obj-$(CONFIG_PM) += pm.o hibernate.o
diff --git a/arch/blackfin/mach-bf609/boards/Kconfig b/arch/blackfin/mach-bf609/boards/Kconfig
new file mode 100644
index 000000000000..30e8b6b0d2ed
--- /dev/null
+++ b/arch/blackfin/mach-bf609/boards/Kconfig
@@ -0,0 +1,12 @@
1choice
2 prompt "System type"
3 default BFIN609_EZKIT
4 help
5 Select your board!
6
7config BFIN609_EZKIT
8 bool "BF609-EZKIT"
9 help
10 BFIN609-EZKIT board support.
11
12endchoice
diff --git a/arch/blackfin/mach-bf609/boards/Makefile b/arch/blackfin/mach-bf609/boards/Makefile
new file mode 100644
index 000000000000..11f98b0882ea
--- /dev/null
+++ b/arch/blackfin/mach-bf609/boards/Makefile
@@ -0,0 +1,5 @@
1#
2# arch/blackfin/mach-bf609/boards/Makefile
3#
4
5obj-$(CONFIG_BFIN609_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
new file mode 100644
index 000000000000..ac64f47217c1
--- /dev/null
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -0,0 +1,1340 @@
1/*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/irq.h>
17#include <linux/i2c.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
20#include <asm/bfin6xx_spi.h>
21#include <asm/dma.h>
22#include <asm/gpio.h>
23#include <asm/nand.h>
24#include <asm/dpmc.h>
25#include <asm/portmux.h>
26#include <asm/bfin_sdh.h>
27#include <linux/input.h>
28#include <linux/spi/ad7877.h>
29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
33const char bfin_board_name[] = "ADI BF609-EZKIT";
34
35/*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
40#include <linux/usb/isp1760.h>
41static struct resource bfin_isp1760_resources[] = {
42 [0] = {
43 .start = 0x2C0C0000,
44 .end = 0x2C0C0000 + 0xfffff,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = IRQ_PG7,
49 .end = IRQ_PG7,
50 .flags = IORESOURCE_IRQ,
51 },
52};
53
54static struct isp1760_platform_data isp1760_priv = {
55 .is_isp1761 = 0,
56 .bus_width_16 = 1,
57 .port1_otg = 0,
58 .analog_oc = 0,
59 .dack_polarity_high = 0,
60 .dreq_polarity_high = 0,
61};
62
63static struct platform_device bfin_isp1760_device = {
64 .name = "isp1760",
65 .id = 0,
66 .dev = {
67 .platform_data = &isp1760_priv,
68 },
69 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
70 .resource = bfin_isp1760_resources,
71};
72#endif
73
74#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
75#include <asm/bfin_rotary.h>
76
77static struct bfin_rotary_platform_data bfin_rotary_data = {
78 /*.rotary_up_key = KEY_UP,*/
79 /*.rotary_down_key = KEY_DOWN,*/
80 .rotary_rel_code = REL_WHEEL,
81 .rotary_button_key = KEY_ENTER,
82 .debounce = 10, /* 0..17 */
83 .mode = ROT_QUAD_ENC | ROT_DEBE,
84};
85
86static struct resource bfin_rotary_resources[] = {
87 {
88 .start = IRQ_CNT,
89 .end = IRQ_CNT,
90 .flags = IORESOURCE_IRQ,
91 },
92};
93
94static struct platform_device bfin_rotary_device = {
95 .name = "bfin-rotary",
96 .id = -1,
97 .num_resources = ARRAY_SIZE(bfin_rotary_resources),
98 .resource = bfin_rotary_resources,
99 .dev = {
100 .platform_data = &bfin_rotary_data,
101 },
102};
103#endif
104
105#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
106#include <linux/stmmac.h>
107
108static unsigned short pins[] = P_RMII0;
109
110static struct stmmac_mdio_bus_data phy_private_data = {
111 .bus_id = 0,
112 .phy_mask = 1,
113};
114
115static struct plat_stmmacenet_data eth_private_data = {
116 .bus_id = 0,
117 .enh_desc = 1,
118 .phy_addr = 1,
119 .mdio_bus_data = &phy_private_data,
120};
121
122static struct platform_device bfin_eth_device = {
123 .name = "stmmaceth",
124 .id = 0,
125 .num_resources = 2,
126 .resource = (struct resource[]) {
127 {
128 .start = EMAC0_MACCFG,
129 .end = EMAC0_MACCFG + 0x1274,
130 .flags = IORESOURCE_MEM,
131 },
132 {
133 .name = "macirq",
134 .start = IRQ_EMAC0_STAT,
135 .end = IRQ_EMAC0_STAT,
136 .flags = IORESOURCE_IRQ,
137 },
138 },
139 .dev = {
140 .power.can_wakeup = 1,
141 .platform_data = &eth_private_data,
142 }
143};
144#endif
145
146#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
147#include <linux/input/adxl34x.h>
148static const struct adxl34x_platform_data adxl34x_info = {
149 .x_axis_offset = 0,
150 .y_axis_offset = 0,
151 .z_axis_offset = 0,
152 .tap_threshold = 0x31,
153 .tap_duration = 0x10,
154 .tap_latency = 0x60,
155 .tap_window = 0xF0,
156 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
157 .act_axis_control = 0xFF,
158 .activity_threshold = 5,
159 .inactivity_threshold = 3,
160 .inactivity_time = 4,
161 .free_fall_threshold = 0x7,
162 .free_fall_time = 0x20,
163 .data_rate = 0x8,
164 .data_range = ADXL_FULL_RES,
165
166 .ev_type = EV_ABS,
167 .ev_code_x = ABS_X, /* EV_REL */
168 .ev_code_y = ABS_Y, /* EV_REL */
169 .ev_code_z = ABS_Z, /* EV_REL */
170
171 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
172
173/* .ev_code_ff = KEY_F,*/ /* EV_KEY */
174/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
175 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
176 .fifo_mode = ADXL_FIFO_STREAM,
177 .orientation_enable = ADXL_EN_ORIENTATION_3D,
178 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
179 .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
180 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
181 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
182};
183#endif
184
185#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
186static struct platform_device rtc_device = {
187 .name = "rtc-bfin",
188 .id = -1,
189};
190#endif
191
192#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
193#ifdef CONFIG_SERIAL_BFIN_UART0
194static struct resource bfin_uart0_resources[] = {
195 {
196 .start = UART0_REVID,
197 .end = UART0_RXDIV+4,
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .start = IRQ_UART0_TX,
202 .end = IRQ_UART0_TX,
203 .flags = IORESOURCE_IRQ,
204 },
205 {
206 .start = IRQ_UART0_RX,
207 .end = IRQ_UART0_RX,
208 .flags = IORESOURCE_IRQ,
209 },
210 {
211 .start = IRQ_UART0_STAT,
212 .end = IRQ_UART0_STAT,
213 .flags = IORESOURCE_IRQ,
214 },
215 {
216 .start = CH_UART0_TX,
217 .end = CH_UART0_TX,
218 .flags = IORESOURCE_DMA,
219 },
220 {
221 .start = CH_UART0_RX,
222 .end = CH_UART0_RX,
223 .flags = IORESOURCE_DMA,
224 },
225#ifdef CONFIG_BFIN_UART0_CTSRTS
226 { /* CTS pin -- 0 means not supported */
227 .start = GPIO_PD10,
228 .end = GPIO_PD10,
229 .flags = IORESOURCE_IO,
230 },
231 { /* RTS pin -- 0 means not supported */
232 .start = GPIO_PD9,
233 .end = GPIO_PD9,
234 .flags = IORESOURCE_IO,
235 },
236#endif
237};
238
239static unsigned short bfin_uart0_peripherals[] = {
240 P_UART0_TX, P_UART0_RX,
241#ifdef CONFIG_BFIN_UART0_CTSRTS
242 P_UART0_RTS, P_UART0_CTS,
243#endif
244 0
245};
246
247static struct platform_device bfin_uart0_device = {
248 .name = "bfin-uart",
249 .id = 0,
250 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
251 .resource = bfin_uart0_resources,
252 .dev = {
253 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
254 },
255};
256#endif
257#ifdef CONFIG_SERIAL_BFIN_UART1
258static struct resource bfin_uart1_resources[] = {
259 {
260 .start = UART1_REVID,
261 .end = UART1_RXDIV+4,
262 .flags = IORESOURCE_MEM,
263 },
264 {
265 .start = IRQ_UART1_TX,
266 .end = IRQ_UART1_TX,
267 .flags = IORESOURCE_IRQ,
268 },
269 {
270 .start = IRQ_UART1_RX,
271 .end = IRQ_UART1_RX,
272 .flags = IORESOURCE_IRQ,
273 },
274 {
275 .start = IRQ_UART1_STAT,
276 .end = IRQ_UART1_STAT,
277 .flags = IORESOURCE_IRQ,
278 },
279 {
280 .start = CH_UART1_TX,
281 .end = CH_UART1_TX,
282 .flags = IORESOURCE_DMA,
283 },
284 {
285 .start = CH_UART1_RX,
286 .end = CH_UART1_RX,
287 .flags = IORESOURCE_DMA,
288 },
289#ifdef CONFIG_BFIN_UART1_CTSRTS
290 { /* CTS pin -- 0 means not supported */
291 .start = GPIO_PG13,
292 .end = GPIO_PG13,
293 .flags = IORESOURCE_IO,
294 },
295 { /* RTS pin -- 0 means not supported */
296 .start = GPIO_PG10,
297 .end = GPIO_PG10,
298 .flags = IORESOURCE_IO,
299 },
300#endif
301};
302
303static unsigned short bfin_uart1_peripherals[] = {
304 P_UART1_TX, P_UART1_RX,
305#ifdef CONFIG_BFIN_UART1_CTSRTS
306 P_UART1_RTS, P_UART1_CTS,
307#endif
308 0
309};
310
311static struct platform_device bfin_uart1_device = {
312 .name = "bfin-uart",
313 .id = 1,
314 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
315 .resource = bfin_uart1_resources,
316 .dev = {
317 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
318 },
319};
320#endif
321#endif
322
323#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
324#ifdef CONFIG_BFIN_SIR0
325static struct resource bfin_sir0_resources[] = {
326 {
327 .start = 0xFFC00400,
328 .end = 0xFFC004FF,
329 .flags = IORESOURCE_MEM,
330 },
331 {
332 .start = IRQ_UART0_TX,
333 .end = IRQ_UART0_TX+1,
334 .flags = IORESOURCE_IRQ,
335 },
336 {
337 .start = CH_UART0_TX,
338 .end = CH_UART0_TX+1,
339 .flags = IORESOURCE_DMA,
340 },
341};
342static struct platform_device bfin_sir0_device = {
343 .name = "bfin_sir",
344 .id = 0,
345 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
346 .resource = bfin_sir0_resources,
347};
348#endif
349#ifdef CONFIG_BFIN_SIR1
350static struct resource bfin_sir1_resources[] = {
351 {
352 .start = 0xFFC02000,
353 .end = 0xFFC020FF,
354 .flags = IORESOURCE_MEM,
355 },
356 {
357 .start = IRQ_UART1_TX,
358 .end = IRQ_UART1_TX+1,
359 .flags = IORESOURCE_IRQ,
360 },
361 {
362 .start = CH_UART1_TX,
363 .end = CH_UART1_TX+1,
364 .flags = IORESOURCE_DMA,
365 },
366};
367static struct platform_device bfin_sir1_device = {
368 .name = "bfin_sir",
369 .id = 1,
370 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
371 .resource = bfin_sir1_resources,
372};
373#endif
374#endif
375
376#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
377static struct resource musb_resources[] = {
378 [0] = {
379 .start = 0xFFCC1000,
380 .end = 0xFFCC1398,
381 .flags = IORESOURCE_MEM,
382 },
383 [1] = { /* general IRQ */
384 .start = IRQ_USB_STAT,
385 .end = IRQ_USB_STAT,
386 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
387 .name = "mc"
388 },
389 [2] = { /* DMA IRQ */
390 .start = IRQ_USB_DMA,
391 .end = IRQ_USB_DMA,
392 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
393 .name = "dma"
394 },
395};
396
397static struct musb_hdrc_config musb_config = {
398 .multipoint = 1,
399 .dyn_fifo = 0,
400 .dma = 1,
401 .num_eps = 16,
402 .dma_channels = 8,
403 .clkin = 48, /* musb CLKIN in MHZ */
404};
405
406static struct musb_hdrc_platform_data musb_plat = {
407#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
408 .mode = MUSB_OTG,
409#elif defined(CONFIG_USB_MUSB_HDRC)
410 .mode = MUSB_HOST,
411#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
412 .mode = MUSB_PERIPHERAL,
413#endif
414 .config = &musb_config,
415};
416
417static u64 musb_dmamask = ~(u32)0;
418
419static struct platform_device musb_device = {
420 .name = "musb-blackfin",
421 .id = 0,
422 .dev = {
423 .dma_mask = &musb_dmamask,
424 .coherent_dma_mask = 0xffffffff,
425 .platform_data = &musb_plat,
426 },
427 .num_resources = ARRAY_SIZE(musb_resources),
428 .resource = musb_resources,
429};
430#endif
431
432#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
433#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
434static struct resource bfin_sport0_uart_resources[] = {
435 {
436 .start = SPORT0_TCR1,
437 .end = SPORT0_MRCS3+4,
438 .flags = IORESOURCE_MEM,
439 },
440 {
441 .start = IRQ_SPORT0_RX,
442 .end = IRQ_SPORT0_RX+1,
443 .flags = IORESOURCE_IRQ,
444 },
445 {
446 .start = IRQ_SPORT0_ERROR,
447 .end = IRQ_SPORT0_ERROR,
448 .flags = IORESOURCE_IRQ,
449 },
450};
451
452static unsigned short bfin_sport0_peripherals[] = {
453 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
454 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
455};
456
457static struct platform_device bfin_sport0_uart_device = {
458 .name = "bfin-sport-uart",
459 .id = 0,
460 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
461 .resource = bfin_sport0_uart_resources,
462 .dev = {
463 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
464 },
465};
466#endif
467#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
468static struct resource bfin_sport1_uart_resources[] = {
469 {
470 .start = SPORT1_TCR1,
471 .end = SPORT1_MRCS3+4,
472 .flags = IORESOURCE_MEM,
473 },
474 {
475 .start = IRQ_SPORT1_RX,
476 .end = IRQ_SPORT1_RX+1,
477 .flags = IORESOURCE_IRQ,
478 },
479 {
480 .start = IRQ_SPORT1_ERROR,
481 .end = IRQ_SPORT1_ERROR,
482 .flags = IORESOURCE_IRQ,
483 },
484};
485
486static unsigned short bfin_sport1_peripherals[] = {
487 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
488 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
489};
490
491static struct platform_device bfin_sport1_uart_device = {
492 .name = "bfin-sport-uart",
493 .id = 1,
494 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
495 .resource = bfin_sport1_uart_resources,
496 .dev = {
497 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
498 },
499};
500#endif
501#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
502static struct resource bfin_sport2_uart_resources[] = {
503 {
504 .start = SPORT2_TCR1,
505 .end = SPORT2_MRCS3+4,
506 .flags = IORESOURCE_MEM,
507 },
508 {
509 .start = IRQ_SPORT2_RX,
510 .end = IRQ_SPORT2_RX+1,
511 .flags = IORESOURCE_IRQ,
512 },
513 {
514 .start = IRQ_SPORT2_ERROR,
515 .end = IRQ_SPORT2_ERROR,
516 .flags = IORESOURCE_IRQ,
517 },
518};
519
520static unsigned short bfin_sport2_peripherals[] = {
521 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
522 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
523};
524
525static struct platform_device bfin_sport2_uart_device = {
526 .name = "bfin-sport-uart",
527 .id = 2,
528 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
529 .resource = bfin_sport2_uart_resources,
530 .dev = {
531 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
532 },
533};
534#endif
535#endif
536
537#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
538
539static unsigned short bfin_can0_peripherals[] = {
540 P_CAN0_RX, P_CAN0_TX, 0
541};
542
543static struct resource bfin_can0_resources[] = {
544 {
545 .start = 0xFFC00A00,
546 .end = 0xFFC00FFF,
547 .flags = IORESOURCE_MEM,
548 },
549 {
550 .start = IRQ_CAN0_RX,
551 .end = IRQ_CAN0_RX,
552 .flags = IORESOURCE_IRQ,
553 },
554 {
555 .start = IRQ_CAN0_TX,
556 .end = IRQ_CAN0_TX,
557 .flags = IORESOURCE_IRQ,
558 },
559 {
560 .start = IRQ_CAN0_STAT,
561 .end = IRQ_CAN0_STAT,
562 .flags = IORESOURCE_IRQ,
563 },
564};
565
566static struct platform_device bfin_can0_device = {
567 .name = "bfin_can",
568 .id = 0,
569 .num_resources = ARRAY_SIZE(bfin_can0_resources),
570 .resource = bfin_can0_resources,
571 .dev = {
572 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
573 },
574};
575
576#endif
577
578#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
579static struct mtd_partition partition_info[] = {
580 {
581 .name = "bootloader(nand)",
582 .offset = 0,
583 .size = 0x80000,
584 }, {
585 .name = "linux kernel(nand)",
586 .offset = MTDPART_OFS_APPEND,
587 .size = 4 * 1024 * 1024,
588 },
589 {
590 .name = "file system(nand)",
591 .offset = MTDPART_OFS_APPEND,
592 .size = MTDPART_SIZ_FULL,
593 },
594};
595
596static struct bf5xx_nand_platform bfin_nand_platform = {
597 .data_width = NFC_NWIDTH_8,
598 .partitions = partition_info,
599 .nr_partitions = ARRAY_SIZE(partition_info),
600 .rd_dly = 3,
601 .wr_dly = 3,
602};
603
604static struct resource bfin_nand_resources[] = {
605 {
606 .start = 0xFFC03B00,
607 .end = 0xFFC03B4F,
608 .flags = IORESOURCE_MEM,
609 },
610 {
611 .start = CH_NFC,
612 .end = CH_NFC,
613 .flags = IORESOURCE_IRQ,
614 },
615};
616
617static struct platform_device bfin_nand_device = {
618 .name = "bfin-nand",
619 .id = 0,
620 .num_resources = ARRAY_SIZE(bfin_nand_resources),
621 .resource = bfin_nand_resources,
622 .dev = {
623 .platform_data = &bfin_nand_platform,
624 },
625};
626#endif
627
628#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
629
630static struct bfin_sd_host bfin_sdh_data = {
631 .dma_chan = CH_RSI,
632 .irq_int0 = IRQ_RSI_INT0,
633 .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
634};
635
636static struct platform_device bfin_sdh_device = {
637 .name = "bfin-sdh",
638 .id = 0,
639 .dev = {
640 .platform_data = &bfin_sdh_data,
641 },
642};
643#endif
644
645#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
646static struct mtd_partition ezkit_partitions[] = {
647 {
648 .name = "bootloader(nor)",
649 .size = 0x80000,
650 .offset = 0,
651 }, {
652 .name = "linux kernel(nor)",
653 .size = 0x400000,
654 .offset = MTDPART_OFS_APPEND,
655 }, {
656 .name = "file system(nor)",
657 .size = 0x1000000 - 0x80000 - 0x400000,
658 .offset = MTDPART_OFS_APPEND,
659 },
660};
661
662int bf609_nor_flash_init(struct platform_device *dev)
663{
664#define CONFIG_SMC_GCTL_VAL 0x00000010
665 const unsigned short pins[] = {
666 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
667 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
668 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
669 };
670
671 peripheral_request_list(pins, "smc0");
672
673 bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
674 bfin_write32(SMC_B0CTL, 0x01002011);
675 bfin_write32(SMC_B0TIM, 0x08170977);
676 bfin_write32(SMC_B0ETIM, 0x00092231);
677 return 0;
678}
679
680static struct physmap_flash_data ezkit_flash_data = {
681 .width = 2,
682 .parts = ezkit_partitions,
683 .init = bf609_nor_flash_init,
684 .nr_parts = ARRAY_SIZE(ezkit_partitions),
685};
686
687static struct resource ezkit_flash_resource = {
688 .start = 0xb0000000,
689 .end = 0xb0ffffff,
690 .flags = IORESOURCE_MEM,
691};
692
693static struct platform_device ezkit_flash_device = {
694 .name = "physmap-flash",
695 .id = 0,
696 .dev = {
697 .platform_data = &ezkit_flash_data,
698 },
699 .num_resources = 1,
700 .resource = &ezkit_flash_resource,
701};
702#endif
703
704#if defined(CONFIG_MTD_M25P80) \
705 || defined(CONFIG_MTD_M25P80_MODULE)
706/* SPI flash chip (w25q32) */
707static struct mtd_partition bfin_spi_flash_partitions[] = {
708 {
709 .name = "bootloader(spi)",
710 .size = 0x00080000,
711 .offset = 0,
712 .mask_flags = MTD_CAP_ROM
713 }, {
714 .name = "linux kernel(spi)",
715 .size = 0x00180000,
716 .offset = MTDPART_OFS_APPEND,
717 }, {
718 .name = "file system(spi)",
719 .size = MTDPART_SIZ_FULL,
720 .offset = MTDPART_OFS_APPEND,
721 }
722};
723
724static struct flash_platform_data bfin_spi_flash_data = {
725 .name = "m25p80",
726 .parts = bfin_spi_flash_partitions,
727 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
728 .type = "w25q32",
729};
730
731static struct bfin6xx_spi_chip spi_flash_chip_info = {
732 .enable_dma = true, /* use dma transfer with this chip*/
733};
734#endif
735
736#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
737static struct bfin6xx_spi_chip spidev_chip_info = {
738 .enable_dma = true,
739};
740#endif
741
742#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
743static struct platform_device bfin_i2s_pcm = {
744 .name = "bfin-i2s-pcm-audio",
745 .id = -1,
746};
747#endif
748
749#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
750 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
751#include <asm/bfin_sport3.h>
752static struct resource bfin_snd_resources[] = {
753 {
754 .start = SPORT0_CTL_A,
755 .end = SPORT0_CTL_A,
756 .flags = IORESOURCE_MEM,
757 },
758 {
759 .start = SPORT0_CTL_B,
760 .end = SPORT0_CTL_B,
761 .flags = IORESOURCE_MEM,
762 },
763 {
764 .start = CH_SPORT0_TX,
765 .end = CH_SPORT0_TX,
766 .flags = IORESOURCE_DMA,
767 },
768 {
769 .start = CH_SPORT0_RX,
770 .end = CH_SPORT0_RX,
771 .flags = IORESOURCE_DMA,
772 },
773 {
774 .start = IRQ_SPORT0_TX_STAT,
775 .end = IRQ_SPORT0_TX_STAT,
776 .flags = IORESOURCE_IRQ,
777 },
778 {
779 .start = IRQ_SPORT0_RX_STAT,
780 .end = IRQ_SPORT0_RX_STAT,
781 .flags = IORESOURCE_IRQ,
782 },
783};
784
785static const unsigned short bfin_snd_pin[] = {
786 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
787 P_SPORT0_BFS, P_SPORT0_BD0, 0,
788};
789
790static struct bfin_snd_platform_data bfin_snd_data = {
791 .pin_req = bfin_snd_pin,
792};
793
794static struct platform_device bfin_i2s = {
795 .name = "bfin-i2s",
796 .num_resources = ARRAY_SIZE(bfin_snd_resources),
797 .resource = bfin_snd_resources,
798 .dev = {
799 .platform_data = &bfin_snd_data,
800 },
801};
802#endif
803
804#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
805 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
806static struct platform_device adau1761_device = {
807 .name = "bfin-eval-adau1x61",
808};
809#endif
810
811#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
812#include <sound/adau17x1.h>
813static struct adau1761_platform_data adau1761_info = {
814 .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
815 .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
816};
817#endif
818
819#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
820 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
821#include <linux/videodev2.h>
822#include <media/blackfin/bfin_capture.h>
823#include <media/blackfin/ppi.h>
824
825static const unsigned short ppi_req[] = {
826 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
827 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
828 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
829 0,
830};
831
832static const struct ppi_info ppi_info = {
833 .type = PPI_TYPE_EPPI3,
834 .dma_ch = CH_EPPI0_CH0,
835 .irq_err = IRQ_EPPI0_STAT,
836 .base = (void __iomem *)EPPI0_STAT,
837 .pin_req = ppi_req,
838};
839
840#if defined(CONFIG_VIDEO_VS6624) \
841 || defined(CONFIG_VIDEO_VS6624_MODULE)
842static struct v4l2_input vs6624_inputs[] = {
843 {
844 .index = 0,
845 .name = "Camera",
846 .type = V4L2_INPUT_TYPE_CAMERA,
847 .std = V4L2_STD_UNKNOWN,
848 },
849};
850
851static struct bcap_route vs6624_routes[] = {
852 {
853 .input = 0,
854 .output = 0,
855 },
856};
857
858static const unsigned vs6624_ce_pin = GPIO_PD1;
859
860static struct bfin_capture_config bfin_capture_data = {
861 .card_name = "BF609",
862 .inputs = vs6624_inputs,
863 .num_inputs = ARRAY_SIZE(vs6624_inputs),
864 .routes = vs6624_routes,
865 .i2c_adapter_id = 0,
866 .board_info = {
867 .type = "vs6624",
868 .addr = 0x10,
869 .platform_data = (void *)&vs6624_ce_pin,
870 },
871 .ppi_info = &ppi_info,
872 .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
873 | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
874 .blank_clocks = 8,
875};
876#endif
877
878static struct platform_device bfin_capture_device = {
879 .name = "bfin_capture",
880 .dev = {
881 .platform_data = &bfin_capture_data,
882 },
883};
884#endif
885
886#if defined(CONFIG_BFIN_CRC)
887#define BFIN_CRC_NAME "bfin-crc"
888
889static struct resource bfin_crc0_resources[] = {
890 {
891 .start = REG_CRC0_CTL,
892 .end = REG_CRC0_REVID+4,
893 .flags = IORESOURCE_MEM,
894 },
895 {
896 .start = IRQ_CRC0_DCNTEXP,
897 .end = IRQ_CRC0_DCNTEXP,
898 .flags = IORESOURCE_IRQ,
899 },
900 {
901 .start = CH_MEM_STREAM0_SRC_CRC0,
902 .end = CH_MEM_STREAM0_SRC_CRC0,
903 .flags = IORESOURCE_DMA,
904 },
905 {
906 .start = CH_MEM_STREAM0_DEST_CRC0,
907 .end = CH_MEM_STREAM0_DEST_CRC0,
908 .flags = IORESOURCE_DMA,
909 },
910};
911
912static struct platform_device bfin_crc0_device = {
913 .name = BFIN_CRC_NAME,
914 .id = 0,
915 .num_resources = ARRAY_SIZE(bfin_crc0_resources),
916 .resource = bfin_crc0_resources,
917};
918
919static struct resource bfin_crc1_resources[] = {
920 {
921 .start = REG_CRC1_CTL,
922 .end = REG_CRC1_REVID+4,
923 .flags = IORESOURCE_MEM,
924 },
925 {
926 .start = IRQ_CRC1_DCNTEXP,
927 .end = IRQ_CRC1_DCNTEXP,
928 .flags = IORESOURCE_IRQ,
929 },
930 {
931 .start = CH_MEM_STREAM1_SRC_CRC1,
932 .end = CH_MEM_STREAM1_SRC_CRC1,
933 .flags = IORESOURCE_DMA,
934 },
935 {
936 .start = CH_MEM_STREAM1_DEST_CRC1,
937 .end = CH_MEM_STREAM1_DEST_CRC1,
938 .flags = IORESOURCE_DMA,
939 },
940};
941
942static struct platform_device bfin_crc1_device = {
943 .name = BFIN_CRC_NAME,
944 .id = 1,
945 .num_resources = ARRAY_SIZE(bfin_crc1_resources),
946 .resource = bfin_crc1_resources,
947};
948#endif
949
950#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
951static const struct ad7877_platform_data bfin_ad7877_ts_info = {
952 .model = 7877,
953 .vref_delay_usecs = 50, /* internal, no capacitor */
954 .x_plate_ohms = 419,
955 .y_plate_ohms = 486,
956 .pressure_max = 1000,
957 .pressure_min = 0,
958 .stopacq_polarity = 1,
959 .first_conversion_delay = 3,
960 .acquisition_time = 1,
961 .averaging = 1,
962 .pen_down_acc_interval = 1,
963};
964#endif
965
966static struct spi_board_info bfin_spi_board_info[] __initdata = {
967#if defined(CONFIG_MTD_M25P80) \
968 || defined(CONFIG_MTD_M25P80_MODULE)
969 {
970 /* the modalias must be the same as spi device driver name */
971 .modalias = "m25p80", /* Name of spi_driver for this device */
972 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
973 .bus_num = 0, /* Framework bus number */
974 .chip_select = 1, /* SPI_SSEL1*/
975 .platform_data = &bfin_spi_flash_data,
976 .controller_data = &spi_flash_chip_info,
977 .mode = SPI_MODE_3,
978 },
979#endif
980#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
981 {
982 .modalias = "ad7877",
983 .platform_data = &bfin_ad7877_ts_info,
984 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */
985 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
986 .bus_num = 0,
987 .chip_select = 2,
988 },
989#endif
990#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
991 {
992 .modalias = "spidev",
993 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
994 .bus_num = 0,
995 .chip_select = 1,
996 .controller_data = &spidev_chip_info,
997 },
998#endif
999#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
1000 {
1001 .modalias = "adxl34x",
1002 .platform_data = &adxl34x_info,
1003 .irq = IRQ_PC5,
1004 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
1005 .bus_num = 1,
1006 .chip_select = 2,
1007 .mode = SPI_MODE_3,
1008 },
1009#endif
1010};
1011#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
1012/* SPI (0) */
1013static struct resource bfin_spi0_resource[] = {
1014 {
1015 .start = SPI0_REGBASE,
1016 .end = SPI0_REGBASE + 0xFF,
1017 .flags = IORESOURCE_MEM,
1018 },
1019 {
1020 .start = CH_SPI0_TX,
1021 .end = CH_SPI0_TX,
1022 .flags = IORESOURCE_DMA,
1023 },
1024 {
1025 .start = CH_SPI0_RX,
1026 .end = CH_SPI0_RX,
1027 .flags = IORESOURCE_DMA,
1028 },
1029};
1030
1031/* SPI (1) */
1032static struct resource bfin_spi1_resource[] = {
1033 {
1034 .start = SPI1_REGBASE,
1035 .end = SPI1_REGBASE + 0xFF,
1036 .flags = IORESOURCE_MEM,
1037 },
1038 {
1039 .start = CH_SPI1_TX,
1040 .end = CH_SPI1_TX,
1041 .flags = IORESOURCE_DMA,
1042 },
1043 {
1044 .start = CH_SPI1_RX,
1045 .end = CH_SPI1_RX,
1046 .flags = IORESOURCE_DMA,
1047 },
1048
1049};
1050
1051/* SPI controller data */
1052static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
1053 .num_chipselect = 4,
1054 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1055};
1056
1057static struct platform_device bf60x_spi_master0 = {
1058 .name = "bfin-spi",
1059 .id = 0, /* Bus number */
1060 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
1061 .resource = bfin_spi0_resource,
1062 .dev = {
1063 .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
1064 },
1065};
1066
1067static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
1068 .num_chipselect = 4,
1069 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1070};
1071
1072static struct platform_device bf60x_spi_master1 = {
1073 .name = "bfin-spi",
1074 .id = 1, /* Bus number */
1075 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
1076 .resource = bfin_spi1_resource,
1077 .dev = {
1078 .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
1079 },
1080};
1081#endif /* spi master and devices */
1082
1083#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1084static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
1085
1086static struct resource bfin_twi0_resource[] = {
1087 [0] = {
1088 .start = TWI0_CLKDIV,
1089 .end = TWI0_CLKDIV + 0xFF,
1090 .flags = IORESOURCE_MEM,
1091 },
1092 [1] = {
1093 .start = IRQ_TWI0,
1094 .end = IRQ_TWI0,
1095 .flags = IORESOURCE_IRQ,
1096 },
1097};
1098
1099static struct platform_device i2c_bfin_twi0_device = {
1100 .name = "i2c-bfin-twi",
1101 .id = 0,
1102 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1103 .resource = bfin_twi0_resource,
1104 .dev = {
1105 .platform_data = &bfin_twi0_pins,
1106 },
1107};
1108
1109static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
1110
1111static struct resource bfin_twi1_resource[] = {
1112 [0] = {
1113 .start = TWI1_CLKDIV,
1114 .end = TWI1_CLKDIV + 0xFF,
1115 .flags = IORESOURCE_MEM,
1116 },
1117 [1] = {
1118 .start = IRQ_TWI1,
1119 .end = IRQ_TWI1,
1120 .flags = IORESOURCE_IRQ,
1121 },
1122};
1123
1124static struct platform_device i2c_bfin_twi1_device = {
1125 .name = "i2c-bfin-twi",
1126 .id = 1,
1127 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1128 .resource = bfin_twi1_resource,
1129 .dev = {
1130 .platform_data = &bfin_twi1_pins,
1131 },
1132};
1133#endif
1134
1135static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
1136#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
1137 {
1138 I2C_BOARD_INFO("adxl34x", 0x53),
1139 .irq = IRQ_PC5,
1140 .platform_data = (void *)&adxl34x_info,
1141 },
1142#endif
1143#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
1144 {
1145 I2C_BOARD_INFO("adau1761", 0x38),
1146 .platform_data = (void *)&adau1761_info
1147 },
1148#endif
1149};
1150
1151static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
1152};
1153
1154static const unsigned int cclk_vlev_datasheet[] =
1155{
1156/*
1157 * Internal VLEV BF54XSBBC1533
1158 ****temporarily using these values until data sheet is updated
1159 */
1160 VRPAIR(VLEV_085, 150000000),
1161 VRPAIR(VLEV_090, 250000000),
1162 VRPAIR(VLEV_110, 276000000),
1163 VRPAIR(VLEV_115, 301000000),
1164 VRPAIR(VLEV_120, 525000000),
1165 VRPAIR(VLEV_125, 550000000),
1166 VRPAIR(VLEV_130, 600000000),
1167};
1168
1169static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1170 .tuple_tab = cclk_vlev_datasheet,
1171 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1172 .vr_settling_time = 25 /* us */,
1173};
1174
1175static struct platform_device bfin_dpmc = {
1176 .name = "bfin dpmc",
1177 .dev = {
1178 .platform_data = &bfin_dmpc_vreg_data,
1179 },
1180};
1181
1182static struct platform_device *ezkit_devices[] __initdata = {
1183
1184 &bfin_dpmc,
1185
1186#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1187 &rtc_device,
1188#endif
1189
1190#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
1191#ifdef CONFIG_SERIAL_BFIN_UART0
1192 &bfin_uart0_device,
1193#endif
1194#ifdef CONFIG_SERIAL_BFIN_UART1
1195 &bfin_uart1_device,
1196#endif
1197#endif
1198
1199#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
1200#ifdef CONFIG_BFIN_SIR0
1201 &bfin_sir0_device,
1202#endif
1203#ifdef CONFIG_BFIN_SIR1
1204 &bfin_sir1_device,
1205#endif
1206#endif
1207
1208#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1209 &bfin_eth_device,
1210#endif
1211
1212#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1213 &musb_device,
1214#endif
1215
1216#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
1217 &bfin_isp1760_device,
1218#endif
1219
1220#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1221#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1222 &bfin_sport0_uart_device,
1223#endif
1224#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1225 &bfin_sport1_uart_device,
1226#endif
1227#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1228 &bfin_sport2_uart_device,
1229#endif
1230#endif
1231
1232#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1233 &bfin_can0_device,
1234#endif
1235
1236#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1237 &bfin_nand_device,
1238#endif
1239
1240#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
1241 &bfin_sdh_device,
1242#endif
1243
1244#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
1245 &bf60x_spi_master0,
1246 &bf60x_spi_master1,
1247#endif
1248
1249#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
1250 &bfin_rotary_device,
1251#endif
1252
1253#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1254 &i2c_bfin_twi0_device,
1255#if !defined(CONFIG_BF542)
1256 &i2c_bfin_twi1_device,
1257#endif
1258#endif
1259
1260#if defined(CONFIG_BFIN_CRC)
1261 &bfin_crc0_device,
1262 &bfin_crc1_device,
1263#endif
1264
1265#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1266 &bfin_device_gpiokeys,
1267#endif
1268
1269#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
1270 &ezkit_flash_device,
1271#endif
1272#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
1273 &bfin_i2s_pcm,
1274#endif
1275#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
1276 defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
1277 &bfin_i2s,
1278#endif
1279#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
1280 defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
1281 &adau1761_device,
1282#endif
1283#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
1284 || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
1285 &bfin_capture_device,
1286#endif
1287};
1288
1289static int __init ezkit_init(void)
1290{
1291 printk(KERN_INFO "%s(): registering device resources\n", __func__);
1292
1293 i2c_register_board_info(0, bfin_i2c_board_info0,
1294 ARRAY_SIZE(bfin_i2c_board_info0));
1295 i2c_register_board_info(1, bfin_i2c_board_info1,
1296 ARRAY_SIZE(bfin_i2c_board_info1));
1297
1298#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
1299 if (!peripheral_request_list(pins, "emac0"))
1300 printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
1301#endif
1302
1303 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
1304
1305 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
1306
1307 return 0;
1308}
1309
1310arch_initcall(ezkit_init);
1311
1312static struct platform_device *ezkit_early_devices[] __initdata = {
1313#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1314#ifdef CONFIG_SERIAL_BFIN_UART0
1315 &bfin_uart0_device,
1316#endif
1317#ifdef CONFIG_SERIAL_BFIN_UART1
1318 &bfin_uart1_device,
1319#endif
1320#endif
1321
1322#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1323#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1324 &bfin_sport0_uart_device,
1325#endif
1326#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1327 &bfin_sport1_uart_device,
1328#endif
1329#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1330 &bfin_sport2_uart_device,
1331#endif
1332#endif
1333};
1334
1335void __init native_machine_early_platform_add_devices(void)
1336{
1337 printk(KERN_INFO "register early platform devices\n");
1338 early_platform_add_devices(ezkit_early_devices,
1339 ARRAY_SIZE(ezkit_early_devices));
1340}
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
new file mode 100644
index 000000000000..7f8f529693ae
--- /dev/null
+++ b/arch/blackfin/mach-bf609/clock.c
@@ -0,0 +1,390 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/list.h>
4#include <linux/errno.h>
5#include <linux/err.h>
6#include <linux/string.h>
7#include <linux/clk.h>
8#include <linux/mutex.h>
9#include <linux/spinlock.h>
10#include <linux/debugfs.h>
11#include <linux/device.h>
12#include <linux/init.h>
13#include <linux/timer.h>
14#include <linux/io.h>
15#include <linux/seq_file.h>
16#include <linux/clkdev.h>
17
18#include <asm/clocks.h>
19
20#define CGU0_CTL_DF (1 << 0)
21
22#define CGU0_CTL_MSEL_SHIFT 8
23#define CGU0_CTL_MSEL_MASK (0x7f << 8)
24
25#define CGU0_STAT_PLLEN (1 << 0)
26#define CGU0_STAT_PLLBP (1 << 1)
27#define CGU0_STAT_PLLLK (1 << 2)
28#define CGU0_STAT_CLKSALGN (1 << 3)
29#define CGU0_STAT_CCBF0 (1 << 4)
30#define CGU0_STAT_CCBF1 (1 << 5)
31#define CGU0_STAT_SCBF0 (1 << 6)
32#define CGU0_STAT_SCBF1 (1 << 7)
33#define CGU0_STAT_DCBF (1 << 8)
34#define CGU0_STAT_OCBF (1 << 9)
35#define CGU0_STAT_ADDRERR (1 << 16)
36#define CGU0_STAT_LWERR (1 << 17)
37#define CGU0_STAT_DIVERR (1 << 18)
38#define CGU0_STAT_WDFMSERR (1 << 19)
39#define CGU0_STAT_WDIVERR (1 << 20)
40#define CGU0_STAT_PLOCKERR (1 << 21)
41
42#define CGU0_DIV_CSEL_SHIFT 0
43#define CGU0_DIV_CSEL_MASK 0x0000001F
44#define CGU0_DIV_S0SEL_SHIFT 5
45#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
46#define CGU0_DIV_SYSSEL_SHIFT 8
47#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
48#define CGU0_DIV_S1SEL_SHIFT 13
49#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
50#define CGU0_DIV_DSEL_SHIFT 16
51#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
52#define CGU0_DIV_OSEL_SHIFT 22
53#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
54
55#define CLK(_clk, _devname, _conname) \
56 { \
57 .clk = &_clk, \
58 .dev_id = _devname, \
59 .con_id = _conname, \
60 }
61
62#define NEEDS_INITIALIZATION 0x11
63
64static LIST_HEAD(clk_list);
65
66static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
67{
68 u32 val2;
69
70 val2 = bfin_read32(reg);
71 val2 &= ~mask;
72 val2 |= val;
73 bfin_write32(reg, val2);
74}
75
76static void clk_reg_set_bits(u32 reg, uint32_t mask)
77{
78 u32 val;
79
80 val = bfin_read32(reg);
81 val |= mask;
82 bfin_write32(reg, val);
83}
84
85static void clk_reg_clear_bits(u32 reg, uint32_t mask)
86{
87 u32 val;
88
89 val = bfin_read32(reg);
90 val &= ~mask;
91 bfin_write32(reg, val);
92}
93
94int wait_for_pll_align(void)
95{
96 int i = 10000;
97 while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
98
99 if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
100 printk(KERN_DEBUG "fail to align clk\n");
101 return -1;
102 }
103 return 0;
104}
105
106int clk_enable(struct clk *clk)
107{
108 int ret = -EIO;
109 if (clk->ops && clk->ops->enable)
110 ret = clk->ops->enable(clk);
111 return ret;
112}
113EXPORT_SYMBOL(clk_enable);
114
115void clk_disable(struct clk *clk)
116{
117 if (clk->ops && clk->ops->disable)
118 clk->ops->disable(clk);
119}
120EXPORT_SYMBOL(clk_disable);
121
122unsigned long clk_get_rate(struct clk *clk)
123{
124 unsigned long ret = 0;
125 if (clk->ops && clk->ops->get_rate)
126 ret = clk->ops->get_rate(clk);
127 return ret;
128}
129EXPORT_SYMBOL(clk_get_rate);
130
131long clk_round_rate(struct clk *clk, unsigned long rate)
132{
133 long ret = -EIO;
134 if (clk->ops && clk->ops->round_rate)
135 ret = clk->ops->round_rate(clk, rate);
136 return ret;
137}
138EXPORT_SYMBOL(clk_round_rate);
139
140int clk_set_rate(struct clk *clk, unsigned long rate)
141{
142 int ret = -EIO;
143 if (clk->ops && clk->ops->set_rate)
144 ret = clk->ops->set_rate(clk, rate);
145 return ret;
146}
147EXPORT_SYMBOL(clk_set_rate);
148
149unsigned long vco_get_rate(struct clk *clk)
150{
151 return clk->rate;
152}
153
154unsigned long pll_get_rate(struct clk *clk)
155{
156 u32 df;
157 u32 msel;
158 u32 ctl = bfin_read32(CGU0_CTL);
159 u32 stat = bfin_read32(CGU0_STAT);
160 if (stat & CGU0_STAT_PLLBP)
161 return 0;
162 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
163 df = (ctl & CGU0_CTL_DF);
164 clk->parent->rate = clk_get_rate(clk->parent);
165 return clk->parent->rate / (df + 1) * msel * 2;
166}
167
168unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
169{
170 u32 div;
171 div = rate / clk->parent->rate;
172 return clk->parent->rate * div;
173}
174
175int pll_set_rate(struct clk *clk, unsigned long rate)
176{
177 u32 msel;
178 u32 stat = bfin_read32(CGU0_STAT);
179 if (!(stat & CGU0_STAT_PLLEN))
180 return -EBUSY;
181 if (!(stat & CGU0_STAT_PLLLK))
182 return -EBUSY;
183 if (wait_for_pll_align())
184 return -EBUSY;
185 msel = rate / clk->parent->rate / 2;
186 clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
187 CGU0_CTL_MSEL_MASK);
188 clk->rate = rate;
189 return 0;
190}
191
192unsigned long cclk_get_rate(struct clk *clk)
193{
194 if (clk->parent)
195 return clk->parent->rate;
196 else
197 return 0;
198}
199
200unsigned long sys_clk_get_rate(struct clk *clk)
201{
202 unsigned long drate;
203 u32 msel;
204 u32 df;
205 u32 ctl = bfin_read32(CGU0_CTL);
206 u32 div = bfin_read32(CGU0_DIV);
207 div = (div & clk->mask) >> clk->shift;
208 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
209 df = (ctl & CGU0_CTL_DF);
210
211 if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
212 drate = clk->parent->rate / (df + 1);
213 drate *= msel;
214 drate /= div;
215 return drate;
216 } else {
217 clk->parent->rate = clk_get_rate(clk->parent);
218 return clk->parent->rate / div;
219 }
220}
221
222unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
223{
224 unsigned long max_rate;
225 unsigned long drate;
226 int i;
227 u32 msel;
228 u32 df;
229 u32 ctl = bfin_read32(CGU0_CTL);
230
231 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
232 df = (ctl & CGU0_CTL_DF);
233 max_rate = clk->parent->rate / (df + 1) * msel;
234
235 if (rate > max_rate)
236 return 0;
237
238 for (i = 1; i < clk->mask; i++) {
239 drate = max_rate / i;
240 if (rate >= drate)
241 return drate;
242 }
243 return 0;
244}
245
246int sys_clk_set_rate(struct clk *clk, unsigned long rate)
247{
248 u32 div = bfin_read32(CGU0_DIV);
249 div = (div & clk->mask) >> clk->shift;
250
251 rate = clk_round_rate(clk, rate);
252
253 if (!rate)
254 return -EINVAL;
255
256 div = (clk_get_rate(clk) * div) / rate;
257
258 if (wait_for_pll_align())
259 return -EBUSY;
260 clk_reg_write_mask(CGU0_DIV, div << clk->shift,
261 clk->mask);
262 clk->rate = rate;
263 return 0;
264}
265
266static struct clk_ops vco_ops = {
267 .get_rate = vco_get_rate,
268};
269
270static struct clk_ops pll_ops = {
271 .get_rate = pll_get_rate,
272 .set_rate = pll_set_rate,
273};
274
275static struct clk_ops cclk_ops = {
276 .get_rate = cclk_get_rate,
277};
278
279static struct clk_ops sys_clk_ops = {
280 .get_rate = sys_clk_get_rate,
281 .set_rate = sys_clk_set_rate,
282 .round_rate = sys_clk_round_rate,
283};
284
285static struct clk sys_clkin = {
286 .name = "SYS_CLKIN",
287 .rate = CONFIG_CLKIN_HZ,
288 .ops = &vco_ops,
289};
290
291static struct clk pll_clk = {
292 .name = "PLLCLK",
293 .rate = 500000000,
294 .parent = &sys_clkin,
295 .ops = &pll_ops,
296 .flags = NEEDS_INITIALIZATION,
297};
298
299static struct clk cclk = {
300 .name = "CCLK",
301 .rate = 500000000,
302 .mask = CGU0_DIV_CSEL_MASK,
303 .shift = CGU0_DIV_CSEL_SHIFT,
304 .parent = &sys_clkin,
305 .ops = &sys_clk_ops,
306 .flags = NEEDS_INITIALIZATION,
307};
308
309static struct clk cclk0 = {
310 .name = "CCLK0",
311 .parent = &cclk,
312 .ops = &cclk_ops,
313};
314
315static struct clk cclk1 = {
316 .name = "CCLK1",
317 .parent = &cclk,
318 .ops = &cclk_ops,
319};
320
321static struct clk sysclk = {
322 .name = "SYSCLK",
323 .rate = 500000000,
324 .mask = CGU0_DIV_SYSSEL_MASK,
325 .shift = CGU0_DIV_SYSSEL_SHIFT,
326 .parent = &sys_clkin,
327 .ops = &sys_clk_ops,
328 .flags = NEEDS_INITIALIZATION,
329};
330
331static struct clk sclk0 = {
332 .name = "SCLK0",
333 .rate = 500000000,
334 .mask = CGU0_DIV_S0SEL_MASK,
335 .shift = CGU0_DIV_S0SEL_SHIFT,
336 .parent = &sysclk,
337 .ops = &sys_clk_ops,
338};
339
340static struct clk sclk1 = {
341 .name = "SCLK1",
342 .rate = 500000000,
343 .mask = CGU0_DIV_S1SEL_MASK,
344 .shift = CGU0_DIV_S1SEL_SHIFT,
345 .parent = &sysclk,
346 .ops = &sys_clk_ops,
347};
348
349static struct clk dclk = {
350 .name = "DCLK",
351 .rate = 500000000,
352 .mask = CGU0_DIV_DSEL_MASK,
353 .shift = CGU0_DIV_DSEL_SHIFT,
354 .parent = &sys_clkin,
355 .ops = &sys_clk_ops,
356};
357
358static struct clk oclk = {
359 .name = "OCLK",
360 .rate = 500000000,
361 .mask = CGU0_DIV_OSEL_MASK,
362 .shift = CGU0_DIV_OSEL_SHIFT,
363 .parent = &pll_clk,
364};
365
366static struct clk_lookup bf609_clks[] = {
367 CLK(sys_clkin, NULL, "SYS_CLKIN"),
368 CLK(pll_clk, NULL, "PLLCLK"),
369 CLK(cclk, NULL, "CCLK"),
370 CLK(cclk0, NULL, "CCLK0"),
371 CLK(cclk1, NULL, "CCLK1"),
372 CLK(sysclk, NULL, "SYSCLK"),
373 CLK(sclk0, NULL, "SCLK0"),
374 CLK(sclk1, NULL, "SCLK1"),
375 CLK(dclk, NULL, "DCLK"),
376 CLK(oclk, NULL, "OCLK"),
377};
378
379int __init clk_init(void)
380{
381 int i;
382 struct clk *clkp;
383 for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
384 clkp = bf609_clks[i].clk;
385 if (clkp->flags & NEEDS_INITIALIZATION)
386 clk_get_rate(clkp);
387 }
388 clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
389 return 0;
390}
diff --git a/arch/blackfin/mach-bf609/dma.c b/arch/blackfin/mach-bf609/dma.c
new file mode 100644
index 000000000000..1da4b38ac22c
--- /dev/null
+++ b/arch/blackfin/mach-bf609/dma.c
@@ -0,0 +1,202 @@
1/*
2 * the simple DMA Implementation for Blackfin
3 *
4 * Copyright 2007-2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/module.h>
10
11#include <asm/blackfin.h>
12#include <asm/dma.h>
13
14struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
15 (struct dma_register *) DMA0_NEXT_DESC_PTR,
16 (struct dma_register *) DMA1_NEXT_DESC_PTR,
17 (struct dma_register *) DMA2_NEXT_DESC_PTR,
18 (struct dma_register *) DMA3_NEXT_DESC_PTR,
19 (struct dma_register *) DMA4_NEXT_DESC_PTR,
20 (struct dma_register *) DMA5_NEXT_DESC_PTR,
21 (struct dma_register *) DMA6_NEXT_DESC_PTR,
22 (struct dma_register *) DMA7_NEXT_DESC_PTR,
23 (struct dma_register *) DMA8_NEXT_DESC_PTR,
24 (struct dma_register *) DMA9_NEXT_DESC_PTR,
25 (struct dma_register *) DMA10_NEXT_DESC_PTR,
26 (struct dma_register *) DMA11_NEXT_DESC_PTR,
27 (struct dma_register *) DMA12_NEXT_DESC_PTR,
28 (struct dma_register *) DMA13_NEXT_DESC_PTR,
29 (struct dma_register *) DMA14_NEXT_DESC_PTR,
30 (struct dma_register *) DMA15_NEXT_DESC_PTR,
31 (struct dma_register *) DMA16_NEXT_DESC_PTR,
32 (struct dma_register *) DMA17_NEXT_DESC_PTR,
33 (struct dma_register *) DMA18_NEXT_DESC_PTR,
34 (struct dma_register *) DMA19_NEXT_DESC_PTR,
35 (struct dma_register *) DMA20_NEXT_DESC_PTR,
36 (struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR,
37 (struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR,
38 (struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR,
39 (struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR,
40 (struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR,
43 (struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR,
44 (struct dma_register *) DMA29_NEXT_DESC_PTR,
45 (struct dma_register *) DMA30_NEXT_DESC_PTR,
46 (struct dma_register *) DMA31_NEXT_DESC_PTR,
47 (struct dma_register *) DMA32_NEXT_DESC_PTR,
48 (struct dma_register *) DMA33_NEXT_DESC_PTR,
49 (struct dma_register *) DMA34_NEXT_DESC_PTR,
50 (struct dma_register *) DMA35_NEXT_DESC_PTR,
51 (struct dma_register *) DMA36_NEXT_DESC_PTR,
52 (struct dma_register *) DMA37_NEXT_DESC_PTR,
53 (struct dma_register *) DMA38_NEXT_DESC_PTR,
54 (struct dma_register *) DMA39_NEXT_DESC_PTR,
55 (struct dma_register *) DMA40_NEXT_DESC_PTR,
56 (struct dma_register *) DMA41_NEXT_DESC_PTR,
57 (struct dma_register *) DMA42_NEXT_DESC_PTR,
58 (struct dma_register *) DMA43_NEXT_DESC_PTR,
59 (struct dma_register *) DMA44_NEXT_DESC_PTR,
60 (struct dma_register *) DMA45_NEXT_DESC_PTR,
61 (struct dma_register *) DMA46_NEXT_DESC_PTR,
62};
63EXPORT_SYMBOL(dma_io_base_addr);
64
65int channel2irq(unsigned int channel)
66{
67 int ret_irq = -1;
68
69 switch (channel) {
70 case CH_SPORT0_RX:
71 ret_irq = IRQ_SPORT0_RX;
72 break;
73 case CH_SPORT0_TX:
74 ret_irq = IRQ_SPORT0_TX;
75 break;
76 case CH_SPORT1_RX:
77 ret_irq = IRQ_SPORT1_RX;
78 break;
79 case CH_SPORT1_TX:
80 ret_irq = IRQ_SPORT1_TX;
81 break;
82 case CH_SPORT2_RX:
83 ret_irq = IRQ_SPORT2_RX;
84 break;
85 case CH_SPORT2_TX:
86 ret_irq = IRQ_SPORT2_TX;
87 break;
88 case CH_SPI0_TX:
89 ret_irq = IRQ_SPI0_TX;
90 break;
91 case CH_SPI0_RX:
92 ret_irq = IRQ_SPI0_RX;
93 break;
94 case CH_SPI1_TX:
95 ret_irq = IRQ_SPI1_TX;
96 break;
97 case CH_SPI1_RX:
98 ret_irq = IRQ_SPI1_RX;
99 break;
100 case CH_RSI:
101 ret_irq = IRQ_RSI;
102 break;
103 case CH_SDU:
104 ret_irq = IRQ_SDU;
105 break;
106 case CH_LP0:
107 ret_irq = IRQ_LP0;
108 break;
109 case CH_LP1:
110 ret_irq = IRQ_LP1;
111 break;
112 case CH_LP2:
113 ret_irq = IRQ_LP2;
114 break;
115 case CH_LP3:
116 ret_irq = IRQ_LP3;
117 break;
118 case CH_UART0_RX:
119 ret_irq = IRQ_UART0_RX;
120 break;
121 case CH_UART0_TX:
122 ret_irq = IRQ_UART0_TX;
123 break;
124 case CH_UART1_RX:
125 ret_irq = IRQ_UART1_RX;
126 break;
127 case CH_UART1_TX:
128 ret_irq = IRQ_UART1_TX;
129 break;
130 case CH_EPPI0_CH0:
131 ret_irq = IRQ_EPPI0_CH0;
132 break;
133 case CH_EPPI0_CH1:
134 ret_irq = IRQ_EPPI0_CH1;
135 break;
136 case CH_EPPI1_CH0:
137 ret_irq = IRQ_EPPI1_CH0;
138 break;
139 case CH_EPPI1_CH1:
140 ret_irq = IRQ_EPPI1_CH1;
141 break;
142 case CH_EPPI2_CH0:
143 ret_irq = IRQ_EPPI2_CH0;
144 break;
145 case CH_EPPI2_CH1:
146 ret_irq = IRQ_EPPI2_CH1;
147 break;
148 case CH_PIXC_CH0:
149 ret_irq = IRQ_PIXC_CH0;
150 break;
151 case CH_PIXC_CH1:
152 ret_irq = IRQ_PIXC_CH1;
153 break;
154 case CH_PIXC_CH2:
155 ret_irq = IRQ_PIXC_CH2;
156 break;
157 case CH_PVP_CPDOB:
158 ret_irq = IRQ_PVP_CPDOB;
159 break;
160 case CH_PVP_CPDOC:
161 ret_irq = IRQ_PVP_CPDOC;
162 break;
163 case CH_PVP_CPSTAT:
164 ret_irq = IRQ_PVP_CPSTAT;
165 break;
166 case CH_PVP_CPCI:
167 ret_irq = IRQ_PVP_CPCI;
168 break;
169 case CH_PVP_MPDO:
170 ret_irq = IRQ_PVP_MPDO;
171 break;
172 case CH_PVP_MPDI:
173 ret_irq = IRQ_PVP_MPDI;
174 break;
175 case CH_PVP_MPSTAT:
176 ret_irq = IRQ_PVP_MPSTAT;
177 break;
178 case CH_PVP_MPCI:
179 ret_irq = IRQ_PVP_MPCI;
180 break;
181 case CH_PVP_CPDOA:
182 ret_irq = IRQ_PVP_CPDOA;
183 break;
184 case CH_MEM_STREAM0_SRC:
185 case CH_MEM_STREAM0_DEST:
186 ret_irq = IRQ_MDMAS0;
187 break;
188 case CH_MEM_STREAM1_SRC:
189 case CH_MEM_STREAM1_DEST:
190 ret_irq = IRQ_MDMAS1;
191 break;
192 case CH_MEM_STREAM2_SRC:
193 case CH_MEM_STREAM2_DEST:
194 ret_irq = IRQ_MDMAS2;
195 break;
196 case CH_MEM_STREAM3_SRC:
197 case CH_MEM_STREAM3_DEST:
198 ret_irq = IRQ_MDMAS3;
199 break;
200 }
201 return ret_irq;
202}
diff --git a/arch/blackfin/mach-bf609/hibernate.S b/arch/blackfin/mach-bf609/hibernate.S
new file mode 100644
index 000000000000..d37a532519c8
--- /dev/null
+++ b/arch/blackfin/mach-bf609/hibernate.S
@@ -0,0 +1,65 @@
1#include <linux/linkage.h>
2#include <asm/blackfin.h>
3#include <asm/dpmc.h>
4
5#define PM_STACK (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
6
7.section .l1.text
8ENTRY(_enter_hibernate)
9 /* switch stack to L1 scratch, prepare for ddr srfr */
10 P0.H = HI(PM_STACK);
11 P0.L = LO(PM_STACK);
12 SP = P0;
13
14 call _bf609_ddr_sr;
15 call _bfin_hibernate_syscontrol;
16
17 P0.H = HI(DPM0_RESTORE4);
18 P0.L = LO(DPM0_RESTORE4);
19 P1.H = _bf609_pm_data;
20 P1.L = _bf609_pm_data;
21 [P0] = P1;
22
23 P0.H = HI(DPM0_CTL);
24 P0.L = LO(DPM0_CTL);
25 R3.H = HI(0x00000010);
26 R3.L = LO(0x00000010);
27
28 bfin_init_pm_bench_cycles;
29
30 [P0] = R3;
31
32 SSYNC;
33ENDPROC(_enter_hibernate_mode)
34
35.section .text
36ENTRY(_bf609_hibernate)
37 bfin_cpu_reg_save;
38 bfin_core_mmr_save;
39
40 P0.H = _bf609_pm_data;
41 P0.L = _bf609_pm_data;
42 R1.H = 0xDEAD;
43 R1.L = 0xBEEF;
44 R2.H = .Lpm_resume_here;
45 R2.L = .Lpm_resume_here;
46 [P0++] = R1;
47 [P0++] = R2;
48 [P0++] = SP;
49
50 P1.H = _enter_hibernate;
51 P1.L = _enter_hibernate;
52
53 call (P1);
54.Lpm_resume_here:
55
56 bfin_core_mmr_restore;
57 bfin_cpu_reg_restore;
58
59 [--sp] = RETI; /* Clear Global Interrupt Disable */
60 SP += 4;
61
62 RTS;
63
64ENDPROC(_bf609_hibernate)
65
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
new file mode 100644
index 000000000000..bdd39aefb565
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h
@@ -0,0 +1,130 @@
1/*
2 * DO NOT EDIT THIS FILE
3 * This file is under version control at
4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE
7 *
8 * Copyright 2004-2011 Analog Devices Inc.
9 * Licensed under the Clear BSD license.
10 */
11
12/* This file should be up to date with:
13 */
14
15#if __SILICON_REVISION__ < 0
16# error will not work on BF506 silicon version
17#endif
18
19#ifndef _MACH_ANOMALY_H_
20#define _MACH_ANOMALY_H_
21
22/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
23#define ANOMALY_05000074 (1)
24/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
25#define ANOMALY_05000119 (1)
26/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
27#define ANOMALY_05000122 (1)
28/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
29#define ANOMALY_05000245 (1)
30/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
31#define ANOMALY_05000254 (1)
32/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
33#define ANOMALY_05000265 (1)
34/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
35#define ANOMALY_05000310 (1)
36/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
37#define ANOMALY_05000366 (1)
38/* Speculative Fetches Can Cause Undesired External FIFO Operations */
39#define ANOMALY_05000416 (1)
40/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
41#define ANOMALY_05000426 (1)
42/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
43#define ANOMALY_05000443 (1)
44/* UART IrDA Receiver Fails on Extended Bit Pulses */
45#define ANOMALY_05000447 (1)
46/* False Hardware Error when RETI Points to Invalid Memory */
47#define ANOMALY_05000461 (1)
48/* PLL Latches Incorrect Settings During Reset */
49#define ANOMALY_05000469 (1)
50/* Incorrect Default MSEL Value in PLL_CTL */
51#define ANOMALY_05000472 (1)
52/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
53#define ANOMALY_05000473 (1)
54/* TESTSET Instruction Cannot Be Interrupted */
55#define ANOMALY_05000477 (1)
56/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
57#define ANOMALY_05000481 (1)
58/* IFLUSH sucks at life */
59#define ANOMALY_05000491 (1)
60/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */
61#define ANOMALY_05001001 (__SILICON_REVISION__ < 1)
62
63/* Anomalies that don't exist on this proc */
64#define ANOMALY_05000099 (0)
65#define ANOMALY_05000120 (0)
66#define ANOMALY_05000125 (0)
67#define ANOMALY_05000149 (0)
68#define ANOMALY_05000158 (0)
69#define ANOMALY_05000171 (0)
70#define ANOMALY_05000179 (0)
71#define ANOMALY_05000182 (0)
72#define ANOMALY_05000183 (0)
73#define ANOMALY_05000189 (0)
74#define ANOMALY_05000198 (0)
75#define ANOMALY_05000202 (0)
76#define ANOMALY_05000215 (0)
77#define ANOMALY_05000219 (0)
78#define ANOMALY_05000220 (0)
79#define ANOMALY_05000227 (0)
80#define ANOMALY_05000230 (0)
81#define ANOMALY_05000231 (0)
82#define ANOMALY_05000233 (0)
83#define ANOMALY_05000234 (0)
84#define ANOMALY_05000242 (0)
85#define ANOMALY_05000244 (0)
86#define ANOMALY_05000248 (0)
87#define ANOMALY_05000250 (0)
88#define ANOMALY_05000257 (0)
89#define ANOMALY_05000261 (0)
90#define ANOMALY_05000263 (0)
91#define ANOMALY_05000266 (0)
92#define ANOMALY_05000273 (0)
93#define ANOMALY_05000274 (0)
94#define ANOMALY_05000278 (0)
95#define ANOMALY_05000281 (0)
96#define ANOMALY_05000283 (0)
97#define ANOMALY_05000285 (0)
98#define ANOMALY_05000287 (0)
99#define ANOMALY_05000301 (0)
100#define ANOMALY_05000305 (0)
101#define ANOMALY_05000307 (0)
102#define ANOMALY_05000311 (0)
103#define ANOMALY_05000312 (0)
104#define ANOMALY_05000315 (0)
105#define ANOMALY_05000323 (0)
106#define ANOMALY_05000353 (1)
107#define ANOMALY_05000357 (0)
108#define ANOMALY_05000362 (1)
109#define ANOMALY_05000363 (0)
110#define ANOMALY_05000364 (0)
111#define ANOMALY_05000371 (0)
112#define ANOMALY_05000380 (0)
113#define ANOMALY_05000386 (0)
114#define ANOMALY_05000389 (0)
115#define ANOMALY_05000400 (0)
116#define ANOMALY_05000402 (0)
117#define ANOMALY_05000412 (0)
118#define ANOMALY_05000432 (0)
119#define ANOMALY_05000440 (0)
120#define ANOMALY_05000448 (0)
121#define ANOMALY_05000456 (0)
122#define ANOMALY_05000450 (0)
123#define ANOMALY_05000465 (0)
124#define ANOMALY_05000467 (0)
125#define ANOMALY_05000474 (0)
126#define ANOMALY_05000475 (0)
127#define ANOMALY_05000480 (0)
128#define ANOMALY_05000485 (0)
129
130#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/bf609.h b/arch/blackfin/mach-bf609/include/mach/bf609.h
new file mode 100644
index 000000000000..c897c2a2fbfa
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/bf609.h
@@ -0,0 +1,93 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef __MACH_BF609_H__
8#define __MACH_BF609_H__
9
10#define OFFSET_(x) ((x) & 0x0000FFFF)
11
12/*some misc defines*/
13#define IMASK_IVG15 0x8000
14#define IMASK_IVG14 0x4000
15#define IMASK_IVG13 0x2000
16#define IMASK_IVG12 0x1000
17
18#define IMASK_IVG11 0x0800
19#define IMASK_IVG10 0x0400
20#define IMASK_IVG9 0x0200
21#define IMASK_IVG8 0x0100
22
23#define IMASK_IVG7 0x0080
24#define IMASK_IVGTMR 0x0040
25#define IMASK_IVGHW 0x0020
26
27/***************************/
28
29
30#define BFIN_DSUBBANKS 4
31#define BFIN_DWAYS 2
32#define BFIN_DLINES 64
33#define BFIN_ISUBBANKS 4
34#define BFIN_IWAYS 4
35#define BFIN_ILINES 32
36
37#define WAY0_L 0x1
38#define WAY1_L 0x2
39#define WAY01_L 0x3
40#define WAY2_L 0x4
41#define WAY02_L 0x5
42#define WAY12_L 0x6
43#define WAY012_L 0x7
44
45#define WAY3_L 0x8
46#define WAY03_L 0x9
47#define WAY13_L 0xA
48#define WAY013_L 0xB
49
50#define WAY32_L 0xC
51#define WAY320_L 0xD
52#define WAY321_L 0xE
53#define WAYALL_L 0xF
54
55#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
56
57/********************************* EBIU Settings ************************************/
58#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
59#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
60
61#ifdef CONFIG_C_AMBEN_ALL
62#define V_AMBEN AMBEN_ALL
63#endif
64#ifdef CONFIG_C_AMBEN
65#define V_AMBEN 0x0
66#endif
67#ifdef CONFIG_C_AMBEN_B0
68#define V_AMBEN AMBEN_B0
69#endif
70#ifdef CONFIG_C_AMBEN_B0_B1
71#define V_AMBEN AMBEN_B0_B1
72#endif
73#ifdef CONFIG_C_AMBEN_B0_B1_B2
74#define V_AMBEN AMBEN_B0_B1_B2
75#endif
76#ifdef CONFIG_C_AMCKEN
77#define V_AMCKEN AMCKEN
78#else
79#define V_AMCKEN 0x0
80#endif
81
82#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
83
84#if defined(CONFIG_BF609)
85# define CPU "BF609"
86# define CPUID 0x27fe /* temperary fake value */
87#endif
88
89#ifndef CPU
90#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
91#endif
92
93#endif /* __MACH_BF609_H__ */
diff --git a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..1fd398147fd9
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
@@ -0,0 +1,17 @@
1/*
2 * mach/bfin_serial.h - Blackfin UART/Serial definitions
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_MACH_SERIAL_H__
10#define __BFIN_MACH_SERIAL_H__
11
12#define BFIN_UART_NR_PORTS 2
13#define BFIN_UART_TX_FIFO_SIZE 8
14
15#define BFIN_UART_BF60X_STYLE
16
17#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/blackfin.h b/arch/blackfin/mach-bf609/include/mach/blackfin.h
new file mode 100644
index 000000000000..b1a48c410711
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/blackfin.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _MACH_BLACKFIN_H_
8#define _MACH_BLACKFIN_H_
9
10#include "bf609.h"
11#include "anomaly.h"
12
13#include <asm/def_LPBlackfin.h>
14#ifdef CONFIG_BF609
15# include "defBF609.h"
16#endif
17
18#ifndef __ASSEMBLY__
19# include <asm/cdef_LPBlackfin.h>
20# ifdef CONFIG_BF609
21# include "cdefBF609.h"
22# endif
23#endif
24
25#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
new file mode 100644
index 000000000000..c4f3fe19acda
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _CDEF_BF609_H
8#define _CDEF_BF609_H
9
10/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */
11#include "cdefBF60x_base.h"
12
13/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
14
15#endif /* _CDEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
new file mode 100644
index 000000000000..4954cf3f7e16
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
@@ -0,0 +1,3252 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _CDEF_BF60X_H
8#define _CDEF_BF60X_H
9
10/* ************************************************************** */
11/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
12/* ************************************************************** */
13
14/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
15
16#define bfin_read_CHIPID() bfin_read32(CHIPID)
17#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
18
19/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
20
21/* SEC0 Registers */
22#define bfin_read_SEC0_CCTL() bfin_read32(SEC0_CCTL)
23#define bfin_write_SEC0_CCTL(val) bfin_write32(SEC0_CCTL, val)
24#define bfin_read_SEC0_CSID() bfin_read32(SEC0_CSID)
25#define bfin_write_SEC0_CSID(val) bfin_write32(SEC0_CSID, val)
26#define bfin_read_SEC_GCTL() bfin_read32(SEC_GCTL)
27#define bfin_write_SEC_GCTL(val) bfin_write32(SEC_GCTL, val)
28
29#define bfin_read_SEC_FCTL() bfin_read32(SEC_FCTL)
30#define bfin_write_SEC_FCTL(val) bfin_write32(SEC_FCTL, val)
31
32#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC_SCTL0 + (sid) * 8))
33#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC_SCTL0 + (sid) * 8), val)
34
35#define bfin_read_SEC_SSTAT(sid) bfin_read32((SEC_SSTAT0 + (sid) * 8))
36#define bfin_write_SEC_SSTAT(sid, val) bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
37
38/* RCU0 Registers */
39#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
40#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
41
42/* Watchdog Timer Registers */
43#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
44#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
45#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
46#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
47#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
48#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
49
50/* RTC Registers */
51
52/* UART0 Registers */
53
54#define bfin_read_UART0_REVID() bfin_read32(UART0_REVID)
55#define bfin_write_UART0_REVID(val) bfin_write32(UART0_REVID, val)
56#define bfin_read_UART0_GCTL() bfin_read32(UART0_GCTL)
57#define bfin_write_UART0_GCTL(val) bfin_write32(UART0_GCTL, val)
58#define bfin_read_UART0_STAT() bfin_read32(UART0_STAT)
59#define bfin_write_UART0_STAT(val) bfin_write32(UART0_STAT, val)
60#define bfin_read_UART0_SCR() bfin_read32(UART0_SCR)
61#define bfin_write_UART0_SCR(val) bfin_write32(UART0_SCR, val)
62#define bfin_read_UART0_CLK() bfin_read32(UART0_CLK)
63#define bfin_write_UART0_CLK(val) bfin_write32(UART0_CLK, val)
64#define bfin_read_UART0_IER() bfin_read32(UART0_IER)
65#define bfin_write_UART0_IER(val) bfin_write32(UART0_IER, val)
66#define bfin_read_UART0_IER_SET() bfin_read32(UART0_IER_SET)
67#define bfin_write_UART0_IER_SET(val) bfin_write32(UART0_IER_SET, val)
68#define bfin_read_UART0_IER_CLEAR() bfin_read32(UART0_IER_CLEAR)
69#define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val)
70#define bfin_read_UART0_RBR() bfin_read32(UART0_RBR)
71#define bfin_write_UART0_RBR(val) bfin_write32(UART0_RBR, val)
72#define bfin_read_UART0_THR() bfin_read32(UART0_THR)
73#define bfin_write_UART0_THR(val) bfin_write32(UART0_THR, val)
74#define bfin_read_UART0_TAIP() bfin_read32(UART0_TAIP)
75#define bfin_write_UART0_TAIP(val) bfin_write32(UART0_TAIP, val)
76#define bfin_read_UART0_TSR() bfin_read32(UART0_TSR)
77#define bfin_write_UART0_TSR(val) bfin_write32(UART0_TSR, val)
78#define bfin_read_UART0_RSR() bfin_read32(UART0_RSR)
79#define bfin_write_UART0_RSR(val) bfin_write32(UART0_RSR, val)
80#define bfin_read_UART0_TXCNT() bfin_read32(UART0_TXCNT)
81#define bfin_write_UART0_TXCNT(val) bfin_write32(UART0_TXCNT, val)
82#define bfin_read_UART0_RXCNT() bfin_read32(UART0_RXCNT)
83#define bfin_write_UART0_RXCNT(val) bfin_write32(UART0_RXCNT, val)
84
85/* UART1 Registers */
86
87#define bfin_read_UART1_REVID() bfin_read32(UART1_REVID)
88#define bfin_write_UART1_REVID(val) bfin_write32(UART1_REVID, val)
89#define bfin_read_UART1_GCTL() bfin_read32(UART1_GCTL)
90#define bfin_write_UART1_GCTL(val) bfin_write32(UART1_GCTL, val)
91#define bfin_read_UART1_STAT() bfin_read32(UART1_STAT)
92#define bfin_write_UART1_STAT(val) bfin_write32(UART1_STAT, val)
93#define bfin_read_UART1_SCR() bfin_read32(UART1_SCR)
94#define bfin_write_UART1_SCR(val) bfin_write32(UART1_SCR, val)
95#define bfin_read_UART1_CLK() bfin_read32(UART1_CLK)
96#define bfin_write_UART1_CLK(val) bfin_write32(UART1_CLK, val)
97#define bfin_read_UART1_IER() bfin_read32(UART1_IER)
98#define bfin_write_UART1_IER(val) bfin_write32(UART1_IER, val)
99#define bfin_read_UART1_IER_SET() bfin_read32(UART1_IER_SET)
100#define bfin_write_UART1_IER_SET(val) bfin_write32(UART1_IER_SET, val)
101#define bfin_read_UART1_IER_CLEAR() bfin_read32(UART1_IER_CLEAR)
102#define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val)
103#define bfin_read_UART1_RBR() bfin_read32(UART1_RBR)
104#define bfin_write_UART1_RBR(val) bfin_write32(UART1_RBR, val)
105#define bfin_read_UART1_THR() bfin_read32(UART1_THR)
106#define bfin_write_UART1_THR(val) bfin_write32(UART1_THR, val)
107#define bfin_read_UART1_TAIP() bfin_read32(UART1_TAIP)
108#define bfin_write_UART1_TAIP(val) bfin_write32(UART1_TAIP, val)
109#define bfin_read_UART1_TSR() bfin_read32(UART1_TSR)
110#define bfin_write_UART1_TSR(val) bfin_write32(UART1_TSR, val)
111#define bfin_read_UART1_RSR() bfin_read32(UART1_RSR)
112#define bfin_write_UART1_RSR(val) bfin_write32(UART1_RSR, val)
113#define bfin_read_UART1_TXCNT() bfin_read32(UART1_TXCNT)
114#define bfin_write_UART1_TXCNT(val) bfin_write32(UART1_TXCNT, val)
115#define bfin_read_UART1_RXCNT() bfin_read32(UART1_RXCNT)
116#define bfin_write_UART1_RXCNT(val) bfin_write32(UART1_RXCNT, val)
117
118
119/* SPI0 Registers */
120
121#define bfin_read_SPI0_CTL() bfin_read32(SPI0_CTL)
122#define bfin_write_SPI0_CTL(val) bfin_write32(SPI0_CTL, val)
123#define bfin_read_SPI0_RXCTL() bfin_read32(SPI0_RXCTL)
124#define bfin_write_SPI0_RXCTL(val) bfin_write32(SPI0_RXCTL, val)
125#define bfin_read_SPI0_TXCTL() bfin_read32(SPI0_TXCTL)
126#define bfin_write_SPI0_TXCTL(val) bfin_write32(SPI0_TXCTL, val)
127#define bfin_read_SPI0_CLK() bfin_read32(SPI0_CLK)
128#define bfin_write_SPI0_CLK(val) bfin_write32(SPI0_CLK, val)
129#define bfin_read_SPI0_DLY() bfin_read32(SPI0_DLY)
130#define bfin_write_SPI0_DLY(val) bfin_write32(SPI0_DLY, val)
131#define bfin_read_SPI0_SLVSEL() bfin_read32(SPI0_SLVSEL)
132#define bfin_write_SPI0_SLVSEL(val) bfin_write32(SPI0_SLVSEL, val)
133#define bfin_read_SPI0_RWC() bfin_read32(SPI0_RWC)
134#define bfin_write_SPI0_RWC(val) bfin_write32(SPI0_RWC, val)
135#define bfin_read_SPI0_RWCR() bfin_read32(SPI0_RWCR)
136#define bfin_write_SPI0_RWCR(val) bfin_write32(SPI0_RWCR, val)
137#define bfin_read_SPI0_TWC() bfin_read32(SPI0_TWC)
138#define bfin_write_SPI0_TWC(val) bfin_write32(SPI0_TWC, val)
139#define bfin_read_SPI0_TWCR() bfin_read32(SPI0_TWCR)
140#define bfin_write_SPI0_TWCR(val) bfin_write32(SPI0_TWCR, val)
141#define bfin_read_SPI0_IMSK() bfin_read32(SPI0_IMSK)
142#define bfin_write_SPI0_IMSK(val) bfin_write32(SPI0_IMSK, val)
143#define bfin_read_SPI0_IMSK_CLR() bfin_read32(SPI0_IMSK_CLR)
144#define bfin_write_SPI0_IMSK_CLR(val) bfin_write32(SPI0_IMSK_CLR, val)
145#define bfin_read_SPI0_IMSK_SET() bfin_read32(SPI0_IMSK_SET)
146#define bfin_write_SPI0_IMSK_SET(val) bfin_write32(SPI0_IMSK_SET, val)
147#define bfin_read_SPI0_STAT() bfin_read32(SPI0_STAT)
148#define bfin_write_SPI0_STAT(val) bfin_write32(SPI0_STAT, val)
149#define bfin_read_SPI0_ILAT() bfin_read32(SPI0_ILAT)
150#define bfin_write_SPI0_ILAT(val) bfin_write32(SPI0_ILAT, val)
151#define bfin_read_SPI0_ILAT_CLR() bfin_read32(SPI0_ILAT_CLR)
152#define bfin_write_SPI0_ILAT_CLR(val) bfin_write32(SPI0_ILAT_CLR, val)
153#define bfin_read_SPI0_RFIFO() bfin_read32(SPI0_RFIFO)
154#define bfin_write_SPI0_RFIFO(val) bfin_write32(SPI0_RFIFO, val)
155#define bfin_read_SPI0_TFIFO() bfin_read32(SPI0_TFIFO)
156#define bfin_write_SPI0_TFIFO(val) bfin_write32(SPI0_TFIFO, val)
157
158/* SPI1 Registers */
159
160#define bfin_read_SPI1_CTL() bfin_read32(SPI1_CTL)
161#define bfin_write_SPI1_CTL(val) bfin_write32(SPI1_CTL, val)
162#define bfin_read_SPI1_RXCTL() bfin_read32(SPI1_RXCTL)
163#define bfin_write_SPI1_RXCTL(val) bfin_write32(SPI1_RXCTL, val)
164#define bfin_read_SPI1_TXCTL() bfin_read32(SPI1_TXCTL)
165#define bfin_write_SPI1_TXCTL(val) bfin_write32(SPI1_TXCTL, val)
166#define bfin_read_SPI1_CLK() bfin_read32(SPI1_CLK)
167#define bfin_write_SPI1_CLK(val) bfin_write32(SPI1_CLK, val)
168#define bfin_read_SPI1_DLY() bfin_read32(SPI1_DLY)
169#define bfin_write_SPI1_DLY(val) bfin_write32(SPI1_DLY, val)
170#define bfin_read_SPI1_SLVSEL() bfin_read32(SPI1_SLVSEL)
171#define bfin_write_SPI1_SLVSEL(val) bfin_write32(SPI1_SLVSEL, val)
172#define bfin_read_SPI1_RWC() bfin_read32(SPI1_RWC)
173#define bfin_write_SPI1_RWC(val) bfin_write32(SPI1_RWC, val)
174#define bfin_read_SPI1_RWCR() bfin_read32(SPI1_RWCR)
175#define bfin_write_SPI1_RWCR(val) bfin_write32(SPI1_RWCR, val)
176#define bfin_read_SPI1_TWC() bfin_read32(SPI1_TWC)
177#define bfin_write_SPI1_TWC(val) bfin_write32(SPI1_TWC, val)
178#define bfin_read_SPI1_TWCR() bfin_read32(SPI1_TWCR)
179#define bfin_write_SPI1_TWCR(val) bfin_write32(SPI1_TWCR, val)
180#define bfin_read_SPI1_IMSK() bfin_read32(SPI1_IMSK)
181#define bfin_write_SPI1_IMSK(val) bfin_write32(SPI1_IMSK, val)
182#define bfin_read_SPI1_IMSK_CLR() bfin_read32(SPI1_IMSK_CLR)
183#define bfin_write_SPI1_IMSK_CLR(val) bfin_write32(SPI1_IMSK_CLR, val)
184#define bfin_read_SPI1_IMSK_SET() bfin_read32(SPI1_IMSK_SET)
185#define bfin_write_SPI1_IMSK_SET(val) bfin_write32(SPI1_IMSK_SET, val)
186#define bfin_read_SPI1_STAT() bfin_read32(SPI1_STAT)
187#define bfin_write_SPI1_STAT(val) bfin_write32(SPI1_STAT, val)
188#define bfin_read_SPI1_ILAT() bfin_read32(SPI1_ILAT)
189#define bfin_write_SPI1_ILAT(val) bfin_write32(SPI1_ILAT, val)
190#define bfin_read_SPI1_ILAT_CLR() bfin_read32(SPI1_ILAT_CLR)
191#define bfin_write_SPI1_ILAT_CLR(val) bfin_write32(SPI1_ILAT_CLR, val)
192#define bfin_read_SPI1_RFIFO() bfin_read32(SPI1_RFIFO)
193#define bfin_write_SPI1_RFIFO(val) bfin_write32(SPI1_RFIFO, val)
194#define bfin_read_SPI1_TFIFO() bfin_read32(SPI1_TFIFO)
195#define bfin_write_SPI1_TFIFO(val) bfin_write32(SPI1_TFIFO, val)
196
197/* Timer 0-7 registers */
198#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
199#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
200#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
201#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
202#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
203#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
204#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
205#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
206#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
207#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
208#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
209#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
210#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
211#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
212#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
213#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
214#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
215#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
216#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
217#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
218#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
219#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
220#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
221#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
222#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
223#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
224#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
225#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
226#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
227#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
228#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
229#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
230#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
231#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
232#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
233#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
234#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
235#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
236#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
237#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
238#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
239#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
240#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
241#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
242#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
243#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
244#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
245#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
246#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
247#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
248#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
249#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
250#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
251#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
252#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
253#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
254#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
255#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
256#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
257#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
258#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
259#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
260#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
261#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
262
263
264
265
266/* Two Wire Interface Registers (TWI0) */
267
268/* SPORT1 Registers */
269
270
271/* SMC Registers */
272#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
273#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
274#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
275#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
276#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
277#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
278#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
279#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
280#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
281#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
282#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
283#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
284#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
285#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
286#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
287#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
288#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
289#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
290#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
291#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
292#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
293#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
294#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
295#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
296#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
297#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
298#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
299
300/* DDR2 Memory Control Registers */
301#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
302#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
303#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
304#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
305#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
306#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
307#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
308#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
309#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
310#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
311#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
312#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
313#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
314#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
315#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
316#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
317#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
318#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
319
320/* DDR BankRead and Write Count Registers */
321
322
323/* DMA Channel 0 Registers */
324
325#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
326#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
327#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
328#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
329#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CONFIG)
330#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CONFIG, val)
331#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_X_COUNT)
332#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_X_COUNT, val)
333#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_X_MODIFY)
334#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_X_MODIFY, val)
335#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_Y_COUNT)
336#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_Y_COUNT, val)
337#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_Y_MODIFY)
338#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_Y_MODIFY, val)
339#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
340#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
341#define bfin_read_DMA0_PREV_DESC_PTR() bfin_read32(DMA0_PREV_DESC_PTR)
342#define bfin_write_DMA0_PREV_DESC_PTR(val) bfin_write32(DMA0_PREV_DESC_PTR, val)
343#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
344#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
345#define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_IRQ_STATUS)
346#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_IRQ_STATUS, val)
347#define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_CURR_X_COUNT)
348#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_CURR_X_COUNT, val)
349#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_CURR_Y_COUNT)
350#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_CURR_Y_COUNT, val)
351#define bfin_read_DMA0_BWL_COUNT() bfin_read32(DMA0_BWL_COUNT)
352#define bfin_write_DMA0_BWL_COUNT(val) bfin_write32(DMA0_BWL_COUNT, val)
353#define bfin_read_DMA0_CURR_BWL_COUNT() bfin_read32(DMA0_CURR_BWL_COUNT)
354#define bfin_write_DMA0_CURR_BWL_COUNT(val) bfin_write32(DMA0_CURR_BWL_COUNT, val)
355#define bfin_read_DMA0_BWM_COUNT() bfin_read32(DMA0_BWM_COUNT)
356#define bfin_write_DMA0_BWM_COUNT(val) bfin_write32(DMA0_BWM_COUNT, val)
357#define bfin_read_DMA0_CURR_BWM_COUNT() bfin_read32(DMA0_CURR_BWM_COUNT)
358#define bfin_write_DMA0_CURR_BWM_COUNT(val) bfin_write32(DMA0_CURR_BWM_COUNT, val)
359
360/* DMA Channel 1 Registers */
361
362#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
363#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
364#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
365#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
366#define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CONFIG)
367#define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CONFIG, val)
368#define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_X_COUNT)
369#define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_X_COUNT, val)
370#define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_X_MODIFY)
371#define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_X_MODIFY, val)
372#define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_Y_COUNT)
373#define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_Y_COUNT, val)
374#define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_Y_MODIFY)
375#define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_Y_MODIFY, val)
376#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
377#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
378#define bfin_read_DMA1_PREV_DESC_PTR() bfin_read32(DMA1_PREV_DESC_PTR)
379#define bfin_write_DMA1_PREV_DESC_PTR(val) bfin_write32(DMA1_PREV_DESC_PTR, val)
380#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
381#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
382#define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_IRQ_STATUS)
383#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_IRQ_STATUS, val)
384#define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_CURR_X_COUNT)
385#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_CURR_X_COUNT, val)
386#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_CURR_Y_COUNT)
387#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_CURR_Y_COUNT, val)
388#define bfin_read_DMA1_BWL_COUNT() bfin_read32(DMA1_BWL_COUNT)
389#define bfin_write_DMA1_BWL_COUNT(val) bfin_write32(DMA1_BWL_COUNT, val)
390#define bfin_read_DMA1_CURR_BWL_COUNT() bfin_read32(DMA1_CURR_BWL_COUNT)
391#define bfin_write_DMA1_CURR_BWL_COUNT(val) bfin_write32(DMA1_CURR_BWL_COUNT, val)
392#define bfin_read_DMA1_BWM_COUNT() bfin_read32(DMA1_BWM_COUNT)
393#define bfin_write_DMA1_BWM_COUNT(val) bfin_write32(DMA1_BWM_COUNT, val)
394#define bfin_read_DMA1_CURR_BWM_COUNT() bfin_read32(DMA1_CURR_BWM_COUNT)
395#define bfin_write_DMA1_CURR_BWM_COUNT(val) bfin_write32(DMA1_CURR_BWM_COUNT, val)
396
397/* DMA Channel 2 Registers */
398
399#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
400#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
401#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
402#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
403#define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CONFIG)
404#define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CONFIG, val)
405#define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_X_COUNT)
406#define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_X_COUNT, val)
407#define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_X_MODIFY)
408#define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_X_MODIFY, val)
409#define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_Y_COUNT)
410#define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_Y_COUNT, val)
411#define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_Y_MODIFY)
412#define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_Y_MODIFY, val)
413#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
414#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
415#define bfin_read_DMA2_PREV_DESC_PTR() bfin_read32(DMA2_PREV_DESC_PTR)
416#define bfin_write_DMA2_PREV_DESC_PTR(val) bfin_write32(DMA2_PREV_DESC_PTR, val)
417#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
418#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
419#define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_IRQ_STATUS)
420#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_IRQ_STATUS, val)
421#define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_CURR_X_COUNT)
422#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_CURR_X_COUNT, val)
423#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_CURR_Y_COUNT)
424#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_CURR_Y_COUNT, val)
425#define bfin_read_DMA2_BWL_COUNT() bfin_read32(DMA2_BWL_COUNT)
426#define bfin_write_DMA2_BWL_COUNT(val) bfin_write32(DMA2_BWL_COUNT, val)
427#define bfin_read_DMA2_CURR_BWL_COUNT() bfin_read32(DMA2_CURR_BWL_COUNT)
428#define bfin_write_DMA2_CURR_BWL_COUNT(val) bfin_write32(DMA2_CURR_BWL_COUNT, val)
429#define bfin_read_DMA2_BWM_COUNT() bfin_read32(DMA2_BWM_COUNT)
430#define bfin_write_DMA2_BWM_COUNT(val) bfin_write32(DMA2_BWM_COUNT, val)
431#define bfin_read_DMA2_CURR_BWM_COUNT() bfin_read32(DMA2_CURR_BWM_COUNT)
432#define bfin_write_DMA2_CURR_BWM_COUNT(val) bfin_write32(DMA2_CURR_BWM_COUNT, val)
433
434/* DMA Channel 3 Registers */
435
436#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
437#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
438#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
439#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
440#define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CONFIG)
441#define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CONFIG, val)
442#define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_X_COUNT)
443#define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_X_COUNT, val)
444#define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_X_MODIFY)
445#define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_X_MODIFY, val)
446#define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_Y_COUNT)
447#define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_Y_COUNT, val)
448#define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_Y_MODIFY)
449#define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_Y_MODIFY, val)
450#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
451#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
452#define bfin_read_DMA3_PREV_DESC_PTR() bfin_read32(DMA3_PREV_DESC_PTR)
453#define bfin_write_DMA3_PREV_DESC_PTR(val) bfin_write32(DMA3_PREV_DESC_PTR, val)
454#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
455#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
456#define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS)
457#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val)
458#define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_CURR_X_COUNT)
459#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_CURR_X_COUNT, val)
460#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_CURR_Y_COUNT)
461#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_CURR_Y_COUNT, val)
462#define bfin_read_DMA3_BWL_COUNT() bfin_read32(DMA3_BWL_COUNT)
463#define bfin_write_DMA3_BWL_COUNT(val) bfin_write32(DMA3_BWL_COUNT, val)
464#define bfin_read_DMA3_CURR_BWL_COUNT() bfin_read32(DMA3_CURR_BWL_COUNT)
465#define bfin_write_DMA3_CURR_BWL_COUNT(val) bfin_write32(DMA3_CURR_BWL_COUNT, val)
466#define bfin_read_DMA3_BWM_COUNT() bfin_read32(DMA3_BWM_COUNT)
467#define bfin_write_DMA3_BWM_COUNT(val) bfin_write32(DMA3_BWM_COUNT, val)
468#define bfin_read_DMA3_CURR_BWM_COUNT() bfin_read32(DMA3_CURR_BWM_COUNT)
469#define bfin_write_DMA3_CURR_BWM_COUNT(val) bfin_write32(DMA3_CURR_BWM_COUNT, val)
470
471/* DMA Channel 4 Registers */
472
473#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
474#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
475#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
476#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
477#define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CONFIG)
478#define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CONFIG, val)
479#define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_X_COUNT)
480#define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_X_COUNT, val)
481#define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_X_MODIFY)
482#define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_X_MODIFY, val)
483#define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_Y_COUNT)
484#define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_Y_COUNT, val)
485#define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_Y_MODIFY)
486#define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_Y_MODIFY, val)
487#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
488#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
489#define bfin_read_DMA4_PREV_DESC_PTR() bfin_read32(DMA4_PREV_DESC_PTR)
490#define bfin_write_DMA4_PREV_DESC_PTR(val) bfin_write32(DMA4_PREV_DESC_PTR, val)
491#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
492#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
493#define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_IRQ_STATUS)
494#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_IRQ_STATUS, val)
495#define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_CURR_X_COUNT)
496#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_CURR_X_COUNT, val)
497#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_CURR_Y_COUNT)
498#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_CURR_Y_COUNT, val)
499#define bfin_read_DMA4_BWL_COUNT() bfin_read32(DMA4_BWL_COUNT)
500#define bfin_write_DMA4_BWL_COUNT(val) bfin_write32(DMA4_BWL_COUNT, val)
501#define bfin_read_DMA4_CURR_BWL_COUNT() bfin_read32(DMA4_CURR_BWL_COUNT)
502#define bfin_write_DMA4_CURR_BWL_COUNT(val) bfin_write32(DMA4_CURR_BWL_COUNT, val)
503#define bfin_read_DMA4_BWM_COUNT() bfin_read32(DMA4_BWM_COUNT)
504#define bfin_write_DMA4_BWM_COUNT(val) bfin_write32(DMA4_BWM_COUNT, val)
505#define bfin_read_DMA4_CURR_BWM_COUNT() bfin_read32(DMA4_CURR_BWM_COUNT)
506#define bfin_write_DMA4_CURR_BWM_COUNT(val) bfin_write32(DMA4_CURR_BWM_COUNT, val)
507
508/* DMA Channel 5 Registers */
509
510#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
511#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
512#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
513#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
514#define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG)
515#define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val)
516#define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_X_COUNT)
517#define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_X_COUNT, val)
518#define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_X_MODIFY)
519#define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_X_MODIFY, val)
520#define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_Y_COUNT)
521#define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_Y_COUNT, val)
522#define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_Y_MODIFY)
523#define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_Y_MODIFY, val)
524#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
525#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
526#define bfin_read_DMA5_PREV_DESC_PTR() bfin_read32(DMA5_PREV_DESC_PTR)
527#define bfin_write_DMA5_PREV_DESC_PTR(val) bfin_write32(DMA5_PREV_DESC_PTR, val)
528#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
529#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
530#define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_IRQ_STATUS)
531#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_IRQ_STATUS, val)
532#define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_CURR_X_COUNT)
533#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_CURR_X_COUNT, val)
534#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_CURR_Y_COUNT)
535#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_CURR_Y_COUNT, val)
536#define bfin_read_DMA5_BWL_COUNT() bfin_read32(DMA5_BWL_COUNT)
537#define bfin_write_DMA5_BWL_COUNT(val) bfin_write32(DMA5_BWL_COUNT, val)
538#define bfin_read_DMA5_CURR_BWL_COUNT() bfin_read32(DMA5_CURR_BWL_COUNT)
539#define bfin_write_DMA5_CURR_BWL_COUNT(val) bfin_write32(DMA5_CURR_BWL_COUNT, val)
540#define bfin_read_DMA5_BWM_COUNT() bfin_read32(DMA5_BWM_COUNT)
541#define bfin_write_DMA5_BWM_COUNT(val) bfin_write32(DMA5_BWM_COUNT, val)
542#define bfin_read_DMA5_CURR_BWM_COUNT() bfin_read32(DMA5_CURR_BWM_COUNT)
543#define bfin_write_DMA5_CURR_BWM_COUNT(val) bfin_write32(DMA5_CURR_BWM_COUNT, val)
544
545/* DMA Channel 6 Registers */
546
547#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
548#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
549#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
550#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
551#define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CONFIG)
552#define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CONFIG, val)
553#define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_X_COUNT)
554#define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_X_COUNT, val)
555#define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_X_MODIFY)
556#define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_X_MODIFY, val)
557#define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_Y_COUNT)
558#define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_Y_COUNT, val)
559#define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_Y_MODIFY)
560#define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_Y_MODIFY, val)
561#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
562#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
563#define bfin_read_DMA6_PREV_DESC_PTR() bfin_read32(DMA6_PREV_DESC_PTR)
564#define bfin_write_DMA6_PREV_DESC_PTR(val) bfin_write32(DMA6_PREV_DESC_PTR, val)
565#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
566#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
567#define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_IRQ_STATUS)
568#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_IRQ_STATUS, val)
569#define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_CURR_X_COUNT)
570#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_CURR_X_COUNT, val)
571#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_CURR_Y_COUNT)
572#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_CURR_Y_COUNT, val)
573#define bfin_read_DMA6_BWL_COUNT() bfin_read32(DMA6_BWL_COUNT)
574#define bfin_write_DMA6_BWL_COUNT(val) bfin_write32(DMA6_BWL_COUNT, val)
575#define bfin_read_DMA6_CURR_BWL_COUNT() bfin_read32(DMA6_CURR_BWL_COUNT)
576#define bfin_write_DMA6_CURR_BWL_COUNT(val) bfin_write32(DMA6_CURR_BWL_COUNT, val)
577#define bfin_read_DMA6_BWM_COUNT() bfin_read32(DMA6_BWM_COUNT)
578#define bfin_write_DMA6_BWM_COUNT(val) bfin_write32(DMA6_BWM_COUNT, val)
579#define bfin_read_DMA6_CURR_BWM_COUNT() bfin_read32(DMA6_CURR_BWM_COUNT)
580#define bfin_write_DMA6_CURR_BWM_COUNT(val) bfin_write32(DMA6_CURR_BWM_COUNT, val)
581
582/* DMA Channel 7 Registers */
583
584#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
585#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
586#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
587#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
588#define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CONFIG)
589#define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CONFIG, val)
590#define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_X_COUNT)
591#define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_X_COUNT, val)
592#define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_X_MODIFY)
593#define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_X_MODIFY, val)
594#define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_Y_COUNT)
595#define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_Y_COUNT, val)
596#define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_Y_MODIFY)
597#define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_Y_MODIFY, val)
598#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
599#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
600#define bfin_read_DMA7_PREV_DESC_PTR() bfin_read32(DMA7_PREV_DESC_PTR)
601#define bfin_write_DMA7_PREV_DESC_PTR(val) bfin_write32(DMA7_PREV_DESC_PTR, val)
602#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
603#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
604#define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_IRQ_STATUS)
605#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_IRQ_STATUS, val)
606#define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_CURR_X_COUNT)
607#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_CURR_X_COUNT, val)
608#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_CURR_Y_COUNT)
609#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_CURR_Y_COUNT, val)
610#define bfin_read_DMA7_BWL_COUNT() bfin_read32(DMA7_BWL_COUNT)
611#define bfin_write_DMA7_BWL_COUNT(val) bfin_write32(DMA7_BWL_COUNT, val)
612#define bfin_read_DMA7_CURR_BWL_COUNT() bfin_read32(DMA7_CURR_BWL_COUNT)
613#define bfin_write_DMA7_CURR_BWL_COUNT(val) bfin_write32(DMA7_CURR_BWL_COUNT, val)
614#define bfin_read_DMA7_BWM_COUNT() bfin_read32(DMA7_BWM_COUNT)
615#define bfin_write_DMA7_BWM_COUNT(val) bfin_write32(DMA7_BWM_COUNT, val)
616#define bfin_read_DMA7_CURR_BWM_COUNT() bfin_read32(DMA7_CURR_BWM_COUNT)
617#define bfin_write_DMA7_CURR_BWM_COUNT(val) bfin_write32(DMA7_CURR_BWM_COUNT, val)
618
619/* DMA Channel 8 Registers */
620
621#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
622#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
623#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
624#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
625#define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CONFIG)
626#define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CONFIG, val)
627#define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_X_COUNT)
628#define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_X_COUNT, val)
629#define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_X_MODIFY)
630#define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_X_MODIFY, val)
631#define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_Y_COUNT)
632#define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_Y_COUNT, val)
633#define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_Y_MODIFY)
634#define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_Y_MODIFY, val)
635#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
636#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
637#define bfin_read_DMA8_PREV_DESC_PTR() bfin_read32(DMA8_PREV_DESC_PTR)
638#define bfin_write_DMA8_PREV_DESC_PTR(val) bfin_write32(DMA8_PREV_DESC_PTR, val)
639#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
640#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
641#define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_IRQ_STATUS)
642#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_IRQ_STATUS, val)
643#define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_CURR_X_COUNT)
644#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_CURR_X_COUNT, val)
645#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_CURR_Y_COUNT)
646#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_CURR_Y_COUNT, val)
647#define bfin_read_DMA8_BWL_COUNT() bfin_read32(DMA8_BWL_COUNT)
648#define bfin_write_DMA8_BWL_COUNT(val) bfin_write32(DMA8_BWL_COUNT, val)
649#define bfin_read_DMA8_CURR_BWL_COUNT() bfin_read32(DMA8_CURR_BWL_COUNT)
650#define bfin_write_DMA8_CURR_BWL_COUNT(val) bfin_write32(DMA8_CURR_BWL_COUNT, val)
651#define bfin_read_DMA8_BWM_COUNT() bfin_read32(DMA8_BWM_COUNT)
652#define bfin_write_DMA8_BWM_COUNT(val) bfin_write32(DMA8_BWM_COUNT, val)
653#define bfin_read_DMA8_CURR_BWM_COUNT() bfin_read32(DMA8_CURR_BWM_COUNT)
654#define bfin_write_DMA8_CURR_BWM_COUNT(val) bfin_write32(DMA8_CURR_BWM_COUNT, val)
655
656/* DMA Channel 9 Registers */
657
658#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
659#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
660#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
661#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
662#define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CONFIG)
663#define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CONFIG, val)
664#define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_X_COUNT)
665#define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_X_COUNT, val)
666#define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_X_MODIFY)
667#define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_X_MODIFY, val)
668#define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_Y_COUNT)
669#define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_Y_COUNT, val)
670#define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_Y_MODIFY)
671#define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_Y_MODIFY, val)
672#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
673#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
674#define bfin_read_DMA9_PREV_DESC_PTR() bfin_read32(DMA9_PREV_DESC_PTR)
675#define bfin_write_DMA9_PREV_DESC_PTR(val) bfin_write32(DMA9_PREV_DESC_PTR, val)
676#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
677#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
678#define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_IRQ_STATUS)
679#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_IRQ_STATUS, val)
680#define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_CURR_X_COUNT)
681#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_CURR_X_COUNT, val)
682#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_CURR_Y_COUNT)
683#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_CURR_Y_COUNT, val)
684#define bfin_read_DMA9_BWL_COUNT() bfin_read32(DMA9_BWL_COUNT)
685#define bfin_write_DMA9_BWL_COUNT(val) bfin_write32(DMA9_BWL_COUNT, val)
686#define bfin_read_DMA9_CURR_BWL_COUNT() bfin_read32(DMA9_CURR_BWL_COUNT)
687#define bfin_write_DMA9_CURR_BWL_COUNT(val) bfin_write32(DMA9_CURR_BWL_COUNT, val)
688#define bfin_read_DMA9_BWM_COUNT() bfin_read32(DMA9_BWM_COUNT)
689#define bfin_write_DMA9_BWM_COUNT(val) bfin_write32(DMA9_BWM_COUNT, val)
690#define bfin_read_DMA9_CURR_BWM_COUNT() bfin_read32(DMA9_CURR_BWM_COUNT)
691#define bfin_write_DMA9_CURR_BWM_COUNT(val) bfin_write32(DMA9_CURR_BWM_COUNT, val)
692
693/* DMA Channel 10 Registers */
694
695#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
696#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
697#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
698#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
699#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CONFIG)
700#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CONFIG, val)
701#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_X_COUNT)
702#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_X_COUNT, val)
703#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_X_MODIFY)
704#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_X_MODIFY, val)
705#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_Y_COUNT)
706#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_Y_COUNT, val)
707#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_Y_MODIFY)
708#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_Y_MODIFY, val)
709#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
710#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
711#define bfin_read_DMA10_PREV_DESC_PTR() bfin_read32(DMA10_PREV_DESC_PTR)
712#define bfin_write_DMA10_PREV_DESC_PTR(val) bfin_write32(DMA10_PREV_DESC_PTR, val)
713#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
714#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
715#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_IRQ_STATUS)
716#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_IRQ_STATUS, val)
717#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_CURR_X_COUNT)
718#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_CURR_X_COUNT, val)
719#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_CURR_Y_COUNT)
720#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_CURR_Y_COUNT, val)
721#define bfin_read_DMA10_BWL_COUNT() bfin_read32(DMA10_BWL_COUNT)
722#define bfin_write_DMA10_BWL_COUNT(val) bfin_write32(DMA10_BWL_COUNT, val)
723#define bfin_read_DMA10_CURR_BWL_COUNT() bfin_read32(DMA10_CURR_BWL_COUNT)
724#define bfin_write_DMA10_CURR_BWL_COUNT(val) bfin_write32(DMA10_CURR_BWL_COUNT, val)
725#define bfin_read_DMA10_BWM_COUNT() bfin_read32(DMA10_BWM_COUNT)
726#define bfin_write_DMA10_BWM_COUNT(val) bfin_write32(DMA10_BWM_COUNT, val)
727#define bfin_read_DMA10_CURR_BWM_COUNT() bfin_read32(DMA10_CURR_BWM_COUNT)
728#define bfin_write_DMA10_CURR_BWM_COUNT(val) bfin_write32(DMA10_CURR_BWM_COUNT, val)
729
730/* DMA Channel 11 Registers */
731
732#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
733#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
734#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
735#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
736#define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CONFIG)
737#define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CONFIG, val)
738#define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_X_COUNT)
739#define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_X_COUNT, val)
740#define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_X_MODIFY)
741#define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_X_MODIFY, val)
742#define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_Y_COUNT)
743#define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_Y_COUNT, val)
744#define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_Y_MODIFY)
745#define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_Y_MODIFY, val)
746#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
747#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
748#define bfin_read_DMA11_PREV_DESC_PTR() bfin_read32(DMA11_PREV_DESC_PTR)
749#define bfin_write_DMA11_PREV_DESC_PTR(val) bfin_write32(DMA11_PREV_DESC_PTR, val)
750#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
751#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
752#define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_IRQ_STATUS)
753#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_IRQ_STATUS, val)
754#define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_CURR_X_COUNT)
755#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_CURR_X_COUNT, val)
756#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_CURR_Y_COUNT)
757#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_CURR_Y_COUNT, val)
758#define bfin_read_DMA11_BWL_COUNT() bfin_read32(DMA11_BWL_COUNT)
759#define bfin_write_DMA11_BWL_COUNT(val) bfin_write32(DMA11_BWL_COUNT, val)
760#define bfin_read_DMA11_CURR_BWL_COUNT() bfin_read32(DMA11_CURR_BWL_COUNT)
761#define bfin_write_DMA11_CURR_BWL_COUNT(val) bfin_write32(DMA11_CURR_BWL_COUNT, val)
762#define bfin_read_DMA11_BWM_COUNT() bfin_read32(DMA11_BWM_COUNT)
763#define bfin_write_DMA11_BWM_COUNT(val) bfin_write32(DMA11_BWM_COUNT, val)
764#define bfin_read_DMA11_CURR_BWM_COUNT() bfin_read32(DMA11_CURR_BWM_COUNT)
765#define bfin_write_DMA11_CURR_BWM_COUNT(val) bfin_write32(DMA11_CURR_BWM_COUNT, val)
766
767/* DMA Channel 12 Registers */
768
769#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
770#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
771#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
772#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
773#define bfin_read_DMA12_CONFIG() bfin_read32(DMA12_CONFIG)
774#define bfin_write_DMA12_CONFIG(val) bfin_write32(DMA12_CONFIG, val)
775#define bfin_read_DMA12_X_COUNT() bfin_read32(DMA12_X_COUNT)
776#define bfin_write_DMA12_X_COUNT(val) bfin_write32(DMA12_X_COUNT, val)
777#define bfin_read_DMA12_X_MODIFY() bfin_read32(DMA12_X_MODIFY)
778#define bfin_write_DMA12_X_MODIFY(val) bfin_write32(DMA12_X_MODIFY, val)
779#define bfin_read_DMA12_Y_COUNT() bfin_read32(DMA12_Y_COUNT)
780#define bfin_write_DMA12_Y_COUNT(val) bfin_write32(DMA12_Y_COUNT, val)
781#define bfin_read_DMA12_Y_MODIFY() bfin_read32(DMA12_Y_MODIFY)
782#define bfin_write_DMA12_Y_MODIFY(val) bfin_write32(DMA12_Y_MODIFY, val)
783#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
784#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
785#define bfin_read_DMA12_PREV_DESC_PTR() bfin_read32(DMA12_PREV_DESC_PTR)
786#define bfin_write_DMA12_PREV_DESC_PTR(val) bfin_write32(DMA12_PREV_DESC_PTR, val)
787#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
788#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
789#define bfin_read_DMA12_IRQ_STATUS() bfin_read32(DMA12_IRQ_STATUS)
790#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write32(DMA12_IRQ_STATUS, val)
791#define bfin_read_DMA12_CURR_X_COUNT() bfin_read32(DMA12_CURR_X_COUNT)
792#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write32(DMA12_CURR_X_COUNT, val)
793#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read32(DMA12_CURR_Y_COUNT)
794#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write32(DMA12_CURR_Y_COUNT, val)
795#define bfin_read_DMA12_BWL_COUNT() bfin_read32(DMA12_BWL_COUNT)
796#define bfin_write_DMA12_BWL_COUNT(val) bfin_write32(DMA12_BWL_COUNT, val)
797#define bfin_read_DMA12_CURR_BWL_COUNT() bfin_read32(DMA12_CURR_BWL_COUNT)
798#define bfin_write_DMA12_CURR_BWL_COUNT(val) bfin_write32(DMA12_CURR_BWL_COUNT, val)
799#define bfin_read_DMA12_BWM_COUNT() bfin_read32(DMA12_BWM_COUNT)
800#define bfin_write_DMA12_BWM_COUNT(val) bfin_write32(DMA12_BWM_COUNT, val)
801#define bfin_read_DMA12_CURR_BWM_COUNT() bfin_read32(DMA12_CURR_BWM_COUNT)
802#define bfin_write_DMA12_CURR_BWM_COUNT(val) bfin_write32(DMA12_CURR_BWM_COUNT, val)
803
804/* DMA Channel 13 Registers */
805
806#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
807#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
808#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
809#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
810#define bfin_read_DMA13_CONFIG() bfin_read32(DMA13_CONFIG)
811#define bfin_write_DMA13_CONFIG(val) bfin_write32(DMA13_CONFIG, val)
812#define bfin_read_DMA13_X_COUNT() bfin_read32(DMA13_X_COUNT)
813#define bfin_write_DMA13_X_COUNT(val) bfin_write32(DMA13_X_COUNT, val)
814#define bfin_read_DMA13_X_MODIFY() bfin_read32(DMA13_X_MODIFY)
815#define bfin_write_DMA13_X_MODIFY(val) bfin_write32(DMA13_X_MODIFY, val)
816#define bfin_read_DMA13_Y_COUNT() bfin_read32(DMA13_Y_COUNT)
817#define bfin_write_DMA13_Y_COUNT(val) bfin_write32(DMA13_Y_COUNT, val)
818#define bfin_read_DMA13_Y_MODIFY() bfin_read32(DMA13_Y_MODIFY)
819#define bfin_write_DMA13_Y_MODIFY(val) bfin_write32(DMA13_Y_MODIFY, val)
820#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
821#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
822#define bfin_read_DMA13_PREV_DESC_PTR() bfin_read32(DMA13_PREV_DESC_PTR)
823#define bfin_write_DMA13_PREV_DESC_PTR(val) bfin_write32(DMA13_PREV_DESC_PTR, val)
824#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
825#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
826#define bfin_read_DMA13_IRQ_STATUS() bfin_read32(DMA13_IRQ_STATUS)
827#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write32(DMA13_IRQ_STATUS, val)
828#define bfin_read_DMA13_CURR_X_COUNT() bfin_read32(DMA13_CURR_X_COUNT)
829#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write32(DMA13_CURR_X_COUNT, val)
830#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read32(DMA13_CURR_Y_COUNT)
831#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write32(DMA13_CURR_Y_COUNT, val)
832#define bfin_read_DMA13_BWL_COUNT() bfin_read32(DMA13_BWL_COUNT)
833#define bfin_write_DMA13_BWL_COUNT(val) bfin_write32(DMA13_BWL_COUNT, val)
834#define bfin_read_DMA13_CURR_BWL_COUNT() bfin_read32(DMA13_CURR_BWL_COUNT)
835#define bfin_write_DMA13_CURR_BWL_COUNT(val) bfin_write32(DMA13_CURR_BWL_COUNT, val)
836#define bfin_read_DMA13_BWM_COUNT() bfin_read32(DMA13_BWM_COUNT)
837#define bfin_write_DMA13_BWM_COUNT(val) bfin_write32(DMA13_BWM_COUNT, val)
838#define bfin_read_DMA13_CURR_BWM_COUNT() bfin_read32(DMA13_CURR_BWM_COUNT)
839#define bfin_write_DMA13_CURR_BWM_COUNT(val) bfin_write32(DMA13_CURR_BWM_COUNT, val)
840
841/* DMA Channel 14 Registers */
842
843#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
844#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
845#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
846#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
847#define bfin_read_DMA14_CONFIG() bfin_read32(DMA14_CONFIG)
848#define bfin_write_DMA14_CONFIG(val) bfin_write32(DMA14_CONFIG, val)
849#define bfin_read_DMA14_X_COUNT() bfin_read32(DMA14_X_COUNT)
850#define bfin_write_DMA14_X_COUNT(val) bfin_write32(DMA14_X_COUNT, val)
851#define bfin_read_DMA14_X_MODIFY() bfin_read32(DMA14_X_MODIFY)
852#define bfin_write_DMA14_X_MODIFY(val) bfin_write32(DMA14_X_MODIFY, val)
853#define bfin_read_DMA14_Y_COUNT() bfin_read32(DMA14_Y_COUNT)
854#define bfin_write_DMA14_Y_COUNT(val) bfin_write32(DMA14_Y_COUNT, val)
855#define bfin_read_DMA14_Y_MODIFY() bfin_read32(DMA14_Y_MODIFY)
856#define bfin_write_DMA14_Y_MODIFY(val) bfin_write32(DMA14_Y_MODIFY, val)
857#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
858#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
859#define bfin_read_DMA14_PREV_DESC_PTR() bfin_read32(DMA14_PREV_DESC_PTR)
860#define bfin_write_DMA14_PREV_DESC_PTR(val) bfin_write32(DMA14_PREV_DESC_PTR, val)
861#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
862#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
863#define bfin_read_DMA14_IRQ_STATUS() bfin_read32(DMA14_IRQ_STATUS)
864#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write32(DMA14_IRQ_STATUS, val)
865#define bfin_read_DMA14_CURR_X_COUNT() bfin_read32(DMA14_CURR_X_COUNT)
866#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write32(DMA14_CURR_X_COUNT, val)
867#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read32(DMA14_CURR_Y_COUNT)
868#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write32(DMA14_CURR_Y_COUNT, val)
869#define bfin_read_DMA14_BWL_COUNT() bfin_read32(DMA14_BWL_COUNT)
870#define bfin_write_DMA14_BWL_COUNT(val) bfin_write32(DMA14_BWL_COUNT, val)
871#define bfin_read_DMA14_CURR_BWL_COUNT() bfin_read32(DMA14_CURR_BWL_COUNT)
872#define bfin_write_DMA14_CURR_BWL_COUNT(val) bfin_write32(DMA14_CURR_BWL_COUNT, val)
873#define bfin_read_DMA14_BWM_COUNT() bfin_read32(DMA14_BWM_COUNT)
874#define bfin_write_DMA14_BWM_COUNT(val) bfin_write32(DMA14_BWM_COUNT, val)
875#define bfin_read_DMA14_CURR_BWM_COUNT() bfin_read32(DMA14_CURR_BWM_COUNT)
876#define bfin_write_DMA14_CURR_BWM_COUNT(val) bfin_write32(DMA14_CURR_BWM_COUNT, val)
877
878/* DMA Channel 15 Registers */
879
880#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
881#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
882#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
883#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
884#define bfin_read_DMA15_CONFIG() bfin_read32(DMA15_CONFIG)
885#define bfin_write_DMA15_CONFIG(val) bfin_write32(DMA15_CONFIG, val)
886#define bfin_read_DMA15_X_COUNT() bfin_read32(DMA15_X_COUNT)
887#define bfin_write_DMA15_X_COUNT(val) bfin_write32(DMA15_X_COUNT, val)
888#define bfin_read_DMA15_X_MODIFY() bfin_read32(DMA15_X_MODIFY)
889#define bfin_write_DMA15_X_MODIFY(val) bfin_write32(DMA15_X_MODIFY, val)
890#define bfin_read_DMA15_Y_COUNT() bfin_read32(DMA15_Y_COUNT)
891#define bfin_write_DMA15_Y_COUNT(val) bfin_write32(DMA15_Y_COUNT, val)
892#define bfin_read_DMA15_Y_MODIFY() bfin_read32(DMA15_Y_MODIFY)
893#define bfin_write_DMA15_Y_MODIFY(val) bfin_write32(DMA15_Y_MODIFY, val)
894#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
895#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
896#define bfin_read_DMA15_PREV_DESC_PTR() bfin_read32(DMA15_PREV_DESC_PTR)
897#define bfin_write_DMA15_PREV_DESC_PTR(val) bfin_write32(DMA15_PREV_DESC_PTR, val)
898#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
899#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
900#define bfin_read_DMA15_IRQ_STATUS() bfin_read32(DMA15_IRQ_STATUS)
901#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write32(DMA15_IRQ_STATUS, val)
902#define bfin_read_DMA15_CURR_X_COUNT() bfin_read32(DMA15_CURR_X_COUNT)
903#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write32(DMA15_CURR_X_COUNT, val)
904#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read32(DMA15_CURR_Y_COUNT)
905#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write32(DMA15_CURR_Y_COUNT, val)
906#define bfin_read_DMA15_BWL_COUNT() bfin_read32(DMA15_BWL_COUNT)
907#define bfin_write_DMA15_BWL_COUNT(val) bfin_write32(DMA15_BWL_COUNT, val)
908#define bfin_read_DMA15_CURR_BWL_COUNT() bfin_read32(DMA15_CURR_BWL_COUNT)
909#define bfin_write_DMA15_CURR_BWL_COUNT(val) bfin_write32(DMA15_CURR_BWL_COUNT, val)
910#define bfin_read_DMA15_BWM_COUNT() bfin_read32(DMA15_BWM_COUNT)
911#define bfin_write_DMA15_BWM_COUNT(val) bfin_write32(DMA15_BWM_COUNT, val)
912#define bfin_read_DMA15_CURR_BWM_COUNT() bfin_read32(DMA15_CURR_BWM_COUNT)
913#define bfin_write_DMA15_CURR_BWM_COUNT(val) bfin_write32(DMA15_CURR_BWM_COUNT, val)
914
915/* DMA Channel 16 Registers */
916
917#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
918#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
919#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
920#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
921#define bfin_read_DMA16_CONFIG() bfin_read32(DMA16_CONFIG)
922#define bfin_write_DMA16_CONFIG(val) bfin_write32(DMA16_CONFIG, val)
923#define bfin_read_DMA16_X_COUNT() bfin_read32(DMA16_X_COUNT)
924#define bfin_write_DMA16_X_COUNT(val) bfin_write32(DMA16_X_COUNT, val)
925#define bfin_read_DMA16_X_MODIFY() bfin_read32(DMA16_X_MODIFY)
926#define bfin_write_DMA16_X_MODIFY(val) bfin_write32(DMA16_X_MODIFY, val)
927#define bfin_read_DMA16_Y_COUNT() bfin_read32(DMA16_Y_COUNT)
928#define bfin_write_DMA16_Y_COUNT(val) bfin_write32(DMA16_Y_COUNT, val)
929#define bfin_read_DMA16_Y_MODIFY() bfin_read32(DMA16_Y_MODIFY)
930#define bfin_write_DMA16_Y_MODIFY(val) bfin_write32(DMA16_Y_MODIFY, val)
931#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
932#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
933#define bfin_read_DMA16_PREV_DESC_PTR() bfin_read32(DMA16_PREV_DESC_PTR)
934#define bfin_write_DMA16_PREV_DESC_PTR(val) bfin_write32(DMA16_PREV_DESC_PTR, val)
935#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
936#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
937#define bfin_read_DMA16_IRQ_STATUS() bfin_read32(DMA16_IRQ_STATUS)
938#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write32(DMA16_IRQ_STATUS, val)
939#define bfin_read_DMA16_CURR_X_COUNT() bfin_read32(DMA16_CURR_X_COUNT)
940#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write32(DMA16_CURR_X_COUNT, val)
941#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read32(DMA16_CURR_Y_COUNT)
942#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write32(DMA16_CURR_Y_COUNT, val)
943#define bfin_read_DMA16_BWL_COUNT() bfin_read32(DMA16_BWL_COUNT)
944#define bfin_write_DMA16_BWL_COUNT(val) bfin_write32(DMA16_BWL_COUNT, val)
945#define bfin_read_DMA16_CURR_BWL_COUNT() bfin_read32(DMA16_CURR_BWL_COUNT)
946#define bfin_write_DMA16_CURR_BWL_COUNT(val) bfin_write32(DMA16_CURR_BWL_COUNT, val)
947#define bfin_read_DMA16_BWM_COUNT() bfin_read32(DMA16_BWM_COUNT)
948#define bfin_write_DMA16_BWM_COUNT(val) bfin_write32(DMA16_BWM_COUNT, val)
949#define bfin_read_DMA16_CURR_BWM_COUNT() bfin_read32(DMA16_CURR_BWM_COUNT)
950#define bfin_write_DMA16_CURR_BWM_COUNT(val) bfin_write32(DMA16_CURR_BWM_COUNT, val)
951
952/* DMA Channel 17 Registers */
953
954#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
955#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
956#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
957#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
958#define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG)
959#define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val)
960#define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT)
961#define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val)
962#define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY)
963#define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val)
964#define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT)
965#define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val)
966#define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY)
967#define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val)
968#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
969#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
970#define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR)
971#define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val)
972#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
973#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
974#define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS)
975#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val)
976#define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT)
977#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val)
978#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT)
979#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val)
980#define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT)
981#define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val)
982#define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT)
983#define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val)
984#define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT)
985#define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val)
986#define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT)
987#define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val)
988
989/* DMA Channel 18 Registers */
990
991#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
992#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
993#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
994#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
995#define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG)
996#define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val)
997#define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT)
998#define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val)
999#define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY)
1000#define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val)
1001#define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT)
1002#define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val)
1003#define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY)
1004#define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val)
1005#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
1006#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
1007#define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR)
1008#define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val)
1009#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
1010#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
1011#define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS)
1012#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val)
1013#define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT)
1014#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val)
1015#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT)
1016#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val)
1017#define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT)
1018#define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val)
1019#define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT)
1020#define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val)
1021#define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT)
1022#define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val)
1023#define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT)
1024#define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val)
1025
1026/* DMA Channel 19 Registers */
1027
1028#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
1029#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
1030#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
1031#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
1032#define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG)
1033#define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val)
1034#define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT)
1035#define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val)
1036#define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY)
1037#define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val)
1038#define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT)
1039#define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val)
1040#define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY)
1041#define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val)
1042#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
1043#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
1044#define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR)
1045#define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val)
1046#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
1047#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
1048#define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS)
1049#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val)
1050#define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT)
1051#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val)
1052#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT)
1053#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val)
1054#define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT)
1055#define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val)
1056#define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT)
1057#define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val)
1058#define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT)
1059#define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val)
1060#define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT)
1061#define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val)
1062
1063/* DMA Channel 20 Registers */
1064
1065#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
1066#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
1067#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
1068#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
1069#define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG)
1070#define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val)
1071#define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT)
1072#define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val)
1073#define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY)
1074#define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val)
1075#define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT)
1076#define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val)
1077#define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY)
1078#define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val)
1079#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
1080#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
1081#define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR)
1082#define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val)
1083#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
1084#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
1085#define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS)
1086#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val)
1087#define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT)
1088#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val)
1089#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT)
1090#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val)
1091#define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT)
1092#define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val)
1093#define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT)
1094#define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val)
1095#define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT)
1096#define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val)
1097#define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT)
1098#define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val)
1099
1100
1101/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
1102
1103#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
1104#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
1105#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
1106#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
1107#define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG)
1108#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
1109#define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
1110#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
1111#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
1112#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
1113#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
1114#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
1115#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
1116#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
1117#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
1118#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
1119#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
1120#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
1121#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
1122#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
1123#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
1124#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
1125#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
1126#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
1127#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
1128#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
1129#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
1130#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
1131#define bfin_read_MDMA0_SRC_CRC0_START_ADDR() bfin_read32(MDMA0_SRC_CRC0_START_ADDR)
1132#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
1133#define bfin_read_MDMA0_SRC_CRC0_CONFIG() bfin_read32(MDMA0_SRC_CRC0_CONFIG)
1134#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val) bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
1135#define bfin_read_MDMA0_SRC_CRC0_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_X_COUNT)
1136#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
1137#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY() bfin_read32(MDMA0_SRC_CRC0_X_MODIFY)
1138#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
1139#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_Y_COUNT)
1140#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
1141#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY() bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY)
1142#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
1143#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR)
1144#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
1145#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR)
1146#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
1147#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR() bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR)
1148#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
1149#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS() bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS)
1150#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
1151#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT)
1152#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
1153#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT)
1154#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
1155
1156/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */
1157
1158#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR)
1159#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
1160#define bfin_read_MDMA1_DEST_CRC1_START_ADDR() bfin_read32(MDMA1_DEST_CRC1_START_ADDR)
1161#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
1162#define bfin_read_MDMA1_DEST_CRC1_CONFIG() bfin_read32(MDMA1_DEST_CRC1_CONFIG)
1163#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val) bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
1164#define bfin_read_MDMA1_DEST_CRC1_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_X_COUNT)
1165#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
1166#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY() bfin_read32(MDMA1_DEST_CRC1_X_MODIFY)
1167#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
1168#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_Y_COUNT)
1169#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
1170#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY() bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY)
1171#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
1172#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR)
1173#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
1174#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR)
1175#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
1176#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR() bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR)
1177#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
1178#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS() bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS)
1179#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
1180#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT)
1181#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
1182#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT)
1183#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
1184#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR)
1185#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
1186#define bfin_read_MDMA1_SRC_CRC1_START_ADDR() bfin_read32(MDMA1_SRC_CRC1_START_ADDR)
1187#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
1188#define bfin_read_MDMA1_SRC_CRC1_CONFIG() bfin_read32(MDMA1_SRC_CRC1_CONFIG)
1189#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val) bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
1190#define bfin_read_MDMA1_SRC_CRC1_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_X_COUNT)
1191#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
1192#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY() bfin_read32(MDMA1_SRC_CRC1_X_MODIFY)
1193#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
1194#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_Y_COUNT)
1195#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
1196#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY() bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY)
1197#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val) bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
1198#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR)
1199#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
1200#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR() bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR)
1201#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val) bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
1202#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR() bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR)
1203#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val) bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
1204#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS() bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS)
1205#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val) bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
1206#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT)
1207#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
1208#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT() bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT)
1209#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val) bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
1210
1211
1212/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */
1213
1214#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR() bfin_read32(MDMA2_DEST_NEXT_DESC_PTR)
1215#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
1216#define bfin_read_MDMA2_DEST_START_ADDR() bfin_read32(MDMA2_DEST_START_ADDR)
1217#define bfin_write_MDMA2_DEST_START_ADDR(val) bfin_write32(MDMA2_DEST_START_ADDR, val)
1218#define bfin_read_MDMA2_DEST_CONFIG() bfin_read32(MDMA2_DEST_CONFIG)
1219#define bfin_write_MDMA2_DEST_CONFIG(val) bfin_write32(MDMA2_DEST_CONFIG, val)
1220#define bfin_read_MDMA2_DEST_X_COUNT() bfin_read32(MDMA2_DEST_X_COUNT)
1221#define bfin_write_MDMA2_DEST_X_COUNT(val) bfin_write32(MDMA2_DEST_X_COUNT, val)
1222#define bfin_read_MDMA2_DEST_X_MODIFY() bfin_read32(MDMA2_DEST_X_MODIFY)
1223#define bfin_write_MDMA2_DEST_X_MODIFY(val) bfin_write32(MDMA2_DEST_X_MODIFY, val)
1224#define bfin_read_MDMA2_DEST_Y_COUNT() bfin_read32(MDMA2_DEST_Y_COUNT)
1225#define bfin_write_MDMA2_DEST_Y_COUNT(val) bfin_write32(MDMA2_DEST_Y_COUNT, val)
1226#define bfin_read_MDMA2_DEST_Y_MODIFY() bfin_read32(MDMA2_DEST_Y_MODIFY)
1227#define bfin_write_MDMA2_DEST_Y_MODIFY(val) bfin_write32(MDMA2_DEST_Y_MODIFY, val)
1228#define bfin_read_MDMA2_DEST_CURR_DESC_PTR() bfin_read32(MDMA2_DEST_CURR_DESC_PTR)
1229#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
1230#define bfin_read_MDMA2_DEST_PREV_DESC_PTR() bfin_read32(MDMA2_DEST_PREV_DESC_PTR)
1231#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
1232#define bfin_read_MDMA2_DEST_CURR_ADDR() bfin_read32(MDMA2_DEST_CURR_ADDR)
1233#define bfin_write_MDMA2_DEST_CURR_ADDR(val) bfin_write32(MDMA2_DEST_CURR_ADDR, val)
1234#define bfin_read_MDMA2_DEST_IRQ_STATUS() bfin_read32(MDMA2_DEST_IRQ_STATUS)
1235#define bfin_write_MDMA2_DEST_IRQ_STATUS(val) bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
1236#define bfin_read_MDMA2_DEST_CURR_X_COUNT() bfin_read32(MDMA2_DEST_CURR_X_COUNT)
1237#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val) bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
1238#define bfin_read_MDMA2_DEST_CURR_Y_COUNT() bfin_read32(MDMA2_DEST_CURR_Y_COUNT)
1239#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
1240#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR() bfin_read32(MDMA2_SRC_NEXT_DESC_PTR)
1241#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
1242#define bfin_read_MDMA2_SRC_START_ADDR() bfin_read32(MDMA2_SRC_START_ADDR)
1243#define bfin_write_MDMA2_SRC_START_ADDR(val) bfin_write32(MDMA2_SRC_START_ADDR, val)
1244#define bfin_read_MDMA2_SRC_CONFIG() bfin_read32(MDMA2_SRC_CONFIG)
1245#define bfin_write_MDMA2_SRC_CONFIG(val) bfin_write32(MDMA2_SRC_CONFIG, val)
1246#define bfin_read_MDMA2_SRC_X_COUNT() bfin_read32(MDMA2_SRC_X_COUNT)
1247#define bfin_write_MDMA2_SRC_X_COUNT(val) bfin_write32(MDMA2_SRC_X_COUNT, val)
1248#define bfin_read_MDMA2_SRC_X_MODIFY() bfin_read32(MDMA2_SRC_X_MODIFY)
1249#define bfin_write_MDMA2_SRC_X_MODIFY(val) bfin_write32(MDMA2_SRC_X_MODIFY, val)
1250#define bfin_read_MDMA2_SRC_Y_COUNT() bfin_read32(MDMA2_SRC_Y_COUNT)
1251#define bfin_write_MDMA2_SRC_Y_COUNT(val) bfin_write32(MDMA2_SRC_Y_COUNT, val)
1252#define bfin_read_MDMA2_SRC_Y_MODIFY() bfin_read32(MDMA2_SRC_Y_MODIFY)
1253#define bfin_write_MDMA2_SRC_Y_MODIFY(val) bfin_write32(MDMA2_SRC_Y_MODIFY, val)
1254#define bfin_read_MDMA2_SRC_CURR_DESC_PTR() bfin_read32(MDMA2_SRC_CURR_DESC_PTR)
1255#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
1256#define bfin_read_MDMA2_SRC_PREV_DESC_PTR() bfin_read32(MDMA2_SRC_PREV_DESC_PTR)
1257#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
1258#define bfin_read_MDMA2_SRC_CURR_ADDR() bfin_read32(MDMA2_SRC_CURR_ADDR)
1259#define bfin_write_MDMA2_SRC_CURR_ADDR(val) bfin_write32(MDMA2_SRC_CURR_ADDR, val)
1260#define bfin_read_MDMA2_SRC_IRQ_STATUS() bfin_read32(MDMA2_SRC_IRQ_STATUS)
1261#define bfin_write_MDMA2_SRC_IRQ_STATUS(val) bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
1262#define bfin_read_MDMA2_SRC_CURR_X_COUNT() bfin_read32(MDMA2_SRC_CURR_X_COUNT)
1263#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val) bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
1264#define bfin_read_MDMA2_SRC_CURR_Y_COUNT() bfin_read32(MDMA2_SRC_CURR_Y_COUNT)
1265#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
1266
1267/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */
1268
1269#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR() bfin_read32(MDMA3_DEST_NEXT_DESC_PTR)
1270#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val) bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
1271#define bfin_read_MDMA3_DEST_START_ADDR() bfin_read32(MDMA3_DEST_START_ADDR)
1272#define bfin_write_MDMA3_DEST_START_ADDR(val) bfin_write32(MDMA3_DEST_START_ADDR, val)
1273#define bfin_read_MDMA3_DEST_CONFIG() bfin_read32(MDMA3_DEST_CONFIG)
1274#define bfin_write_MDMA3_DEST_CONFIG(val) bfin_write32(MDMA3_DEST_CONFIG, val)
1275#define bfin_read_MDMA3_DEST_X_COUNT() bfin_read32(MDMA3_DEST_X_COUNT)
1276#define bfin_write_MDMA3_DEST_X_COUNT(val) bfin_write32(MDMA3_DEST_X_COUNT, val)
1277#define bfin_read_MDMA3_DEST_X_MODIFY() bfin_read32(MDMA3_DEST_X_MODIFY)
1278#define bfin_write_MDMA3_DEST_X_MODIFY(val) bfin_write32(MDMA3_DEST_X_MODIFY, val)
1279#define bfin_read_MDMA3_DEST_Y_COUNT() bfin_read32(MDMA3_DEST_Y_COUNT)
1280#define bfin_write_MDMA3_DEST_Y_COUNT(val) bfin_write32(MDMA3_DEST_Y_COUNT, val)
1281#define bfin_read_MDMA3_DEST_Y_MODIFY() bfin_read32(MDMA3_DEST_Y_MODIFY)
1282#define bfin_write_MDMA3_DEST_Y_MODIFY(val) bfin_write32(MDMA3_DEST_Y_MODIFY, val)
1283#define bfin_read_MDMA3_DEST_CURR_DESC_PTR() bfin_read32(MDMA3_DEST_CURR_DESC_PTR)
1284#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val) bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
1285#define bfin_read_MDMA3_DEST_PREV_DESC_PTR() bfin_read32(MDMA3_DEST_PREV_DESC_PTR)
1286#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val) bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
1287#define bfin_read_MDMA3_DEST_CURR_ADDR() bfin_read32(MDMA3_DEST_CURR_ADDR)
1288#define bfin_write_MDMA3_DEST_CURR_ADDR(val) bfin_write32(MDMA3_DEST_CURR_ADDR, val)
1289#define bfin_read_MDMA3_DEST_IRQ_STATUS() bfin_read32(MDMA3_DEST_IRQ_STATUS)
1290#define bfin_write_MDMA3_DEST_IRQ_STATUS(val) bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
1291#define bfin_read_MDMA3_DEST_CURR_X_COUNT() bfin_read32(MDMA3_DEST_CURR_X_COUNT)
1292#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val) bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
1293#define bfin_read_MDMA3_DEST_CURR_Y_COUNT() bfin_read32(MDMA3_DEST_CURR_Y_COUNT)
1294#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val) bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
1295#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR() bfin_read32(MDMA3_SRC_NEXT_DESC_PTR)
1296#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val) bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
1297#define bfin_read_MDMA3_SRC_START_ADDR() bfin_read32(MDMA3_SRC_START_ADDR)
1298#define bfin_write_MDMA3_SRC_START_ADDR(val) bfin_write32(MDMA3_SRC_START_ADDR, val)
1299#define bfin_read_MDMA3_SRC_CONFIG() bfin_read32(MDMA3_SRC_CONFIG)
1300#define bfin_write_MDMA3_SRC_CONFIG(val) bfin_write32(MDMA3_SRC_CONFIG, val)
1301#define bfin_read_MDMA3_SRC_X_COUNT() bfin_read32(MDMA3_SRC_X_COUNT)
1302#define bfin_write_MDMA3_SRC_X_COUNT(val) bfin_write32(MDMA3_SRC_X_COUNT, val)
1303#define bfin_read_MDMA3_SRC_X_MODIFY() bfin_read32(MDMA3_SRC_X_MODIFY)
1304#define bfin_write_MDMA3_SRC_X_MODIFY(val) bfin_write32(MDMA3_SRC_X_MODIFY, val)
1305#define bfin_read_MDMA3_SRC_Y_COUNT() bfin_read32(MDMA3_SRC_Y_COUNT)
1306#define bfin_write_MDMA3_SRC_Y_COUNT(val) bfin_write32(MDMA3_SRC_Y_COUNT, val)
1307#define bfin_read_MDMA3_SRC_Y_MODIFY() bfin_read32(MDMA3_SRC_Y_MODIFY)
1308#define bfin_write_MDMA3_SRC_Y_MODIFY(val) bfin_write32(MDMA3_SRC_Y_MODIFY, val)
1309#define bfin_read_MDMA3_SRC_CURR_DESC_PTR() bfin_read32(MDMA3_SRC_CURR_DESC_PTR)
1310#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val) bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
1311#define bfin_read_MDMA3_SRC_PREV_DESC_PTR() bfin_read32(MDMA3_SRC_PREV_DESC_PTR)
1312#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val) bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
1313#define bfin_read_MDMA3_SRC_CURR_ADDR() bfin_read32(MDMA3_SRC_CURR_ADDR)
1314#define bfin_write_MDMA3_SRC_CURR_ADDR(val) bfin_write32(MDMA3_SRC_CURR_ADDR, val)
1315#define bfin_read_MDMA3_SRC_IRQ_STATUS() bfin_read32(MDMA3_SRC_IRQ_STATUS)
1316#define bfin_write_MDMA3_SRC_IRQ_STATUS(val) bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
1317#define bfin_read_MDMA3_SRC_CURR_X_COUNT() bfin_read32(MDMA3_SRC_CURR_X_COUNT)
1318#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val) bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
1319#define bfin_read_MDMA3_SRC_CURR_Y_COUNT() bfin_read32(MDMA3_SRC_CURR_Y_COUNT)
1320#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val) bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
1321
1322
1323/* DMA Channel 29 Registers */
1324
1325#define bfin_read_DMA29_NEXT_DESC_PTR() bfin_read32(DMA29_NEXT_DESC_PTR)
1326#define bfin_write_DMA29_NEXT_DESC_PTR(val) bfin_write32(DMA29_NEXT_DESC_PTR, val)
1327#define bfin_read_DMA29_START_ADDR() bfin_read32(DMA29_START_ADDR)
1328#define bfin_write_DMA29_START_ADDR(val) bfin_write32(DMA29_START_ADDR, val)
1329#define bfin_read_DMA29_CONFIG() bfin_read32(DMA29_CONFIG)
1330#define bfin_write_DMA29_CONFIG(val) bfin_write32(DMA29_CONFIG, val)
1331#define bfin_read_DMA29_X_COUNT() bfin_read32(DMA29_X_COUNT)
1332#define bfin_write_DMA29_X_COUNT(val) bfin_write32(DMA29_X_COUNT, val)
1333#define bfin_read_DMA29_X_MODIFY() bfin_read32(DMA29_X_MODIFY)
1334#define bfin_write_DMA29_X_MODIFY(val) bfin_write32(DMA29_X_MODIFY, val)
1335#define bfin_read_DMA29_Y_COUNT() bfin_read32(DMA29_Y_COUNT)
1336#define bfin_write_DMA29_Y_COUNT(val) bfin_write32(DMA29_Y_COUNT, val)
1337#define bfin_read_DMA29_Y_MODIFY() bfin_read32(DMA29_Y_MODIFY)
1338#define bfin_write_DMA29_Y_MODIFY(val) bfin_write32(DMA29_Y_MODIFY, val)
1339#define bfin_read_DMA29_CURR_DESC_PTR() bfin_read32(DMA29_CURR_DESC_PTR)
1340#define bfin_write_DMA29_CURR_DESC_PTR(val) bfin_write32(DMA29_CURR_DESC_PTR, val)
1341#define bfin_read_DMA29_PREV_DESC_PTR() bfin_read32(DMA29_PREV_DESC_PTR)
1342#define bfin_write_DMA29_PREV_DESC_PTR(val) bfin_write32(DMA29_PREV_DESC_PTR, val)
1343#define bfin_read_DMA29_CURR_ADDR() bfin_read32(DMA29_CURR_ADDR)
1344#define bfin_write_DMA29_CURR_ADDR(val) bfin_write32(DMA29_CURR_ADDR, val)
1345#define bfin_read_DMA29_IRQ_STATUS() bfin_read32(DMA29_IRQ_STATUS)
1346#define bfin_write_DMA29_IRQ_STATUS(val) bfin_write32(DMA29_IRQ_STATUS, val)
1347#define bfin_read_DMA29_CURR_X_COUNT() bfin_read32(DMA29_CURR_X_COUNT)
1348#define bfin_write_DMA29_CURR_X_COUNT(val) bfin_write32(DMA29_CURR_X_COUNT, val)
1349#define bfin_read_DMA29_CURR_Y_COUNT() bfin_read32(DMA29_CURR_Y_COUNT)
1350#define bfin_write_DMA29_CURR_Y_COUNT(val) bfin_write32(DMA29_CURR_Y_COUNT, val)
1351#define bfin_read_DMA29_BWL_COUNT() bfin_read32(DMA29_BWL_COUNT)
1352#define bfin_write_DMA29_BWL_COUNT(val) bfin_write32(DMA29_BWL_COUNT, val)
1353#define bfin_read_DMA29_CURR_BWL_COUNT() bfin_read32(DMA29_CURR_BWL_COUNT)
1354#define bfin_write_DMA29_CURR_BWL_COUNT(val) bfin_write32(DMA29_CURR_BWL_COUNT, val)
1355#define bfin_read_DMA29_BWM_COUNT() bfin_read32(DMA29_BWM_COUNT)
1356#define bfin_write_DMA29_BWM_COUNT(val) bfin_write32(DMA29_BWM_COUNT, val)
1357#define bfin_read_DMA29_CURR_BWM_COUNT() bfin_read32(DMA29_CURR_BWM_COUNT)
1358#define bfin_write_DMA29_CURR_BWM_COUNT(val) bfin_write32(DMA29_CURR_BWM_COUNT, val)
1359
1360/* DMA Channel 30 Registers */
1361
1362#define bfin_read_DMA30_NEXT_DESC_PTR() bfin_read32(DMA30_NEXT_DESC_PTR)
1363#define bfin_write_DMA30_NEXT_DESC_PTR(val) bfin_write32(DMA30_NEXT_DESC_PTR, val)
1364#define bfin_read_DMA30_START_ADDR() bfin_read32(DMA30_START_ADDR)
1365#define bfin_write_DMA30_START_ADDR(val) bfin_write32(DMA30_START_ADDR, val)
1366#define bfin_read_DMA30_CONFIG() bfin_read32(DMA30_CONFIG)
1367#define bfin_write_DMA30_CONFIG(val) bfin_write32(DMA30_CONFIG, val)
1368#define bfin_read_DMA30_X_COUNT() bfin_read32(DMA30_X_COUNT)
1369#define bfin_write_DMA30_X_COUNT(val) bfin_write32(DMA30_X_COUNT, val)
1370#define bfin_read_DMA30_X_MODIFY() bfin_read32(DMA30_X_MODIFY)
1371#define bfin_write_DMA30_X_MODIFY(val) bfin_write32(DMA30_X_MODIFY, val)
1372#define bfin_read_DMA30_Y_COUNT() bfin_read32(DMA30_Y_COUNT)
1373#define bfin_write_DMA30_Y_COUNT(val) bfin_write32(DMA30_Y_COUNT, val)
1374#define bfin_read_DMA30_Y_MODIFY() bfin_read32(DMA30_Y_MODIFY)
1375#define bfin_write_DMA30_Y_MODIFY(val) bfin_write32(DMA30_Y_MODIFY, val)
1376#define bfin_read_DMA30_CURR_DESC_PTR() bfin_read32(DMA30_CURR_DESC_PTR)
1377#define bfin_write_DMA30_CURR_DESC_PTR(val) bfin_write32(DMA30_CURR_DESC_PTR, val)
1378#define bfin_read_DMA30_PREV_DESC_PTR() bfin_read32(DMA30_PREV_DESC_PTR)
1379#define bfin_write_DMA30_PREV_DESC_PTR(val) bfin_write32(DMA30_PREV_DESC_PTR, val)
1380#define bfin_read_DMA30_CURR_ADDR() bfin_read32(DMA30_CURR_ADDR)
1381#define bfin_write_DMA30_CURR_ADDR(val) bfin_write32(DMA30_CURR_ADDR, val)
1382#define bfin_read_DMA30_IRQ_STATUS() bfin_read32(DMA30_IRQ_STATUS)
1383#define bfin_write_DMA30_IRQ_STATUS(val) bfin_write32(DMA30_IRQ_STATUS, val)
1384#define bfin_read_DMA30_CURR_X_COUNT() bfin_read32(DMA30_CURR_X_COUNT)
1385#define bfin_write_DMA30_CURR_X_COUNT(val) bfin_write32(DMA30_CURR_X_COUNT, val)
1386#define bfin_read_DMA30_CURR_Y_COUNT() bfin_read32(DMA30_CURR_Y_COUNT)
1387#define bfin_write_DMA30_CURR_Y_COUNT(val) bfin_write32(DMA30_CURR_Y_COUNT, val)
1388#define bfin_read_DMA30_BWL_COUNT() bfin_read32(DMA30_BWL_COUNT)
1389#define bfin_write_DMA30_BWL_COUNT(val) bfin_write32(DMA30_BWL_COUNT, val)
1390#define bfin_read_DMA30_CURR_BWL_COUNT() bfin_read32(DMA30_CURR_BWL_COUNT)
1391#define bfin_write_DMA30_CURR_BWL_COUNT(val) bfin_write32(DMA30_CURR_BWL_COUNT, val)
1392#define bfin_read_DMA30_BWM_COUNT() bfin_read32(DMA30_BWM_COUNT)
1393#define bfin_write_DMA30_BWM_COUNT(val) bfin_write32(DMA30_BWM_COUNT, val)
1394#define bfin_read_DMA30_CURR_BWM_COUNT() bfin_read32(DMA30_CURR_BWM_COUNT)
1395#define bfin_write_DMA30_CURR_BWM_COUNT(val) bfin_write32(DMA30_CURR_BWM_COUNT, val)
1396
1397/* DMA Channel 31 Registers */
1398
1399#define bfin_read_DMA31_NEXT_DESC_PTR() bfin_read32(DMA31_NEXT_DESC_PTR)
1400#define bfin_write_DMA31_NEXT_DESC_PTR(val) bfin_write32(DMA31_NEXT_DESC_PTR, val)
1401#define bfin_read_DMA31_START_ADDR() bfin_read32(DMA31_START_ADDR)
1402#define bfin_write_DMA31_START_ADDR(val) bfin_write32(DMA31_START_ADDR, val)
1403#define bfin_read_DMA31_CONFIG() bfin_read32(DMA31_CONFIG)
1404#define bfin_write_DMA31_CONFIG(val) bfin_write32(DMA31_CONFIG, val)
1405#define bfin_read_DMA31_X_COUNT() bfin_read32(DMA31_X_COUNT)
1406#define bfin_write_DMA31_X_COUNT(val) bfin_write32(DMA31_X_COUNT, val)
1407#define bfin_read_DMA31_X_MODIFY() bfin_read32(DMA31_X_MODIFY)
1408#define bfin_write_DMA31_X_MODIFY(val) bfin_write32(DMA31_X_MODIFY, val)
1409#define bfin_read_DMA31_Y_COUNT() bfin_read32(DMA31_Y_COUNT)
1410#define bfin_write_DMA31_Y_COUNT(val) bfin_write32(DMA31_Y_COUNT, val)
1411#define bfin_read_DMA31_Y_MODIFY() bfin_read32(DMA31_Y_MODIFY)
1412#define bfin_write_DMA31_Y_MODIFY(val) bfin_write32(DMA31_Y_MODIFY, val)
1413#define bfin_read_DMA31_CURR_DESC_PTR() bfin_read32(DMA31_CURR_DESC_PTR)
1414#define bfin_write_DMA31_CURR_DESC_PTR(val) bfin_write32(DMA31_CURR_DESC_PTR, val)
1415#define bfin_read_DMA31_PREV_DESC_PTR() bfin_read32(DMA31_PREV_DESC_PTR)
1416#define bfin_write_DMA31_PREV_DESC_PTR(val) bfin_write32(DMA31_PREV_DESC_PTR, val)
1417#define bfin_read_DMA31_CURR_ADDR() bfin_read32(DMA31_CURR_ADDR)
1418#define bfin_write_DMA31_CURR_ADDR(val) bfin_write32(DMA31_CURR_ADDR, val)
1419#define bfin_read_DMA31_IRQ_STATUS() bfin_read32(DMA31_IRQ_STATUS)
1420#define bfin_write_DMA31_IRQ_STATUS(val) bfin_write32(DMA31_IRQ_STATUS, val)
1421#define bfin_read_DMA31_CURR_X_COUNT() bfin_read32(DMA31_CURR_X_COUNT)
1422#define bfin_write_DMA31_CURR_X_COUNT(val) bfin_write32(DMA31_CURR_X_COUNT, val)
1423#define bfin_read_DMA31_CURR_Y_COUNT() bfin_read32(DMA31_CURR_Y_COUNT)
1424#define bfin_write_DMA31_CURR_Y_COUNT(val) bfin_write32(DMA31_CURR_Y_COUNT, val)
1425#define bfin_read_DMA31_BWL_COUNT() bfin_read32(DMA31_BWL_COUNT)
1426#define bfin_write_DMA31_BWL_COUNT(val) bfin_write32(DMA31_BWL_COUNT, val)
1427#define bfin_read_DMA31_CURR_BWL_COUNT() bfin_read32(DMA31_CURR_BWL_COUNT)
1428#define bfin_write_DMA31_CURR_BWL_COUNT(val) bfin_write32(DMA31_CURR_BWL_COUNT, val)
1429#define bfin_read_DMA31_BWM_COUNT() bfin_read32(DMA31_BWM_COUNT)
1430#define bfin_write_DMA31_BWM_COUNT(val) bfin_write32(DMA31_BWM_COUNT, val)
1431#define bfin_read_DMA31_CURR_BWM_COUNT() bfin_read32(DMA31_CURR_BWM_COUNT)
1432#define bfin_write_DMA31_CURR_BWM_COUNT(val) bfin_write32(DMA31_CURR_BWM_COUNT, val)
1433
1434/* DMA Channel 32 Registers */
1435
1436#define bfin_read_DMA32_NEXT_DESC_PTR() bfin_read32(DMA32_NEXT_DESC_PTR)
1437#define bfin_write_DMA32_NEXT_DESC_PTR(val) bfin_write32(DMA32_NEXT_DESC_PTR, val)
1438#define bfin_read_DMA32_START_ADDR() bfin_read32(DMA32_START_ADDR)
1439#define bfin_write_DMA32_START_ADDR(val) bfin_write32(DMA32_START_ADDR, val)
1440#define bfin_read_DMA32_CONFIG() bfin_read32(DMA32_CONFIG)
1441#define bfin_write_DMA32_CONFIG(val) bfin_write32(DMA32_CONFIG, val)
1442#define bfin_read_DMA32_X_COUNT() bfin_read32(DMA32_X_COUNT)
1443#define bfin_write_DMA32_X_COUNT(val) bfin_write32(DMA32_X_COUNT, val)
1444#define bfin_read_DMA32_X_MODIFY() bfin_read32(DMA32_X_MODIFY)
1445#define bfin_write_DMA32_X_MODIFY(val) bfin_write32(DMA32_X_MODIFY, val)
1446#define bfin_read_DMA32_Y_COUNT() bfin_read32(DMA32_Y_COUNT)
1447#define bfin_write_DMA32_Y_COUNT(val) bfin_write32(DMA32_Y_COUNT, val)
1448#define bfin_read_DMA32_Y_MODIFY() bfin_read32(DMA32_Y_MODIFY)
1449#define bfin_write_DMA32_Y_MODIFY(val) bfin_write32(DMA32_Y_MODIFY, val)
1450#define bfin_read_DMA32_CURR_DESC_PTR() bfin_read32(DMA32_CURR_DESC_PTR)
1451#define bfin_write_DMA32_CURR_DESC_PTR(val) bfin_write32(DMA32_CURR_DESC_PTR, val)
1452#define bfin_read_DMA32_PREV_DESC_PTR() bfin_read32(DMA32_PREV_DESC_PTR)
1453#define bfin_write_DMA32_PREV_DESC_PTR(val) bfin_write32(DMA32_PREV_DESC_PTR, val)
1454#define bfin_read_DMA32_CURR_ADDR() bfin_read32(DMA32_CURR_ADDR)
1455#define bfin_write_DMA32_CURR_ADDR(val) bfin_write32(DMA32_CURR_ADDR, val)
1456#define bfin_read_DMA32_IRQ_STATUS() bfin_read32(DMA32_IRQ_STATUS)
1457#define bfin_write_DMA32_IRQ_STATUS(val) bfin_write32(DMA32_IRQ_STATUS, val)
1458#define bfin_read_DMA32_CURR_X_COUNT() bfin_read32(DMA32_CURR_X_COUNT)
1459#define bfin_write_DMA32_CURR_X_COUNT(val) bfin_write32(DMA32_CURR_X_COUNT, val)
1460#define bfin_read_DMA32_CURR_Y_COUNT() bfin_read32(DMA32_CURR_Y_COUNT)
1461#define bfin_write_DMA32_CURR_Y_COUNT(val) bfin_write32(DMA32_CURR_Y_COUNT, val)
1462#define bfin_read_DMA32_BWL_COUNT() bfin_read32(DMA32_BWL_COUNT)
1463#define bfin_write_DMA32_BWL_COUNT(val) bfin_write32(DMA32_BWL_COUNT, val)
1464#define bfin_read_DMA32_CURR_BWL_COUNT() bfin_read32(DMA32_CURR_BWL_COUNT)
1465#define bfin_write_DMA32_CURR_BWL_COUNT(val) bfin_write32(DMA32_CURR_BWL_COUNT, val)
1466#define bfin_read_DMA32_BWM_COUNT() bfin_read32(DMA32_BWM_COUNT)
1467#define bfin_write_DMA32_BWM_COUNT(val) bfin_write32(DMA32_BWM_COUNT, val)
1468#define bfin_read_DMA32_CURR_BWM_COUNT() bfin_read32(DMA32_CURR_BWM_COUNT)
1469#define bfin_write_DMA32_CURR_BWM_COUNT(val) bfin_write32(DMA32_CURR_BWM_COUNT, val)
1470
1471/* DMA Channel 33 Registers */
1472
1473#define bfin_read_DMA33_NEXT_DESC_PTR() bfin_read32(DMA33_NEXT_DESC_PTR)
1474#define bfin_write_DMA33_NEXT_DESC_PTR(val) bfin_write32(DMA33_NEXT_DESC_PTR, val)
1475#define bfin_read_DMA33_START_ADDR() bfin_read32(DMA33_START_ADDR)
1476#define bfin_write_DMA33_START_ADDR(val) bfin_write32(DMA33_START_ADDR, val)
1477#define bfin_read_DMA33_CONFIG() bfin_read32(DMA33_CONFIG)
1478#define bfin_write_DMA33_CONFIG(val) bfin_write32(DMA33_CONFIG, val)
1479#define bfin_read_DMA33_X_COUNT() bfin_read32(DMA33_X_COUNT)
1480#define bfin_write_DMA33_X_COUNT(val) bfin_write32(DMA33_X_COUNT, val)
1481#define bfin_read_DMA33_X_MODIFY() bfin_read32(DMA33_X_MODIFY)
1482#define bfin_write_DMA33_X_MODIFY(val) bfin_write32(DMA33_X_MODIFY, val)
1483#define bfin_read_DMA33_Y_COUNT() bfin_read32(DMA33_Y_COUNT)
1484#define bfin_write_DMA33_Y_COUNT(val) bfin_write32(DMA33_Y_COUNT, val)
1485#define bfin_read_DMA33_Y_MODIFY() bfin_read32(DMA33_Y_MODIFY)
1486#define bfin_write_DMA33_Y_MODIFY(val) bfin_write32(DMA33_Y_MODIFY, val)
1487#define bfin_read_DMA33_CURR_DESC_PTR() bfin_read32(DMA33_CURR_DESC_PTR)
1488#define bfin_write_DMA33_CURR_DESC_PTR(val) bfin_write32(DMA33_CURR_DESC_PTR, val)
1489#define bfin_read_DMA33_PREV_DESC_PTR() bfin_read32(DMA33_PREV_DESC_PTR)
1490#define bfin_write_DMA33_PREV_DESC_PTR(val) bfin_write32(DMA33_PREV_DESC_PTR, val)
1491#define bfin_read_DMA33_CURR_ADDR() bfin_read32(DMA33_CURR_ADDR)
1492#define bfin_write_DMA33_CURR_ADDR(val) bfin_write32(DMA33_CURR_ADDR, val)
1493#define bfin_read_DMA33_IRQ_STATUS() bfin_read32(DMA33_IRQ_STATUS)
1494#define bfin_write_DMA33_IRQ_STATUS(val) bfin_write32(DMA33_IRQ_STATUS, val)
1495#define bfin_read_DMA33_CURR_X_COUNT() bfin_read32(DMA33_CURR_X_COUNT)
1496#define bfin_write_DMA33_CURR_X_COUNT(val) bfin_write32(DMA33_CURR_X_COUNT, val)
1497#define bfin_read_DMA33_CURR_Y_COUNT() bfin_read32(DMA33_CURR_Y_COUNT)
1498#define bfin_write_DMA33_CURR_Y_COUNT(val) bfin_write32(DMA33_CURR_Y_COUNT, val)
1499#define bfin_read_DMA33_BWL_COUNT() bfin_read32(DMA33_BWL_COUNT)
1500#define bfin_write_DMA33_BWL_COUNT(val) bfin_write32(DMA33_BWL_COUNT, val)
1501#define bfin_read_DMA33_CURR_BWL_COUNT() bfin_read32(DMA33_CURR_BWL_COUNT)
1502#define bfin_write_DMA33_CURR_BWL_COUNT(val) bfin_write32(DMA33_CURR_BWL_COUNT, val)
1503#define bfin_read_DMA33_BWM_COUNT() bfin_read32(DMA33_BWM_COUNT)
1504#define bfin_write_DMA33_BWM_COUNT(val) bfin_write32(DMA33_BWM_COUNT, val)
1505#define bfin_read_DMA33_CURR_BWM_COUNT() bfin_read32(DMA33_CURR_BWM_COUNT)
1506#define bfin_write_DMA33_CURR_BWM_COUNT(val) bfin_write32(DMA33_CURR_BWM_COUNT, val)
1507
1508/* DMA Channel 34 Registers */
1509
1510#define bfin_read_DMA34_NEXT_DESC_PTR() bfin_read32(DMA34_NEXT_DESC_PTR)
1511#define bfin_write_DMA34_NEXT_DESC_PTR(val) bfin_write32(DMA34_NEXT_DESC_PTR, val)
1512#define bfin_read_DMA34_START_ADDR() bfin_read32(DMA34_START_ADDR)
1513#define bfin_write_DMA34_START_ADDR(val) bfin_write32(DMA34_START_ADDR, val)
1514#define bfin_read_DMA34_CONFIG() bfin_read32(DMA34_CONFIG)
1515#define bfin_write_DMA34_CONFIG(val) bfin_write32(DMA34_CONFIG, val)
1516#define bfin_read_DMA34_X_COUNT() bfin_read32(DMA34_X_COUNT)
1517#define bfin_write_DMA34_X_COUNT(val) bfin_write32(DMA34_X_COUNT, val)
1518#define bfin_read_DMA34_X_MODIFY() bfin_read32(DMA34_X_MODIFY)
1519#define bfin_write_DMA34_X_MODIFY(val) bfin_write32(DMA34_X_MODIFY, val)
1520#define bfin_read_DMA34_Y_COUNT() bfin_read32(DMA34_Y_COUNT)
1521#define bfin_write_DMA34_Y_COUNT(val) bfin_write32(DMA34_Y_COUNT, val)
1522#define bfin_read_DMA34_Y_MODIFY() bfin_read32(DMA34_Y_MODIFY)
1523#define bfin_write_DMA34_Y_MODIFY(val) bfin_write32(DMA34_Y_MODIFY, val)
1524#define bfin_read_DMA34_CURR_DESC_PTR() bfin_read32(DMA34_CURR_DESC_PTR)
1525#define bfin_write_DMA34_CURR_DESC_PTR(val) bfin_write32(DMA34_CURR_DESC_PTR, val)
1526#define bfin_read_DMA34_PREV_DESC_PTR() bfin_read32(DMA34_PREV_DESC_PTR)
1527#define bfin_write_DMA34_PREV_DESC_PTR(val) bfin_write32(DMA34_PREV_DESC_PTR, val)
1528#define bfin_read_DMA34_CURR_ADDR() bfin_read32(DMA34_CURR_ADDR)
1529#define bfin_write_DMA34_CURR_ADDR(val) bfin_write32(DMA34_CURR_ADDR, val)
1530#define bfin_read_DMA34_IRQ_STATUS() bfin_read32(DMA34_IRQ_STATUS)
1531#define bfin_write_DMA34_IRQ_STATUS(val) bfin_write32(DMA34_IRQ_STATUS, val)
1532#define bfin_read_DMA34_CURR_X_COUNT() bfin_read32(DMA34_CURR_X_COUNT)
1533#define bfin_write_DMA34_CURR_X_COUNT(val) bfin_write32(DMA34_CURR_X_COUNT, val)
1534#define bfin_read_DMA34_CURR_Y_COUNT() bfin_read32(DMA34_CURR_Y_COUNT)
1535#define bfin_write_DMA34_CURR_Y_COUNT(val) bfin_write32(DMA34_CURR_Y_COUNT, val)
1536#define bfin_read_DMA34_BWL_COUNT() bfin_read32(DMA34_BWL_COUNT)
1537#define bfin_write_DMA34_BWL_COUNT(val) bfin_write32(DMA34_BWL_COUNT, val)
1538#define bfin_read_DMA34_CURR_BWL_COUNT() bfin_read32(DMA34_CURR_BWL_COUNT)
1539#define bfin_write_DMA34_CURR_BWL_COUNT(val) bfin_write32(DMA34_CURR_BWL_COUNT, val)
1540#define bfin_read_DMA34_BWM_COUNT() bfin_read32(DMA34_BWM_COUNT)
1541#define bfin_write_DMA34_BWM_COUNT(val) bfin_write32(DMA34_BWM_COUNT, val)
1542#define bfin_read_DMA34_CURR_BWM_COUNT() bfin_read32(DMA34_CURR_BWM_COUNT)
1543#define bfin_write_DMA34_CURR_BWM_COUNT(val) bfin_write32(DMA34_CURR_BWM_COUNT, val)
1544
1545/* DMA Channel 35 Registers */
1546
1547#define bfin_read_DMA35_NEXT_DESC_PTR() bfin_read32(DMA35_NEXT_DESC_PTR)
1548#define bfin_write_DMA35_NEXT_DESC_PTR(val) bfin_write32(DMA35_NEXT_DESC_PTR, val)
1549#define bfin_read_DMA35_START_ADDR() bfin_read32(DMA35_START_ADDR)
1550#define bfin_write_DMA35_START_ADDR(val) bfin_write32(DMA35_START_ADDR, val)
1551#define bfin_read_DMA35_CONFIG() bfin_read32(DMA35_CONFIG)
1552#define bfin_write_DMA35_CONFIG(val) bfin_write32(DMA35_CONFIG, val)
1553#define bfin_read_DMA35_X_COUNT() bfin_read32(DMA35_X_COUNT)
1554#define bfin_write_DMA35_X_COUNT(val) bfin_write32(DMA35_X_COUNT, val)
1555#define bfin_read_DMA35_X_MODIFY() bfin_read32(DMA35_X_MODIFY)
1556#define bfin_write_DMA35_X_MODIFY(val) bfin_write32(DMA35_X_MODIFY, val)
1557#define bfin_read_DMA35_Y_COUNT() bfin_read32(DMA35_Y_COUNT)
1558#define bfin_write_DMA35_Y_COUNT(val) bfin_write32(DMA35_Y_COUNT, val)
1559#define bfin_read_DMA35_Y_MODIFY() bfin_read32(DMA35_Y_MODIFY)
1560#define bfin_write_DMA35_Y_MODIFY(val) bfin_write32(DMA35_Y_MODIFY, val)
1561#define bfin_read_DMA35_CURR_DESC_PTR() bfin_read32(DMA35_CURR_DESC_PTR)
1562#define bfin_write_DMA35_CURR_DESC_PTR(val) bfin_write32(DMA35_CURR_DESC_PTR, val)
1563#define bfin_read_DMA35_PREV_DESC_PTR() bfin_read32(DMA35_PREV_DESC_PTR)
1564#define bfin_write_DMA35_PREV_DESC_PTR(val) bfin_write32(DMA35_PREV_DESC_PTR, val)
1565#define bfin_read_DMA35_CURR_ADDR() bfin_read32(DMA35_CURR_ADDR)
1566#define bfin_write_DMA35_CURR_ADDR(val) bfin_write32(DMA35_CURR_ADDR, val)
1567#define bfin_read_DMA35_IRQ_STATUS() bfin_read32(DMA35_IRQ_STATUS)
1568#define bfin_write_DMA35_IRQ_STATUS(val) bfin_write32(DMA35_IRQ_STATUS, val)
1569#define bfin_read_DMA35_CURR_X_COUNT() bfin_read32(DMA35_CURR_X_COUNT)
1570#define bfin_write_DMA35_CURR_X_COUNT(val) bfin_write32(DMA35_CURR_X_COUNT, val)
1571#define bfin_read_DMA35_CURR_Y_COUNT() bfin_read32(DMA35_CURR_Y_COUNT)
1572#define bfin_write_DMA35_CURR_Y_COUNT(val) bfin_write32(DMA35_CURR_Y_COUNT, val)
1573#define bfin_read_DMA35_BWL_COUNT() bfin_read32(DMA35_BWL_COUNT)
1574#define bfin_write_DMA35_BWL_COUNT(val) bfin_write32(DMA35_BWL_COUNT, val)
1575#define bfin_read_DMA35_CURR_BWL_COUNT() bfin_read32(DMA35_CURR_BWL_COUNT)
1576#define bfin_write_DMA35_CURR_BWL_COUNT(val) bfin_write32(DMA35_CURR_BWL_COUNT, val)
1577#define bfin_read_DMA35_BWM_COUNT() bfin_read32(DMA35_BWM_COUNT)
1578#define bfin_write_DMA35_BWM_COUNT(val) bfin_write32(DMA35_BWM_COUNT, val)
1579#define bfin_read_DMA35_CURR_BWM_COUNT() bfin_read32(DMA35_CURR_BWM_COUNT)
1580#define bfin_write_DMA35_CURR_BWM_COUNT(val) bfin_write32(DMA35_CURR_BWM_COUNT, val)
1581
1582/* DMA Channel 36 Registers */
1583
1584#define bfin_read_DMA36_NEXT_DESC_PTR() bfin_read32(DMA36_NEXT_DESC_PTR)
1585#define bfin_write_DMA36_NEXT_DESC_PTR(val) bfin_write32(DMA36_NEXT_DESC_PTR, val)
1586#define bfin_read_DMA36_START_ADDR() bfin_read32(DMA36_START_ADDR)
1587#define bfin_write_DMA36_START_ADDR(val) bfin_write32(DMA36_START_ADDR, val)
1588#define bfin_read_DMA36_CONFIG() bfin_read32(DMA36_CONFIG)
1589#define bfin_write_DMA36_CONFIG(val) bfin_write32(DMA36_CONFIG, val)
1590#define bfin_read_DMA36_X_COUNT() bfin_read32(DMA36_X_COUNT)
1591#define bfin_write_DMA36_X_COUNT(val) bfin_write32(DMA36_X_COUNT, val)
1592#define bfin_read_DMA36_X_MODIFY() bfin_read32(DMA36_X_MODIFY)
1593#define bfin_write_DMA36_X_MODIFY(val) bfin_write32(DMA36_X_MODIFY, val)
1594#define bfin_read_DMA36_Y_COUNT() bfin_read32(DMA36_Y_COUNT)
1595#define bfin_write_DMA36_Y_COUNT(val) bfin_write32(DMA36_Y_COUNT, val)
1596#define bfin_read_DMA36_Y_MODIFY() bfin_read32(DMA36_Y_MODIFY)
1597#define bfin_write_DMA36_Y_MODIFY(val) bfin_write32(DMA36_Y_MODIFY, val)
1598#define bfin_read_DMA36_CURR_DESC_PTR() bfin_read32(DMA36_CURR_DESC_PTR)
1599#define bfin_write_DMA36_CURR_DESC_PTR(val) bfin_write32(DMA36_CURR_DESC_PTR, val)
1600#define bfin_read_DMA36_PREV_DESC_PTR() bfin_read32(DMA36_PREV_DESC_PTR)
1601#define bfin_write_DMA36_PREV_DESC_PTR(val) bfin_write32(DMA36_PREV_DESC_PTR, val)
1602#define bfin_read_DMA36_CURR_ADDR() bfin_read32(DMA36_CURR_ADDR)
1603#define bfin_write_DMA36_CURR_ADDR(val) bfin_write32(DMA36_CURR_ADDR, val)
1604#define bfin_read_DMA36_IRQ_STATUS() bfin_read32(DMA36_IRQ_STATUS)
1605#define bfin_write_DMA36_IRQ_STATUS(val) bfin_write32(DMA36_IRQ_STATUS, val)
1606#define bfin_read_DMA36_CURR_X_COUNT() bfin_read32(DMA36_CURR_X_COUNT)
1607#define bfin_write_DMA36_CURR_X_COUNT(val) bfin_write32(DMA36_CURR_X_COUNT, val)
1608#define bfin_read_DMA36_CURR_Y_COUNT() bfin_read32(DMA36_CURR_Y_COUNT)
1609#define bfin_write_DMA36_CURR_Y_COUNT(val) bfin_write32(DMA36_CURR_Y_COUNT, val)
1610#define bfin_read_DMA36_BWL_COUNT() bfin_read32(DMA36_BWL_COUNT)
1611#define bfin_write_DMA36_BWL_COUNT(val) bfin_write32(DMA36_BWL_COUNT, val)
1612#define bfin_read_DMA36_CURR_BWL_COUNT() bfin_read32(DMA36_CURR_BWL_COUNT)
1613#define bfin_write_DMA36_CURR_BWL_COUNT(val) bfin_write32(DMA36_CURR_BWL_COUNT, val)
1614#define bfin_read_DMA36_BWM_COUNT() bfin_read32(DMA36_BWM_COUNT)
1615#define bfin_write_DMA36_BWM_COUNT(val) bfin_write32(DMA36_BWM_COUNT, val)
1616#define bfin_read_DMA36_CURR_BWM_COUNT() bfin_read32(DMA36_CURR_BWM_COUNT)
1617#define bfin_write_DMA36_CURR_BWM_COUNT(val) bfin_write32(DMA36_CURR_BWM_COUNT, val)
1618
1619/* DMA Channel 37 Registers */
1620
1621#define bfin_read_DMA37_NEXT_DESC_PTR() bfin_read32(DMA37_NEXT_DESC_PTR)
1622#define bfin_write_DMA37_NEXT_DESC_PTR(val) bfin_write32(DMA37_NEXT_DESC_PTR, val)
1623#define bfin_read_DMA37_START_ADDR() bfin_read32(DMA37_START_ADDR)
1624#define bfin_write_DMA37_START_ADDR(val) bfin_write32(DMA37_START_ADDR, val)
1625#define bfin_read_DMA37_CONFIG() bfin_read32(DMA37_CONFIG)
1626#define bfin_write_DMA37_CONFIG(val) bfin_write32(DMA37_CONFIG, val)
1627#define bfin_read_DMA37_X_COUNT() bfin_read32(DMA37_X_COUNT)
1628#define bfin_write_DMA37_X_COUNT(val) bfin_write32(DMA37_X_COUNT, val)
1629#define bfin_read_DMA37_X_MODIFY() bfin_read32(DMA37_X_MODIFY)
1630#define bfin_write_DMA37_X_MODIFY(val) bfin_write32(DMA37_X_MODIFY, val)
1631#define bfin_read_DMA37_Y_COUNT() bfin_read32(DMA37_Y_COUNT)
1632#define bfin_write_DMA37_Y_COUNT(val) bfin_write32(DMA37_Y_COUNT, val)
1633#define bfin_read_DMA37_Y_MODIFY() bfin_read32(DMA37_Y_MODIFY)
1634#define bfin_write_DMA37_Y_MODIFY(val) bfin_write32(DMA37_Y_MODIFY, val)
1635#define bfin_read_DMA37_CURR_DESC_PTR() bfin_read32(DMA37_CURR_DESC_PTR)
1636#define bfin_write_DMA37_CURR_DESC_PTR(val) bfin_write32(DMA37_CURR_DESC_PTR, val)
1637#define bfin_read_DMA37_PREV_DESC_PTR() bfin_read32(DMA37_PREV_DESC_PTR)
1638#define bfin_write_DMA37_PREV_DESC_PTR(val) bfin_write32(DMA37_PREV_DESC_PTR, val)
1639#define bfin_read_DMA37_CURR_ADDR() bfin_read32(DMA37_CURR_ADDR)
1640#define bfin_write_DMA37_CURR_ADDR(val) bfin_write32(DMA37_CURR_ADDR, val)
1641#define bfin_read_DMA37_IRQ_STATUS() bfin_read32(DMA37_IRQ_STATUS)
1642#define bfin_write_DMA37_IRQ_STATUS(val) bfin_write32(DMA37_IRQ_STATUS, val)
1643#define bfin_read_DMA37_CURR_X_COUNT() bfin_read32(DMA37_CURR_X_COUNT)
1644#define bfin_write_DMA37_CURR_X_COUNT(val) bfin_write32(DMA37_CURR_X_COUNT, val)
1645#define bfin_read_DMA37_CURR_Y_COUNT() bfin_read32(DMA37_CURR_Y_COUNT)
1646#define bfin_write_DMA37_CURR_Y_COUNT(val) bfin_write32(DMA37_CURR_Y_COUNT, val)
1647#define bfin_read_DMA37_BWL_COUNT() bfin_read32(DMA37_BWL_COUNT)
1648#define bfin_write_DMA37_BWL_COUNT(val) bfin_write32(DMA37_BWL_COUNT, val)
1649#define bfin_read_DMA37_CURR_BWL_COUNT() bfin_read32(DMA37_CURR_BWL_COUNT)
1650#define bfin_write_DMA37_CURR_BWL_COUNT(val) bfin_write32(DMA37_CURR_BWL_COUNT, val)
1651#define bfin_read_DMA37_BWM_COUNT() bfin_read32(DMA37_BWM_COUNT)
1652#define bfin_write_DMA37_BWM_COUNT(val) bfin_write32(DMA37_BWM_COUNT, val)
1653#define bfin_read_DMA37_CURR_BWM_COUNT() bfin_read32(DMA37_CURR_BWM_COUNT)
1654#define bfin_write_DMA37_CURR_BWM_COUNT(val) bfin_write32(DMA37_CURR_BWM_COUNT, val)
1655
1656/* DMA Channel 38 Registers */
1657
1658#define bfin_read_DMA38_NEXT_DESC_PTR() bfin_read32(DMA38_NEXT_DESC_PTR)
1659#define bfin_write_DMA38_NEXT_DESC_PTR(val) bfin_write32(DMA38_NEXT_DESC_PTR, val)
1660#define bfin_read_DMA38_START_ADDR() bfin_read32(DMA38_START_ADDR)
1661#define bfin_write_DMA38_START_ADDR(val) bfin_write32(DMA38_START_ADDR, val)
1662#define bfin_read_DMA38_CONFIG() bfin_read32(DMA38_CONFIG)
1663#define bfin_write_DMA38_CONFIG(val) bfin_write32(DMA38_CONFIG, val)
1664#define bfin_read_DMA38_X_COUNT() bfin_read32(DMA38_X_COUNT)
1665#define bfin_write_DMA38_X_COUNT(val) bfin_write32(DMA38_X_COUNT, val)
1666#define bfin_read_DMA38_X_MODIFY() bfin_read32(DMA38_X_MODIFY)
1667#define bfin_write_DMA38_X_MODIFY(val) bfin_write32(DMA38_X_MODIFY, val)
1668#define bfin_read_DMA38_Y_COUNT() bfin_read32(DMA38_Y_COUNT)
1669#define bfin_write_DMA38_Y_COUNT(val) bfin_write32(DMA38_Y_COUNT, val)
1670#define bfin_read_DMA38_Y_MODIFY() bfin_read32(DMA38_Y_MODIFY)
1671#define bfin_write_DMA38_Y_MODIFY(val) bfin_write32(DMA38_Y_MODIFY, val)
1672#define bfin_read_DMA38_CURR_DESC_PTR() bfin_read32(DMA38_CURR_DESC_PTR)
1673#define bfin_write_DMA38_CURR_DESC_PTR(val) bfin_write32(DMA38_CURR_DESC_PTR, val)
1674#define bfin_read_DMA38_PREV_DESC_PTR() bfin_read32(DMA38_PREV_DESC_PTR)
1675#define bfin_write_DMA38_PREV_DESC_PTR(val) bfin_write32(DMA38_PREV_DESC_PTR, val)
1676#define bfin_read_DMA38_CURR_ADDR() bfin_read32(DMA38_CURR_ADDR)
1677#define bfin_write_DMA38_CURR_ADDR(val) bfin_write32(DMA38_CURR_ADDR, val)
1678#define bfin_read_DMA38_IRQ_STATUS() bfin_read32(DMA38_IRQ_STATUS)
1679#define bfin_write_DMA38_IRQ_STATUS(val) bfin_write32(DMA38_IRQ_STATUS, val)
1680#define bfin_read_DMA38_CURR_X_COUNT() bfin_read32(DMA38_CURR_X_COUNT)
1681#define bfin_write_DMA38_CURR_X_COUNT(val) bfin_write32(DMA38_CURR_X_COUNT, val)
1682#define bfin_read_DMA38_CURR_Y_COUNT() bfin_read32(DMA38_CURR_Y_COUNT)
1683#define bfin_write_DMA38_CURR_Y_COUNT(val) bfin_write32(DMA38_CURR_Y_COUNT, val)
1684#define bfin_read_DMA38_BWL_COUNT() bfin_read32(DMA38_BWL_COUNT)
1685#define bfin_write_DMA38_BWL_COUNT(val) bfin_write32(DMA38_BWL_COUNT, val)
1686#define bfin_read_DMA38_CURR_BWL_COUNT() bfin_read32(DMA38_CURR_BWL_COUNT)
1687#define bfin_write_DMA38_CURR_BWL_COUNT(val) bfin_write32(DMA38_CURR_BWL_COUNT, val)
1688#define bfin_read_DMA38_BWM_COUNT() bfin_read32(DMA38_BWM_COUNT)
1689#define bfin_write_DMA38_BWM_COUNT(val) bfin_write32(DMA38_BWM_COUNT, val)
1690#define bfin_read_DMA38_CURR_BWM_COUNT() bfin_read32(DMA38_CURR_BWM_COUNT)
1691#define bfin_write_DMA38_CURR_BWM_COUNT(val) bfin_write32(DMA38_CURR_BWM_COUNT, val)
1692
1693/* DMA Channel 39 Registers */
1694
1695#define bfin_read_DMA39_NEXT_DESC_PTR() bfin_read32(DMA39_NEXT_DESC_PTR)
1696#define bfin_write_DMA39_NEXT_DESC_PTR(val) bfin_write32(DMA39_NEXT_DESC_PTR, val)
1697#define bfin_read_DMA39_START_ADDR() bfin_read32(DMA39_START_ADDR)
1698#define bfin_write_DMA39_START_ADDR(val) bfin_write32(DMA39_START_ADDR, val)
1699#define bfin_read_DMA39_CONFIG() bfin_read32(DMA39_CONFIG)
1700#define bfin_write_DMA39_CONFIG(val) bfin_write32(DMA39_CONFIG, val)
1701#define bfin_read_DMA39_X_COUNT() bfin_read32(DMA39_X_COUNT)
1702#define bfin_write_DMA39_X_COUNT(val) bfin_write32(DMA39_X_COUNT, val)
1703#define bfin_read_DMA39_X_MODIFY() bfin_read32(DMA39_X_MODIFY)
1704#define bfin_write_DMA39_X_MODIFY(val) bfin_write32(DMA39_X_MODIFY, val)
1705#define bfin_read_DMA39_Y_COUNT() bfin_read32(DMA39_Y_COUNT)
1706#define bfin_write_DMA39_Y_COUNT(val) bfin_write32(DMA39_Y_COUNT, val)
1707#define bfin_read_DMA39_Y_MODIFY() bfin_read32(DMA39_Y_MODIFY)
1708#define bfin_write_DMA39_Y_MODIFY(val) bfin_write32(DMA39_Y_MODIFY, val)
1709#define bfin_read_DMA39_CURR_DESC_PTR() bfin_read32(DMA39_CURR_DESC_PTR)
1710#define bfin_write_DMA39_CURR_DESC_PTR(val) bfin_write32(DMA39_CURR_DESC_PTR, val)
1711#define bfin_read_DMA39_PREV_DESC_PTR() bfin_read32(DMA39_PREV_DESC_PTR)
1712#define bfin_write_DMA39_PREV_DESC_PTR(val) bfin_write32(DMA39_PREV_DESC_PTR, val)
1713#define bfin_read_DMA39_CURR_ADDR() bfin_read32(DMA39_CURR_ADDR)
1714#define bfin_write_DMA39_CURR_ADDR(val) bfin_write32(DMA39_CURR_ADDR, val)
1715#define bfin_read_DMA39_IRQ_STATUS() bfin_read32(DMA39_IRQ_STATUS)
1716#define bfin_write_DMA39_IRQ_STATUS(val) bfin_write32(DMA39_IRQ_STATUS, val)
1717#define bfin_read_DMA39_CURR_X_COUNT() bfin_read32(DMA39_CURR_X_COUNT)
1718#define bfin_write_DMA39_CURR_X_COUNT(val) bfin_write32(DMA39_CURR_X_COUNT, val)
1719#define bfin_read_DMA39_CURR_Y_COUNT() bfin_read32(DMA39_CURR_Y_COUNT)
1720#define bfin_write_DMA39_CURR_Y_COUNT(val) bfin_write32(DMA39_CURR_Y_COUNT, val)
1721#define bfin_read_DMA39_BWL_COUNT() bfin_read32(DMA39_BWL_COUNT)
1722#define bfin_write_DMA39_BWL_COUNT(val) bfin_write32(DMA39_BWL_COUNT, val)
1723#define bfin_read_DMA39_CURR_BWL_COUNT() bfin_read32(DMA39_CURR_BWL_COUNT)
1724#define bfin_write_DMA39_CURR_BWL_COUNT(val) bfin_write32(DMA39_CURR_BWL_COUNT, val)
1725#define bfin_read_DMA39_BWM_COUNT() bfin_read32(DMA39_BWM_COUNT)
1726#define bfin_write_DMA39_BWM_COUNT(val) bfin_write32(DMA39_BWM_COUNT, val)
1727#define bfin_read_DMA39_CURR_BWM_COUNT() bfin_read32(DMA39_CURR_BWM_COUNT)
1728#define bfin_write_DMA39_CURR_BWM_COUNT(val) bfin_write32(DMA39_CURR_BWM_COUNT, val)
1729
1730/* DMA Channel 40 Registers */
1731
1732#define bfin_read_DMA40_NEXT_DESC_PTR() bfin_read32(DMA40_NEXT_DESC_PTR)
1733#define bfin_write_DMA40_NEXT_DESC_PTR(val) bfin_write32(DMA40_NEXT_DESC_PTR, val)
1734#define bfin_read_DMA40_START_ADDR() bfin_read32(DMA40_START_ADDR)
1735#define bfin_write_DMA40_START_ADDR(val) bfin_write32(DMA40_START_ADDR, val)
1736#define bfin_read_DMA40_CONFIG() bfin_read32(DMA40_CONFIG)
1737#define bfin_write_DMA40_CONFIG(val) bfin_write32(DMA40_CONFIG, val)
1738#define bfin_read_DMA40_X_COUNT() bfin_read32(DMA40_X_COUNT)
1739#define bfin_write_DMA40_X_COUNT(val) bfin_write32(DMA40_X_COUNT, val)
1740#define bfin_read_DMA40_X_MODIFY() bfin_read32(DMA40_X_MODIFY)
1741#define bfin_write_DMA40_X_MODIFY(val) bfin_write32(DMA40_X_MODIFY, val)
1742#define bfin_read_DMA40_Y_COUNT() bfin_read32(DMA40_Y_COUNT)
1743#define bfin_write_DMA40_Y_COUNT(val) bfin_write32(DMA40_Y_COUNT, val)
1744#define bfin_read_DMA40_Y_MODIFY() bfin_read32(DMA40_Y_MODIFY)
1745#define bfin_write_DMA40_Y_MODIFY(val) bfin_write32(DMA40_Y_MODIFY, val)
1746#define bfin_read_DMA40_CURR_DESC_PTR() bfin_read32(DMA40_CURR_DESC_PTR)
1747#define bfin_write_DMA40_CURR_DESC_PTR(val) bfin_write32(DMA40_CURR_DESC_PTR, val)
1748#define bfin_read_DMA40_PREV_DESC_PTR() bfin_read32(DMA40_PREV_DESC_PTR)
1749#define bfin_write_DMA40_PREV_DESC_PTR(val) bfin_write32(DMA40_PREV_DESC_PTR, val)
1750#define bfin_read_DMA40_CURR_ADDR() bfin_read32(DMA40_CURR_ADDR)
1751#define bfin_write_DMA40_CURR_ADDR(val) bfin_write32(DMA40_CURR_ADDR, val)
1752#define bfin_read_DMA40_IRQ_STATUS() bfin_read32(DMA40_IRQ_STATUS)
1753#define bfin_write_DMA40_IRQ_STATUS(val) bfin_write32(DMA40_IRQ_STATUS, val)
1754#define bfin_read_DMA40_CURR_X_COUNT() bfin_read32(DMA40_CURR_X_COUNT)
1755#define bfin_write_DMA40_CURR_X_COUNT(val) bfin_write32(DMA40_CURR_X_COUNT, val)
1756#define bfin_read_DMA40_CURR_Y_COUNT() bfin_read32(DMA40_CURR_Y_COUNT)
1757#define bfin_write_DMA40_CURR_Y_COUNT(val) bfin_write32(DMA40_CURR_Y_COUNT, val)
1758#define bfin_read_DMA40_BWL_COUNT() bfin_read32(DMA40_BWL_COUNT)
1759#define bfin_write_DMA40_BWL_COUNT(val) bfin_write32(DMA40_BWL_COUNT, val)
1760#define bfin_read_DMA40_CURR_BWL_COUNT() bfin_read32(DMA40_CURR_BWL_COUNT)
1761#define bfin_write_DMA40_CURR_BWL_COUNT(val) bfin_write32(DMA40_CURR_BWL_COUNT, val)
1762#define bfin_read_DMA40_BWM_COUNT() bfin_read32(DMA40_BWM_COUNT)
1763#define bfin_write_DMA40_BWM_COUNT(val) bfin_write32(DMA40_BWM_COUNT, val)
1764#define bfin_read_DMA40_CURR_BWM_COUNT() bfin_read32(DMA40_CURR_BWM_COUNT)
1765#define bfin_write_DMA40_CURR_BWM_COUNT(val) bfin_write32(DMA40_CURR_BWM_COUNT, val)
1766
1767/* DMA Channel 41 Registers */
1768
1769#define bfin_read_DMA41_NEXT_DESC_PTR() bfin_read32(DMA41_NEXT_DESC_PTR)
1770#define bfin_write_DMA41_NEXT_DESC_PTR(val) bfin_write32(DMA41_NEXT_DESC_PTR, val)
1771#define bfin_read_DMA41_START_ADDR() bfin_read32(DMA41_START_ADDR)
1772#define bfin_write_DMA41_START_ADDR(val) bfin_write32(DMA41_START_ADDR, val)
1773#define bfin_read_DMA41_CONFIG() bfin_read32(DMA41_CONFIG)
1774#define bfin_write_DMA41_CONFIG(val) bfin_write32(DMA41_CONFIG, val)
1775#define bfin_read_DMA41_X_COUNT() bfin_read32(DMA41_X_COUNT)
1776#define bfin_write_DMA41_X_COUNT(val) bfin_write32(DMA41_X_COUNT, val)
1777#define bfin_read_DMA41_X_MODIFY() bfin_read32(DMA41_X_MODIFY)
1778#define bfin_write_DMA41_X_MODIFY(val) bfin_write32(DMA41_X_MODIFY, val)
1779#define bfin_read_DMA41_Y_COUNT() bfin_read32(DMA41_Y_COUNT)
1780#define bfin_write_DMA41_Y_COUNT(val) bfin_write32(DMA41_Y_COUNT, val)
1781#define bfin_read_DMA41_Y_MODIFY() bfin_read32(DMA41_Y_MODIFY)
1782#define bfin_write_DMA41_Y_MODIFY(val) bfin_write32(DMA41_Y_MODIFY, val)
1783#define bfin_read_DMA41_CURR_DESC_PTR() bfin_read32(DMA41_CURR_DESC_PTR)
1784#define bfin_write_DMA41_CURR_DESC_PTR(val) bfin_write32(DMA41_CURR_DESC_PTR, val)
1785#define bfin_read_DMA41_PREV_DESC_PTR() bfin_read32(DMA41_PREV_DESC_PTR)
1786#define bfin_write_DMA41_PREV_DESC_PTR(val) bfin_write32(DMA41_PREV_DESC_PTR, val)
1787#define bfin_read_DMA41_CURR_ADDR() bfin_read32(DMA41_CURR_ADDR)
1788#define bfin_write_DMA41_CURR_ADDR(val) bfin_write32(DMA41_CURR_ADDR, val)
1789#define bfin_read_DMA41_IRQ_STATUS() bfin_read32(DMA41_IRQ_STATUS)
1790#define bfin_write_DMA41_IRQ_STATUS(val) bfin_write32(DMA41_IRQ_STATUS, val)
1791#define bfin_read_DMA41_CURR_X_COUNT() bfin_read32(DMA41_CURR_X_COUNT)
1792#define bfin_write_DMA41_CURR_X_COUNT(val) bfin_write32(DMA41_CURR_X_COUNT, val)
1793#define bfin_read_DMA41_CURR_Y_COUNT() bfin_read32(DMA41_CURR_Y_COUNT)
1794#define bfin_write_DMA41_CURR_Y_COUNT(val) bfin_write32(DMA41_CURR_Y_COUNT, val)
1795#define bfin_read_DMA41_BWL_COUNT() bfin_read32(DMA41_BWL_COUNT)
1796#define bfin_write_DMA41_BWL_COUNT(val) bfin_write32(DMA41_BWL_COUNT, val)
1797#define bfin_read_DMA41_CURR_BWL_COUNT() bfin_read32(DMA41_CURR_BWL_COUNT)
1798#define bfin_write_DMA41_CURR_BWL_COUNT(val) bfin_write32(DMA41_CURR_BWL_COUNT, val)
1799#define bfin_read_DMA41_BWM_COUNT() bfin_read32(DMA41_BWM_COUNT)
1800#define bfin_write_DMA41_BWM_COUNT(val) bfin_write32(DMA41_BWM_COUNT, val)
1801#define bfin_read_DMA41_CURR_BWM_COUNT() bfin_read32(DMA41_CURR_BWM_COUNT)
1802#define bfin_write_DMA41_CURR_BWM_COUNT(val) bfin_write32(DMA41_CURR_BWM_COUNT, val)
1803
1804/* DMA Channel 42 Registers */
1805
1806#define bfin_read_DMA42_NEXT_DESC_PTR() bfin_read32(DMA42_NEXT_DESC_PTR)
1807#define bfin_write_DMA42_NEXT_DESC_PTR(val) bfin_write32(DMA42_NEXT_DESC_PTR, val)
1808#define bfin_read_DMA42_START_ADDR() bfin_read32(DMA42_START_ADDR)
1809#define bfin_write_DMA42_START_ADDR(val) bfin_write32(DMA42_START_ADDR, val)
1810#define bfin_read_DMA42_CONFIG() bfin_read32(DMA42_CONFIG)
1811#define bfin_write_DMA42_CONFIG(val) bfin_write32(DMA42_CONFIG, val)
1812#define bfin_read_DMA42_X_COUNT() bfin_read32(DMA42_X_COUNT)
1813#define bfin_write_DMA42_X_COUNT(val) bfin_write32(DMA42_X_COUNT, val)
1814#define bfin_read_DMA42_X_MODIFY() bfin_read32(DMA42_X_MODIFY)
1815#define bfin_write_DMA42_X_MODIFY(val) bfin_write32(DMA42_X_MODIFY, val)
1816#define bfin_read_DMA42_Y_COUNT() bfin_read32(DMA42_Y_COUNT)
1817#define bfin_write_DMA42_Y_COUNT(val) bfin_write32(DMA42_Y_COUNT, val)
1818#define bfin_read_DMA42_Y_MODIFY() bfin_read32(DMA42_Y_MODIFY)
1819#define bfin_write_DMA42_Y_MODIFY(val) bfin_write32(DMA42_Y_MODIFY, val)
1820#define bfin_read_DMA42_CURR_DESC_PTR() bfin_read32(DMA42_CURR_DESC_PTR)
1821#define bfin_write_DMA42_CURR_DESC_PTR(val) bfin_write32(DMA42_CURR_DESC_PTR, val)
1822#define bfin_read_DMA42_PREV_DESC_PTR() bfin_read32(DMA42_PREV_DESC_PTR)
1823#define bfin_write_DMA42_PREV_DESC_PTR(val) bfin_write32(DMA42_PREV_DESC_PTR, val)
1824#define bfin_read_DMA42_CURR_ADDR() bfin_read32(DMA42_CURR_ADDR)
1825#define bfin_write_DMA42_CURR_ADDR(val) bfin_write32(DMA42_CURR_ADDR, val)
1826#define bfin_read_DMA42_IRQ_STATUS() bfin_read32(DMA42_IRQ_STATUS)
1827#define bfin_write_DMA42_IRQ_STATUS(val) bfin_write32(DMA42_IRQ_STATUS, val)
1828#define bfin_read_DMA42_CURR_X_COUNT() bfin_read32(DMA42_CURR_X_COUNT)
1829#define bfin_write_DMA42_CURR_X_COUNT(val) bfin_write32(DMA42_CURR_X_COUNT, val)
1830#define bfin_read_DMA42_CURR_Y_COUNT() bfin_read32(DMA42_CURR_Y_COUNT)
1831#define bfin_write_DMA42_CURR_Y_COUNT(val) bfin_write32(DMA42_CURR_Y_COUNT, val)
1832#define bfin_read_DMA42_BWL_COUNT() bfin_read32(DMA42_BWL_COUNT)
1833#define bfin_write_DMA42_BWL_COUNT(val) bfin_write32(DMA42_BWL_COUNT, val)
1834#define bfin_read_DMA42_CURR_BWL_COUNT() bfin_read32(DMA42_CURR_BWL_COUNT)
1835#define bfin_write_DMA42_CURR_BWL_COUNT(val) bfin_write32(DMA42_CURR_BWL_COUNT, val)
1836#define bfin_read_DMA42_BWM_COUNT() bfin_read32(DMA42_BWM_COUNT)
1837#define bfin_write_DMA42_BWM_COUNT(val) bfin_write32(DMA42_BWM_COUNT, val)
1838#define bfin_read_DMA42_CURR_BWM_COUNT() bfin_read32(DMA42_CURR_BWM_COUNT)
1839#define bfin_write_DMA42_CURR_BWM_COUNT(val) bfin_write32(DMA42_CURR_BWM_COUNT, val)
1840
1841/* DMA Channel 43 Registers */
1842
1843#define bfin_read_DMA43_NEXT_DESC_PTR() bfin_read32(DMA43_NEXT_DESC_PTR)
1844#define bfin_write_DMA43_NEXT_DESC_PTR(val) bfin_write32(DMA43_NEXT_DESC_PTR, val)
1845#define bfin_read_DMA43_START_ADDR() bfin_read32(DMA43_START_ADDR)
1846#define bfin_write_DMA43_START_ADDR(val) bfin_write32(DMA43_START_ADDR, val)
1847#define bfin_read_DMA43_CONFIG() bfin_read32(DMA43_CONFIG)
1848#define bfin_write_DMA43_CONFIG(val) bfin_write32(DMA43_CONFIG, val)
1849#define bfin_read_DMA43_X_COUNT() bfin_read32(DMA43_X_COUNT)
1850#define bfin_write_DMA43_X_COUNT(val) bfin_write32(DMA43_X_COUNT, val)
1851#define bfin_read_DMA43_X_MODIFY() bfin_read32(DMA43_X_MODIFY)
1852#define bfin_write_DMA43_X_MODIFY(val) bfin_write32(DMA43_X_MODIFY, val)
1853#define bfin_read_DMA43_Y_COUNT() bfin_read32(DMA43_Y_COUNT)
1854#define bfin_write_DMA43_Y_COUNT(val) bfin_write32(DMA43_Y_COUNT, val)
1855#define bfin_read_DMA43_Y_MODIFY() bfin_read32(DMA43_Y_MODIFY)
1856#define bfin_write_DMA43_Y_MODIFY(val) bfin_write32(DMA43_Y_MODIFY, val)
1857#define bfin_read_DMA43_CURR_DESC_PTR() bfin_read32(DMA43_CURR_DESC_PTR)
1858#define bfin_write_DMA43_CURR_DESC_PTR(val) bfin_write32(DMA43_CURR_DESC_PTR, val)
1859#define bfin_read_DMA43_PREV_DESC_PTR() bfin_read32(DMA43_PREV_DESC_PTR)
1860#define bfin_write_DMA43_PREV_DESC_PTR(val) bfin_write32(DMA43_PREV_DESC_PTR, val)
1861#define bfin_read_DMA43_CURR_ADDR() bfin_read32(DMA43_CURR_ADDR)
1862#define bfin_write_DMA43_CURR_ADDR(val) bfin_write32(DMA43_CURR_ADDR, val)
1863#define bfin_read_DMA43_IRQ_STATUS() bfin_read32(DMA43_IRQ_STATUS)
1864#define bfin_write_DMA43_IRQ_STATUS(val) bfin_write32(DMA43_IRQ_STATUS, val)
1865#define bfin_read_DMA43_CURR_X_COUNT() bfin_read32(DMA43_CURR_X_COUNT)
1866#define bfin_write_DMA43_CURR_X_COUNT(val) bfin_write32(DMA43_CURR_X_COUNT, val)
1867#define bfin_read_DMA43_CURR_Y_COUNT() bfin_read32(DMA43_CURR_Y_COUNT)
1868#define bfin_write_DMA43_CURR_Y_COUNT(val) bfin_write32(DMA43_CURR_Y_COUNT, val)
1869#define bfin_read_DMA43_BWL_COUNT() bfin_read32(DMA43_BWL_COUNT)
1870#define bfin_write_DMA43_BWL_COUNT(val) bfin_write32(DMA43_BWL_COUNT, val)
1871#define bfin_read_DMA43_CURR_BWL_COUNT() bfin_read32(DMA43_CURR_BWL_COUNT)
1872#define bfin_write_DMA43_CURR_BWL_COUNT(val) bfin_write32(DMA43_CURR_BWL_COUNT, val)
1873#define bfin_read_DMA43_BWM_COUNT() bfin_read32(DMA43_BWM_COUNT)
1874#define bfin_write_DMA43_BWM_COUNT(val) bfin_write32(DMA43_BWM_COUNT, val)
1875#define bfin_read_DMA43_CURR_BWM_COUNT() bfin_read32(DMA43_CURR_BWM_COUNT)
1876#define bfin_write_DMA43_CURR_BWM_COUNT(val) bfin_write32(DMA43_CURR_BWM_COUNT, val)
1877
1878/* DMA Channel 44 Registers */
1879
1880#define bfin_read_DMA44_NEXT_DESC_PTR() bfin_read32(DMA44_NEXT_DESC_PTR)
1881#define bfin_write_DMA44_NEXT_DESC_PTR(val) bfin_write32(DMA44_NEXT_DESC_PTR, val)
1882#define bfin_read_DMA44_START_ADDR() bfin_read32(DMA44_START_ADDR)
1883#define bfin_write_DMA44_START_ADDR(val) bfin_write32(DMA44_START_ADDR, val)
1884#define bfin_read_DMA44_CONFIG() bfin_read32(DMA44_CONFIG)
1885#define bfin_write_DMA44_CONFIG(val) bfin_write32(DMA44_CONFIG, val)
1886#define bfin_read_DMA44_X_COUNT() bfin_read32(DMA44_X_COUNT)
1887#define bfin_write_DMA44_X_COUNT(val) bfin_write32(DMA44_X_COUNT, val)
1888#define bfin_read_DMA44_X_MODIFY() bfin_read32(DMA44_X_MODIFY)
1889#define bfin_write_DMA44_X_MODIFY(val) bfin_write32(DMA44_X_MODIFY, val)
1890#define bfin_read_DMA44_Y_COUNT() bfin_read32(DMA44_Y_COUNT)
1891#define bfin_write_DMA44_Y_COUNT(val) bfin_write32(DMA44_Y_COUNT, val)
1892#define bfin_read_DMA44_Y_MODIFY() bfin_read32(DMA44_Y_MODIFY)
1893#define bfin_write_DMA44_Y_MODIFY(val) bfin_write32(DMA44_Y_MODIFY, val)
1894#define bfin_read_DMA44_CURR_DESC_PTR() bfin_read32(DMA44_CURR_DESC_PTR)
1895#define bfin_write_DMA44_CURR_DESC_PTR(val) bfin_write32(DMA44_CURR_DESC_PTR, val)
1896#define bfin_read_DMA44_PREV_DESC_PTR() bfin_read32(DMA44_PREV_DESC_PTR)
1897#define bfin_write_DMA44_PREV_DESC_PTR(val) bfin_write32(DMA44_PREV_DESC_PTR, val)
1898#define bfin_read_DMA44_CURR_ADDR() bfin_read32(DMA44_CURR_ADDR)
1899#define bfin_write_DMA44_CURR_ADDR(val) bfin_write32(DMA44_CURR_ADDR, val)
1900#define bfin_read_DMA44_IRQ_STATUS() bfin_read32(DMA44_IRQ_STATUS)
1901#define bfin_write_DMA44_IRQ_STATUS(val) bfin_write32(DMA44_IRQ_STATUS, val)
1902#define bfin_read_DMA44_CURR_X_COUNT() bfin_read32(DMA44_CURR_X_COUNT)
1903#define bfin_write_DMA44_CURR_X_COUNT(val) bfin_write32(DMA44_CURR_X_COUNT, val)
1904#define bfin_read_DMA44_CURR_Y_COUNT() bfin_read32(DMA44_CURR_Y_COUNT)
1905#define bfin_write_DMA44_CURR_Y_COUNT(val) bfin_write32(DMA44_CURR_Y_COUNT, val)
1906#define bfin_read_DMA44_BWL_COUNT() bfin_read32(DMA44_BWL_COUNT)
1907#define bfin_write_DMA44_BWL_COUNT(val) bfin_write32(DMA44_BWL_COUNT, val)
1908#define bfin_read_DMA44_CURR_BWL_COUNT() bfin_read32(DMA44_CURR_BWL_COUNT)
1909#define bfin_write_DMA44_CURR_BWL_COUNT(val) bfin_write32(DMA44_CURR_BWL_COUNT, val)
1910#define bfin_read_DMA44_BWM_COUNT() bfin_read32(DMA44_BWM_COUNT)
1911#define bfin_write_DMA44_BWM_COUNT(val) bfin_write32(DMA44_BWM_COUNT, val)
1912#define bfin_read_DMA44_CURR_BWM_COUNT() bfin_read32(DMA44_CURR_BWM_COUNT)
1913#define bfin_write_DMA44_CURR_BWM_COUNT(val) bfin_write32(DMA44_CURR_BWM_COUNT, val)
1914
1915/* DMA Channel 45 Registers */
1916
1917#define bfin_read_DMA45_NEXT_DESC_PTR() bfin_read32(DMA45_NEXT_DESC_PTR)
1918#define bfin_write_DMA45_NEXT_DESC_PTR(val) bfin_write32(DMA45_NEXT_DESC_PTR, val)
1919#define bfin_read_DMA45_START_ADDR() bfin_read32(DMA45_START_ADDR)
1920#define bfin_write_DMA45_START_ADDR(val) bfin_write32(DMA45_START_ADDR, val)
1921#define bfin_read_DMA45_CONFIG() bfin_read32(DMA45_CONFIG)
1922#define bfin_write_DMA45_CONFIG(val) bfin_write32(DMA45_CONFIG, val)
1923#define bfin_read_DMA45_X_COUNT() bfin_read32(DMA45_X_COUNT)
1924#define bfin_write_DMA45_X_COUNT(val) bfin_write32(DMA45_X_COUNT, val)
1925#define bfin_read_DMA45_X_MODIFY() bfin_read32(DMA45_X_MODIFY)
1926#define bfin_write_DMA45_X_MODIFY(val) bfin_write32(DMA45_X_MODIFY, val)
1927#define bfin_read_DMA45_Y_COUNT() bfin_read32(DMA45_Y_COUNT)
1928#define bfin_write_DMA45_Y_COUNT(val) bfin_write32(DMA45_Y_COUNT, val)
1929#define bfin_read_DMA45_Y_MODIFY() bfin_read32(DMA45_Y_MODIFY)
1930#define bfin_write_DMA45_Y_MODIFY(val) bfin_write32(DMA45_Y_MODIFY, val)
1931#define bfin_read_DMA45_CURR_DESC_PTR() bfin_read32(DMA45_CURR_DESC_PTR)
1932#define bfin_write_DMA45_CURR_DESC_PTR(val) bfin_write32(DMA45_CURR_DESC_PTR, val)
1933#define bfin_read_DMA45_PREV_DESC_PTR() bfin_read32(DMA45_PREV_DESC_PTR)
1934#define bfin_write_DMA45_PREV_DESC_PTR(val) bfin_write32(DMA45_PREV_DESC_PTR, val)
1935#define bfin_read_DMA45_CURR_ADDR() bfin_read32(DMA45_CURR_ADDR)
1936#define bfin_write_DMA45_CURR_ADDR(val) bfin_write32(DMA45_CURR_ADDR, val)
1937#define bfin_read_DMA45_IRQ_STATUS() bfin_read32(DMA45_IRQ_STATUS)
1938#define bfin_write_DMA45_IRQ_STATUS(val) bfin_write32(DMA45_IRQ_STATUS, val)
1939#define bfin_read_DMA45_CURR_X_COUNT() bfin_read32(DMA45_CURR_X_COUNT)
1940#define bfin_write_DMA45_CURR_X_COUNT(val) bfin_write32(DMA45_CURR_X_COUNT, val)
1941#define bfin_read_DMA45_CURR_Y_COUNT() bfin_read32(DMA45_CURR_Y_COUNT)
1942#define bfin_write_DMA45_CURR_Y_COUNT(val) bfin_write32(DMA45_CURR_Y_COUNT, val)
1943#define bfin_read_DMA45_BWL_COUNT() bfin_read32(DMA45_BWL_COUNT)
1944#define bfin_write_DMA45_BWL_COUNT(val) bfin_write32(DMA45_BWL_COUNT, val)
1945#define bfin_read_DMA45_CURR_BWL_COUNT() bfin_read32(DMA45_CURR_BWL_COUNT)
1946#define bfin_write_DMA45_CURR_BWL_COUNT(val) bfin_write32(DMA45_CURR_BWL_COUNT, val)
1947#define bfin_read_DMA45_BWM_COUNT() bfin_read32(DMA45_BWM_COUNT)
1948#define bfin_write_DMA45_BWM_COUNT(val) bfin_write32(DMA45_BWM_COUNT, val)
1949#define bfin_read_DMA45_CURR_BWM_COUNT() bfin_read32(DMA45_CURR_BWM_COUNT)
1950#define bfin_write_DMA45_CURR_BWM_COUNT(val) bfin_write32(DMA45_CURR_BWM_COUNT, val)
1951
1952/* DMA Channel 46 Registers */
1953
1954#define bfin_read_DMA46_NEXT_DESC_PTR() bfin_read32(DMA46_NEXT_DESC_PTR)
1955#define bfin_write_DMA46_NEXT_DESC_PTR(val) bfin_write32(DMA46_NEXT_DESC_PTR, val)
1956#define bfin_read_DMA46_START_ADDR() bfin_read32(DMA46_START_ADDR)
1957#define bfin_write_DMA46_START_ADDR(val) bfin_write32(DMA46_START_ADDR, val)
1958#define bfin_read_DMA46_CONFIG() bfin_read32(DMA46_CONFIG)
1959#define bfin_write_DMA46_CONFIG(val) bfin_write32(DMA46_CONFIG, val)
1960#define bfin_read_DMA46_X_COUNT() bfin_read32(DMA46_X_COUNT)
1961#define bfin_write_DMA46_X_COUNT(val) bfin_write32(DMA46_X_COUNT, val)
1962#define bfin_read_DMA46_X_MODIFY() bfin_read32(DMA46_X_MODIFY)
1963#define bfin_write_DMA46_X_MODIFY(val) bfin_write32(DMA46_X_MODIFY, val)
1964#define bfin_read_DMA46_Y_COUNT() bfin_read32(DMA46_Y_COUNT)
1965#define bfin_write_DMA46_Y_COUNT(val) bfin_write32(DMA46_Y_COUNT, val)
1966#define bfin_read_DMA46_Y_MODIFY() bfin_read32(DMA46_Y_MODIFY)
1967#define bfin_write_DMA46_Y_MODIFY(val) bfin_write32(DMA46_Y_MODIFY, val)
1968#define bfin_read_DMA46_CURR_DESC_PTR() bfin_read32(DMA46_CURR_DESC_PTR)
1969#define bfin_write_DMA46_CURR_DESC_PTR(val) bfin_write32(DMA46_CURR_DESC_PTR, val)
1970#define bfin_read_DMA46_PREV_DESC_PTR() bfin_read32(DMA46_PREV_DESC_PTR)
1971#define bfin_write_DMA46_PREV_DESC_PTR(val) bfin_write32(DMA46_PREV_DESC_PTR, val)
1972#define bfin_read_DMA46_CURR_ADDR() bfin_read32(DMA46_CURR_ADDR)
1973#define bfin_write_DMA46_CURR_ADDR(val) bfin_write32(DMA46_CURR_ADDR, val)
1974#define bfin_read_DMA46_IRQ_STATUS() bfin_read32(DMA46_IRQ_STATUS)
1975#define bfin_write_DMA46_IRQ_STATUS(val) bfin_write32(DMA46_IRQ_STATUS, val)
1976#define bfin_read_DMA46_CURR_X_COUNT() bfin_read32(DMA46_CURR_X_COUNT)
1977#define bfin_write_DMA46_CURR_X_COUNT(val) bfin_write32(DMA46_CURR_X_COUNT, val)
1978#define bfin_read_DMA46_CURR_Y_COUNT() bfin_read32(DMA46_CURR_Y_COUNT)
1979#define bfin_write_DMA46_CURR_Y_COUNT(val) bfin_write32(DMA46_CURR_Y_COUNT, val)
1980#define bfin_read_DMA46_BWL_COUNT() bfin_read32(DMA46_BWL_COUNT)
1981#define bfin_write_DMA46_BWL_COUNT(val) bfin_write32(DMA46_BWL_COUNT, val)
1982#define bfin_read_DMA46_CURR_BWL_COUNT() bfin_read32(DMA46_CURR_BWL_COUNT)
1983#define bfin_write_DMA46_CURR_BWL_COUNT(val) bfin_write32(DMA46_CURR_BWL_COUNT, val)
1984#define bfin_read_DMA46_BWM_COUNT() bfin_read32(DMA46_BWM_COUNT)
1985#define bfin_write_DMA46_BWM_COUNT(val) bfin_write32(DMA46_BWM_COUNT, val)
1986#define bfin_read_DMA46_CURR_BWM_COUNT() bfin_read32(DMA46_CURR_BWM_COUNT)
1987#define bfin_write_DMA46_CURR_BWM_COUNT(val) bfin_write32(DMA46_CURR_BWM_COUNT, val)
1988
1989
1990/* EPPI1 Registers */
1991
1992
1993/* Port Interrubfin_read_()t 0 Registers (32-bit) */
1994
1995#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
1996#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
1997#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
1998#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
1999#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
2000#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
2001#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
2002#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
2003#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
2004#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
2005#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
2006#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
2007#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
2008#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
2009#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
2010#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
2011#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
2012#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
2013#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
2014#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
2015
2016/* Port Interrubfin_read_()t 1 Registers (32-bit) */
2017
2018#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
2019#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
2020#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
2021#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
2022#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
2023#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
2024#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
2025#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
2026#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
2027#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
2028#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
2029#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
2030#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
2031#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
2032#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
2033#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
2034#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
2035#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
2036#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
2037#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
2038
2039/* Port Interrubfin_read_()t 2 Registers (32-bit) */
2040
2041#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
2042#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
2043#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
2044#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
2045#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
2046#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
2047#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
2048#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
2049#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
2050#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
2051#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
2052#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
2053#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
2054#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
2055#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
2056#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
2057#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
2058#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
2059#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
2060#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
2061
2062/* Port Interrubfin_read_()t 3 Registers (32-bit) */
2063
2064#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
2065#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
2066#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
2067#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
2068#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
2069#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
2070#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
2071#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
2072#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
2073#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
2074#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
2075#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
2076#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
2077#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
2078#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
2079#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
2080#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
2081#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
2082#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
2083#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
2084
2085/* Port Interrubfin_read_()t 4 Registers (32-bit) */
2086
2087#define bfin_read_PINT4_MASK_SET() bfin_read32(PINT4_MASK_SET)
2088#define bfin_write_PINT4_MASK_SET(val) bfin_write32(PINT4_MASK_SET, val)
2089#define bfin_read_PINT4_MASK_CLEAR() bfin_read32(PINT4_MASK_CLEAR)
2090#define bfin_write_PINT4_MASK_CLEAR(val) bfin_write32(PINT4_MASK_CLEAR, val)
2091#define bfin_read_PINT4_REQUEST() bfin_read32(PINT4_REQUEST)
2092#define bfin_write_PINT4_REQUEST(val) bfin_write32(PINT4_REQUEST, val)
2093#define bfin_read_PINT4_ASSIGN() bfin_read32(PINT4_ASSIGN)
2094#define bfin_write_PINT4_ASSIGN(val) bfin_write32(PINT4_ASSIGN, val)
2095#define bfin_read_PINT4_EDGE_SET() bfin_read32(PINT4_EDGE_SET)
2096#define bfin_write_PINT4_EDGE_SET(val) bfin_write32(PINT4_EDGE_SET, val)
2097#define bfin_read_PINT4_EDGE_CLEAR() bfin_read32(PINT4_EDGE_CLEAR)
2098#define bfin_write_PINT4_EDGE_CLEAR(val) bfin_write32(PINT4_EDGE_CLEAR, val)
2099#define bfin_read_PINT4_INVERT_SET() bfin_read32(PINT4_INVERT_SET)
2100#define bfin_write_PINT4_INVERT_SET(val) bfin_write32(PINT4_INVERT_SET, val)
2101#define bfin_read_PINT4_INVERT_CLEAR() bfin_read32(PINT4_INVERT_CLEAR)
2102#define bfin_write_PINT4_INVERT_CLEAR(val) bfin_write32(PINT4_INVERT_CLEAR, val)
2103#define bfin_read_PINT4_PINSTATE() bfin_read32(PINT4_PINSTATE)
2104#define bfin_write_PINT4_PINSTATE(val) bfin_write32(PINT4_PINSTATE, val)
2105#define bfin_read_PINT4_LATCH() bfin_read32(PINT4_LATCH)
2106#define bfin_write_PINT4_LATCH(val) bfin_write32(PINT4_LATCH, val)
2107
2108/* Port Interrubfin_read_()t 5 Registers (32-bit) */
2109
2110#define bfin_read_PINT5_MASK_SET() bfin_read32(PINT5_MASK_SET)
2111#define bfin_write_PINT5_MASK_SET(val) bfin_write32(PINT5_MASK_SET, val)
2112#define bfin_read_PINT5_MASK_CLEAR() bfin_read32(PINT5_MASK_CLEAR)
2113#define bfin_write_PINT5_MASK_CLEAR(val) bfin_write32(PINT5_MASK_CLEAR, val)
2114#define bfin_read_PINT5_REQUEST() bfin_read32(PINT5_REQUEST)
2115#define bfin_write_PINT5_REQUEST(val) bfin_write32(PINT5_REQUEST, val)
2116#define bfin_read_PINT5_ASSIGN() bfin_read32(PINT5_ASSIGN)
2117#define bfin_write_PINT5_ASSIGN(val) bfin_write32(PINT5_ASSIGN, val)
2118#define bfin_read_PINT5_EDGE_SET() bfin_read32(PINT5_EDGE_SET)
2119#define bfin_write_PINT5_EDGE_SET(val) bfin_write32(PINT5_EDGE_SET, val)
2120#define bfin_read_PINT5_EDGE_CLEAR() bfin_read32(PINT5_EDGE_CLEAR)
2121#define bfin_write_PINT5_EDGE_CLEAR(val) bfin_write32(PINT5_EDGE_CLEAR, val)
2122#define bfin_read_PINT5_INVERT_SET() bfin_read32(PINT5_INVERT_SET)
2123#define bfin_write_PINT5_INVERT_SET(val) bfin_write32(PINT5_INVERT_SET, val)
2124#define bfin_read_PINT5_INVERT_CLEAR() bfin_read32(PINT5_INVERT_CLEAR)
2125#define bfin_write_PINT5_INVERT_CLEAR(val) bfin_write32(PINT5_INVERT_CLEAR, val)
2126#define bfin_read_PINT5_PINSTATE() bfin_read32(PINT5_PINSTATE)
2127#define bfin_write_PINT5_PINSTATE(val) bfin_write32(PINT5_PINSTATE, val)
2128#define bfin_read_PINT5_LATCH() bfin_read32(PINT5_LATCH)
2129#define bfin_write_PINT5_LATCH(val) bfin_write32(PINT5_LATCH, val)
2130
2131/* Port A Registers */
2132
2133#define bfin_read_PORTA_FER() bfin_read32(PORTA_FER)
2134#define bfin_write_PORTA_FER(val) bfin_write32(PORTA_FER, val)
2135#define bfin_read_PORTA_FER_SET() bfin_read32(PORTA_FER_SET)
2136#define bfin_write_PORTA_FER_SET(val) bfin_write32(PORTA_FER_SET, val)
2137#define bfin_read_PORTA_FER_CLEAR() bfin_read32(PORTA_FER_CLEAR)
2138#define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val)
2139#define bfin_read_PORTA() bfin_read32(PORTA)
2140#define bfin_write_PORTA(val) bfin_write32(PORTA, val)
2141#define bfin_read_PORTA_SET() bfin_read32(PORTA_SET)
2142#define bfin_write_PORTA_SET(val) bfin_write32(PORTA_SET, val)
2143#define bfin_read_PORTA_CLEAR() bfin_read32(PORTA_CLEAR)
2144#define bfin_write_PORTA_CLEAR(val) bfin_write32(PORTA_CLEAR, val)
2145#define bfin_read_PORTA_DIR() bfin_read32(PORTA_DIR)
2146#define bfin_write_PORTA_DIR(val) bfin_write32(PORTA_DIR, val)
2147#define bfin_read_PORTA_DIR_SET() bfin_read32(PORTA_DIR_SET)
2148#define bfin_write_PORTA_DIR_SET(val) bfin_write32(PORTA_DIR_SET, val)
2149#define bfin_read_PORTA_DIR_CLEAR() bfin_read32(PORTA_DIR_CLEAR)
2150#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val)
2151#define bfin_read_PORTA_INEN() bfin_read32(PORTA_INEN)
2152#define bfin_write_PORTA_INEN(val) bfin_write32(PORTA_INEN, val)
2153#define bfin_read_PORTA_INEN_SET() bfin_read32(PORTA_INEN_SET)
2154#define bfin_write_PORTA_INEN_SET(val) bfin_write32(PORTA_INEN_SET, val)
2155#define bfin_read_PORTA_INEN_CLEAR() bfin_read32(PORTA_INEN_CLEAR)
2156#define bfin_write_PORTA_INEN_CLEAR(val) bfin_write32(PORTA_INEN_CLEAR, val)
2157#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
2158#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
2159#define bfin_read_PORTA_DATA_TGL() bfin_read32(PORTA_DATA_TGL)
2160#define bfin_write_PORTA_DATA_TGL(val) bfin_write32(PORTA_DATA_TGL, val)
2161#define bfin_read_PORTA_POL() bfin_read32(PORTA_POL)
2162#define bfin_write_PORTA_POL(val) bfin_write32(PORTA_POL, val)
2163#define bfin_read_PORTA_POL_SET() bfin_read32(PORTA_POL_SET)
2164#define bfin_write_PORTA_POL_SET(val) bfin_write32(PORTA_POL_SET, val)
2165#define bfin_read_PORTA_POL_CLEAR() bfin_read32(PORTA_POL_CLEAR)
2166#define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val)
2167#define bfin_read_PORTA_LOCK() bfin_read32(PORTA_LOCK)
2168#define bfin_write_PORTA_LOCK(val) bfin_write32(PORTA_LOCK, val)
2169#define bfin_read_PORTA_REVID() bfin_read32(PORTA_REVID)
2170#define bfin_write_PORTA_REVID(val) bfin_write32(PORTA_REVID, val)
2171
2172
2173
2174/* Port B Registers */
2175#define bfin_read_PORTB_FER() bfin_read32(PORTB_FER)
2176#define bfin_write_PORTB_FER(val) bfin_write32(PORTB_FER, val)
2177#define bfin_read_PORTB_FER_SET() bfin_read32(PORTB_FER_SET)
2178#define bfin_write_PORTB_FER_SET(val) bfin_write32(PORTB_FER_SET, val)
2179#define bfin_read_PORTB_FER_CLEAR() bfin_read32(PORTB_FER_CLEAR)
2180#define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val)
2181#define bfin_read_PORTB() bfin_read32(PORTB)
2182#define bfin_write_PORTB(val) bfin_write32(PORTB, val)
2183#define bfin_read_PORTB_SET() bfin_read32(PORTB_SET)
2184#define bfin_write_PORTB_SET(val) bfin_write32(PORTB_SET, val)
2185#define bfin_read_PORTB_CLEAR() bfin_read32(PORTB_CLEAR)
2186#define bfin_write_PORTB_CLEAR(val) bfin_write32(PORTB_CLEAR, val)
2187#define bfin_read_PORTB_DIR() bfin_read32(PORTB_DIR)
2188#define bfin_write_PORTB_DIR(val) bfin_write32(PORTB_DIR, val)
2189#define bfin_read_PORTB_DIR_SET() bfin_read32(PORTB_DIR_SET)
2190#define bfin_write_PORTB_DIR_SET(val) bfin_write32(PORTB_DIR_SET, val)
2191#define bfin_read_PORTB_DIR_CLEAR() bfin_read32(PORTB_DIR_CLEAR)
2192#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val)
2193#define bfin_read_PORTB_INEN() bfin_read32(PORTB_INEN)
2194#define bfin_write_PORTB_INEN(val) bfin_write32(PORTB_INEN, val)
2195#define bfin_read_PORTB_INEN_SET() bfin_read32(PORTB_INEN_SET)
2196#define bfin_write_PORTB_INEN_SET(val) bfin_write32(PORTB_INEN_SET, val)
2197#define bfin_read_PORTB_INEN_CLEAR() bfin_read32(PORTB_INEN_CLEAR)
2198#define bfin_write_PORTB_INEN_CLEAR(val) bfin_write32(PORTB_INEN_CLEAR, val)
2199#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
2200#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
2201#define bfin_read_PORTB_DATA_TGL() bfin_read32(PORTB_DATA_TGL)
2202#define bfin_write_PORTB_DATA_TGL(val) bfin_write32(PORTB_DATA_TGL, val)
2203#define bfin_read_PORTB_POL() bfin_read32(PORTB_POL)
2204#define bfin_write_PORTB_POL(val) bfin_write32(PORTB_POL, val)
2205#define bfin_read_PORTB_POL_SET() bfin_read32(PORTB_POL_SET)
2206#define bfin_write_PORTB_POL_SET(val) bfin_write32(PORTB_POL_SET, val)
2207#define bfin_read_PORTB_POL_CLEAR() bfin_read32(PORTB_POL_CLEAR)
2208#define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val)
2209#define bfin_read_PORTB_LOCK() bfin_read32(PORTB_LOCK)
2210#define bfin_write_PORTB_LOCK(val) bfin_write32(PORTB_LOCK, val)
2211#define bfin_read_PORTB_REVID() bfin_read32(PORTB_REVID)
2212#define bfin_write_PORTB_REVID(val) bfin_write32(PORTB_REVID, val)
2213
2214
2215/* Port C Registers */
2216#define bfin_read_PORTC_FER() bfin_read32(PORTC_FER)
2217#define bfin_write_PORTC_FER(val) bfin_write32(PORTC_FER, val)
2218#define bfin_read_PORTC_FER_SET() bfin_read32(PORTC_FER_SET)
2219#define bfin_write_PORTC_FER_SET(val) bfin_write32(PORTC_FER_SET, val)
2220#define bfin_read_PORTC_FER_CLEAR() bfin_read32(PORTC_FER_CLEAR)
2221#define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val)
2222#define bfin_read_PORTC() bfin_read32(PORTC)
2223#define bfin_write_PORTC(val) bfin_write32(PORTC, val)
2224#define bfin_read_PORTC_SET() bfin_read32(PORTC_SET)
2225#define bfin_write_PORTC_SET(val) bfin_write32(PORTC_SET, val)
2226#define bfin_read_PORTC_CLEAR() bfin_read32(PORTC_CLEAR)
2227#define bfin_write_PORTC_CLEAR(val) bfin_write32(PORTC_CLEAR, val)
2228#define bfin_read_PORTC_DIR() bfin_read32(PORTC_DIR)
2229#define bfin_write_PORTC_DIR(val) bfin_write32(PORTC_DIR, val)
2230#define bfin_read_PORTC_DIR_SET() bfin_read32(PORTC_DIR_SET)
2231#define bfin_write_PORTC_DIR_SET(val) bfin_write32(PORTC_DIR_SET, val)
2232#define bfin_read_PORTC_DIR_CLEAR() bfin_read32(PORTC_DIR_CLEAR)
2233#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val)
2234#define bfin_read_PORTC_INEN() bfin_read32(PORTC_INEN)
2235#define bfin_write_PORTC_INEN(val) bfin_write32(PORTC_INEN, val)
2236#define bfin_read_PORTC_INEN_SET() bfin_read32(PORTC_INEN_SET)
2237#define bfin_write_PORTC_INEN_SET(val) bfin_write32(PORTC_INEN_SET, val)
2238#define bfin_read_PORTC_INEN_CLEAR() bfin_read32(PORTC_INEN_CLEAR)
2239#define bfin_write_PORTC_INEN_CLEAR(val) bfin_write32(PORTC_INEN_CLEAR, val)
2240#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
2241#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
2242#define bfin_read_PORTC_DATA_TGL() bfin_read32(PORTC_DATA_TGL)
2243#define bfin_write_PORTC_DATA_TGL(val) bfin_write32(PORTC_DATA_TGL, val)
2244#define bfin_read_PORTC_POL() bfin_read32(PORTC_POL)
2245#define bfin_write_PORTC_POL(val) bfin_write32(PORTC_POL, val)
2246#define bfin_read_PORTC_POL_SET() bfin_read32(PORTC_POL_SET)
2247#define bfin_write_PORTC_POL_SET(val) bfin_write32(PORTC_POL_SET, val)
2248#define bfin_read_PORTC_POL_CLEAR() bfin_read32(PORTC_POL_CLEAR)
2249#define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val)
2250#define bfin_read_PORTC_LOCK() bfin_read32(PORTC_LOCK)
2251#define bfin_write_PORTC_LOCK(val) bfin_write32(PORTC_LOCK, val)
2252#define bfin_read_PORTC_REVID() bfin_read32(PORTC_REVID)
2253#define bfin_write_PORTC_REVID(val) bfin_write32(PORTC_REVID, val)
2254
2255
2256/* Port D Registers */
2257#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
2258#define bfin_write_PORTD_FER(val) bfin_write32(PORTD_FER, val)
2259#define bfin_read_PORTD_FER_SET() bfin_read32(PORTD_FER_SET)
2260#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
2261#define bfin_read_PORTD_FER_CLEAR() bfin_read32(PORTD_FER_CLEAR)
2262#define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val)
2263#define bfin_read_PORTD() bfin_read32(PORTD)
2264#define bfin_write_PORTD(val) bfin_write32(PORTD, val)
2265#define bfin_read_PORTD_SET() bfin_read32(PORTD_SET)
2266#define bfin_write_PORTD_SET(val) bfin_write32(PORTD_SET, val)
2267#define bfin_read_PORTD_CLEAR() bfin_read32(PORTD_CLEAR)
2268#define bfin_write_PORTD_CLEAR(val) bfin_write32(PORTD_CLEAR, val)
2269#define bfin_read_PORTD_DIR() bfin_read32(PORTD_DIR)
2270#define bfin_write_PORTD_DIR(val) bfin_write32(PORTD_DIR, val)
2271#define bfin_read_PORTD_DIR_SET() bfin_read32(PORTD_DIR_SET)
2272#define bfin_write_PORTD_DIR_SET(val) bfin_write32(PORTD_DIR_SET, val)
2273#define bfin_read_PORTD_DIR_CLEAR() bfin_read32(PORTD_DIR_CLEAR)
2274#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val)
2275#define bfin_read_PORTD_INEN() bfin_read32(PORTD_INEN)
2276#define bfin_write_PORTD_INEN(val) bfin_write32(PORTD_INEN, val)
2277#define bfin_read_PORTD_INEN_SET() bfin_read32(PORTD_INEN_SET)
2278#define bfin_write_PORTD_INEN_SET(val) bfin_write32(PORTD_INEN_SET, val)
2279#define bfin_read_PORTD_INEN_CLEAR() bfin_read32(PORTD_INEN_CLEAR)
2280#define bfin_write_PORTD_INEN_CLEAR(val) bfin_write32(PORTD_INEN_CLEAR, val)
2281#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
2282#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
2283#define bfin_read_PORTD_DATA_TGL() bfin_read32(PORTD_DATA_TGL)
2284#define bfin_write_PORTD_DATA_TGL(val) bfin_write32(PORTD_DATA_TGL, val)
2285#define bfin_read_PORTD_POL() bfin_read32(PORTD_POL)
2286#define bfin_write_PORTD_POL(val) bfin_write32(PORTD_POL, val)
2287#define bfin_read_PORTD_POL_SET() bfin_read32(PORTD_POL_SET)
2288#define bfin_write_PORTD_POL_SET(val) bfin_write32(PORTD_POL_SET, val)
2289#define bfin_read_PORTD_POL_CLEAR() bfin_read32(PORTD_POL_CLEAR)
2290#define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val)
2291#define bfin_read_PORTD_LOCK() bfin_read32(PORTD_LOCK)
2292#define bfin_write_PORTD_LOCK(val) bfin_write32(PORTD_LOCK, val)
2293#define bfin_read_PORTD_REVID() bfin_read32(PORTD_REVID)
2294#define bfin_write_PORTD_REVID(val) bfin_write32(PORTD_REVID, val)
2295
2296
2297/* Port E Registers */
2298#define bfin_read_PORTE_FER() bfin_read32(PORTE_FER)
2299#define bfin_write_PORTE_FER(val) bfin_write32(PORTE_FER, val)
2300#define bfin_read_PORTE_FER_SET() bfin_read32(PORTE_FER_SET)
2301#define bfin_write_PORTE_FER_SET(val) bfin_write32(PORTE_FER_SET, val)
2302#define bfin_read_PORTE_FER_CLEAR() bfin_read32(PORTE_FER_CLEAR)
2303#define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val)
2304#define bfin_read_PORTE() bfin_read32(PORTE)
2305#define bfin_write_PORTE(val) bfin_write32(PORTE, val)
2306#define bfin_read_PORTE_SET() bfin_read32(PORTE_SET)
2307#define bfin_write_PORTE_SET(val) bfin_write32(PORTE_SET, val)
2308#define bfin_read_PORTE_CLEAR() bfin_read32(PORTE_CLEAR)
2309#define bfin_write_PORTE_CLEAR(val) bfin_write32(PORTE_CLEAR, val)
2310#define bfin_read_PORTE_DIR() bfin_read32(PORTE_DIR)
2311#define bfin_write_PORTE_DIR(val) bfin_write32(PORTE_DIR, val)
2312#define bfin_read_PORTE_DIR_SET() bfin_read32(PORTE_DIR_SET)
2313#define bfin_write_PORTE_DIR_SET(val) bfin_write32(PORTE_DIR_SET, val)
2314#define bfin_read_PORTE_DIR_CLEAR() bfin_read32(PORTE_DIR_CLEAR)
2315#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val)
2316#define bfin_read_PORTE_INEN() bfin_read32(PORTE_INEN)
2317#define bfin_write_PORTE_INEN(val) bfin_write32(PORTE_INEN, val)
2318#define bfin_read_PORTE_INEN_SET() bfin_read32(PORTE_INEN_SET)
2319#define bfin_write_PORTE_INEN_SET(val) bfin_write32(PORTE_INEN_SET, val)
2320#define bfin_read_PORTE_INEN_CLEAR() bfin_read32(PORTE_INEN_CLEAR)
2321#define bfin_write_PORTE_INEN_CLEAR(val) bfin_write32(PORTE_INEN_CLEAR, val)
2322#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
2323#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
2324#define bfin_read_PORTE_DATA_TGL() bfin_read32(PORTE_DATA_TGL)
2325#define bfin_write_PORTE_DATA_TGL(val) bfin_write32(PORTE_DATA_TGL, val)
2326#define bfin_read_PORTE_POL() bfin_read32(PORTE_POL)
2327#define bfin_write_PORTE_POL(val) bfin_write32(PORTE_POL, val)
2328#define bfin_read_PORTE_POL_SET() bfin_read32(PORTE_POL_SET)
2329#define bfin_write_PORTE_POL_SET(val) bfin_write32(PORTE_POL_SET, val)
2330#define bfin_read_PORTE_POL_CLEAR() bfin_read32(PORTE_POL_CLEAR)
2331#define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val)
2332#define bfin_read_PORTE_LOCK() bfin_read32(PORTE_LOCK)
2333#define bfin_write_PORTE_LOCK(val) bfin_write32(PORTE_LOCK, val)
2334#define bfin_read_PORTE_REVID() bfin_read32(PORTE_REVID)
2335#define bfin_write_PORTE_REVID(val) bfin_write32(PORTE_REVID, val)
2336
2337
2338/* Port F Registers */
2339#define bfin_read_PORTF_FER() bfin_read32(PORTF_FER)
2340#define bfin_write_PORTF_FER(val) bfin_write32(PORTF_FER, val)
2341#define bfin_read_PORTF_FER_SET() bfin_read32(PORTF_FER_SET)
2342#define bfin_write_PORTF_FER_SET(val) bfin_write32(PORTF_FER_SET, val)
2343#define bfin_read_PORTF_FER_CLEAR() bfin_read32(PORTF_FER_CLEAR)
2344#define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val)
2345#define bfin_read_PORTF() bfin_read32(PORTF)
2346#define bfin_write_PORTF(val) bfin_write32(PORTF, val)
2347#define bfin_read_PORTF_SET() bfin_read32(PORTF_SET)
2348#define bfin_write_PORTF_SET(val) bfin_write32(PORTF_SET, val)
2349#define bfin_read_PORTF_CLEAR() bfin_read32(PORTF_CLEAR)
2350#define bfin_write_PORTF_CLEAR(val) bfin_write32(PORTF_CLEAR, val)
2351#define bfin_read_PORTF_DIR() bfin_read32(PORTF_DIR)
2352#define bfin_write_PORTF_DIR(val) bfin_write32(PORTF_DIR, val)
2353#define bfin_read_PORTF_DIR_SET() bfin_read32(PORTF_DIR_SET)
2354#define bfin_write_PORTF_DIR_SET(val) bfin_write32(PORTF_DIR_SET, val)
2355#define bfin_read_PORTF_DIR_CLEAR() bfin_read32(PORTF_DIR_CLEAR)
2356#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val)
2357#define bfin_read_PORTF_INEN() bfin_read32(PORTF_INEN)
2358#define bfin_write_PORTF_INEN(val) bfin_write32(PORTF_INEN, val)
2359#define bfin_read_PORTF_INEN_SET() bfin_read32(PORTF_INEN_SET)
2360#define bfin_write_PORTF_INEN_SET(val) bfin_write32(PORTF_INEN_SET, val)
2361#define bfin_read_PORTF_INEN_CLEAR() bfin_read32(PORTF_INEN_CLEAR)
2362#define bfin_write_PORTF_INEN_CLEAR(val) bfin_write32(PORTF_INEN_CLEAR, val)
2363#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
2364#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
2365#define bfin_read_PORTF_DATA_TGL() bfin_read32(PORTF_DATA_TGL)
2366#define bfin_write_PORTF_DATA_TGL(val) bfin_write32(PORTF_DATA_TGL, val)
2367#define bfin_read_PORTF_POL() bfin_read32(PORTF_POL)
2368#define bfin_write_PORTF_POL(val) bfin_write32(PORTF_POL, val)
2369#define bfin_read_PORTF_POL_SET() bfin_read32(PORTF_POL_SET)
2370#define bfin_write_PORTF_POL_SET(val) bfin_write32(PORTF_POL_SET, val)
2371#define bfin_read_PORTF_POL_CLEAR() bfin_read32(PORTF_POL_CLEAR)
2372#define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val)
2373#define bfin_read_PORTF_LOCK() bfin_read32(PORTF_LOCK)
2374#define bfin_write_PORTF_LOCK(val) bfin_write32(PORTF_LOCK, val)
2375#define bfin_read_PORTF_REVID() bfin_read32(PORTF_REVID)
2376#define bfin_write_PORTF_REVID(val) bfin_write32(PORTF_REVID, val)
2377
2378
2379/* Port G Registers */
2380#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
2381#define bfin_write_PORTG_FER(val) bfin_write32(PORTG_FER, val)
2382#define bfin_read_PORTG_FER_SET() bfin_read32(PORTG_FER_SET)
2383#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
2384#define bfin_read_PORTG_FER_CLEAR() bfin_read32(PORTG_FER_CLEAR)
2385#define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val)
2386#define bfin_read_PORTG() bfin_read32(PORTG)
2387#define bfin_write_PORTG(val) bfin_write32(PORTG, val)
2388#define bfin_read_PORTG_SET() bfin_read32(PORTG_SET)
2389#define bfin_write_PORTG_SET(val) bfin_write32(PORTG_SET, val)
2390#define bfin_read_PORTG_CLEAR() bfin_read32(PORTG_CLEAR)
2391#define bfin_write_PORTG_CLEAR(val) bfin_write32(PORTG_CLEAR, val)
2392#define bfin_read_PORTG_DIR() bfin_read32(PORTG_DIR)
2393#define bfin_write_PORTG_DIR(val) bfin_write32(PORTG_DIR, val)
2394#define bfin_read_PORTG_DIR_SET() bfin_read32(PORTG_DIR_SET)
2395#define bfin_write_PORTG_DIR_SET(val) bfin_write32(PORTG_DIR_SET, val)
2396#define bfin_read_PORTG_DIR_CLEAR() bfin_read32(PORTG_DIR_CLEAR)
2397#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val)
2398#define bfin_read_PORTG_INEN() bfin_read32(PORTG_INEN)
2399#define bfin_write_PORTG_INEN(val) bfin_write32(PORTG_INEN, val)
2400#define bfin_read_PORTG_INEN_SET() bfin_read32(PORTG_INEN_SET)
2401#define bfin_write_PORTG_INEN_SET(val) bfin_write32(PORTG_INEN_SET, val)
2402#define bfin_read_PORTG_INEN_CLEAR() bfin_read32(PORTG_INEN_CLEAR)
2403#define bfin_write_PORTG_INEN_CLEAR(val) bfin_write32(PORTG_INEN_CLEAR, val)
2404#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
2405#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
2406#define bfin_read_PORTG_DATA_TGL() bfin_read32(PORTG_DATA_TGL)
2407#define bfin_write_PORTG_DATA_TGL(val) bfin_write32(PORTG_DATA_TGL, val)
2408#define bfin_read_PORTG_POL() bfin_read32(PORTG_POL)
2409#define bfin_write_PORTG_POL(val) bfin_write32(PORTG_POL, val)
2410#define bfin_read_PORTG_POL_SET() bfin_read32(PORTG_POL_SET)
2411#define bfin_write_PORTG_POL_SET(val) bfin_write32(PORTG_POL_SET, val)
2412#define bfin_read_PORTG_POL_CLEAR() bfin_read32(PORTG_POL_CLEAR)
2413#define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val)
2414#define bfin_read_PORTG_LOCK() bfin_read32(PORTG_LOCK)
2415#define bfin_write_PORTG_LOCK(val) bfin_write32(PORTG_LOCK, val)
2416#define bfin_read_PORTG_REVID() bfin_read32(PORTG_REVID)
2417#define bfin_write_PORTG_REVID(val) bfin_write32(PORTG_REVID, val)
2418
2419
2420
2421
2422/* CAN Controller 0 Config 1 Registers */
2423
2424#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
2425#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
2426#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
2427#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
2428#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
2429#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
2430#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
2431#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
2432#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
2433#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
2434#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
2435#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
2436#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
2437#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
2438#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
2439#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
2440#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
2441#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
2442#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
2443#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
2444#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
2445#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
2446#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
2447#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
2448#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
2449#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
2450
2451/* CAN Controller 0 Config 2 Registers */
2452
2453#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
2454#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
2455#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
2456#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
2457#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
2458#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
2459#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
2460#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
2461#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
2462#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
2463#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
2464#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
2465#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
2466#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
2467#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
2468#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
2469#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
2470#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
2471#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
2472#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
2473#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
2474#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
2475#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
2476#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
2477#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
2478#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
2479
2480/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
2481
2482#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
2483#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
2484#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
2485#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
2486#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
2487#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
2488#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
2489#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
2490#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
2491#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
2492#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
2493#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
2494#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
2495#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
2496#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
2497#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
2498#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
2499#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
2500#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
2501#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
2502#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
2503#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
2504#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
2505#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
2506#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
2507#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
2508#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
2509#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
2510#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
2511#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
2512#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
2513#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
2514
2515/* CAN Controller 0 Accebfin_read_()tance Registers */
2516
2517#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
2518#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
2519#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
2520#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
2521#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
2522#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
2523#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
2524#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
2525#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
2526#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
2527#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
2528#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
2529#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
2530#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
2531#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
2532#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
2533#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
2534#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
2535#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
2536#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
2537#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
2538#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
2539#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
2540#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
2541#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
2542#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
2543#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
2544#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
2545#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
2546#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
2547#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
2548#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
2549#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
2550#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
2551#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
2552#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
2553#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
2554#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
2555#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
2556#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
2557#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
2558#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
2559#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
2560#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
2561#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
2562#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
2563#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
2564#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
2565#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
2566#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
2567#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
2568#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
2569#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
2570#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
2571#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
2572#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
2573#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
2574#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
2575#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
2576#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
2577#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
2578#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
2579#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
2580#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
2581
2582/* CAN Controller 0 Accebfin_read_()tance Registers */
2583
2584#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
2585#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
2586#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
2587#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
2588#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
2589#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
2590#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
2591#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
2592#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
2593#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
2594#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
2595#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
2596#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
2597#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
2598#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
2599#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
2600#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
2601#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
2602#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
2603#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
2604#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
2605#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
2606#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
2607#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
2608#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
2609#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
2610#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
2611#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
2612#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
2613#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
2614#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
2615#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
2616#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
2617#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
2618#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
2619#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
2620#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
2621#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
2622#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
2623#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
2624#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
2625#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
2626#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
2627#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
2628#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
2629#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
2630#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
2631#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
2632#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
2633#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
2634#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
2635#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
2636#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
2637#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
2638#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
2639#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
2640#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
2641#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
2642#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
2643#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
2644#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
2645#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
2646#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
2647#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
2648
2649/* CAN Controller 0 Mailbox Data Registers */
2650
2651#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
2652#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
2653#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
2654#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
2655#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
2656#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
2657#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
2658#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
2659#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
2660#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
2661#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
2662#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
2663#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
2664#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
2665#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
2666#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
2667#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
2668#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
2669#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
2670#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
2671#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
2672#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
2673#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
2674#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
2675#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
2676#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
2677#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
2678#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
2679#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
2680#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
2681#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
2682#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
2683#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
2684#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
2685#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
2686#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
2687#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
2688#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
2689#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
2690#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
2691#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
2692#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
2693#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
2694#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
2695#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
2696#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
2697#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
2698#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
2699#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
2700#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
2701#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
2702#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
2703#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
2704#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
2705#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
2706#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
2707#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
2708#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
2709#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
2710#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
2711#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
2712#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
2713#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
2714#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
2715#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
2716#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
2717#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
2718#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
2719#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
2720#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
2721#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
2722#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
2723#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
2724#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
2725#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
2726#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
2727#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
2728#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
2729#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
2730#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
2731#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
2732#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
2733#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
2734#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
2735#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
2736#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
2737#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
2738#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
2739#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
2740#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
2741#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
2742#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
2743#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
2744#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
2745#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
2746#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
2747#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
2748#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
2749#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
2750#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
2751#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
2752#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
2753#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
2754#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
2755#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
2756#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
2757#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
2758#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
2759#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
2760#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
2761#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
2762#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
2763#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
2764#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
2765#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
2766#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
2767#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
2768#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
2769#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
2770#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
2771#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
2772#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
2773#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
2774#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
2775#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
2776#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
2777#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
2778#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
2779#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
2780#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
2781#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
2782#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
2783#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
2784#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
2785#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
2786#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
2787#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
2788#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
2789#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
2790#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
2791#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
2792#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
2793#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
2794#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
2795#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
2796#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
2797#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
2798#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
2799#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
2800#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
2801#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
2802#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
2803#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
2804#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
2805#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
2806#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
2807#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
2808#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
2809#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
2810#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
2811#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
2812#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
2813#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
2814#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
2815#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
2816#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
2817#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
2818#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
2819#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
2820#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
2821#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
2822#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
2823#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
2824#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
2825#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
2826#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
2827#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
2828#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
2829#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
2830#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
2831#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
2832#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
2833#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
2834#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
2835#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
2836#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
2837#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
2838#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
2839#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
2840#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
2841#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
2842#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
2843#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
2844#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
2845#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
2846#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
2847#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
2848#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
2849#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
2850#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
2851#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
2852#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
2853#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
2854#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
2855#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
2856#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
2857#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
2858#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
2859#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
2860#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
2861#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
2862#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
2863#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
2864#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
2865#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
2866#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
2867#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
2868#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
2869#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
2870#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
2871#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
2872#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
2873#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
2874#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
2875#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
2876#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
2877#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
2878#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
2879#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
2880#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
2881#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
2882#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
2883#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
2884#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
2885#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
2886#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
2887#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
2888#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
2889#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
2890#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
2891#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
2892#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
2893#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
2894#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
2895#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
2896#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
2897#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
2898#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
2899#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
2900#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
2901#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
2902#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
2903#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
2904#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
2905#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
2906#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
2907
2908/* CAN Controller 0 Mailbox Data Registers */
2909
2910#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
2911#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
2912#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
2913#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
2914#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
2915#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
2916#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
2917#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
2918#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
2919#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
2920#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
2921#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
2922#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
2923#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
2924#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
2925#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
2926#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
2927#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
2928#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
2929#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
2930#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
2931#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
2932#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
2933#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
2934#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
2935#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
2936#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
2937#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
2938#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
2939#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
2940#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
2941#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
2942#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
2943#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
2944#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
2945#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
2946#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
2947#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
2948#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
2949#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
2950#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
2951#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
2952#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
2953#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
2954#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
2955#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
2956#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
2957#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
2958#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
2959#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
2960#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
2961#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
2962#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
2963#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
2964#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
2965#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
2966#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
2967#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
2968#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
2969#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
2970#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
2971#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
2972#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
2973#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
2974#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
2975#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
2976#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
2977#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
2978#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
2979#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
2980#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
2981#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
2982#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
2983#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
2984#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
2985#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
2986#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
2987#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
2988#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
2989#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
2990#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
2991#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
2992#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
2993#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
2994#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
2995#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
2996#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
2997#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
2998#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
2999#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
3000#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
3001#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
3002#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
3003#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
3004#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
3005#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
3006#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
3007#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
3008#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
3009#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
3010#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
3011#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
3012#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
3013#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
3014#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
3015#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
3016#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
3017#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
3018#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
3019#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
3020#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
3021#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
3022#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
3023#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
3024#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
3025#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
3026#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
3027#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
3028#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
3029#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
3030#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
3031#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
3032#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
3033#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
3034#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
3035#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
3036#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
3037#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
3038#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
3039#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
3040#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
3041#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
3042#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
3043#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
3044#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
3045#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
3046#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
3047#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
3048#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
3049#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
3050#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
3051#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
3052#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
3053#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
3054#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
3055#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
3056#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
3057#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
3058#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
3059#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
3060#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
3061#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
3062#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
3063#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
3064#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
3065#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
3066#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
3067#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
3068#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
3069#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
3070#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
3071#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
3072#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
3073#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
3074#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
3075#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
3076#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
3077#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
3078#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
3079#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
3080#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
3081#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
3082#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
3083#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
3084#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
3085#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
3086#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
3087#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
3088#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
3089#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
3090#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
3091#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
3092#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
3093#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
3094#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
3095#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
3096#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
3097#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
3098#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
3099#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
3100#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
3101#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
3102#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
3103#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
3104#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
3105#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
3106#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
3107#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
3108#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
3109#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
3110#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
3111#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
3112#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
3113#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
3114#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
3115#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
3116#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
3117#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
3118#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
3119#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
3120#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
3121#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
3122#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
3123#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
3124#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
3125#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
3126#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
3127#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
3128#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
3129#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
3130#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
3131#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
3132#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
3133#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
3134#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
3135#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
3136#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
3137#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
3138#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
3139#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
3140#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
3141#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
3142#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
3143#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
3144#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
3145#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
3146#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
3147#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
3148#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
3149#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
3150#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
3151#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
3152#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
3153#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
3154#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
3155#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
3156#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
3157#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
3158#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
3159#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
3160#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
3161#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
3162#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
3163#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
3164#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
3165#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
3166
3167/* Counter Registers */
3168
3169#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
3170#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
3171#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
3172#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
3173#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
3174#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
3175#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
3176#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
3177#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
3178#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
3179#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
3180#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
3181#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
3182#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
3183#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
3184#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
3185
3186/* RSI Register */
3187#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
3188#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
3189#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
3190#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
3191#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
3192#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
3193#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
3194#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
3195#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
3196#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
3197#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
3198#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
3199#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
3200#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
3201#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
3202#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
3203#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
3204#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
3205#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
3206#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
3207#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
3208#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
3209#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
3210#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
3211#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
3212#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
3213#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
3214#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
3215#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
3216#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
3217#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
3218#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
3219#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
3220#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
3221#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
3222#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
3223#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ)
3224#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val)
3225#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
3226#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
3227#define bfin_read_RSI_E_STATUS() bfin_read32(RSI_ESTAT)
3228#define bfin_write_RSI_E_STATUS(val) bfin_write32(RSI_ESTAT, val)
3229#define bfin_read_RSI_E_MASK() bfin_read32(RSI_EMASK)
3230#define bfin_write_RSI_E_MASK(val) bfin_write32(RSI_EMASK, val)
3231#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
3232#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
3233#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
3234#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
3235#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
3236#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
3237#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
3238#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
3239#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
3240#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
3241#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
3242#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
3243
3244/* usb register */
3245#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC)
3246#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
3247#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
3248#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
3249#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
3250
3251#endif /* _CDEF_BF60X_H */
3252
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h
new file mode 100644
index 000000000000..19690cc42113
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/defBF609.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF609_H
8#define _DEF_BF609_H
9
10/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */
11#include "defBF60x_base.h"
12
13/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
14
15#endif /* _DEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
new file mode 100644
index 000000000000..6aac38544cc9
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
@@ -0,0 +1,3587 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the Clear BSD license or the GPL-2 (or later)
5 */
6
7#ifndef _DEF_BF60X_H
8#define _DEF_BF60X_H
9
10
11/* ************************************************************** */
12/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x */
13/* ************************************************************** */
14
15
16/* =========================
17 CNT Registers
18 ========================= */
19
20/* =========================
21 CNT0
22 ========================= */
23#define CNT_CONFIG 0xFFC00400 /* CNT0 Configuration Register */
24#define CNT_IMASK 0xFFC00404 /* CNT0 Interrupt Mask Register */
25#define CNT_STATUS 0xFFC00408 /* CNT0 Status Register */
26#define CNT_COMMAND 0xFFC0040C /* CNT0 Command Register */
27#define CNT_DEBOUNCE 0xFFC00410 /* CNT0 Debounce Register */
28#define CNT_COUNTER 0xFFC00414 /* CNT0 Counter Register */
29#define CNT_MAX 0xFFC00418 /* CNT0 Maximum Count Register */
30#define CNT_MIN 0xFFC0041C /* CNT0 Minimum Count Register */
31
32
33/* =========================
34 RSI Registers
35 ========================= */
36
37#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */
38#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */
39#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */
40#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
41#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */
42#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */
43#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */
44#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */
45#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */
46#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */
47#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */
48#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
49#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */
50#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */
51#define RSI_MASK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
52#define RSI_MASK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
53#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
54#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 This register contains bit to dis CCS gen */
55#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
56#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Acknowledge Timeout Register */
57#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
58#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
59#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
60#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */
61#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */
62#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */
63#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */
64#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Identification Register */
65#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Identification Register */
66#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Identification Register */
67#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Identification Register */
68
69/* =========================
70 CAN Registers
71 ========================= */
72
73/* =========================
74 CAN0
75 ========================= */
76#define CAN0_MC1 0xFFC00A00 /* CAN0 Mailbox Configuration Register 1 */
77#define CAN0_MD1 0xFFC00A04 /* CAN0 Mailbox Direction Register 1 */
78#define CAN0_TRS1 0xFFC00A08 /* CAN0 Transmission Request Set Register 1 */
79#define CAN0_TRR1 0xFFC00A0C /* CAN0 Transmission Request Reset Register 1 */
80#define CAN0_TA1 0xFFC00A10 /* CAN0 Transmission Acknowledge Register 1 */
81#define CAN0_AA1 0xFFC00A14 /* CAN0 Abort Acknowledge Register 1 */
82#define CAN0_RMP1 0xFFC00A18 /* CAN0 Receive Message Pending Register 1 */
83#define CAN0_RML1 0xFFC00A1C /* CAN0 Receive Message Lost Register 1 */
84#define CAN0_MBTIF1 0xFFC00A20 /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
85#define CAN0_MBRIF1 0xFFC00A24 /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
86#define CAN0_MBIM1 0xFFC00A28 /* CAN0 Mailbox Interrupt Mask Register 1 */
87#define CAN0_RFH1 0xFFC00A2C /* CAN0 Remote Frame Handling Register 1 */
88#define CAN0_OPSS1 0xFFC00A30 /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
89#define CAN0_MC2 0xFFC00A40 /* CAN0 Mailbox Configuration Register 2 */
90#define CAN0_MD2 0xFFC00A44 /* CAN0 Mailbox Direction Register 2 */
91#define CAN0_TRS2 0xFFC00A48 /* CAN0 Transmission Request Set Register 2 */
92#define CAN0_TRR2 0xFFC00A4C /* CAN0 Transmission Request Reset Register 2 */
93#define CAN0_TA2 0xFFC00A50 /* CAN0 Transmission Acknowledge Register 2 */
94#define CAN0_AA2 0xFFC00A54 /* CAN0 Abort Acknowledge Register 2 */
95#define CAN0_RMP2 0xFFC00A58 /* CAN0 Receive Message Pending Register 2 */
96#define CAN0_RML2 0xFFC00A5C /* CAN0 Receive Message Lost Register 2 */
97#define CAN0_MBTIF2 0xFFC00A60 /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
98#define CAN0_MBRIF2 0xFFC00A64 /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
99#define CAN0_MBIM2 0xFFC00A68 /* CAN0 Mailbox Interrupt Mask Register 2 */
100#define CAN0_RFH2 0xFFC00A6C /* CAN0 Remote Frame Handling Register 2 */
101#define CAN0_OPSS2 0xFFC00A70 /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
102#define CAN0_CLOCK 0xFFC00A80 /* CAN0 Clock Register */
103#define CAN0_TIMING 0xFFC00A84 /* CAN0 Timing Register */
104#define CAN0_DEBUG 0xFFC00A88 /* CAN0 Debug Register */
105#define CAN0_STATUS 0xFFC00A8C /* CAN0 Status Register */
106#define CAN0_CEC 0xFFC00A90 /* CAN0 Error Counter Register */
107#define CAN0_GIS 0xFFC00A94 /* CAN0 Global CAN Interrupt Status */
108#define CAN0_GIM 0xFFC00A98 /* CAN0 Global CAN Interrupt Mask */
109#define CAN0_GIF 0xFFC00A9C /* CAN0 Global CAN Interrupt Flag */
110#define CAN0_CONTROL 0xFFC00AA0 /* CAN0 CAN Master Control Register */
111#define CAN0_INTR 0xFFC00AA4 /* CAN0 Interrupt Pending Register */
112#define CAN0_MBTD 0xFFC00AAC /* CAN0 Temporary Mailbox Disable Register */
113#define CAN0_EWR 0xFFC00AB0 /* CAN0 Error Counter Warning Level Register */
114#define CAN0_ESR 0xFFC00AB4 /* CAN0 Error Status Register */
115#define CAN0_UCCNT 0xFFC00AC4 /* CAN0 Universal Counter Register */
116#define CAN0_UCRC 0xFFC00AC8 /* CAN0 Universal Counter Reload/Capture Register */
117#define CAN0_UCCNF 0xFFC00ACC /* CAN0 Universal Counter Configuration Mode Register */
118#define CAN0_AM00L 0xFFC00B00 /* CAN0 Acceptance Mask Register (L) */
119#define CAN0_AM01L 0xFFC00B08 /* CAN0 Acceptance Mask Register (L) */
120#define CAN0_AM02L 0xFFC00B10 /* CAN0 Acceptance Mask Register (L) */
121#define CAN0_AM03L 0xFFC00B18 /* CAN0 Acceptance Mask Register (L) */
122#define CAN0_AM04L 0xFFC00B20 /* CAN0 Acceptance Mask Register (L) */
123#define CAN0_AM05L 0xFFC00B28 /* CAN0 Acceptance Mask Register (L) */
124#define CAN0_AM06L 0xFFC00B30 /* CAN0 Acceptance Mask Register (L) */
125#define CAN0_AM07L 0xFFC00B38 /* CAN0 Acceptance Mask Register (L) */
126#define CAN0_AM08L 0xFFC00B40 /* CAN0 Acceptance Mask Register (L) */
127#define CAN0_AM09L 0xFFC00B48 /* CAN0 Acceptance Mask Register (L) */
128#define CAN0_AM10L 0xFFC00B50 /* CAN0 Acceptance Mask Register (L) */
129#define CAN0_AM11L 0xFFC00B58 /* CAN0 Acceptance Mask Register (L) */
130#define CAN0_AM12L 0xFFC00B60 /* CAN0 Acceptance Mask Register (L) */
131#define CAN0_AM13L 0xFFC00B68 /* CAN0 Acceptance Mask Register (L) */
132#define CAN0_AM14L 0xFFC00B70 /* CAN0 Acceptance Mask Register (L) */
133#define CAN0_AM15L 0xFFC00B78 /* CAN0 Acceptance Mask Register (L) */
134#define CAN0_AM16L 0xFFC00B80 /* CAN0 Acceptance Mask Register (L) */
135#define CAN0_AM17L 0xFFC00B88 /* CAN0 Acceptance Mask Register (L) */
136#define CAN0_AM18L 0xFFC00B90 /* CAN0 Acceptance Mask Register (L) */
137#define CAN0_AM19L 0xFFC00B98 /* CAN0 Acceptance Mask Register (L) */
138#define CAN0_AM20L 0xFFC00BA0 /* CAN0 Acceptance Mask Register (L) */
139#define CAN0_AM21L 0xFFC00BA8 /* CAN0 Acceptance Mask Register (L) */
140#define CAN0_AM22L 0xFFC00BB0 /* CAN0 Acceptance Mask Register (L) */
141#define CAN0_AM23L 0xFFC00BB8 /* CAN0 Acceptance Mask Register (L) */
142#define CAN0_AM24L 0xFFC00BC0 /* CAN0 Acceptance Mask Register (L) */
143#define CAN0_AM25L 0xFFC00BC8 /* CAN0 Acceptance Mask Register (L) */
144#define CAN0_AM26L 0xFFC00BD0 /* CAN0 Acceptance Mask Register (L) */
145#define CAN0_AM27L 0xFFC00BD8 /* CAN0 Acceptance Mask Register (L) */
146#define CAN0_AM28L 0xFFC00BE0 /* CAN0 Acceptance Mask Register (L) */
147#define CAN0_AM29L 0xFFC00BE8 /* CAN0 Acceptance Mask Register (L) */
148#define CAN0_AM30L 0xFFC00BF0 /* CAN0 Acceptance Mask Register (L) */
149#define CAN0_AM31L 0xFFC00BF8 /* CAN0 Acceptance Mask Register (L) */
150#define CAN0_AM00H 0xFFC00B04 /* CAN0 Acceptance Mask Register (H) */
151#define CAN0_AM01H 0xFFC00B0C /* CAN0 Acceptance Mask Register (H) */
152#define CAN0_AM02H 0xFFC00B14 /* CAN0 Acceptance Mask Register (H) */
153#define CAN0_AM03H 0xFFC00B1C /* CAN0 Acceptance Mask Register (H) */
154#define CAN0_AM04H 0xFFC00B24 /* CAN0 Acceptance Mask Register (H) */
155#define CAN0_AM05H 0xFFC00B2C /* CAN0 Acceptance Mask Register (H) */
156#define CAN0_AM06H 0xFFC00B34 /* CAN0 Acceptance Mask Register (H) */
157#define CAN0_AM07H 0xFFC00B3C /* CAN0 Acceptance Mask Register (H) */
158#define CAN0_AM08H 0xFFC00B44 /* CAN0 Acceptance Mask Register (H) */
159#define CAN0_AM09H 0xFFC00B4C /* CAN0 Acceptance Mask Register (H) */
160#define CAN0_AM10H 0xFFC00B54 /* CAN0 Acceptance Mask Register (H) */
161#define CAN0_AM11H 0xFFC00B5C /* CAN0 Acceptance Mask Register (H) */
162#define CAN0_AM12H 0xFFC00B64 /* CAN0 Acceptance Mask Register (H) */
163#define CAN0_AM13H 0xFFC00B6C /* CAN0 Acceptance Mask Register (H) */
164#define CAN0_AM14H 0xFFC00B74 /* CAN0 Acceptance Mask Register (H) */
165#define CAN0_AM15H 0xFFC00B7C /* CAN0 Acceptance Mask Register (H) */
166#define CAN0_AM16H 0xFFC00B84 /* CAN0 Acceptance Mask Register (H) */
167#define CAN0_AM17H 0xFFC00B8C /* CAN0 Acceptance Mask Register (H) */
168#define CAN0_AM18H 0xFFC00B94 /* CAN0 Acceptance Mask Register (H) */
169#define CAN0_AM19H 0xFFC00B9C /* CAN0 Acceptance Mask Register (H) */
170#define CAN0_AM20H 0xFFC00BA4 /* CAN0 Acceptance Mask Register (H) */
171#define CAN0_AM21H 0xFFC00BAC /* CAN0 Acceptance Mask Register (H) */
172#define CAN0_AM22H 0xFFC00BB4 /* CAN0 Acceptance Mask Register (H) */
173#define CAN0_AM23H 0xFFC00BBC /* CAN0 Acceptance Mask Register (H) */
174#define CAN0_AM24H 0xFFC00BC4 /* CAN0 Acceptance Mask Register (H) */
175#define CAN0_AM25H 0xFFC00BCC /* CAN0 Acceptance Mask Register (H) */
176#define CAN0_AM26H 0xFFC00BD4 /* CAN0 Acceptance Mask Register (H) */
177#define CAN0_AM27H 0xFFC00BDC /* CAN0 Acceptance Mask Register (H) */
178#define CAN0_AM28H 0xFFC00BE4 /* CAN0 Acceptance Mask Register (H) */
179#define CAN0_AM29H 0xFFC00BEC /* CAN0 Acceptance Mask Register (H) */
180#define CAN0_AM30H 0xFFC00BF4 /* CAN0 Acceptance Mask Register (H) */
181#define CAN0_AM31H 0xFFC00BFC /* CAN0 Acceptance Mask Register (H) */
182#define CAN0_MB00_DATA0 0xFFC00C00 /* CAN0 Mailbox Word 0 Register */
183#define CAN0_MB01_DATA0 0xFFC00C20 /* CAN0 Mailbox Word 0 Register */
184#define CAN0_MB02_DATA0 0xFFC00C40 /* CAN0 Mailbox Word 0 Register */
185#define CAN0_MB03_DATA0 0xFFC00C60 /* CAN0 Mailbox Word 0 Register */
186#define CAN0_MB04_DATA0 0xFFC00C80 /* CAN0 Mailbox Word 0 Register */
187#define CAN0_MB05_DATA0 0xFFC00CA0 /* CAN0 Mailbox Word 0 Register */
188#define CAN0_MB06_DATA0 0xFFC00CC0 /* CAN0 Mailbox Word 0 Register */
189#define CAN0_MB07_DATA0 0xFFC00CE0 /* CAN0 Mailbox Word 0 Register */
190#define CAN0_MB08_DATA0 0xFFC00D00 /* CAN0 Mailbox Word 0 Register */
191#define CAN0_MB09_DATA0 0xFFC00D20 /* CAN0 Mailbox Word 0 Register */
192#define CAN0_MB10_DATA0 0xFFC00D40 /* CAN0 Mailbox Word 0 Register */
193#define CAN0_MB11_DATA0 0xFFC00D60 /* CAN0 Mailbox Word 0 Register */
194#define CAN0_MB12_DATA0 0xFFC00D80 /* CAN0 Mailbox Word 0 Register */
195#define CAN0_MB13_DATA0 0xFFC00DA0 /* CAN0 Mailbox Word 0 Register */
196#define CAN0_MB14_DATA0 0xFFC00DC0 /* CAN0 Mailbox Word 0 Register */
197#define CAN0_MB15_DATA0 0xFFC00DE0 /* CAN0 Mailbox Word 0 Register */
198#define CAN0_MB16_DATA0 0xFFC00E00 /* CAN0 Mailbox Word 0 Register */
199#define CAN0_MB17_DATA0 0xFFC00E20 /* CAN0 Mailbox Word 0 Register */
200#define CAN0_MB18_DATA0 0xFFC00E40 /* CAN0 Mailbox Word 0 Register */
201#define CAN0_MB19_DATA0 0xFFC00E60 /* CAN0 Mailbox Word 0 Register */
202#define CAN0_MB20_DATA0 0xFFC00E80 /* CAN0 Mailbox Word 0 Register */
203#define CAN0_MB21_DATA0 0xFFC00EA0 /* CAN0 Mailbox Word 0 Register */
204#define CAN0_MB22_DATA0 0xFFC00EC0 /* CAN0 Mailbox Word 0 Register */
205#define CAN0_MB23_DATA0 0xFFC00EE0 /* CAN0 Mailbox Word 0 Register */
206#define CAN0_MB24_DATA0 0xFFC00F00 /* CAN0 Mailbox Word 0 Register */
207#define CAN0_MB25_DATA0 0xFFC00F20 /* CAN0 Mailbox Word 0 Register */
208#define CAN0_MB26_DATA0 0xFFC00F40 /* CAN0 Mailbox Word 0 Register */
209#define CAN0_MB27_DATA0 0xFFC00F60 /* CAN0 Mailbox Word 0 Register */
210#define CAN0_MB28_DATA0 0xFFC00F80 /* CAN0 Mailbox Word 0 Register */
211#define CAN0_MB29_DATA0 0xFFC00FA0 /* CAN0 Mailbox Word 0 Register */
212#define CAN0_MB30_DATA0 0xFFC00FC0 /* CAN0 Mailbox Word 0 Register */
213#define CAN0_MB31_DATA0 0xFFC00FE0 /* CAN0 Mailbox Word 0 Register */
214#define CAN0_MB00_DATA1 0xFFC00C04 /* CAN0 Mailbox Word 1 Register */
215#define CAN0_MB01_DATA1 0xFFC00C24 /* CAN0 Mailbox Word 1 Register */
216#define CAN0_MB02_DATA1 0xFFC00C44 /* CAN0 Mailbox Word 1 Register */
217#define CAN0_MB03_DATA1 0xFFC00C64 /* CAN0 Mailbox Word 1 Register */
218#define CAN0_MB04_DATA1 0xFFC00C84 /* CAN0 Mailbox Word 1 Register */
219#define CAN0_MB05_DATA1 0xFFC00CA4 /* CAN0 Mailbox Word 1 Register */
220#define CAN0_MB06_DATA1 0xFFC00CC4 /* CAN0 Mailbox Word 1 Register */
221#define CAN0_MB07_DATA1 0xFFC00CE4 /* CAN0 Mailbox Word 1 Register */
222#define CAN0_MB08_DATA1 0xFFC00D04 /* CAN0 Mailbox Word 1 Register */
223#define CAN0_MB09_DATA1 0xFFC00D24 /* CAN0 Mailbox Word 1 Register */
224#define CAN0_MB10_DATA1 0xFFC00D44 /* CAN0 Mailbox Word 1 Register */
225#define CAN0_MB11_DATA1 0xFFC00D64 /* CAN0 Mailbox Word 1 Register */
226#define CAN0_MB12_DATA1 0xFFC00D84 /* CAN0 Mailbox Word 1 Register */
227#define CAN0_MB13_DATA1 0xFFC00DA4 /* CAN0 Mailbox Word 1 Register */
228#define CAN0_MB14_DATA1 0xFFC00DC4 /* CAN0 Mailbox Word 1 Register */
229#define CAN0_MB15_DATA1 0xFFC00DE4 /* CAN0 Mailbox Word 1 Register */
230#define CAN0_MB16_DATA1 0xFFC00E04 /* CAN0 Mailbox Word 1 Register */
231#define CAN0_MB17_DATA1 0xFFC00E24 /* CAN0 Mailbox Word 1 Register */
232#define CAN0_MB18_DATA1 0xFFC00E44 /* CAN0 Mailbox Word 1 Register */
233#define CAN0_MB19_DATA1 0xFFC00E64 /* CAN0 Mailbox Word 1 Register */
234#define CAN0_MB20_DATA1 0xFFC00E84 /* CAN0 Mailbox Word 1 Register */
235#define CAN0_MB21_DATA1 0xFFC00EA4 /* CAN0 Mailbox Word 1 Register */
236#define CAN0_MB22_DATA1 0xFFC00EC4 /* CAN0 Mailbox Word 1 Register */
237#define CAN0_MB23_DATA1 0xFFC00EE4 /* CAN0 Mailbox Word 1 Register */
238#define CAN0_MB24_DATA1 0xFFC00F04 /* CAN0 Mailbox Word 1 Register */
239#define CAN0_MB25_DATA1 0xFFC00F24 /* CAN0 Mailbox Word 1 Register */
240#define CAN0_MB26_DATA1 0xFFC00F44 /* CAN0 Mailbox Word 1 Register */
241#define CAN0_MB27_DATA1 0xFFC00F64 /* CAN0 Mailbox Word 1 Register */
242#define CAN0_MB28_DATA1 0xFFC00F84 /* CAN0 Mailbox Word 1 Register */
243#define CAN0_MB29_DATA1 0xFFC00FA4 /* CAN0 Mailbox Word 1 Register */
244#define CAN0_MB30_DATA1 0xFFC00FC4 /* CAN0 Mailbox Word 1 Register */
245#define CAN0_MB31_DATA1 0xFFC00FE4 /* CAN0 Mailbox Word 1 Register */
246#define CAN0_MB00_DATA2 0xFFC00C08 /* CAN0 Mailbox Word 2 Register */
247#define CAN0_MB01_DATA2 0xFFC00C28 /* CAN0 Mailbox Word 2 Register */
248#define CAN0_MB02_DATA2 0xFFC00C48 /* CAN0 Mailbox Word 2 Register */
249#define CAN0_MB03_DATA2 0xFFC00C68 /* CAN0 Mailbox Word 2 Register */
250#define CAN0_MB04_DATA2 0xFFC00C88 /* CAN0 Mailbox Word 2 Register */
251#define CAN0_MB05_DATA2 0xFFC00CA8 /* CAN0 Mailbox Word 2 Register */
252#define CAN0_MB06_DATA2 0xFFC00CC8 /* CAN0 Mailbox Word 2 Register */
253#define CAN0_MB07_DATA2 0xFFC00CE8 /* CAN0 Mailbox Word 2 Register */
254#define CAN0_MB08_DATA2 0xFFC00D08 /* CAN0 Mailbox Word 2 Register */
255#define CAN0_MB09_DATA2 0xFFC00D28 /* CAN0 Mailbox Word 2 Register */
256#define CAN0_MB10_DATA2 0xFFC00D48 /* CAN0 Mailbox Word 2 Register */
257#define CAN0_MB11_DATA2 0xFFC00D68 /* CAN0 Mailbox Word 2 Register */
258#define CAN0_MB12_DATA2 0xFFC00D88 /* CAN0 Mailbox Word 2 Register */
259#define CAN0_MB13_DATA2 0xFFC00DA8 /* CAN0 Mailbox Word 2 Register */
260#define CAN0_MB14_DATA2 0xFFC00DC8 /* CAN0 Mailbox Word 2 Register */
261#define CAN0_MB15_DATA2 0xFFC00DE8 /* CAN0 Mailbox Word 2 Register */
262#define CAN0_MB16_DATA2 0xFFC00E08 /* CAN0 Mailbox Word 2 Register */
263#define CAN0_MB17_DATA2 0xFFC00E28 /* CAN0 Mailbox Word 2 Register */
264#define CAN0_MB18_DATA2 0xFFC00E48 /* CAN0 Mailbox Word 2 Register */
265#define CAN0_MB19_DATA2 0xFFC00E68 /* CAN0 Mailbox Word 2 Register */
266#define CAN0_MB20_DATA2 0xFFC00E88 /* CAN0 Mailbox Word 2 Register */
267#define CAN0_MB21_DATA2 0xFFC00EA8 /* CAN0 Mailbox Word 2 Register */
268#define CAN0_MB22_DATA2 0xFFC00EC8 /* CAN0 Mailbox Word 2 Register */
269#define CAN0_MB23_DATA2 0xFFC00EE8 /* CAN0 Mailbox Word 2 Register */
270#define CAN0_MB24_DATA2 0xFFC00F08 /* CAN0 Mailbox Word 2 Register */
271#define CAN0_MB25_DATA2 0xFFC00F28 /* CAN0 Mailbox Word 2 Register */
272#define CAN0_MB26_DATA2 0xFFC00F48 /* CAN0 Mailbox Word 2 Register */
273#define CAN0_MB27_DATA2 0xFFC00F68 /* CAN0 Mailbox Word 2 Register */
274#define CAN0_MB28_DATA2 0xFFC00F88 /* CAN0 Mailbox Word 2 Register */
275#define CAN0_MB29_DATA2 0xFFC00FA8 /* CAN0 Mailbox Word 2 Register */
276#define CAN0_MB30_DATA2 0xFFC00FC8 /* CAN0 Mailbox Word 2 Register */
277#define CAN0_MB31_DATA2 0xFFC00FE8 /* CAN0 Mailbox Word 2 Register */
278#define CAN0_MB00_DATA3 0xFFC00C0C /* CAN0 Mailbox Word 3 Register */
279#define CAN0_MB01_DATA3 0xFFC00C2C /* CAN0 Mailbox Word 3 Register */
280#define CAN0_MB02_DATA3 0xFFC00C4C /* CAN0 Mailbox Word 3 Register */
281#define CAN0_MB03_DATA3 0xFFC00C6C /* CAN0 Mailbox Word 3 Register */
282#define CAN0_MB04_DATA3 0xFFC00C8C /* CAN0 Mailbox Word 3 Register */
283#define CAN0_MB05_DATA3 0xFFC00CAC /* CAN0 Mailbox Word 3 Register */
284#define CAN0_MB06_DATA3 0xFFC00CCC /* CAN0 Mailbox Word 3 Register */
285#define CAN0_MB07_DATA3 0xFFC00CEC /* CAN0 Mailbox Word 3 Register */
286#define CAN0_MB08_DATA3 0xFFC00D0C /* CAN0 Mailbox Word 3 Register */
287#define CAN0_MB09_DATA3 0xFFC00D2C /* CAN0 Mailbox Word 3 Register */
288#define CAN0_MB10_DATA3 0xFFC00D4C /* CAN0 Mailbox Word 3 Register */
289#define CAN0_MB11_DATA3 0xFFC00D6C /* CAN0 Mailbox Word 3 Register */
290#define CAN0_MB12_DATA3 0xFFC00D8C /* CAN0 Mailbox Word 3 Register */
291#define CAN0_MB13_DATA3 0xFFC00DAC /* CAN0 Mailbox Word 3 Register */
292#define CAN0_MB14_DATA3 0xFFC00DCC /* CAN0 Mailbox Word 3 Register */
293#define CAN0_MB15_DATA3 0xFFC00DEC /* CAN0 Mailbox Word 3 Register */
294#define CAN0_MB16_DATA3 0xFFC00E0C /* CAN0 Mailbox Word 3 Register */
295#define CAN0_MB17_DATA3 0xFFC00E2C /* CAN0 Mailbox Word 3 Register */
296#define CAN0_MB18_DATA3 0xFFC00E4C /* CAN0 Mailbox Word 3 Register */
297#define CAN0_MB19_DATA3 0xFFC00E6C /* CAN0 Mailbox Word 3 Register */
298#define CAN0_MB20_DATA3 0xFFC00E8C /* CAN0 Mailbox Word 3 Register */
299#define CAN0_MB21_DATA3 0xFFC00EAC /* CAN0 Mailbox Word 3 Register */
300#define CAN0_MB22_DATA3 0xFFC00ECC /* CAN0 Mailbox Word 3 Register */
301#define CAN0_MB23_DATA3 0xFFC00EEC /* CAN0 Mailbox Word 3 Register */
302#define CAN0_MB24_DATA3 0xFFC00F0C /* CAN0 Mailbox Word 3 Register */
303#define CAN0_MB25_DATA3 0xFFC00F2C /* CAN0 Mailbox Word 3 Register */
304#define CAN0_MB26_DATA3 0xFFC00F4C /* CAN0 Mailbox Word 3 Register */
305#define CAN0_MB27_DATA3 0xFFC00F6C /* CAN0 Mailbox Word 3 Register */
306#define CAN0_MB28_DATA3 0xFFC00F8C /* CAN0 Mailbox Word 3 Register */
307#define CAN0_MB29_DATA3 0xFFC00FAC /* CAN0 Mailbox Word 3 Register */
308#define CAN0_MB30_DATA3 0xFFC00FCC /* CAN0 Mailbox Word 3 Register */
309#define CAN0_MB31_DATA3 0xFFC00FEC /* CAN0 Mailbox Word 3 Register */
310#define CAN0_MB00_LENGTH 0xFFC00C10 /* CAN0 Mailbox Word 4 Register */
311#define CAN0_MB01_LENGTH 0xFFC00C30 /* CAN0 Mailbox Word 4 Register */
312#define CAN0_MB02_LENGTH 0xFFC00C50 /* CAN0 Mailbox Word 4 Register */
313#define CAN0_MB03_LENGTH 0xFFC00C70 /* CAN0 Mailbox Word 4 Register */
314#define CAN0_MB04_LENGTH 0xFFC00C90 /* CAN0 Mailbox Word 4 Register */
315#define CAN0_MB05_LENGTH 0xFFC00CB0 /* CAN0 Mailbox Word 4 Register */
316#define CAN0_MB06_LENGTH 0xFFC00CD0 /* CAN0 Mailbox Word 4 Register */
317#define CAN0_MB07_LENGTH 0xFFC00CF0 /* CAN0 Mailbox Word 4 Register */
318#define CAN0_MB08_LENGTH 0xFFC00D10 /* CAN0 Mailbox Word 4 Register */
319#define CAN0_MB09_LENGTH 0xFFC00D30 /* CAN0 Mailbox Word 4 Register */
320#define CAN0_MB10_LENGTH 0xFFC00D50 /* CAN0 Mailbox Word 4 Register */
321#define CAN0_MB11_LENGTH 0xFFC00D70 /* CAN0 Mailbox Word 4 Register */
322#define CAN0_MB12_LENGTH 0xFFC00D90 /* CAN0 Mailbox Word 4 Register */
323#define CAN0_MB13_LENGTH 0xFFC00DB0 /* CAN0 Mailbox Word 4 Register */
324#define CAN0_MB14_LENGTH 0xFFC00DD0 /* CAN0 Mailbox Word 4 Register */
325#define CAN0_MB15_LENGTH 0xFFC00DF0 /* CAN0 Mailbox Word 4 Register */
326#define CAN0_MB16_LENGTH 0xFFC00E10 /* CAN0 Mailbox Word 4 Register */
327#define CAN0_MB17_LENGTH 0xFFC00E30 /* CAN0 Mailbox Word 4 Register */
328#define CAN0_MB18_LENGTH 0xFFC00E50 /* CAN0 Mailbox Word 4 Register */
329#define CAN0_MB19_LENGTH 0xFFC00E70 /* CAN0 Mailbox Word 4 Register */
330#define CAN0_MB20_LENGTH 0xFFC00E90 /* CAN0 Mailbox Word 4 Register */
331#define CAN0_MB21_LENGTH 0xFFC00EB0 /* CAN0 Mailbox Word 4 Register */
332#define CAN0_MB22_LENGTH 0xFFC00ED0 /* CAN0 Mailbox Word 4 Register */
333#define CAN0_MB23_LENGTH 0xFFC00EF0 /* CAN0 Mailbox Word 4 Register */
334#define CAN0_MB24_LENGTH 0xFFC00F10 /* CAN0 Mailbox Word 4 Register */
335#define CAN0_MB25_LENGTH 0xFFC00F30 /* CAN0 Mailbox Word 4 Register */
336#define CAN0_MB26_LENGTH 0xFFC00F50 /* CAN0 Mailbox Word 4 Register */
337#define CAN0_MB27_LENGTH 0xFFC00F70 /* CAN0 Mailbox Word 4 Register */
338#define CAN0_MB28_LENGTH 0xFFC00F90 /* CAN0 Mailbox Word 4 Register */
339#define CAN0_MB29_LENGTH 0xFFC00FB0 /* CAN0 Mailbox Word 4 Register */
340#define CAN0_MB30_LENGTH 0xFFC00FD0 /* CAN0 Mailbox Word 4 Register */
341#define CAN0_MB31_LENGTH 0xFFC00FF0 /* CAN0 Mailbox Word 4 Register */
342#define CAN0_MB00_TIMESTAMP 0xFFC00C14 /* CAN0 Mailbox Word 5 Register */
343#define CAN0_MB01_TIMESTAMP 0xFFC00C34 /* CAN0 Mailbox Word 5 Register */
344#define CAN0_MB02_TIMESTAMP 0xFFC00C54 /* CAN0 Mailbox Word 5 Register */
345#define CAN0_MB03_TIMESTAMP 0xFFC00C74 /* CAN0 Mailbox Word 5 Register */
346#define CAN0_MB04_TIMESTAMP 0xFFC00C94 /* CAN0 Mailbox Word 5 Register */
347#define CAN0_MB05_TIMESTAMP 0xFFC00CB4 /* CAN0 Mailbox Word 5 Register */
348#define CAN0_MB06_TIMESTAMP 0xFFC00CD4 /* CAN0 Mailbox Word 5 Register */
349#define CAN0_MB07_TIMESTAMP 0xFFC00CF4 /* CAN0 Mailbox Word 5 Register */
350#define CAN0_MB08_TIMESTAMP 0xFFC00D14 /* CAN0 Mailbox Word 5 Register */
351#define CAN0_MB09_TIMESTAMP 0xFFC00D34 /* CAN0 Mailbox Word 5 Register */
352#define CAN0_MB10_TIMESTAMP 0xFFC00D54 /* CAN0 Mailbox Word 5 Register */
353#define CAN0_MB11_TIMESTAMP 0xFFC00D74 /* CAN0 Mailbox Word 5 Register */
354#define CAN0_MB12_TIMESTAMP 0xFFC00D94 /* CAN0 Mailbox Word 5 Register */
355#define CAN0_MB13_TIMESTAMP 0xFFC00DB4 /* CAN0 Mailbox Word 5 Register */
356#define CAN0_MB14_TIMESTAMP 0xFFC00DD4 /* CAN0 Mailbox Word 5 Register */
357#define CAN0_MB15_TIMESTAMP 0xFFC00DF4 /* CAN0 Mailbox Word 5 Register */
358#define CAN0_MB16_TIMESTAMP 0xFFC00E14 /* CAN0 Mailbox Word 5 Register */
359#define CAN0_MB17_TIMESTAMP 0xFFC00E34 /* CAN0 Mailbox Word 5 Register */
360#define CAN0_MB18_TIMESTAMP 0xFFC00E54 /* CAN0 Mailbox Word 5 Register */
361#define CAN0_MB19_TIMESTAMP 0xFFC00E74 /* CAN0 Mailbox Word 5 Register */
362#define CAN0_MB20_TIMESTAMP 0xFFC00E94 /* CAN0 Mailbox Word 5 Register */
363#define CAN0_MB21_TIMESTAMP 0xFFC00EB4 /* CAN0 Mailbox Word 5 Register */
364#define CAN0_MB22_TIMESTAMP 0xFFC00ED4 /* CAN0 Mailbox Word 5 Register */
365#define CAN0_MB23_TIMESTAMP 0xFFC00EF4 /* CAN0 Mailbox Word 5 Register */
366#define CAN0_MB24_TIMESTAMP 0xFFC00F14 /* CAN0 Mailbox Word 5 Register */
367#define CAN0_MB25_TIMESTAMP 0xFFC00F34 /* CAN0 Mailbox Word 5 Register */
368#define CAN0_MB26_TIMESTAMP 0xFFC00F54 /* CAN0 Mailbox Word 5 Register */
369#define CAN0_MB27_TIMESTAMP 0xFFC00F74 /* CAN0 Mailbox Word 5 Register */
370#define CAN0_MB28_TIMESTAMP 0xFFC00F94 /* CAN0 Mailbox Word 5 Register */
371#define CAN0_MB29_TIMESTAMP 0xFFC00FB4 /* CAN0 Mailbox Word 5 Register */
372#define CAN0_MB30_TIMESTAMP 0xFFC00FD4 /* CAN0 Mailbox Word 5 Register */
373#define CAN0_MB31_TIMESTAMP 0xFFC00FF4 /* CAN0 Mailbox Word 5 Register */
374#define CAN0_MB00_ID0 0xFFC00C18 /* CAN0 Mailbox Word 6 Register */
375#define CAN0_MB01_ID0 0xFFC00C38 /* CAN0 Mailbox Word 6 Register */
376#define CAN0_MB02_ID0 0xFFC00C58 /* CAN0 Mailbox Word 6 Register */
377#define CAN0_MB03_ID0 0xFFC00C78 /* CAN0 Mailbox Word 6 Register */
378#define CAN0_MB04_ID0 0xFFC00C98 /* CAN0 Mailbox Word 6 Register */
379#define CAN0_MB05_ID0 0xFFC00CB8 /* CAN0 Mailbox Word 6 Register */
380#define CAN0_MB06_ID0 0xFFC00CD8 /* CAN0 Mailbox Word 6 Register */
381#define CAN0_MB07_ID0 0xFFC00CF8 /* CAN0 Mailbox Word 6 Register */
382#define CAN0_MB08_ID0 0xFFC00D18 /* CAN0 Mailbox Word 6 Register */
383#define CAN0_MB09_ID0 0xFFC00D38 /* CAN0 Mailbox Word 6 Register */
384#define CAN0_MB10_ID0 0xFFC00D58 /* CAN0 Mailbox Word 6 Register */
385#define CAN0_MB11_ID0 0xFFC00D78 /* CAN0 Mailbox Word 6 Register */
386#define CAN0_MB12_ID0 0xFFC00D98 /* CAN0 Mailbox Word 6 Register */
387#define CAN0_MB13_ID0 0xFFC00DB8 /* CAN0 Mailbox Word 6 Register */
388#define CAN0_MB14_ID0 0xFFC00DD8 /* CAN0 Mailbox Word 6 Register */
389#define CAN0_MB15_ID0 0xFFC00DF8 /* CAN0 Mailbox Word 6 Register */
390#define CAN0_MB16_ID0 0xFFC00E18 /* CAN0 Mailbox Word 6 Register */
391#define CAN0_MB17_ID0 0xFFC00E38 /* CAN0 Mailbox Word 6 Register */
392#define CAN0_MB18_ID0 0xFFC00E58 /* CAN0 Mailbox Word 6 Register */
393#define CAN0_MB19_ID0 0xFFC00E78 /* CAN0 Mailbox Word 6 Register */
394#define CAN0_MB20_ID0 0xFFC00E98 /* CAN0 Mailbox Word 6 Register */
395#define CAN0_MB21_ID0 0xFFC00EB8 /* CAN0 Mailbox Word 6 Register */
396#define CAN0_MB22_ID0 0xFFC00ED8 /* CAN0 Mailbox Word 6 Register */
397#define CAN0_MB23_ID0 0xFFC00EF8 /* CAN0 Mailbox Word 6 Register */
398#define CAN0_MB24_ID0 0xFFC00F18 /* CAN0 Mailbox Word 6 Register */
399#define CAN0_MB25_ID0 0xFFC00F38 /* CAN0 Mailbox Word 6 Register */
400#define CAN0_MB26_ID0 0xFFC00F58 /* CAN0 Mailbox Word 6 Register */
401#define CAN0_MB27_ID0 0xFFC00F78 /* CAN0 Mailbox Word 6 Register */
402#define CAN0_MB28_ID0 0xFFC00F98 /* CAN0 Mailbox Word 6 Register */
403#define CAN0_MB29_ID0 0xFFC00FB8 /* CAN0 Mailbox Word 6 Register */
404#define CAN0_MB30_ID0 0xFFC00FD8 /* CAN0 Mailbox Word 6 Register */
405#define CAN0_MB31_ID0 0xFFC00FF8 /* CAN0 Mailbox Word 6 Register */
406#define CAN0_MB00_ID1 0xFFC00C1C /* CAN0 Mailbox Word 7 Register */
407#define CAN0_MB01_ID1 0xFFC00C3C /* CAN0 Mailbox Word 7 Register */
408#define CAN0_MB02_ID1 0xFFC00C5C /* CAN0 Mailbox Word 7 Register */
409#define CAN0_MB03_ID1 0xFFC00C7C /* CAN0 Mailbox Word 7 Register */
410#define CAN0_MB04_ID1 0xFFC00C9C /* CAN0 Mailbox Word 7 Register */
411#define CAN0_MB05_ID1 0xFFC00CBC /* CAN0 Mailbox Word 7 Register */
412#define CAN0_MB06_ID1 0xFFC00CDC /* CAN0 Mailbox Word 7 Register */
413#define CAN0_MB07_ID1 0xFFC00CFC /* CAN0 Mailbox Word 7 Register */
414#define CAN0_MB08_ID1 0xFFC00D1C /* CAN0 Mailbox Word 7 Register */
415#define CAN0_MB09_ID1 0xFFC00D3C /* CAN0 Mailbox Word 7 Register */
416#define CAN0_MB10_ID1 0xFFC00D5C /* CAN0 Mailbox Word 7 Register */
417#define CAN0_MB11_ID1 0xFFC00D7C /* CAN0 Mailbox Word 7 Register */
418#define CAN0_MB12_ID1 0xFFC00D9C /* CAN0 Mailbox Word 7 Register */
419#define CAN0_MB13_ID1 0xFFC00DBC /* CAN0 Mailbox Word 7 Register */
420#define CAN0_MB14_ID1 0xFFC00DDC /* CAN0 Mailbox Word 7 Register */
421#define CAN0_MB15_ID1 0xFFC00DFC /* CAN0 Mailbox Word 7 Register */
422#define CAN0_MB16_ID1 0xFFC00E1C /* CAN0 Mailbox Word 7 Register */
423#define CAN0_MB17_ID1 0xFFC00E3C /* CAN0 Mailbox Word 7 Register */
424#define CAN0_MB18_ID1 0xFFC00E5C /* CAN0 Mailbox Word 7 Register */
425#define CAN0_MB19_ID1 0xFFC00E7C /* CAN0 Mailbox Word 7 Register */
426#define CAN0_MB20_ID1 0xFFC00E9C /* CAN0 Mailbox Word 7 Register */
427#define CAN0_MB21_ID1 0xFFC00EBC /* CAN0 Mailbox Word 7 Register */
428#define CAN0_MB22_ID1 0xFFC00EDC /* CAN0 Mailbox Word 7 Register */
429#define CAN0_MB23_ID1 0xFFC00EFC /* CAN0 Mailbox Word 7 Register */
430#define CAN0_MB24_ID1 0xFFC00F1C /* CAN0 Mailbox Word 7 Register */
431#define CAN0_MB25_ID1 0xFFC00F3C /* CAN0 Mailbox Word 7 Register */
432#define CAN0_MB26_ID1 0xFFC00F5C /* CAN0 Mailbox Word 7 Register */
433#define CAN0_MB27_ID1 0xFFC00F7C /* CAN0 Mailbox Word 7 Register */
434#define CAN0_MB28_ID1 0xFFC00F9C /* CAN0 Mailbox Word 7 Register */
435#define CAN0_MB29_ID1 0xFFC00FBC /* CAN0 Mailbox Word 7 Register */
436#define CAN0_MB30_ID1 0xFFC00FDC /* CAN0 Mailbox Word 7 Register */
437#define CAN0_MB31_ID1 0xFFC00FFC /* CAN0 Mailbox Word 7 Register */
438
439/* =========================
440 LINK PORT Registers
441 ========================= */
442#define LP0_CTL 0xFFC01000 /* LP0 Control Register */
443#define LP0_STAT 0xFFC01004 /* LP0 Status Register */
444#define LP0_DIV 0xFFC01008 /* LP0 Clock Divider Value */
445#define LP0_CNT 0xFFC0100C /* LP0 Current Count Value of Clock Divider */
446#define LP0_TX 0xFFC01010 /* LP0 Transmit Buffer */
447#define LP0_RX 0xFFC01014 /* LP0 Receive Buffer */
448#define LP0_TXIN_SHDW 0xFFC01018 /* LP0 Shadow Input Transmit Buffer */
449#define LP0_TXOUT_SHDW 0xFFC0101C /* LP0 Shadow Output Transmit Buffer */
450#define LP1_CTL 0xFFC01100 /* LP1 Control Register */
451#define LP1_STAT 0xFFC01104 /* LP1 Status Register */
452#define LP1_DIV 0xFFC01108 /* LP1 Clock Divider Value */
453#define LP1_CNT 0xFFC0110C /* LP1 Current Count Value of Clock Divider */
454#define LP1_TX 0xFFC01110 /* LP1 Transmit Buffer */
455#define LP1_RX 0xFFC01114 /* LP1 Receive Buffer */
456#define LP1_TXIN_SHDW 0xFFC01118 /* LP1 Shadow Input Transmit Buffer */
457#define LP1_TXOUT_SHDW 0xFFC0111C /* LP1 Shadow Output Transmit Buffer */
458#define LP2_CTL 0xFFC01200 /* LP2 Control Register */
459#define LP2_STAT 0xFFC01204 /* LP2 Status Register */
460#define LP2_DIV 0xFFC01208 /* LP2 Clock Divider Value */
461#define LP2_CNT 0xFFC0120C /* LP2 Current Count Value of Clock Divider */
462#define LP2_TX 0xFFC01210 /* LP2 Transmit Buffer */
463#define LP2_RX 0xFFC01214 /* LP2 Receive Buffer */
464#define LP2_TXIN_SHDW 0xFFC01218 /* LP2 Shadow Input Transmit Buffer */
465#define LP2_TXOUT_SHDW 0xFFC0121C /* LP2 Shadow Output Transmit Buffer */
466#define LP3_CTL 0xFFC01300 /* LP3 Control Register */
467#define LP3_STAT 0xFFC01304 /* LP3 Status Register */
468#define LP3_DIV 0xFFC01308 /* LP3 Clock Divider Value */
469#define LP3_CNT 0xFFC0130C /* LP3 Current Count Value of Clock Divider */
470#define LP3_TX 0xFFC01310 /* LP3 Transmit Buffer */
471#define LP3_RX 0xFFC01314 /* LP3 Receive Buffer */
472#define LP3_TXIN_SHDW 0xFFC01318 /* LP3 Shadow Input Transmit Buffer */
473#define LP3_TXOUT_SHDW 0xFFC0131C /* LP3 Shadow Output Transmit Buffer */
474
475/* =========================
476 TIMER Registers
477 ========================= */
478#define TIMER_REVID 0xFFC01400 /* GPTIMER Timer IP Version ID */
479#define TIMER_RUN 0xFFC01404 /* GPTIMER Timer Run Register */
480#define TIMER_RUN_SET 0xFFC01408 /* GPTIMER Run Register Alias to Set */
481#define TIMER_RUN_CLR 0xFFC0140C /* GPTIMER Run Register Alias to Clear */
482#define TIMER_STOP_CFG 0xFFC01410 /* GPTIMER Stop Config Register */
483#define TIMER_STOP_CFG_SET 0xFFC01414 /* GPTIMER Stop Config Alias to Set */
484#define TIMER_STOP_CFG_CLR 0xFFC01418 /* GPTIMER Stop Config Alias to Clear */
485#define TIMER_DATA_IMSK 0xFFC0141C /* GPTIMER Data Interrupt Mask register */
486#define TIMER_STAT_IMSK 0xFFC01420 /* GPTIMER Status Interrupt Mask register */
487#define TIMER_TRG_MSK 0xFFC01424 /* GPTIMER Output Trigger Mask register */
488#define TIMER_TRG_IE 0xFFC01428 /* GPTIMER Slave Trigger Enable register */
489#define TIMER_DATA_ILAT 0xFFC0142C /* GPTIMER Data Interrupt Register */
490#define TIMER_STAT_ILAT 0xFFC01430 /* GPTIMER Status (Error) Interrupt Register */
491#define TIMER_ERR_TYPE 0xFFC01434 /* GPTIMER Register Indicating Type of Error */
492#define TIMER_BCAST_PER 0xFFC01438 /* GPTIMER Broadcast Period */
493#define TIMER_BCAST_WID 0xFFC0143C /* GPTIMER Broadcast Width */
494#define TIMER_BCAST_DLY 0xFFC01440 /* GPTIMER Broadcast Delay */
495
496/* =========================
497 TIMER0~7
498 ========================= */
499#define TIMER0_CONFIG 0xFFC01460 /* TIMER0 Per Timer Config Register */
500#define TIMER0_COUNTER 0xFFC01464 /* TIMER0 Per Timer Counter Register */
501#define TIMER0_PERIOD 0xFFC01468 /* TIMER0 Per Timer Period Register */
502#define TIMER0_WIDTH 0xFFC0146C /* TIMER0 Per Timer Width Register */
503#define TIMER0_DELAY 0xFFC01470 /* TIMER0 Per Timer Delay Register */
504
505#define TIMER1_CONFIG 0xFFC01480 /* TIMER1 Per Timer Config Register */
506#define TIMER1_COUNTER 0xFFC01484 /* TIMER1 Per Timer Counter Register */
507#define TIMER1_PERIOD 0xFFC01488 /* TIMER1 Per Timer Period Register */
508#define TIMER1_WIDTH 0xFFC0148C /* TIMER1 Per Timer Width Register */
509#define TIMER1_DELAY 0xFFC01490 /* TIMER1 Per Timer Delay Register */
510
511#define TIMER2_CONFIG 0xFFC014A0 /* TIMER2 Per Timer Config Register */
512#define TIMER2_COUNTER 0xFFC014A4 /* TIMER2 Per Timer Counter Register */
513#define TIMER2_PERIOD 0xFFC014A8 /* TIMER2 Per Timer Period Register */
514#define TIMER2_WIDTH 0xFFC014AC /* TIMER2 Per Timer Width Register */
515#define TIMER2_DELAY 0xFFC014B0 /* TIMER2 Per Timer Delay Register */
516
517#define TIMER3_CONFIG 0xFFC014C0 /* TIMER3 Per Timer Config Register */
518#define TIMER3_COUNTER 0xFFC014C4 /* TIMER3 Per Timer Counter Register */
519#define TIMER3_PERIOD 0xFFC014C8 /* TIMER3 Per Timer Period Register */
520#define TIMER3_WIDTH 0xFFC014CC /* TIMER3 Per Timer Width Register */
521#define TIMER3_DELAY 0xFFC014D0 /* TIMER3 Per Timer Delay Register */
522
523#define TIMER4_CONFIG 0xFFC014E0 /* TIMER4 Per Timer Config Register */
524#define TIMER4_COUNTER 0xFFC014E4 /* TIMER4 Per Timer Counter Register */
525#define TIMER4_PERIOD 0xFFC014E8 /* TIMER4 Per Timer Period Register */
526#define TIMER4_WIDTH 0xFFC014EC /* TIMER4 Per Timer Width Register */
527#define TIMER4_DELAY 0xFFC014F0 /* TIMER4 Per Timer Delay Register */
528
529#define TIMER5_CONFIG 0xFFC01500 /* TIMER5 Per Timer Config Register */
530#define TIMER5_COUNTER 0xFFC01504 /* TIMER5 Per Timer Counter Register */
531#define TIMER5_PERIOD 0xFFC01508 /* TIMER5 Per Timer Period Register */
532#define TIMER5_WIDTH 0xFFC0150C /* TIMER5 Per Timer Width Register */
533#define TIMER5_DELAY 0xFFC01510 /* TIMER5 Per Timer Delay Register */
534
535#define TIMER6_CONFIG 0xFFC01520 /* TIMER6 Per Timer Config Register */
536#define TIMER6_COUNTER 0xFFC01524 /* TIMER6 Per Timer Counter Register */
537#define TIMER6_PERIOD 0xFFC01528 /* TIMER6 Per Timer Period Register */
538#define TIMER6_WIDTH 0xFFC0152C /* TIMER6 Per Timer Width Register */
539#define TIMER6_DELAY 0xFFC01530 /* TIMER6 Per Timer Delay Register */
540
541#define TIMER7_CONFIG 0xFFC01540 /* TIMER7 Per Timer Config Register */
542#define TIMER7_COUNTER 0xFFC01544 /* TIMER7 Per Timer Counter Register */
543#define TIMER7_PERIOD 0xFFC01548 /* TIMER7 Per Timer Period Register */
544#define TIMER7_WIDTH 0xFFC0154C /* TIMER7 Per Timer Width Register */
545#define TIMER7_DELAY 0xFFC01550 /* TIMER7 Per Timer Delay Register */
546
547/* =========================
548 CRC Registers
549 ========================= */
550
551/* =========================
552 CRC0
553 ========================= */
554#define REG_CRC0_CTL 0xFFC01C00 /* CRC0 Control Register */
555#define REG_CRC0_DCNT 0xFFC01C04 /* CRC0 Data Word Count Register */
556#define REG_CRC0_DCNTRLD 0xFFC01C08 /* CRC0 Data Word Count Reload Register */
557#define REG_CRC0_COMP 0xFFC01C14 /* CRC0 DATA Compare Register */
558#define REG_CRC0_FILLVAL 0xFFC01C18 /* CRC0 Fill Value Register */
559#define REG_CRC0_DFIFO 0xFFC01C1C /* CRC0 DATA FIFO Register */
560#define REG_CRC0_INEN 0xFFC01C20 /* CRC0 Interrupt Enable Register */
561#define REG_CRC0_INEN_SET 0xFFC01C24 /* CRC0 Interrupt Enable Set Register */
562#define REG_CRC0_INEN_CLR 0xFFC01C28 /* CRC0 Interrupt Enable Clear Register */
563#define REG_CRC0_POLY 0xFFC01C2C /* CRC0 Polynomial Register */
564#define REG_CRC0_STAT 0xFFC01C40 /* CRC0 Status Register */
565#define REG_CRC0_DCNTCAP 0xFFC01C44 /* CRC0 DATA Count Capture Register */
566#define REG_CRC0_RESULT_FIN 0xFFC01C4C /* CRC0 Final CRC Result Register */
567#define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 Current CRC Result Register */
568#define REG_CRC0_REVID 0xFFC01C60 /* CRC0 Revision ID Register */
569
570/* =========================
571 CRC1
572 ========================= */
573#define REG_CRC1_CTL 0xFFC01D00 /* CRC1 Control Register */
574#define REG_CRC1_DCNT 0xFFC01D04 /* CRC1 Data Word Count Register */
575#define REG_CRC1_DCNTRLD 0xFFC01D08 /* CRC1 Data Word Count Reload Register */
576#define REG_CRC1_COMP 0xFFC01D14 /* CRC1 DATA Compare Register */
577#define REG_CRC1_FILLVAL 0xFFC01D18 /* CRC1 Fill Value Register */
578#define REG_CRC1_DFIFO 0xFFC01D1C /* CRC1 DATA FIFO Register */
579#define REG_CRC1_INEN 0xFFC01D20 /* CRC1 Interrupt Enable Register */
580#define REG_CRC1_INEN_SET 0xFFC01D24 /* CRC1 Interrupt Enable Set Register */
581#define REG_CRC1_INEN_CLR 0xFFC01D28 /* CRC1 Interrupt Enable Clear Register */
582#define REG_CRC1_POLY 0xFFC01D2C /* CRC1 Polynomial Register */
583#define REG_CRC1_STAT 0xFFC01D40 /* CRC1 Status Register */
584#define REG_CRC1_DCNTCAP 0xFFC01D44 /* CRC1 DATA Count Capture Register */
585#define REG_CRC1_RESULT_FIN 0xFFC01D4C /* CRC1 Final CRC Result Register */
586#define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 Current CRC Result Register */
587#define REG_CRC1_REVID 0xFFC01D60 /* CRC1 Revision ID Register */
588
589/* =========================
590 TWI Registers
591 ========================= */
592
593/* =========================
594 TWI0
595 ========================= */
596#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */
597#define TWI0_CONTROL 0xFFC01E04 /* TWI0 Control Register */
598#define TWI0_SLAVE_CTL 0xFFC01E08 /* TWI0 Slave Mode Control Register */
599#define TWI0_SLAVE_STAT 0xFFC01E0C /* TWI0 Slave Mode Status Register */
600#define TWI0_SLAVE_ADDR 0xFFC01E10 /* TWI0 Slave Mode Address Register */
601#define TWI0_MASTER_CTL 0xFFC01E14 /* TWI0 Master Mode Control Registers */
602#define TWI0_MASTER_STAT 0xFFC01E18 /* TWI0 Master Mode Status Register */
603#define TWI0_MASTER_ADDR 0xFFC01E1C /* TWI0 Master Mode Address Register */
604#define TWI0_INT_STAT 0xFFC01E20 /* TWI0 Interrupt Status Register */
605#define TWI0_INT_MASK 0xFFC01E24 /* TWI0 Interrupt Mask Register */
606#define TWI0_FIFO_CTL 0xFFC01E28 /* TWI0 FIFO Control Register */
607#define TWI0_FIFO_STAT 0xFFC01E2C /* TWI0 FIFO Status Register */
608#define TWI0_XMT_DATA8 0xFFC01E80 /* TWI0 FIFO Transmit Data Single-Byte Register */
609#define TWI0_XMT_DATA16 0xFFC01E84 /* TWI0 FIFO Transmit Data Double-Byte Register */
610#define TWI0_RCV_DATA8 0xFFC01E88 /* TWI0 FIFO Transmit Data Single-Byte Register */
611#define TWI0_RCV_DATA16 0xFFC01E8C /* TWI0 FIFO Transmit Data Double-Byte Register */
612
613/* =========================
614 TWI1
615 ========================= */
616#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
617#define TWI1_CONTROL 0xFFC01F04 /* TWI1 Control Register */
618#define TWI1_SLAVE_CTL 0xFFC01F08 /* TWI1 Slave Mode Control Register */
619#define TWI1_SLAVE_STAT 0xFFC01F0C /* TWI1 Slave Mode Status Register */
620#define TWI1_SLAVE_ADDR 0xFFC01F10 /* TWI1 Slave Mode Address Register */
621#define TWI1_MASTER_CTL 0xFFC01F14 /* TWI1 Master Mode Control Registers */
622#define TWI1_MASTER_STAT 0xFFC01F18 /* TWI1 Master Mode Status Register */
623#define TWI1_MASTER_ADDR 0xFFC01F1C /* TWI1 Master Mode Address Register */
624#define TWI1_INT_STAT 0xFFC01F20 /* TWI1 Interrupt Status Register */
625#define TWI1_INT_MASK 0xFFC01F24 /* TWI1 Interrupt Mask Register */
626#define TWI1_FIFO_CTL 0xFFC01F28 /* TWI1 FIFO Control Register */
627#define TWI1_FIFO_STAT 0xFFC01F2C /* TWI1 FIFO Status Register */
628#define TWI1_XMT_DATA8 0xFFC01F80 /* TWI1 FIFO Transmit Data Single-Byte Register */
629#define TWI1_XMT_DATA16 0xFFC01F84 /* TWI1 FIFO Transmit Data Double-Byte Register */
630#define TWI1_RCV_DATA8 0xFFC01F88 /* TWI1 FIFO Transmit Data Single-Byte Register */
631#define TWI1_RCV_DATA16 0xFFC01F8C /* TWI1 FIFO Transmit Data Double-Byte Register */
632
633
634/* =========================
635 UART Registers
636 ========================= */
637
638/* =========================
639 UART0
640 ========================= */
641#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
642#define UART0_CTL 0xFFC02004 /* UART0 Control Register */
643#define UART0_STAT 0xFFC02008 /* UART0 Status Register */
644#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
645#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
646#define UART0_IER 0xFFC02014 /* UART0 Interrupt Mask Register */
647#define UART0_IER_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
648#define UART0_IER_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
649#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
650#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
651#define UART0_TAIP 0xFFC02028 /* UART0 Transmit Address/Insert Pulse Register */
652#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
653#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
654#define UART0_TXDIV 0xFFC02034 /* UART0 Transmit Clock Devider Register */
655#define UART0_RXDIV 0xFFC02038 /* UART0 Receive Clock Devider Register */
656
657/* =========================
658 UART1
659 ========================= */
660#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
661#define UART1_CTL 0xFFC02404 /* UART1 Control Register */
662#define UART1_STAT 0xFFC02408 /* UART1 Status Register */
663#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
664#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
665#define UART1_IER 0xFFC02414 /* UART1 Interrupt Mask Register */
666#define UART1_IER_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
667#define UART1_IER_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
668#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
669#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
670#define UART1_TAIP 0xFFC02428 /* UART1 Transmit Address/Insert Pulse Register */
671#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
672#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
673#define UART1_TXDIV 0xFFC02434 /* UART1 Transmit Clock Devider Register */
674#define UART1_RXDIV 0xFFC02438 /* UART1 Receive Clock Devider Register */
675
676
677/* =========================
678 PORT Registers
679 ========================= */
680
681/* =========================
682 PORTA
683 ========================= */
684#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable Register */
685#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set Register */
686#define PORTA_FER_CLEAR 0xFFC03008 /* PORTA Port x Function Enable Clear Register */
687#define PORTA_DATA 0xFFC0300C /* PORTA Port x GPIO Data Register */
688#define PORTA_DATA_SET 0xFFC03010 /* PORTA Port x GPIO Data Set Register */
689#define PORTA_DATA_CLEAR 0xFFC03014 /* PORTA Port x GPIO Data Clear Register */
690#define PORTA_DIR 0xFFC03018 /* PORTA Port x GPIO Direction Register */
691#define PORTA_DIR_SET 0xFFC0301C /* PORTA Port x GPIO Direction Set Register */
692#define PORTA_DIR_CLEAR 0xFFC03020 /* PORTA Port x GPIO Direction Clear Register */
693#define PORTA_INEN 0xFFC03024 /* PORTA Port x GPIO Input Enable Register */
694#define PORTA_INEN_SET 0xFFC03028 /* PORTA Port x GPIO Input Enable Set Register */
695#define PORTA_INEN_CLEAR 0xFFC0302C /* PORTA Port x GPIO Input Enable Clear Register */
696#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control Register */
697#define PORTA_DATA_TGL 0xFFC03034 /* PORTA Port x GPIO Input Enable Toggle Register */
698#define PORTA_POL 0xFFC03038 /* PORTA Port x GPIO Programming Inversion Register */
699#define PORTA_POL_SET 0xFFC0303C /* PORTA Port x GPIO Programming Inversion Set Register */
700#define PORTA_POL_CLEAR 0xFFC03040 /* PORTA Port x GPIO Programming Inversion Clear Register */
701#define PORTA_LOCK 0xFFC03044 /* PORTA Port x GPIO Lock Register */
702#define PORTA_REVID 0xFFC0307C /* PORTA Port x GPIO Revision ID */
703
704/* =========================
705 PORTB
706 ========================= */
707#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable Register */
708#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set Register */
709#define PORTB_FER_CLEAR 0xFFC03088 /* PORTB Port x Function Enable Clear Register */
710#define PORTB_DATA 0xFFC0308C /* PORTB Port x GPIO Data Register */
711#define PORTB_DATA_SET 0xFFC03090 /* PORTB Port x GPIO Data Set Register */
712#define PORTB_DATA_CLEAR 0xFFC03094 /* PORTB Port x GPIO Data Clear Register */
713#define PORTB_DIR 0xFFC03098 /* PORTB Port x GPIO Direction Register */
714#define PORTB_DIR_SET 0xFFC0309C /* PORTB Port x GPIO Direction Set Register */
715#define PORTB_DIR_CLEAR 0xFFC030A0 /* PORTB Port x GPIO Direction Clear Register */
716#define PORTB_INEN 0xFFC030A4 /* PORTB Port x GPIO Input Enable Register */
717#define PORTB_INEN_SET 0xFFC030A8 /* PORTB Port x GPIO Input Enable Set Register */
718#define PORTB_INEN_CLEAR 0xFFC030AC /* PORTB Port x GPIO Input Enable Clear Register */
719#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control Register */
720#define PORTB_DATA_TGL 0xFFC030B4 /* PORTB Port x GPIO Input Enable Toggle Register */
721#define PORTB_POL 0xFFC030B8 /* PORTB Port x GPIO Programming Inversion Register */
722#define PORTB_POL_SET 0xFFC030BC /* PORTB Port x GPIO Programming Inversion Set Register */
723#define PORTB_POL_CLEAR 0xFFC030C0 /* PORTB Port x GPIO Programming Inversion Clear Register */
724#define PORTB_LOCK 0xFFC030C4 /* PORTB Port x GPIO Lock Register */
725#define PORTB_REVID 0xFFC030FC /* PORTB Port x GPIO Revision ID */
726
727/* =========================
728 PORTC
729 ========================= */
730#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable Register */
731#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set Register */
732#define PORTC_FER_CLEAR 0xFFC03108 /* PORTC Port x Function Enable Clear Register */
733#define PORTC_DATA 0xFFC0310C /* PORTC Port x GPIO Data Register */
734#define PORTC_DATA_SET 0xFFC03110 /* PORTC Port x GPIO Data Set Register */
735#define PORTC_DATA_CLEAR 0xFFC03114 /* PORTC Port x GPIO Data Clear Register */
736#define PORTC_DIR 0xFFC03118 /* PORTC Port x GPIO Direction Register */
737#define PORTC_DIR_SET 0xFFC0311C /* PORTC Port x GPIO Direction Set Register */
738#define PORTC_DIR_CLEAR 0xFFC03120 /* PORTC Port x GPIO Direction Clear Register */
739#define PORTC_INEN 0xFFC03124 /* PORTC Port x GPIO Input Enable Register */
740#define PORTC_INEN_SET 0xFFC03128 /* PORTC Port x GPIO Input Enable Set Register */
741#define PORTC_INEN_CLEAR 0xFFC0312C /* PORTC Port x GPIO Input Enable Clear Register */
742#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control Register */
743#define PORTC_DATA_TGL 0xFFC03134 /* PORTC Port x GPIO Input Enable Toggle Register */
744#define PORTC_POL 0xFFC03138 /* PORTC Port x GPIO Programming Inversion Register */
745#define PORTC_POL_SET 0xFFC0313C /* PORTC Port x GPIO Programming Inversion Set Register */
746#define PORTC_POL_CLEAR 0xFFC03140 /* PORTC Port x GPIO Programming Inversion Clear Register */
747#define PORTC_LOCK 0xFFC03144 /* PORTC Port x GPIO Lock Register */
748#define PORTC_REVID 0xFFC0317C /* PORTC Port x GPIO Revision ID */
749
750/* =========================
751 PORTD
752 ========================= */
753#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable Register */
754#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set Register */
755#define PORTD_FER_CLEAR 0xFFC03188 /* PORTD Port x Function Enable Clear Register */
756#define PORTD_DATA 0xFFC0318C /* PORTD Port x GPIO Data Register */
757#define PORTD_DATA_SET 0xFFC03190 /* PORTD Port x GPIO Data Set Register */
758#define PORTD_DATA_CLEAR 0xFFC03194 /* PORTD Port x GPIO Data Clear Register */
759#define PORTD_DIR 0xFFC03198 /* PORTD Port x GPIO Direction Register */
760#define PORTD_DIR_SET 0xFFC0319C /* PORTD Port x GPIO Direction Set Register */
761#define PORTD_DIR_CLEAR 0xFFC031A0 /* PORTD Port x GPIO Direction Clear Register */
762#define PORTD_INEN 0xFFC031A4 /* PORTD Port x GPIO Input Enable Register */
763#define PORTD_INEN_SET 0xFFC031A8 /* PORTD Port x GPIO Input Enable Set Register */
764#define PORTD_INEN_CLEAR 0xFFC031AC /* PORTD Port x GPIO Input Enable Clear Register */
765#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control Register */
766#define PORTD_DATA_TGL 0xFFC031B4 /* PORTD Port x GPIO Input Enable Toggle Register */
767#define PORTD_POL 0xFFC031B8 /* PORTD Port x GPIO Programming Inversion Register */
768#define PORTD_POL_SET 0xFFC031BC /* PORTD Port x GPIO Programming Inversion Set Register */
769#define PORTD_POL_CLEAR 0xFFC031C0 /* PORTD Port x GPIO Programming Inversion Clear Register */
770#define PORTD_LOCK 0xFFC031C4 /* PORTD Port x GPIO Lock Register */
771#define PORTD_REVID 0xFFC031FC /* PORTD Port x GPIO Revision ID */
772
773/* =========================
774 PORTE
775 ========================= */
776#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable Register */
777#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set Register */
778#define PORTE_FER_CLEAR 0xFFC03208 /* PORTE Port x Function Enable Clear Register */
779#define PORTE_DATA 0xFFC0320C /* PORTE Port x GPIO Data Register */
780#define PORTE_DATA_SET 0xFFC03210 /* PORTE Port x GPIO Data Set Register */
781#define PORTE_DATA_CLEAR 0xFFC03214 /* PORTE Port x GPIO Data Clear Register */
782#define PORTE_DIR 0xFFC03218 /* PORTE Port x GPIO Direction Register */
783#define PORTE_DIR_SET 0xFFC0321C /* PORTE Port x GPIO Direction Set Register */
784#define PORTE_DIR_CLEAR 0xFFC03220 /* PORTE Port x GPIO Direction Clear Register */
785#define PORTE_INEN 0xFFC03224 /* PORTE Port x GPIO Input Enable Register */
786#define PORTE_INEN_SET 0xFFC03228 /* PORTE Port x GPIO Input Enable Set Register */
787#define PORTE_INEN_CLEAR 0xFFC0322C /* PORTE Port x GPIO Input Enable Clear Register */
788#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control Register */
789#define PORTE_DATA_TGL 0xFFC03234 /* PORTE Port x GPIO Input Enable Toggle Register */
790#define PORTE_POL 0xFFC03238 /* PORTE Port x GPIO Programming Inversion Register */
791#define PORTE_POL_SET 0xFFC0323C /* PORTE Port x GPIO Programming Inversion Set Register */
792#define PORTE_POL_CLEAR 0xFFC03240 /* PORTE Port x GPIO Programming Inversion Clear Register */
793#define PORTE_LOCK 0xFFC03244 /* PORTE Port x GPIO Lock Register */
794#define PORTE_REVID 0xFFC0327C /* PORTE Port x GPIO Revision ID */
795
796/* =========================
797 PORTF
798 ========================= */
799#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable Register */
800#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set Register */
801#define PORTF_FER_CLEAR 0xFFC03288 /* PORTF Port x Function Enable Clear Register */
802#define PORTF_DATA 0xFFC0328C /* PORTF Port x GPIO Data Register */
803#define PORTF_DATA_SET 0xFFC03290 /* PORTF Port x GPIO Data Set Register */
804#define PORTF_DATA_CLEAR 0xFFC03294 /* PORTF Port x GPIO Data Clear Register */
805#define PORTF_DIR 0xFFC03298 /* PORTF Port x GPIO Direction Register */
806#define PORTF_DIR_SET 0xFFC0329C /* PORTF Port x GPIO Direction Set Register */
807#define PORTF_DIR_CLEAR 0xFFC032A0 /* PORTF Port x GPIO Direction Clear Register */
808#define PORTF_INEN 0xFFC032A4 /* PORTF Port x GPIO Input Enable Register */
809#define PORTF_INEN_SET 0xFFC032A8 /* PORTF Port x GPIO Input Enable Set Register */
810#define PORTF_INEN_CLEAR 0xFFC032AC /* PORTF Port x GPIO Input Enable Clear Register */
811#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control Register */
812#define PORTF_DATA_TGL 0xFFC032B4 /* PORTF Port x GPIO Input Enable Toggle Register */
813#define PORTF_POL 0xFFC032B8 /* PORTF Port x GPIO Programming Inversion Register */
814#define PORTF_POL_SET 0xFFC032BC /* PORTF Port x GPIO Programming Inversion Set Register */
815#define PORTF_POL_CLEAR 0xFFC032C0 /* PORTF Port x GPIO Programming Inversion Clear Register */
816#define PORTF_LOCK 0xFFC032C4 /* PORTF Port x GPIO Lock Register */
817#define PORTF_REVID 0xFFC032FC /* PORTF Port x GPIO Revision ID */
818
819/* =========================
820 PORTG
821 ========================= */
822#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable Register */
823#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set Register */
824#define PORTG_FER_CLEAR 0xFFC03308 /* PORTG Port x Function Enable Clear Register */
825#define PORTG_DATA 0xFFC0330C /* PORTG Port x GPIO Data Register */
826#define PORTG_DATA_SET 0xFFC03310 /* PORTG Port x GPIO Data Set Register */
827#define PORTG_DATA_CLEAR 0xFFC03314 /* PORTG Port x GPIO Data Clear Register */
828#define PORTG_DIR 0xFFC03318 /* PORTG Port x GPIO Direction Register */
829#define PORTG_DIR_SET 0xFFC0331C /* PORTG Port x GPIO Direction Set Register */
830#define PORTG_DIR_CLEAR 0xFFC03320 /* PORTG Port x GPIO Direction Clear Register */
831#define PORTG_INEN 0xFFC03324 /* PORTG Port x GPIO Input Enable Register */
832#define PORTG_INEN_SET 0xFFC03328 /* PORTG Port x GPIO Input Enable Set Register */
833#define PORTG_INEN_CLEAR 0xFFC0332C /* PORTG Port x GPIO Input Enable Clear Register */
834#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control Register */
835#define PORTG_DATA_TGL 0xFFC03334 /* PORTG Port x GPIO Input Enable Toggle Register */
836#define PORTG_POL 0xFFC03338 /* PORTG Port x GPIO Programming Inversion Register */
837#define PORTG_POL_SET 0xFFC0333C /* PORTG Port x GPIO Programming Inversion Set Register */
838#define PORTG_POL_CLEAR 0xFFC03340 /* PORTG Port x GPIO Programming Inversion Clear Register */
839#define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */
840#define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */
841
842
843/* =========================
844 PINT Registers
845 ========================= */
846
847/* =========================
848 PINT0
849 ========================= */
850#define PINT0_MASK_SET 0xFFC04000 /* PINT0 Pint Mask Set Register */
851#define PINT0_MASK_CLEAR 0xFFC04004 /* PINT0 Pint Mask Clear Register */
852#define PINT0_REQUEST 0xFFC04008 /* PINT0 Pint Request Register */
853#define PINT0_ASSIGN 0xFFC0400C /* PINT0 Pint Assign Register */
854#define PINT0_EDGE_SET 0xFFC04010 /* PINT0 Pint Edge Set Register */
855#define PINT0_EDGE_CLEAR 0xFFC04014 /* PINT0 Pint Edge Clear Register */
856#define PINT0_INVERT_SET 0xFFC04018 /* PINT0 Pint Invert Set Register */
857#define PINT0_INVERT_CLEAR 0xFFC0401C /* PINT0 Pint Invert Clear Register */
858#define PINT0_PINSTATE 0xFFC04020 /* PINT0 Pint Pinstate Register */
859#define PINT0_LATCH 0xFFC04024 /* PINT0 Pint Latch Register */
860
861/* =========================
862 PINT1
863 ========================= */
864#define PINT1_MASK_SET 0xFFC04100 /* PINT1 Pint Mask Set Register */
865#define PINT1_MASK_CLEAR 0xFFC04104 /* PINT1 Pint Mask Clear Register */
866#define PINT1_REQUEST 0xFFC04108 /* PINT1 Pint Request Register */
867#define PINT1_ASSIGN 0xFFC0410C /* PINT1 Pint Assign Register */
868#define PINT1_EDGE_SET 0xFFC04110 /* PINT1 Pint Edge Set Register */
869#define PINT1_EDGE_CLEAR 0xFFC04114 /* PINT1 Pint Edge Clear Register */
870#define PINT1_INVERT_SET 0xFFC04118 /* PINT1 Pint Invert Set Register */
871#define PINT1_INVERT_CLEAR 0xFFC0411C /* PINT1 Pint Invert Clear Register */
872#define PINT1_PINSTATE 0xFFC04120 /* PINT1 Pint Pinstate Register */
873#define PINT1_LATCH 0xFFC04124 /* PINT1 Pint Latch Register */
874
875/* =========================
876 PINT2
877 ========================= */
878#define PINT2_MASK_SET 0xFFC04200 /* PINT2 Pint Mask Set Register */
879#define PINT2_MASK_CLEAR 0xFFC04204 /* PINT2 Pint Mask Clear Register */
880#define PINT2_REQUEST 0xFFC04208 /* PINT2 Pint Request Register */
881#define PINT2_ASSIGN 0xFFC0420C /* PINT2 Pint Assign Register */
882#define PINT2_EDGE_SET 0xFFC04210 /* PINT2 Pint Edge Set Register */
883#define PINT2_EDGE_CLEAR 0xFFC04214 /* PINT2 Pint Edge Clear Register */
884#define PINT2_INVERT_SET 0xFFC04218 /* PINT2 Pint Invert Set Register */
885#define PINT2_INVERT_CLEAR 0xFFC0421C /* PINT2 Pint Invert Clear Register */
886#define PINT2_PINSTATE 0xFFC04220 /* PINT2 Pint Pinstate Register */
887#define PINT2_LATCH 0xFFC04224 /* PINT2 Pint Latch Register */
888
889/* =========================
890 PINT3
891 ========================= */
892#define PINT3_MASK_SET 0xFFC04300 /* PINT3 Pint Mask Set Register */
893#define PINT3_MASK_CLEAR 0xFFC04304 /* PINT3 Pint Mask Clear Register */
894#define PINT3_REQUEST 0xFFC04308 /* PINT3 Pint Request Register */
895#define PINT3_ASSIGN 0xFFC0430C /* PINT3 Pint Assign Register */
896#define PINT3_EDGE_SET 0xFFC04310 /* PINT3 Pint Edge Set Register */
897#define PINT3_EDGE_CLEAR 0xFFC04314 /* PINT3 Pint Edge Clear Register */
898#define PINT3_INVERT_SET 0xFFC04318 /* PINT3 Pint Invert Set Register */
899#define PINT3_INVERT_CLEAR 0xFFC0431C /* PINT3 Pint Invert Clear Register */
900#define PINT3_PINSTATE 0xFFC04320 /* PINT3 Pint Pinstate Register */
901#define PINT3_LATCH 0xFFC04324 /* PINT3 Pint Latch Register */
902
903/* =========================
904 PINT4
905 ========================= */
906#define PINT4_MASK_SET 0xFFC04400 /* PINT4 Pint Mask Set Register */
907#define PINT4_MASK_CLEAR 0xFFC04404 /* PINT4 Pint Mask Clear Register */
908#define PINT4_REQUEST 0xFFC04408 /* PINT4 Pint Request Register */
909#define PINT4_ASSIGN 0xFFC0440C /* PINT4 Pint Assign Register */
910#define PINT4_EDGE_SET 0xFFC04410 /* PINT4 Pint Edge Set Register */
911#define PINT4_EDGE_CLEAR 0xFFC04414 /* PINT4 Pint Edge Clear Register */
912#define PINT4_INVERT_SET 0xFFC04418 /* PINT4 Pint Invert Set Register */
913#define PINT4_INVERT_CLEAR 0xFFC0441C /* PINT4 Pint Invert Clear Register */
914#define PINT4_PINSTATE 0xFFC04420 /* PINT4 Pint Pinstate Register */
915#define PINT4_LATCH 0xFFC04424 /* PINT4 Pint Latch Register */
916
917/* =========================
918 PINT5
919 ========================= */
920#define PINT5_MASK_SET 0xFFC04500 /* PINT5 Pint Mask Set Register */
921#define PINT5_MASK_CLEAR 0xFFC04504 /* PINT5 Pint Mask Clear Register */
922#define PINT5_REQUEST 0xFFC04508 /* PINT5 Pint Request Register */
923#define PINT5_ASSIGN 0xFFC0450C /* PINT5 Pint Assign Register */
924#define PINT5_EDGE_SET 0xFFC04510 /* PINT5 Pint Edge Set Register */
925#define PINT5_EDGE_CLEAR 0xFFC04514 /* PINT5 Pint Edge Clear Register */
926#define PINT5_INVERT_SET 0xFFC04518 /* PINT5 Pint Invert Set Register */
927#define PINT5_INVERT_CLEAR 0xFFC0451C /* PINT5 Pint Invert Clear Register */
928#define PINT5_PINSTATE 0xFFC04520 /* PINT5 Pint Pinstate Register */
929#define PINT5_LATCH 0xFFC04524 /* PINT5 Pint Latch Register */
930
931
932/* =========================
933 SMC Registers
934 ========================= */
935
936/* =========================
937 SMC0
938 ========================= */
939#define SMC_GCTL 0xFFC16004 /* SMC0 SMC Control Register */
940#define SMC_GSTAT 0xFFC16008 /* SMC0 SMC Status Register */
941#define SMC_B0CTL 0xFFC1600C /* SMC0 SMC Bank0 Control Register */
942#define SMC_B0TIM 0xFFC16010 /* SMC0 SMC Bank0 Timing Register */
943#define SMC_B0ETIM 0xFFC16014 /* SMC0 SMC Bank0 Extended Timing Register */
944#define SMC_B1CTL 0xFFC1601C /* SMC0 SMC BANK1 Control Register */
945#define SMC_B1TIM 0xFFC16020 /* SMC0 SMC BANK1 Timing Register */
946#define SMC_B1ETIM 0xFFC16024 /* SMC0 SMC BANK1 Extended Timing Register */
947#define SMC_B2CTL 0xFFC1602C /* SMC0 SMC BANK2 Control Register */
948#define SMC_B2TIM 0xFFC16030 /* SMC0 SMC BANK2 Timing Register */
949#define SMC_B2ETIM 0xFFC16034 /* SMC0 SMC BANK2 Extended Timing Register */
950#define SMC_B3CTL 0xFFC1603C /* SMC0 SMC BANK3 Control Register */
951#define SMC_B3TIM 0xFFC16040 /* SMC0 SMC BANK3 Timing Register */
952#define SMC_B3ETIM 0xFFC16044 /* SMC0 SMC BANK3 Extended Timing Register */
953
954
955/* =========================
956 WDOG Registers
957 ========================= */
958
959/* =========================
960 WDOG0
961 ========================= */
962#define WDOG0_CTL 0xFFC17000 /* WDOG0 Control Register */
963#define WDOG0_CNT 0xFFC17004 /* WDOG0 Count Register */
964#define WDOG0_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
965#define WDOG_CTL WDOG0_CTL
966#define WDOG_CNT WDOG0_CNT
967#define WDOG_STAT WDOG0_STAT
968
969/* =========================
970 WDOG1
971 ========================= */
972#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
973#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
974#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
975
976
977/* =========================
978 SDU Registers
979 ========================= */
980
981/* =========================
982 SDU0
983 ========================= */
984#define SDU0_IDCODE 0xFFC1F020 /* SDU0 ID Code Register */
985#define SDU0_CTL 0xFFC1F050 /* SDU0 Control Register */
986#define SDU0_STAT 0xFFC1F054 /* SDU0 Status Register */
987#define SDU0_MACCTL 0xFFC1F058 /* SDU0 Memory Access Control Register */
988#define SDU0_MACADDR 0xFFC1F05C /* SDU0 Memory Access Address Register */
989#define SDU0_MACDATA 0xFFC1F060 /* SDU0 Memory Access Data Register */
990#define SDU0_DMARD 0xFFC1F064 /* SDU0 DMA Read Data Register */
991#define SDU0_DMAWD 0xFFC1F068 /* SDU0 DMA Write Data Register */
992#define SDU0_MSG 0xFFC1F080 /* SDU0 Message Register */
993#define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */
994#define SDU0_MSG_CLR 0xFFC1F088 /* SDU0 Message Clear Register */
995#define SDU0_GHLT 0xFFC1F08C /* SDU0 Group Halt Register */
996
997
998/* =========================
999 EMAC Registers
1000 ========================= */
1001/* =========================
1002 EMAC0
1003 ========================= */
1004#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
1005#define EMAC0_MACFRMFILT 0xFFC20004 /* EMAC0 Filter Register for filtering Received Frames */
1006#define EMAC0_HASHTBL_HI 0xFFC20008 /* EMAC0 Contains the Upper 32 bits of the hash table */
1007#define EMAC0_HASHTBL_LO 0xFFC2000C /* EMAC0 Contains the lower 32 bits of the hash table */
1008#define EMAC0_GMII_ADDR 0xFFC20010 /* EMAC0 Management Address Register */
1009#define EMAC0_GMII_DATA 0xFFC20014 /* EMAC0 Management Data Register */
1010#define EMAC0_FLOWCTL 0xFFC20018 /* EMAC0 MAC FLow Control Register */
1011#define EMAC0_VLANTAG 0xFFC2001C /* EMAC0 VLAN Tag Register */
1012#define EMAC0_VER 0xFFC20020 /* EMAC0 EMAC Version Register */
1013#define EMAC0_DBG 0xFFC20024 /* EMAC0 EMAC Debug Register */
1014#define EMAC0_RMTWKUP 0xFFC20028 /* EMAC0 Remote wake up frame register */
1015#define EMAC0_PMT_CTLSTAT 0xFFC2002C /* EMAC0 PMT Control and Status Register */
1016#define EMAC0_ISTAT 0xFFC20038 /* EMAC0 EMAC Interrupt Status Register */
1017#define EMAC0_IMSK 0xFFC2003C /* EMAC0 EMAC Interrupt Mask Register */
1018#define EMAC0_ADDR0_HI 0xFFC20040 /* EMAC0 EMAC Address0 High Register */
1019#define EMAC0_ADDR0_LO 0xFFC20044 /* EMAC0 EMAC Address0 Low Register */
1020#define EMAC0_MMC_CTL 0xFFC20100 /* EMAC0 MMC Control Register */
1021#define EMAC0_MMC_RXINT 0xFFC20104 /* EMAC0 MMC RX Interrupt Register */
1022#define EMAC0_MMC_TXINT 0xFFC20108 /* EMAC0 MMC TX Interrupt Register */
1023#define EMAC0_MMC_RXIMSK 0xFFC2010C /* EMAC0 MMC RX Interrupt Mask Register */
1024#define EMAC0_MMC_TXIMSK 0xFFC20110 /* EMAC0 MMC TX Interrupt Mask Register */
1025#define EMAC0_TXOCTCNT_GB 0xFFC20114 /* EMAC0 Num bytes transmitted exclusive of preamble */
1026#define EMAC0_TXFRMCNT_GB 0xFFC20118 /* EMAC0 Num frames transmitted exclusive of retired */
1027#define EMAC0_TXBCASTFRM_G 0xFFC2011C /* EMAC0 Number of good broadcast frames transmitted. */
1028#define EMAC0_TXMCASTFRM_G 0xFFC20120 /* EMAC0 Number of good multicast frames transmitted. */
1029#define EMAC0_TX64_GB 0xFFC20124 /* EMAC0 Number of 64 byte length frames */
1030#define EMAC0_TX65TO127_GB 0xFFC20128 /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
1031#define EMAC0_TX128TO255_GB 0xFFC2012C /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
1032#define EMAC0_TX256TO511_GB 0xFFC20130 /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
1033#define EMAC0_TX512TO1023_GB 0xFFC20134 /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
1034#define EMAC0_TX1024TOMAX_GB 0xFFC20138 /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
1035#define EMAC0_TXUCASTFRM_GB 0xFFC2013C /* EMAC0 Number of good and bad unicast frames transmitted */
1036#define EMAC0_TXMCASTFRM_GB 0xFFC20140 /* EMAC0 Number of good and bad multicast frames transmitted */
1037#define EMAC0_TXBCASTFRM_GB 0xFFC20144 /* EMAC0 Number of good and bad broadcast frames transmitted */
1038#define EMAC0_TXUNDR_ERR 0xFFC20148 /* EMAC0 Number of frames aborted due to frame underflow error */
1039#define EMAC0_TXSNGCOL_G 0xFFC2014C /* EMAC0 Number of transmitted frames after single collision */
1040#define EMAC0_TXMULTCOL_G 0xFFC20150 /* EMAC0 Number of transmitted frames with more than one collision */
1041#define EMAC0_TXDEFERRED 0xFFC20154 /* EMAC0 Number of transmitted frames after deferral */
1042#define EMAC0_TXLATECOL 0xFFC20158 /* EMAC0 Number of frames aborted due to late collision error */
1043#define EMAC0_TXEXCESSCOL 0xFFC2015C /* EMAC0 Number of aborted frames due to excessive collisions */
1044#define EMAC0_TXCARR_ERR 0xFFC20160 /* EMAC0 Number of aborted frames due to carrier sense error */
1045#define EMAC0_TXOCTCNT_G 0xFFC20164 /* EMAC0 Number of bytes transmitted in good frames only */
1046#define EMAC0_TXFRMCNT_G 0xFFC20168 /* EMAC0 Number of good frames transmitted. */
1047#define EMAC0_TXEXCESSDEF 0xFFC2016C /* EMAC0 Number of frames aborted due to excessive deferral */
1048#define EMAC0_TXPAUSEFRM 0xFFC20170 /* EMAC0 Number of good PAUSE frames transmitted. */
1049#define EMAC0_TXVLANFRM_G 0xFFC20174 /* EMAC0 Number of VLAN frames transmitted */
1050#define EMAC0_RXFRMCNT_GB 0xFFC20180 /* EMAC0 Number of good and bad frames received. */
1051#define EMAC0_RXOCTCNT_GB 0xFFC20184 /* EMAC0 Number of bytes received in good and bad frames */
1052#define EMAC0_RXOCTCNT_G 0xFFC20188 /* EMAC0 Number of bytes received only in good frames */
1053#define EMAC0_RXBCASTFRM_G 0xFFC2018C /* EMAC0 Number of good broadcast frames received. */
1054#define EMAC0_RXMCASTFRM_G 0xFFC20190 /* EMAC0 Number of good multicast frames received */
1055#define EMAC0_RXCRC_ERR 0xFFC20194 /* EMAC0 Number of frames received with CRC error */
1056#define EMAC0_RXALIGN_ERR 0xFFC20198 /* EMAC0 Number of frames with alignment error */
1057#define EMAC0_RXRUNT_ERR 0xFFC2019C /* EMAC0 Number of frames received with runt error. */
1058#define EMAC0_RXJAB_ERR 0xFFC201A0 /* EMAC0 Number of frames received with length greater than 1518 */
1059#define EMAC0_RXUSIZE_G 0xFFC201A4 /* EMAC0 Number of frames received with length 64 */
1060#define EMAC0_RXOSIZE_G 0xFFC201A8 /* EMAC0 Number of frames received with length greater than maxium */
1061#define EMAC0_RX64_GB 0xFFC201AC /* EMAC0 Number of good and bad frames of lengh 64 bytes */
1062#define EMAC0_RX65TO127_GB 0xFFC201B0 /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
1063#define EMAC0_RX128TO255_GB 0xFFC201B4 /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
1064#define EMAC0_RX256TO511_GB 0xFFC201B8 /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
1065#define EMAC0_RX512TO1023_GB 0xFFC201BC /* EMAC0 Number of good and bad frames received between 512-1023 */
1066#define EMAC0_RX1024TOMAX_GB 0xFFC201C0 /* EMAC0 Number of frames received between 1024 and maxsize */
1067#define EMAC0_RXUCASTFRM_G 0xFFC201C4 /* EMAC0 Number of good unicast frames received. */
1068#define EMAC0_RXLEN_ERR 0xFFC201C8 /* EMAC0 Number of frames received with length error */
1069#define EMAC0_RXOORTYPE 0xFFC201CC /* EMAC0 Number of frames with length not equal to valid frame size */
1070#define EMAC0_RXPAUSEFRM 0xFFC201D0 /* EMAC0 Number of good and valid PAUSE frames received. */
1071#define EMAC0_RXFIFO_OVF 0xFFC201D4 /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
1072#define EMAC0_RXVLANFRM_GB 0xFFC201D8 /* EMAC0 Number of good and bad VLAN frames received. */
1073#define EMAC0_RXWDOG_ERR 0xFFC201DC /* EMAC0 Frames received with error due to watchdog timeout */
1074#define EMAC0_IPC_RXIMSK 0xFFC20200 /* EMAC0 MMC IPC RX Interrupt Mask Register */
1075#define EMAC0_IPC_RXINT 0xFFC20208 /* EMAC0 MMC IPC RX Interrupt Register */
1076#define EMAC0_RXIPV4_GD_FRM 0xFFC20210 /* EMAC0 Number of good IPv4 datagrams */
1077#define EMAC0_RXIPV4_HDR_ERR_FRM 0xFFC20214 /* EMAC0 Number of IPv4 datagrams with header errors */
1078#define EMAC0_RXIPV4_NOPAY_FRM 0xFFC20218 /* EMAC0 Number of IPv4 datagrams without checksum */
1079#define EMAC0_RXIPV4_FRAG_FRM 0xFFC2021C /* EMAC0 Number of good IPv4 datagrams with fragmentation */
1080#define EMAC0_RXIPV4_UDSBL_FRM 0xFFC20220 /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
1081#define EMAC0_RXIPV6_GD_FRM 0xFFC20224 /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
1082#define EMAC0_RXIPV6_HDR_ERR_FRM 0xFFC20228 /* EMAC0 Number of IPv6 datagrams with header errors */
1083#define EMAC0_RXIPV6_NOPAY_FRM 0xFFC2022C /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
1084#define EMAC0_RXUDP_GD_FRM 0xFFC20230 /* EMAC0 Number of good IP datagrames with good UDP payload */
1085#define EMAC0_RXUDP_ERR_FRM 0xFFC20234 /* EMAC0 Number of good IP datagrams with UDP checksum errors */
1086#define EMAC0_RXTCP_GD_FRM 0xFFC20238 /* EMAC0 Number of good IP datagrams with a good TCP payload */
1087#define EMAC0_RXTCP_ERR_FRM 0xFFC2023C /* EMAC0 Number of good IP datagrams with TCP checksum errors */
1088#define EMAC0_RXICMP_GD_FRM 0xFFC20240 /* EMAC0 Number of good IP datagrams with a good ICMP payload */
1089#define EMAC0_RXICMP_ERR_FRM 0xFFC20244 /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
1090#define EMAC0_RXIPV4_GD_OCT 0xFFC20250 /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
1091#define EMAC0_RXIPV4_HDR_ERR_OCT 0xFFC20254 /* EMAC0 Bytes received in IPv4 datagrams with header errors */
1092#define EMAC0_RXIPV4_NOPAY_OCT 0xFFC20258 /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
1093#define EMAC0_RXIPV4_FRAG_OCT 0xFFC2025C /* EMAC0 Bytes received in fragmented IPv4 datagrams */
1094#define EMAC0_RXIPV4_UDSBL_OCT 0xFFC20260 /* EMAC0 Bytes received in UDP segment with checksum disabled */
1095#define EMAC0_RXIPV6_GD_OCT 0xFFC20264 /* EMAC0 Bytes received in good IPv6 including tcp,udp or icmp load */
1096#define EMAC0_RXIPV6_HDR_ERR_OCT 0xFFC20268 /* EMAC0 Number of bytes received in IPv6 with header errors */
1097#define EMAC0_RXIPV6_NOPAY_OCT 0xFFC2026C /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
1098#define EMAC0_RXUDP_GD_OCT 0xFFC20270 /* EMAC0 Number of bytes received in good UDP segments */
1099#define EMAC0_RXUDP_ERR_OCT 0xFFC20274 /* EMAC0 Number of bytes received in UDP segment with checksum err */
1100#define EMAC0_RXTCP_GD_OCT 0xFFC20278 /* EMAC0 Number of bytes received in a good TCP segment */
1101#define EMAC0_RXTCP_ERR_OCT 0xFFC2027C /* EMAC0 Number of bytes received in TCP segment with checksum err */
1102#define EMAC0_RXICMP_GD_OCT 0xFFC20280 /* EMAC0 Number of bytes received in a good ICMP segment */
1103#define EMAC0_RXICMP_ERR_OCT 0xFFC20284 /* EMAC0 Bytes received in an ICMP segment with checksum errors */
1104#define EMAC0_TM_CTL 0xFFC20700 /* EMAC0 EMAC Time Stamp Control Register */
1105#define EMAC0_TM_SUBSEC 0xFFC20704 /* EMAC0 EMAC Time Stamp Sub Second Increment */
1106#define EMAC0_TM_SEC 0xFFC20708 /* EMAC0 EMAC Time Stamp Second Register */
1107#define EMAC0_TM_NSEC 0xFFC2070C /* EMAC0 EMAC Time Stamp Nano Second Register */
1108#define EMAC0_TM_SECUPDT 0xFFC20710 /* EMAC0 EMAC Time Stamp Seconds Update */
1109#define EMAC0_TM_NSECUPDT 0xFFC20714 /* EMAC0 EMAC Time Stamp Nano Seconds Update */
1110#define EMAC0_TM_ADDEND 0xFFC20718 /* EMAC0 EMAC Time Stamp Addend Register */
1111#define EMAC0_TM_TGTM 0xFFC2071C /* EMAC0 EMAC Time Stamp Target Time Sec. */
1112#define EMAC0_TM_NTGTM 0xFFC20720 /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
1113#define EMAC0_TM_HISEC 0xFFC20724 /* EMAC0 EMAC Time Stamp High Second Register */
1114#define EMAC0_TM_STMPSTAT 0xFFC20728 /* EMAC0 EMAC Time Stamp Status Register */
1115#define EMAC0_TM_PPSCTL 0xFFC2072C /* EMAC0 EMAC PPS Control Register */
1116#define EMAC0_TM_AUXSTMP_NSEC 0xFFC20730 /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
1117#define EMAC0_TM_AUXSTMP_SEC 0xFFC20734 /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
1118#define EMAC0_DMA_BUSMODE 0xFFC21000 /* EMAC0 Bus Operating Modes for EMAC DMA */
1119#define EMAC0_DMA_TXPOLL 0xFFC21004 /* EMAC0 TX DMA Poll demand register */
1120#define EMAC0_DMA_RXPOLL 0xFFC21008 /* EMAC0 RX DMA Poll demand register */
1121#define EMAC0_DMA_RXDSC_ADDR 0xFFC2100C /* EMAC0 RX Descriptor List Address */
1122#define EMAC0_DMA_TXDSC_ADDR 0xFFC21010 /* EMAC0 TX Descriptor List Address */
1123#define EMAC0_DMA_STAT 0xFFC21014 /* EMAC0 DMA Status Register */
1124#define EMAC0_DMA_OPMODE 0xFFC21018 /* EMAC0 DMA Operation Mode Register */
1125#define EMAC0_DMA_IEN 0xFFC2101C /* EMAC0 DMA Interrupt Enable Register */
1126#define EMAC0_DMA_MISS_FRM 0xFFC21020 /* EMAC0 DMA missed frame and buffer overflow counter */
1127#define EMAC0_DMA_RXIWDOG 0xFFC21024 /* EMAC0 DMA RX Interrupt Watch Dog timer */
1128#define EMAC0_DMA_BMMODE 0xFFC21028 /* EMAC0 AXI Bus Mode Register */
1129#define EMAC0_DMA_BMSTAT 0xFFC2102C /* EMAC0 AXI Status Register */
1130#define EMAC0_DMA_TXDSC_CUR 0xFFC21048 /* EMAC0 TX current descriptor register */
1131#define EMAC0_DMA_RXDSC_CUR 0xFFC2104C /* EMAC0 RX current descriptor register */
1132#define EMAC0_DMA_TXBUF_CUR 0xFFC21050 /* EMAC0 TX current buffer pointer register */
1133#define EMAC0_DMA_RXBUF_CUR 0xFFC21054 /* EMAC0 RX current buffer pointer register */
1134#define EMAC0_HWFEAT 0xFFC21058 /* EMAC0 Hardware Feature Register */
1135
1136/* =========================
1137 EMAC1
1138 ========================= */
1139#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
1140#define EMAC1_MACFRMFILT 0xFFC22004 /* EMAC1 Filter Register for filtering Received Frames */
1141#define EMAC1_HASHTBL_HI 0xFFC22008 /* EMAC1 Contains the Upper 32 bits of the hash table */
1142#define EMAC1_HASHTBL_LO 0xFFC2200C /* EMAC1 Contains the lower 32 bits of the hash table */
1143#define EMAC1_GMII_ADDR 0xFFC22010 /* EMAC1 Management Address Register */
1144#define EMAC1_GMII_DATA 0xFFC22014 /* EMAC1 Management Data Register */
1145#define EMAC1_FLOWCTL 0xFFC22018 /* EMAC1 MAC FLow Control Register */
1146#define EMAC1_VLANTAG 0xFFC2201C /* EMAC1 VLAN Tag Register */
1147#define EMAC1_VER 0xFFC22020 /* EMAC1 EMAC Version Register */
1148#define EMAC1_DBG 0xFFC22024 /* EMAC1 EMAC Debug Register */
1149#define EMAC1_RMTWKUP 0xFFC22028 /* EMAC1 Remote wake up frame register */
1150#define EMAC1_PMT_CTLSTAT 0xFFC2202C /* EMAC1 PMT Control and Status Register */
1151#define EMAC1_ISTAT 0xFFC22038 /* EMAC1 EMAC Interrupt Status Register */
1152#define EMAC1_IMSK 0xFFC2203C /* EMAC1 EMAC Interrupt Mask Register */
1153#define EMAC1_ADDR0_HI 0xFFC22040 /* EMAC1 EMAC Address0 High Register */
1154#define EMAC1_ADDR0_LO 0xFFC22044 /* EMAC1 EMAC Address0 Low Register */
1155#define EMAC1_MMC_CTL 0xFFC22100 /* EMAC1 MMC Control Register */
1156#define EMAC1_MMC_RXINT 0xFFC22104 /* EMAC1 MMC RX Interrupt Register */
1157#define EMAC1_MMC_TXINT 0xFFC22108 /* EMAC1 MMC TX Interrupt Register */
1158#define EMAC1_MMC_RXIMSK 0xFFC2210C /* EMAC1 MMC RX Interrupt Mask Register */
1159#define EMAC1_MMC_TXIMSK 0xFFC22110 /* EMAC1 MMC TX Interrupt Mask Register */
1160#define EMAC1_TXOCTCNT_GB 0xFFC22114 /* EMAC1 Num bytes transmitted exclusive of preamble */
1161#define EMAC1_TXFRMCNT_GB 0xFFC22118 /* EMAC1 Num frames transmitted exclusive of retired */
1162#define EMAC1_TXBCASTFRM_G 0xFFC2211C /* EMAC1 Number of good broadcast frames transmitted. */
1163#define EMAC1_TXMCASTFRM_G 0xFFC22120 /* EMAC1 Number of good multicast frames transmitted. */
1164#define EMAC1_TX64_GB 0xFFC22124 /* EMAC1 Number of 64 byte length frames */
1165#define EMAC1_TX65TO127_GB 0xFFC22128 /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
1166#define EMAC1_TX128TO255_GB 0xFFC2212C /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
1167#define EMAC1_TX256TO511_GB 0xFFC22130 /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
1168#define EMAC1_TX512TO1023_GB 0xFFC22134 /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
1169#define EMAC1_TX1024TOMAX_GB 0xFFC22138 /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
1170#define EMAC1_TXUCASTFRM_GB 0xFFC2213C /* EMAC1 Number of good and bad unicast frames transmitted */
1171#define EMAC1_TXMCASTFRM_GB 0xFFC22140 /* EMAC1 Number of good and bad multicast frames transmitted */
1172#define EMAC1_TXBCASTFRM_GB 0xFFC22144 /* EMAC1 Number of good and bad broadcast frames transmitted */
1173#define EMAC1_TXUNDR_ERR 0xFFC22148 /* EMAC1 Number of frames aborted due to frame underflow error */
1174#define EMAC1_TXSNGCOL_G 0xFFC2214C /* EMAC1 Number of transmitted frames after single collision */
1175#define EMAC1_TXMULTCOL_G 0xFFC22150 /* EMAC1 Number of transmitted frames with more than one collision */
1176#define EMAC1_TXDEFERRED 0xFFC22154 /* EMAC1 Number of transmitted frames after deferral */
1177#define EMAC1_TXLATECOL 0xFFC22158 /* EMAC1 Number of frames aborted due to late collision error */
1178#define EMAC1_TXEXCESSCOL 0xFFC2215C /* EMAC1 Number of aborted frames due to excessive collisions */
1179#define EMAC1_TXCARR_ERR 0xFFC22160 /* EMAC1 Number of aborted frames due to carrier sense error */
1180#define EMAC1_TXOCTCNT_G 0xFFC22164 /* EMAC1 Number of bytes transmitted in good frames only */
1181#define EMAC1_TXFRMCNT_G 0xFFC22168 /* EMAC1 Number of good frames transmitted. */
1182#define EMAC1_TXEXCESSDEF 0xFFC2216C /* EMAC1 Number of frames aborted due to excessive deferral */
1183#define EMAC1_TXPAUSEFRM 0xFFC22170 /* EMAC1 Number of good PAUSE frames transmitted. */
1184#define EMAC1_TXVLANFRM_G 0xFFC22174 /* EMAC1 Number of VLAN frames transmitted */
1185#define EMAC1_RXFRMCNT_GB 0xFFC22180 /* EMAC1 Number of good and bad frames received. */
1186#define EMAC1_RXOCTCNT_GB 0xFFC22184 /* EMAC1 Number of bytes received in good and bad frames */
1187#define EMAC1_RXOCTCNT_G 0xFFC22188 /* EMAC1 Number of bytes received only in good frames */
1188#define EMAC1_RXBCASTFRM_G 0xFFC2218C /* EMAC1 Number of good broadcast frames received. */
1189#define EMAC1_RXMCASTFRM_G 0xFFC22190 /* EMAC1 Number of good multicast frames received */
1190#define EMAC1_RXCRC_ERR 0xFFC22194 /* EMAC1 Number of frames received with CRC error */
1191#define EMAC1_RXALIGN_ERR 0xFFC22198 /* EMAC1 Number of frames with alignment error */
1192#define EMAC1_RXRUNT_ERR 0xFFC2219C /* EMAC1 Number of frames received with runt error. */
1193#define EMAC1_RXJAB_ERR 0xFFC221A0 /* EMAC1 Number of frames received with length greater than 1518 */
1194#define EMAC1_RXUSIZE_G 0xFFC221A4 /* EMAC1 Number of frames received with length 64 */
1195#define EMAC1_RXOSIZE_G 0xFFC221A8 /* EMAC1 Number of frames received with length greater than maxium */
1196#define EMAC1_RX64_GB 0xFFC221AC /* EMAC1 Number of good and bad frames of lengh 64 bytes */
1197#define EMAC1_RX65TO127_GB 0xFFC221B0 /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
1198#define EMAC1_RX128TO255_GB 0xFFC221B4 /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
1199#define EMAC1_RX256TO511_GB 0xFFC221B8 /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
1200#define EMAC1_RX512TO1023_GB 0xFFC221BC /* EMAC1 Number of good and bad frames received between 512-1023 */
1201#define EMAC1_RX1024TOMAX_GB 0xFFC221C0 /* EMAC1 Number of frames received between 1024 and maxsize */
1202#define EMAC1_RXUCASTFRM_G 0xFFC221C4 /* EMAC1 Number of good unicast frames received. */
1203#define EMAC1_RXLEN_ERR 0xFFC221C8 /* EMAC1 Number of frames received with length error */
1204#define EMAC1_RXOORTYPE 0xFFC221CC /* EMAC1 Number of frames with length not equal to valid frame size */
1205#define EMAC1_RXPAUSEFRM 0xFFC221D0 /* EMAC1 Number of good and valid PAUSE frames received. */
1206#define EMAC1_RXFIFO_OVF 0xFFC221D4 /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
1207#define EMAC1_RXVLANFRM_GB 0xFFC221D8 /* EMAC1 Number of good and bad VLAN frames received. */
1208#define EMAC1_RXWDOG_ERR 0xFFC221DC /* EMAC1 Frames received with error due to watchdog timeout */
1209#define EMAC1_IPC_RXIMSK 0xFFC22200 /* EMAC1 MMC IPC RX Interrupt Mask Register */
1210#define EMAC1_IPC_RXINT 0xFFC22208 /* EMAC1 MMC IPC RX Interrupt Register */
1211#define EMAC1_RXIPV4_GD_FRM 0xFFC22210 /* EMAC1 Number of good IPv4 datagrams */
1212#define EMAC1_RXIPV4_HDR_ERR_FRM 0xFFC22214 /* EMAC1 Number of IPv4 datagrams with header errors */
1213#define EMAC1_RXIPV4_NOPAY_FRM 0xFFC22218 /* EMAC1 Number of IPv4 datagrams without checksum */
1214#define EMAC1_RXIPV4_FRAG_FRM 0xFFC2221C /* EMAC1 Number of good IPv4 datagrams with fragmentation */
1215#define EMAC1_RXIPV4_UDSBL_FRM 0xFFC22220 /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
1216#define EMAC1_RXIPV6_GD_FRM 0xFFC22224 /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
1217#define EMAC1_RXIPV6_HDR_ERR_FRM 0xFFC22228 /* EMAC1 Number of IPv6 datagrams with header errors */
1218#define EMAC1_RXIPV6_NOPAY_FRM 0xFFC2222C /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
1219#define EMAC1_RXUDP_GD_FRM 0xFFC22230 /* EMAC1 Number of good IP datagrames with good UDP payload */
1220#define EMAC1_RXUDP_ERR_FRM 0xFFC22234 /* EMAC1 Number of good IP datagrams with UDP checksum errors */
1221#define EMAC1_RXTCP_GD_FRM 0xFFC22238 /* EMAC1 Number of good IP datagrams with a good TCP payload */
1222#define EMAC1_RXTCP_ERR_FRM 0xFFC2223C /* EMAC1 Number of good IP datagrams with TCP checksum errors */
1223#define EMAC1_RXICMP_GD_FRM 0xFFC22240 /* EMAC1 Number of good IP datagrams with a good ICMP payload */
1224#define EMAC1_RXICMP_ERR_FRM 0xFFC22244 /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
1225#define EMAC1_RXIPV4_GD_OCT 0xFFC22250 /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
1226#define EMAC1_RXIPV4_HDR_ERR_OCT 0xFFC22254 /* EMAC1 Bytes received in IPv4 datagrams with header errors */
1227#define EMAC1_RXIPV4_NOPAY_OCT 0xFFC22258 /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
1228#define EMAC1_RXIPV4_FRAG_OCT 0xFFC2225C /* EMAC1 Bytes received in fragmented IPv4 datagrams */
1229#define EMAC1_RXIPV4_UDSBL_OCT 0xFFC22260 /* EMAC1 Bytes received in UDP segment with checksum disabled */
1230#define EMAC1_RXIPV6_GD_OCT 0xFFC22264 /* EMAC1 Bytes received in good IPv6 including tcp,udp or icmp load */
1231#define EMAC1_RXIPV6_HDR_ERR_OCT 0xFFC22268 /* EMAC1 Number of bytes received in IPv6 with header errors */
1232#define EMAC1_RXIPV6_NOPAY_OCT 0xFFC2226C /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
1233#define EMAC1_RXUDP_GD_OCT 0xFFC22270 /* EMAC1 Number of bytes received in good UDP segments */
1234#define EMAC1_RXUDP_ERR_OCT 0xFFC22274 /* EMAC1 Number of bytes received in UDP segment with checksum err */
1235#define EMAC1_RXTCP_GD_OCT 0xFFC22278 /* EMAC1 Number of bytes received in a good TCP segment */
1236#define EMAC1_RXTCP_ERR_OCT 0xFFC2227C /* EMAC1 Number of bytes received in TCP segment with checksum err */
1237#define EMAC1_RXICMP_GD_OCT 0xFFC22280 /* EMAC1 Number of bytes received in a good ICMP segment */
1238#define EMAC1_RXICMP_ERR_OCT 0xFFC22284 /* EMAC1 Bytes received in an ICMP segment with checksum errors */
1239#define EMAC1_TM_CTL 0xFFC22700 /* EMAC1 EMAC Time Stamp Control Register */
1240#define EMAC1_TM_SUBSEC 0xFFC22704 /* EMAC1 EMAC Time Stamp Sub Second Increment */
1241#define EMAC1_TM_SEC 0xFFC22708 /* EMAC1 EMAC Time Stamp Second Register */
1242#define EMAC1_TM_NSEC 0xFFC2270C /* EMAC1 EMAC Time Stamp Nano Second Register */
1243#define EMAC1_TM_SECUPDT 0xFFC22710 /* EMAC1 EMAC Time Stamp Seconds Update */
1244#define EMAC1_TM_NSECUPDT 0xFFC22714 /* EMAC1 EMAC Time Stamp Nano Seconds Update */
1245#define EMAC1_TM_ADDEND 0xFFC22718 /* EMAC1 EMAC Time Stamp Addend Register */
1246#define EMAC1_TM_TGTM 0xFFC2271C /* EMAC1 EMAC Time Stamp Target Time Sec. */
1247#define EMAC1_TM_NTGTM 0xFFC22720 /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
1248#define EMAC1_TM_HISEC 0xFFC22724 /* EMAC1 EMAC Time Stamp High Second Register */
1249#define EMAC1_TM_STMPSTAT 0xFFC22728 /* EMAC1 EMAC Time Stamp Status Register */
1250#define EMAC1_TM_PPSCTL 0xFFC2272C /* EMAC1 EMAC PPS Control Register */
1251#define EMAC1_TM_AUXSTMP_NSEC 0xFFC22730 /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
1252#define EMAC1_TM_AUXSTMP_SEC 0xFFC22734 /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
1253#define EMAC1_DMA_BUSMODE 0xFFC23000 /* EMAC1 Bus Operating Modes for EMAC DMA */
1254#define EMAC1_DMA_TXPOLL 0xFFC23004 /* EMAC1 TX DMA Poll demand register */
1255#define EMAC1_DMA_RXPOLL 0xFFC23008 /* EMAC1 RX DMA Poll demand register */
1256#define EMAC1_DMA_RXDSC_ADDR 0xFFC2300C /* EMAC1 RX Descriptor List Address */
1257#define EMAC1_DMA_TXDSC_ADDR 0xFFC23010 /* EMAC1 TX Descriptor List Address */
1258#define EMAC1_DMA_STAT 0xFFC23014 /* EMAC1 DMA Status Register */
1259#define EMAC1_DMA_OPMODE 0xFFC23018 /* EMAC1 DMA Operation Mode Register */
1260#define EMAC1_DMA_IEN 0xFFC2301C /* EMAC1 DMA Interrupt Enable Register */
1261#define EMAC1_DMA_MISS_FRM 0xFFC23020 /* EMAC1 DMA missed frame and buffer overflow counter */
1262#define EMAC1_DMA_RXIWDOG 0xFFC23024 /* EMAC1 DMA RX Interrupt Watch Dog timer */
1263#define EMAC1_DMA_BMMODE 0xFFC23028 /* EMAC1 AXI Bus Mode Register */
1264#define EMAC1_DMA_BMSTAT 0xFFC2302C /* EMAC1 AXI Status Register */
1265#define EMAC1_DMA_TXDSC_CUR 0xFFC23048 /* EMAC1 TX current descriptor register */
1266#define EMAC1_DMA_RXDSC_CUR 0xFFC2304C /* EMAC1 RX current descriptor register */
1267#define EMAC1_DMA_TXBUF_CUR 0xFFC23050 /* EMAC1 TX current buffer pointer register */
1268#define EMAC1_DMA_RXBUF_CUR 0xFFC23054 /* EMAC1 RX current buffer pointer register */
1269#define EMAC1_HWFEAT 0xFFC23058 /* EMAC1 Hardware Feature Register */
1270
1271
1272/* =========================
1273 SPI Registers
1274 ========================= */
1275
1276/* =========================
1277 SPI0
1278 ========================= */
1279#define SPI0_REGBASE 0xFFC40400
1280#define SPI0_CTL 0xFFC40404 /* SPI0 Control Register */
1281#define SPI0_RXCTL 0xFFC40408 /* SPI0 RX Control Register */
1282#define SPI0_TXCTL 0xFFC4040C /* SPI0 TX Control Register */
1283#define SPI0_CLK 0xFFC40410 /* SPI0 Clock Rate Register */
1284#define SPI0_DLY 0xFFC40414 /* SPI0 Delay Register */
1285#define SPI0_SLVSEL 0xFFC40418 /* SPI0 Slave Select Register */
1286#define SPI0_RWC 0xFFC4041C /* SPI0 Received Word-Count Register */
1287#define SPI0_RWCR 0xFFC40420 /* SPI0 Received Word-Count Reload Register */
1288#define SPI0_TWC 0xFFC40424 /* SPI0 Transmitted Word-Count Register */
1289#define SPI0_TWCR 0xFFC40428 /* SPI0 Transmitted Word-Count Reload Register */
1290#define SPI0_IMSK 0xFFC40430 /* SPI0 Interrupt Mask Register */
1291#define SPI0_IMSK_CLR 0xFFC40434 /* SPI0 Interrupt Mask Clear Register */
1292#define SPI0_IMSK_SET 0xFFC40438 /* SPI0 Interrupt Mask Set Register */
1293#define SPI0_STAT 0xFFC40440 /* SPI0 Status Register */
1294#define SPI0_ILAT 0xFFC40444 /* SPI0 Masked Interrupt Condition Register */
1295#define SPI0_ILAT_CLR 0xFFC40448 /* SPI0 Masked Interrupt Clear Register */
1296#define SPI0_RFIFO 0xFFC40450 /* SPI0 Receive FIFO Data Register */
1297#define SPI0_TFIFO 0xFFC40458 /* SPI0 Transmit FIFO Data Register */
1298
1299/* =========================
1300 SPI1
1301 ========================= */
1302#define SPI1_REGBASE 0xFFC40500
1303#define SPI1_CTL 0xFFC40504 /* SPI1 Control Register */
1304#define SPI1_RXCTL 0xFFC40508 /* SPI1 RX Control Register */
1305#define SPI1_TXCTL 0xFFC4050C /* SPI1 TX Control Register */
1306#define SPI1_CLK 0xFFC40510 /* SPI1 Clock Rate Register */
1307#define SPI1_DLY 0xFFC40514 /* SPI1 Delay Register */
1308#define SPI1_SLVSEL 0xFFC40518 /* SPI1 Slave Select Register */
1309#define SPI1_RWC 0xFFC4051C /* SPI1 Received Word-Count Register */
1310#define SPI1_RWCR 0xFFC40520 /* SPI1 Received Word-Count Reload Register */
1311#define SPI1_TWC 0xFFC40524 /* SPI1 Transmitted Word-Count Register */
1312#define SPI1_TWCR 0xFFC40528 /* SPI1 Transmitted Word-Count Reload Register */
1313#define SPI1_IMSK 0xFFC40530 /* SPI1 Interrupt Mask Register */
1314#define SPI1_IMSK_CLR 0xFFC40534 /* SPI1 Interrupt Mask Clear Register */
1315#define SPI1_IMSK_SET 0xFFC40538 /* SPI1 Interrupt Mask Set Register */
1316#define SPI1_STAT 0xFFC40540 /* SPI1 Status Register */
1317#define SPI1_ILAT 0xFFC40544 /* SPI1 Masked Interrupt Condition Register */
1318#define SPI1_ILAT_CLR 0xFFC40548 /* SPI1 Masked Interrupt Clear Register */
1319#define SPI1_RFIFO 0xFFC40550 /* SPI1 Receive FIFO Data Register */
1320#define SPI1_TFIFO 0xFFC40558 /* SPI1 Transmit FIFO Data Register */
1321
1322/* =========================
1323 SPORT Registers
1324 ========================= */
1325
1326/* =========================
1327 SPORT0
1328 ========================= */
1329#define SPORT0_CTL_A 0xFFC40000 /* SPORT0 'A' Control Register */
1330#define SPORT0_DIV_A 0xFFC40004 /* SPORT0 'A' Clock and FS Divide Register */
1331#define SPORT0_MCTL_A 0xFFC40008 /* SPORT0 'A' Multichannel Control Register */
1332#define SPORT0_CS0_A 0xFFC4000C /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
1333#define SPORT0_CS1_A 0xFFC40010 /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
1334#define SPORT0_CS2_A 0xFFC40014 /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
1335#define SPORT0_CS3_A 0xFFC40018 /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
1336#define SPORT0_CNT_A 0xFFC4001C /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
1337#define SPORT0_ERR_A 0xFFC40020 /* SPORT0 'A' Error Register */
1338#define SPORT0_MSTAT_A 0xFFC40024 /* SPORT0 'A' Multichannel Mode Status Register */
1339#define SPORT0_CTL2_A 0xFFC40028 /* SPORT0 'A' Control Register 2 */
1340#define SPORT0_TXPRI_A 0xFFC40040 /* SPORT0 'A' Primary Channel Transmit Buffer Register */
1341#define SPORT0_RXPRI_A 0xFFC40044 /* SPORT0 'A' Primary Channel Receive Buffer Register */
1342#define SPORT0_TXSEC_A 0xFFC40048 /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
1343#define SPORT0_RXSEC_A 0xFFC4004C /* SPORT0 'A' Secondary Channel Receive Buffer Register */
1344#define SPORT0_CTL_B 0xFFC40080 /* SPORT0 'B' Control Register */
1345#define SPORT0_DIV_B 0xFFC40084 /* SPORT0 'B' Clock and FS Divide Register */
1346#define SPORT0_MCTL_B 0xFFC40088 /* SPORT0 'B' Multichannel Control Register */
1347#define SPORT0_CS0_B 0xFFC4008C /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
1348#define SPORT0_CS1_B 0xFFC40090 /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
1349#define SPORT0_CS2_B 0xFFC40094 /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
1350#define SPORT0_CS3_B 0xFFC40098 /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
1351#define SPORT0_CNT_B 0xFFC4009C /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
1352#define SPORT0_ERR_B 0xFFC400A0 /* SPORT0 'B' Error Register */
1353#define SPORT0_MSTAT_B 0xFFC400A4 /* SPORT0 'B' Multichannel Mode Status Register */
1354#define SPORT0_CTL2_B 0xFFC400A8 /* SPORT0 'B' Control Register 2 */
1355#define SPORT0_TXPRI_B 0xFFC400C0 /* SPORT0 'B' Primary Channel Transmit Buffer Register */
1356#define SPORT0_RXPRI_B 0xFFC400C4 /* SPORT0 'B' Primary Channel Receive Buffer Register */
1357#define SPORT0_TXSEC_B 0xFFC400C8 /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
1358#define SPORT0_RXSEC_B 0xFFC400CC /* SPORT0 'B' Secondary Channel Receive Buffer Register */
1359
1360/* =========================
1361 SPORT1
1362 ========================= */
1363#define SPORT1_CTL_A 0xFFC40100 /* SPORT1 'A' Control Register */
1364#define SPORT1_DIV_A 0xFFC40104 /* SPORT1 'A' Clock and FS Divide Register */
1365#define SPORT1_MCTL_A 0xFFC40108 /* SPORT1 'A' Multichannel Control Register */
1366#define SPORT1_CS0_A 0xFFC4010C /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
1367#define SPORT1_CS1_A 0xFFC40110 /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
1368#define SPORT1_CS2_A 0xFFC40114 /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
1369#define SPORT1_CS3_A 0xFFC40118 /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
1370#define SPORT1_CNT_A 0xFFC4011C /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
1371#define SPORT1_ERR_A 0xFFC40120 /* SPORT1 'A' Error Register */
1372#define SPORT1_MSTAT_A 0xFFC40124 /* SPORT1 'A' Multichannel Mode Status Register */
1373#define SPORT1_CTL2_A 0xFFC40128 /* SPORT1 'A' Control Register 2 */
1374#define SPORT1_TXPRI_A 0xFFC40140 /* SPORT1 'A' Primary Channel Transmit Buffer Register */
1375#define SPORT1_RXPRI_A 0xFFC40144 /* SPORT1 'A' Primary Channel Receive Buffer Register */
1376#define SPORT1_TXSEC_A 0xFFC40148 /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
1377#define SPORT1_RXSEC_A 0xFFC4014C /* SPORT1 'A' Secondary Channel Receive Buffer Register */
1378#define SPORT1_CTL_B 0xFFC40180 /* SPORT1 'B' Control Register */
1379#define SPORT1_DIV_B 0xFFC40184 /* SPORT1 'B' Clock and FS Divide Register */
1380#define SPORT1_MCTL_B 0xFFC40188 /* SPORT1 'B' Multichannel Control Register */
1381#define SPORT1_CS0_B 0xFFC4018C /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
1382#define SPORT1_CS1_B 0xFFC40190 /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
1383#define SPORT1_CS2_B 0xFFC40194 /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
1384#define SPORT1_CS3_B 0xFFC40198 /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
1385#define SPORT1_CNT_B 0xFFC4019C /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
1386#define SPORT1_ERR_B 0xFFC401A0 /* SPORT1 'B' Error Register */
1387#define SPORT1_MSTAT_B 0xFFC401A4 /* SPORT1 'B' Multichannel Mode Status Register */
1388#define SPORT1_CTL2_B 0xFFC401A8 /* SPORT1 'B' Control Register 2 */
1389#define SPORT1_TXPRI_B 0xFFC401C0 /* SPORT1 'B' Primary Channel Transmit Buffer Register */
1390#define SPORT1_RXPRI_B 0xFFC401C4 /* SPORT1 'B' Primary Channel Receive Buffer Register */
1391#define SPORT1_TXSEC_B 0xFFC401C8 /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
1392#define SPORT1_RXSEC_B 0xFFC401CC /* SPORT1 'B' Secondary Channel Receive Buffer Register */
1393
1394/* =========================
1395 SPORT2
1396 ========================= */
1397#define SPORT2_CTL_A 0xFFC40200 /* SPORT2 'A' Control Register */
1398#define SPORT2_DIV_A 0xFFC40204 /* SPORT2 'A' Clock and FS Divide Register */
1399#define SPORT2_MCTL_A 0xFFC40208 /* SPORT2 'A' Multichannel Control Register */
1400#define SPORT2_CS0_A 0xFFC4020C /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
1401#define SPORT2_CS1_A 0xFFC40210 /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
1402#define SPORT2_CS2_A 0xFFC40214 /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
1403#define SPORT2_CS3_A 0xFFC40218 /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
1404#define SPORT2_CNT_A 0xFFC4021C /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
1405#define SPORT2_ERR_A 0xFFC40220 /* SPORT2 'A' Error Register */
1406#define SPORT2_MSTAT_A 0xFFC40224 /* SPORT2 'A' Multichannel Mode Status Register */
1407#define SPORT2_CTL2_A 0xFFC40228 /* SPORT2 'A' Control Register 2 */
1408#define SPORT2_TXPRI_A 0xFFC40240 /* SPORT2 'A' Primary Channel Transmit Buffer Register */
1409#define SPORT2_RXPRI_A 0xFFC40244 /* SPORT2 'A' Primary Channel Receive Buffer Register */
1410#define SPORT2_TXSEC_A 0xFFC40248 /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
1411#define SPORT2_RXSEC_A 0xFFC4024C /* SPORT2 'A' Secondary Channel Receive Buffer Register */
1412#define SPORT2_CTL_B 0xFFC40280 /* SPORT2 'B' Control Register */
1413#define SPORT2_DIV_B 0xFFC40284 /* SPORT2 'B' Clock and FS Divide Register */
1414#define SPORT2_MCTL_B 0xFFC40288 /* SPORT2 'B' Multichannel Control Register */
1415#define SPORT2_CS0_B 0xFFC4028C /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
1416#define SPORT2_CS1_B 0xFFC40290 /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
1417#define SPORT2_CS2_B 0xFFC40294 /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
1418#define SPORT2_CS3_B 0xFFC40298 /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
1419#define SPORT2_CNT_B 0xFFC4029C /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
1420#define SPORT2_ERR_B 0xFFC402A0 /* SPORT2 'B' Error Register */
1421#define SPORT2_MSTAT_B 0xFFC402A4 /* SPORT2 'B' Multichannel Mode Status Register */
1422#define SPORT2_CTL2_B 0xFFC402A8 /* SPORT2 'B' Control Register 2 */
1423#define SPORT2_TXPRI_B 0xFFC402C0 /* SPORT2 'B' Primary Channel Transmit Buffer Register */
1424#define SPORT2_RXPRI_B 0xFFC402C4 /* SPORT2 'B' Primary Channel Receive Buffer Register */
1425#define SPORT2_TXSEC_B 0xFFC402C8 /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
1426#define SPORT2_RXSEC_B 0xFFC402CC /* SPORT2 'B' Secondary Channel Receive Buffer Register */
1427
1428/* =========================
1429 EPPI Registers
1430 ========================= */
1431
1432/* =========================
1433 EPPI0
1434 ========================= */
1435#define EPPI0_STAT 0xFFC18000 /* EPPI0 Status Register */
1436#define EPPI0_HCNT 0xFFC18004 /* EPPI0 Horizontal Transfer Count Register */
1437#define EPPI0_HDLY 0xFFC18008 /* EPPI0 Horizontal Delay Count Register */
1438#define EPPI0_VCNT 0xFFC1800C /* EPPI0 Vertical Transfer Count Register */
1439#define EPPI0_VDLY 0xFFC18010 /* EPPI0 Vertical Delay Count Register */
1440#define EPPI0_FRAME 0xFFC18014 /* EPPI0 Lines Per Frame Register */
1441#define EPPI0_LINE 0xFFC18018 /* EPPI0 Samples Per Line Register */
1442#define EPPI0_CLKDIV 0xFFC1801C /* EPPI0 Clock Divide Register */
1443#define EPPI0_CTL 0xFFC18020 /* EPPI0 Control Register */
1444#define EPPI0_FS1_WLHB 0xFFC18024 /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
1445#define EPPI0_FS1_PASPL 0xFFC18028 /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
1446#define EPPI0_FS2_WLVB 0xFFC1802C /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
1447#define EPPI0_FS2_PALPF 0xFFC18030 /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
1448#define EPPI0_IMSK 0xFFC18034 /* EPPI0 Interrupt Mask Register */
1449#define EPPI0_ODDCLIP 0xFFC1803C /* EPPI0 Clipping Register for ODD (Chroma) Data */
1450#define EPPI0_EVENCLIP 0xFFC18040 /* EPPI0 Clipping Register for EVEN (Luma) Data */
1451#define EPPI0_FS1_DLY 0xFFC18044 /* EPPI0 Frame Sync 1 Delay Value */
1452#define EPPI0_FS2_DLY 0xFFC18048 /* EPPI0 Frame Sync 2 Delay Value */
1453#define EPPI0_CTL2 0xFFC1804C /* EPPI0 Control Register 2 */
1454
1455/* =========================
1456 EPPI1
1457 ========================= */
1458#define EPPI1_STAT 0xFFC18400 /* EPPI1 Status Register */
1459#define EPPI1_HCNT 0xFFC18404 /* EPPI1 Horizontal Transfer Count Register */
1460#define EPPI1_HDLY 0xFFC18408 /* EPPI1 Horizontal Delay Count Register */
1461#define EPPI1_VCNT 0xFFC1840C /* EPPI1 Vertical Transfer Count Register */
1462#define EPPI1_VDLY 0xFFC18410 /* EPPI1 Vertical Delay Count Register */
1463#define EPPI1_FRAME 0xFFC18414 /* EPPI1 Lines Per Frame Register */
1464#define EPPI1_LINE 0xFFC18418 /* EPPI1 Samples Per Line Register */
1465#define EPPI1_CLKDIV 0xFFC1841C /* EPPI1 Clock Divide Register */
1466#define EPPI1_CTL 0xFFC18420 /* EPPI1 Control Register */
1467#define EPPI1_FS1_WLHB 0xFFC18424 /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
1468#define EPPI1_FS1_PASPL 0xFFC18428 /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
1469#define EPPI1_FS2_WLVB 0xFFC1842C /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
1470#define EPPI1_FS2_PALPF 0xFFC18430 /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
1471#define EPPI1_IMSK 0xFFC18434 /* EPPI1 Interrupt Mask Register */
1472#define EPPI1_ODDCLIP 0xFFC1843C /* EPPI1 Clipping Register for ODD (Chroma) Data */
1473#define EPPI1_EVENCLIP 0xFFC18440 /* EPPI1 Clipping Register for EVEN (Luma) Data */
1474#define EPPI1_FS1_DLY 0xFFC18444 /* EPPI1 Frame Sync 1 Delay Value */
1475#define EPPI1_FS2_DLY 0xFFC18448 /* EPPI1 Frame Sync 2 Delay Value */
1476#define EPPI1_CTL2 0xFFC1844C /* EPPI1 Control Register 2 */
1477
1478/* =========================
1479 EPPI2
1480 ========================= */
1481#define EPPI2_STAT 0xFFC18800 /* EPPI2 Status Register */
1482#define EPPI2_HCNT 0xFFC18804 /* EPPI2 Horizontal Transfer Count Register */
1483#define EPPI2_HDLY 0xFFC18808 /* EPPI2 Horizontal Delay Count Register */
1484#define EPPI2_VCNT 0xFFC1880C /* EPPI2 Vertical Transfer Count Register */
1485#define EPPI2_VDLY 0xFFC18810 /* EPPI2 Vertical Delay Count Register */
1486#define EPPI2_FRAME 0xFFC18814 /* EPPI2 Lines Per Frame Register */
1487#define EPPI2_LINE 0xFFC18818 /* EPPI2 Samples Per Line Register */
1488#define EPPI2_CLKDIV 0xFFC1881C /* EPPI2 Clock Divide Register */
1489#define EPPI2_CTL 0xFFC18820 /* EPPI2 Control Register */
1490#define EPPI2_FS1_WLHB 0xFFC18824 /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
1491#define EPPI2_FS1_PASPL 0xFFC18828 /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
1492#define EPPI2_FS2_WLVB 0xFFC1882C /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
1493#define EPPI2_FS2_PALPF 0xFFC18830 /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
1494#define EPPI2_IMSK 0xFFC18834 /* EPPI2 Interrupt Mask Register */
1495#define EPPI2_ODDCLIP 0xFFC1883C /* EPPI2 Clipping Register for ODD (Chroma) Data */
1496#define EPPI2_EVENCLIP 0xFFC18840 /* EPPI2 Clipping Register for EVEN (Luma) Data */
1497#define EPPI2_FS1_DLY 0xFFC18844 /* EPPI2 Frame Sync 1 Delay Value */
1498#define EPPI2_FS2_DLY 0xFFC18848 /* EPPI2 Frame Sync 2 Delay Value */
1499#define EPPI2_CTL2 0xFFC1884C /* EPPI2 Control Register 2 */
1500
1501
1502
1503/* =========================
1504 DDE Registers
1505 ========================= */
1506
1507/* =========================
1508 DMA0
1509 ========================= */
1510#define DMA0_NEXT_DESC_PTR 0xFFC41000 /* DMA0 Pointer to Next Initial Descriptor */
1511#define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */
1512#define DMA0_CONFIG 0xFFC41008 /* DMA0 Configuration Register */
1513#define DMA0_X_COUNT 0xFFC4100C /* DMA0 Inner Loop Count Start Value */
1514#define DMA0_X_MODIFY 0xFFC41010 /* DMA0 Inner Loop Address Increment */
1515#define DMA0_Y_COUNT 0xFFC41014 /* DMA0 Outer Loop Count Start Value (2D only) */
1516#define DMA0_Y_MODIFY 0xFFC41018 /* DMA0 Outer Loop Address Increment (2D only) */
1517#define DMA0_CURR_DESC_PTR 0xFFC41024 /* DMA0 Current Descriptor Pointer */
1518#define DMA0_PREV_DESC_PTR 0xFFC41028 /* DMA0 Previous Initial Descriptor Pointer */
1519#define DMA0_CURR_ADDR 0xFFC4102C /* DMA0 Current Address */
1520#define DMA0_IRQ_STATUS 0xFFC41030 /* DMA0 Status Register */
1521#define DMA0_CURR_X_COUNT 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
1522#define DMA0_CURR_Y_COUNT 0xFFC41038 /* DMA0 Current Row Count (2D only) */
1523#define DMA0_BWL_COUNT 0xFFC41040 /* DMA0 Bandwidth Limit Count */
1524#define DMA0_CURR_BWL_COUNT 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */
1525#define DMA0_BWM_COUNT 0xFFC41048 /* DMA0 Bandwidth Monitor Count */
1526#define DMA0_CURR_BWM_COUNT 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */
1527
1528/* =========================
1529 DMA1
1530 ========================= */
1531#define DMA1_NEXT_DESC_PTR 0xFFC41080 /* DMA1 Pointer to Next Initial Descriptor */
1532#define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */
1533#define DMA1_CONFIG 0xFFC41088 /* DMA1 Configuration Register */
1534#define DMA1_X_COUNT 0xFFC4108C /* DMA1 Inner Loop Count Start Value */
1535#define DMA1_X_MODIFY 0xFFC41090 /* DMA1 Inner Loop Address Increment */
1536#define DMA1_Y_COUNT 0xFFC41094 /* DMA1 Outer Loop Count Start Value (2D only) */
1537#define DMA1_Y_MODIFY 0xFFC41098 /* DMA1 Outer Loop Address Increment (2D only) */
1538#define DMA1_CURR_DESC_PTR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */
1539#define DMA1_PREV_DESC_PTR 0xFFC410A8 /* DMA1 Previous Initial Descriptor Pointer */
1540#define DMA1_CURR_ADDR 0xFFC410AC /* DMA1 Current Address */
1541#define DMA1_IRQ_STATUS 0xFFC410B0 /* DMA1 Status Register */
1542#define DMA1_CURR_X_COUNT 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
1543#define DMA1_CURR_Y_COUNT 0xFFC410B8 /* DMA1 Current Row Count (2D only) */
1544#define DMA1_BWL_COUNT 0xFFC410C0 /* DMA1 Bandwidth Limit Count */
1545#define DMA1_CURR_BWL_COUNT 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */
1546#define DMA1_BWM_COUNT 0xFFC410C8 /* DMA1 Bandwidth Monitor Count */
1547#define DMA1_CURR_BWM_COUNT 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */
1548
1549/* =========================
1550 DMA2
1551 ========================= */
1552#define DMA2_NEXT_DESC_PTR 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */
1553#define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */
1554#define DMA2_CONFIG 0xFFC41108 /* DMA2 Configuration Register */
1555#define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */
1556#define DMA2_X_MODIFY 0xFFC41110 /* DMA2 Inner Loop Address Increment */
1557#define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */
1558#define DMA2_Y_MODIFY 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */
1559#define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */
1560#define DMA2_PREV_DESC_PTR 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */
1561#define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */
1562#define DMA2_IRQ_STATUS 0xFFC41130 /* DMA2 Status Register */
1563#define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
1564#define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */
1565#define DMA2_BWL_COUNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */
1566#define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */
1567#define DMA2_BWM_COUNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */
1568#define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */
1569
1570/* =========================
1571 DMA3
1572 ========================= */
1573#define DMA3_NEXT_DESC_PTR 0xFFC41180 /* DMA3 Pointer to Next Initial Descriptor */
1574#define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */
1575#define DMA3_CONFIG 0xFFC41188 /* DMA3 Configuration Register */
1576#define DMA3_X_COUNT 0xFFC4118C /* DMA3 Inner Loop Count Start Value */
1577#define DMA3_X_MODIFY 0xFFC41190 /* DMA3 Inner Loop Address Increment */
1578#define DMA3_Y_COUNT 0xFFC41194 /* DMA3 Outer Loop Count Start Value (2D only) */
1579#define DMA3_Y_MODIFY 0xFFC41198 /* DMA3 Outer Loop Address Increment (2D only) */
1580#define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */
1581#define DMA3_PREV_DESC_PTR 0xFFC411A8 /* DMA3 Previous Initial Descriptor Pointer */
1582#define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */
1583#define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */
1584#define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
1585#define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */
1586#define DMA3_BWL_COUNT 0xFFC411C0 /* DMA3 Bandwidth Limit Count */
1587#define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */
1588#define DMA3_BWM_COUNT 0xFFC411C8 /* DMA3 Bandwidth Monitor Count */
1589#define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */
1590
1591/* =========================
1592 DMA4
1593 ========================= */
1594#define DMA4_NEXT_DESC_PTR 0xFFC41200 /* DMA4 Pointer to Next Initial Descriptor */
1595#define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */
1596#define DMA4_CONFIG 0xFFC41208 /* DMA4 Configuration Register */
1597#define DMA4_X_COUNT 0xFFC4120C /* DMA4 Inner Loop Count Start Value */
1598#define DMA4_X_MODIFY 0xFFC41210 /* DMA4 Inner Loop Address Increment */
1599#define DMA4_Y_COUNT 0xFFC41214 /* DMA4 Outer Loop Count Start Value (2D only) */
1600#define DMA4_Y_MODIFY 0xFFC41218 /* DMA4 Outer Loop Address Increment (2D only) */
1601#define DMA4_CURR_DESC_PTR 0xFFC41224 /* DMA4 Current Descriptor Pointer */
1602#define DMA4_PREV_DESC_PTR 0xFFC41228 /* DMA4 Previous Initial Descriptor Pointer */
1603#define DMA4_CURR_ADDR 0xFFC4122C /* DMA4 Current Address */
1604#define DMA4_IRQ_STATUS 0xFFC41230 /* DMA4 Status Register */
1605#define DMA4_CURR_X_COUNT 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
1606#define DMA4_CURR_Y_COUNT 0xFFC41238 /* DMA4 Current Row Count (2D only) */
1607#define DMA4_BWL_COUNT 0xFFC41240 /* DMA4 Bandwidth Limit Count */
1608#define DMA4_CURR_BWL_COUNT 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */
1609#define DMA4_BWM_COUNT 0xFFC41248 /* DMA4 Bandwidth Monitor Count */
1610#define DMA4_CURR_BWM_COUNT 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */
1611
1612/* =========================
1613 DMA5
1614 ========================= */
1615#define DMA5_NEXT_DESC_PTR 0xFFC41280 /* DMA5 Pointer to Next Initial Descriptor */
1616#define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */
1617#define DMA5_CONFIG 0xFFC41288 /* DMA5 Configuration Register */
1618#define DMA5_X_COUNT 0xFFC4128C /* DMA5 Inner Loop Count Start Value */
1619#define DMA5_X_MODIFY 0xFFC41290 /* DMA5 Inner Loop Address Increment */
1620#define DMA5_Y_COUNT 0xFFC41294 /* DMA5 Outer Loop Count Start Value (2D only) */
1621#define DMA5_Y_MODIFY 0xFFC41298 /* DMA5 Outer Loop Address Increment (2D only) */
1622#define DMA5_CURR_DESC_PTR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */
1623#define DMA5_PREV_DESC_PTR 0xFFC412A8 /* DMA5 Previous Initial Descriptor Pointer */
1624#define DMA5_CURR_ADDR 0xFFC412AC /* DMA5 Current Address */
1625#define DMA5_IRQ_STATUS 0xFFC412B0 /* DMA5 Status Register */
1626#define DMA5_CURR_X_COUNT 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
1627#define DMA5_CURR_Y_COUNT 0xFFC412B8 /* DMA5 Current Row Count (2D only) */
1628#define DMA5_BWL_COUNT 0xFFC412C0 /* DMA5 Bandwidth Limit Count */
1629#define DMA5_CURR_BWL_COUNT 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */
1630#define DMA5_BWM_COUNT 0xFFC412C8 /* DMA5 Bandwidth Monitor Count */
1631#define DMA5_CURR_BWM_COUNT 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */
1632
1633/* =========================
1634 DMA6
1635 ========================= */
1636#define DMA6_NEXT_DESC_PTR 0xFFC41300 /* DMA6 Pointer to Next Initial Descriptor */
1637#define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */
1638#define DMA6_CONFIG 0xFFC41308 /* DMA6 Configuration Register */
1639#define DMA6_X_COUNT 0xFFC4130C /* DMA6 Inner Loop Count Start Value */
1640#define DMA6_X_MODIFY 0xFFC41310 /* DMA6 Inner Loop Address Increment */
1641#define DMA6_Y_COUNT 0xFFC41314 /* DMA6 Outer Loop Count Start Value (2D only) */
1642#define DMA6_Y_MODIFY 0xFFC41318 /* DMA6 Outer Loop Address Increment (2D only) */
1643#define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */
1644#define DMA6_PREV_DESC_PTR 0xFFC41328 /* DMA6 Previous Initial Descriptor Pointer */
1645#define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */
1646#define DMA6_IRQ_STATUS 0xFFC41330 /* DMA6 Status Register */
1647#define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
1648#define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */
1649#define DMA6_BWL_COUNT 0xFFC41340 /* DMA6 Bandwidth Limit Count */
1650#define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */
1651#define DMA6_BWM_COUNT 0xFFC41348 /* DMA6 Bandwidth Monitor Count */
1652#define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */
1653
1654/* =========================
1655 DMA7
1656 ========================= */
1657#define DMA7_NEXT_DESC_PTR 0xFFC41380 /* DMA7 Pointer to Next Initial Descriptor */
1658#define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */
1659#define DMA7_CONFIG 0xFFC41388 /* DMA7 Configuration Register */
1660#define DMA7_X_COUNT 0xFFC4138C /* DMA7 Inner Loop Count Start Value */
1661#define DMA7_X_MODIFY 0xFFC41390 /* DMA7 Inner Loop Address Increment */
1662#define DMA7_Y_COUNT 0xFFC41394 /* DMA7 Outer Loop Count Start Value (2D only) */
1663#define DMA7_Y_MODIFY 0xFFC41398 /* DMA7 Outer Loop Address Increment (2D only) */
1664#define DMA7_CURR_DESC_PTR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */
1665#define DMA7_PREV_DESC_PTR 0xFFC413A8 /* DMA7 Previous Initial Descriptor Pointer */
1666#define DMA7_CURR_ADDR 0xFFC413AC /* DMA7 Current Address */
1667#define DMA7_IRQ_STATUS 0xFFC413B0 /* DMA7 Status Register */
1668#define DMA7_CURR_X_COUNT 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
1669#define DMA7_CURR_Y_COUNT 0xFFC413B8 /* DMA7 Current Row Count (2D only) */
1670#define DMA7_BWL_COUNT 0xFFC413C0 /* DMA7 Bandwidth Limit Count */
1671#define DMA7_CURR_BWL_COUNT 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */
1672#define DMA7_BWM_COUNT 0xFFC413C8 /* DMA7 Bandwidth Monitor Count */
1673#define DMA7_CURR_BWM_COUNT 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */
1674
1675/* =========================
1676 DMA8
1677 ========================= */
1678#define DMA8_NEXT_DESC_PTR 0xFFC41400 /* DMA8 Pointer to Next Initial Descriptor */
1679#define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */
1680#define DMA8_CONFIG 0xFFC41408 /* DMA8 Configuration Register */
1681#define DMA8_X_COUNT 0xFFC4140C /* DMA8 Inner Loop Count Start Value */
1682#define DMA8_X_MODIFY 0xFFC41410 /* DMA8 Inner Loop Address Increment */
1683#define DMA8_Y_COUNT 0xFFC41414 /* DMA8 Outer Loop Count Start Value (2D only) */
1684#define DMA8_Y_MODIFY 0xFFC41418 /* DMA8 Outer Loop Address Increment (2D only) */
1685#define DMA8_CURR_DESC_PTR 0xFFC41424 /* DMA8 Current Descriptor Pointer */
1686#define DMA8_PREV_DESC_PTR 0xFFC41428 /* DMA8 Previous Initial Descriptor Pointer */
1687#define DMA8_CURR_ADDR 0xFFC4142C /* DMA8 Current Address */
1688#define DMA8_IRQ_STATUS 0xFFC41430 /* DMA8 Status Register */
1689#define DMA8_CURR_X_COUNT 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
1690#define DMA8_CURR_Y_COUNT 0xFFC41438 /* DMA8 Current Row Count (2D only) */
1691#define DMA8_BWL_COUNT 0xFFC41440 /* DMA8 Bandwidth Limit Count */
1692#define DMA8_CURR_BWL_COUNT 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */
1693#define DMA8_BWM_COUNT 0xFFC41448 /* DMA8 Bandwidth Monitor Count */
1694#define DMA8_CURR_BWM_COUNT 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */
1695
1696/* =========================
1697 DMA9
1698 ========================= */
1699#define DMA9_NEXT_DESC_PTR 0xFFC41480 /* DMA9 Pointer to Next Initial Descriptor */
1700#define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */
1701#define DMA9_CONFIG 0xFFC41488 /* DMA9 Configuration Register */
1702#define DMA9_X_COUNT 0xFFC4148C /* DMA9 Inner Loop Count Start Value */
1703#define DMA9_X_MODIFY 0xFFC41490 /* DMA9 Inner Loop Address Increment */
1704#define DMA9_Y_COUNT 0xFFC41494 /* DMA9 Outer Loop Count Start Value (2D only) */
1705#define DMA9_Y_MODIFY 0xFFC41498 /* DMA9 Outer Loop Address Increment (2D only) */
1706#define DMA9_CURR_DESC_PTR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */
1707#define DMA9_PREV_DESC_PTR 0xFFC414A8 /* DMA9 Previous Initial Descriptor Pointer */
1708#define DMA9_CURR_ADDR 0xFFC414AC /* DMA9 Current Address */
1709#define DMA9_IRQ_STATUS 0xFFC414B0 /* DMA9 Status Register */
1710#define DMA9_CURR_X_COUNT 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
1711#define DMA9_CURR_Y_COUNT 0xFFC414B8 /* DMA9 Current Row Count (2D only) */
1712#define DMA9_BWL_COUNT 0xFFC414C0 /* DMA9 Bandwidth Limit Count */
1713#define DMA9_CURR_BWL_COUNT 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */
1714#define DMA9_BWM_COUNT 0xFFC414C8 /* DMA9 Bandwidth Monitor Count */
1715#define DMA9_CURR_BWM_COUNT 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */
1716
1717/* =========================
1718 DMA10
1719 ========================= */
1720#define DMA10_NEXT_DESC_PTR 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */
1721#define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */
1722#define DMA10_CONFIG 0xFFC05008 /* DMA10 Configuration Register */
1723#define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
1724#define DMA10_X_MODIFY 0xFFC05010 /* DMA10 Inner Loop Address Increment */
1725#define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */
1726#define DMA10_Y_MODIFY 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */
1727#define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
1728#define DMA10_PREV_DESC_PTR 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */
1729#define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */
1730#define DMA10_IRQ_STATUS 0xFFC05030 /* DMA10 Status Register */
1731#define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
1732#define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */
1733#define DMA10_BWL_COUNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
1734#define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
1735#define DMA10_BWM_COUNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
1736#define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */
1737
1738/* =========================
1739 DMA11
1740 ========================= */
1741#define DMA11_NEXT_DESC_PTR 0xFFC05080 /* DMA11 Pointer to Next Initial Descriptor */
1742#define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */
1743#define DMA11_CONFIG 0xFFC05088 /* DMA11 Configuration Register */
1744#define DMA11_X_COUNT 0xFFC0508C /* DMA11 Inner Loop Count Start Value */
1745#define DMA11_X_MODIFY 0xFFC05090 /* DMA11 Inner Loop Address Increment */
1746#define DMA11_Y_COUNT 0xFFC05094 /* DMA11 Outer Loop Count Start Value (2D only) */
1747#define DMA11_Y_MODIFY 0xFFC05098 /* DMA11 Outer Loop Address Increment (2D only) */
1748#define DMA11_CURR_DESC_PTR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */
1749#define DMA11_PREV_DESC_PTR 0xFFC050A8 /* DMA11 Previous Initial Descriptor Pointer */
1750#define DMA11_CURR_ADDR 0xFFC050AC /* DMA11 Current Address */
1751#define DMA11_IRQ_STATUS 0xFFC050B0 /* DMA11 Status Register */
1752#define DMA11_CURR_X_COUNT 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
1753#define DMA11_CURR_Y_COUNT 0xFFC050B8 /* DMA11 Current Row Count (2D only) */
1754#define DMA11_BWL_COUNT 0xFFC050C0 /* DMA11 Bandwidth Limit Count */
1755#define DMA11_CURR_BWL_COUNT 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */
1756#define DMA11_BWM_COUNT 0xFFC050C8 /* DMA11 Bandwidth Monitor Count */
1757#define DMA11_CURR_BWM_COUNT 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */
1758
1759/* =========================
1760 DMA12
1761 ========================= */
1762#define DMA12_NEXT_DESC_PTR 0xFFC05100 /* DMA12 Pointer to Next Initial Descriptor */
1763#define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */
1764#define DMA12_CONFIG 0xFFC05108 /* DMA12 Configuration Register */
1765#define DMA12_X_COUNT 0xFFC0510C /* DMA12 Inner Loop Count Start Value */
1766#define DMA12_X_MODIFY 0xFFC05110 /* DMA12 Inner Loop Address Increment */
1767#define DMA12_Y_COUNT 0xFFC05114 /* DMA12 Outer Loop Count Start Value (2D only) */
1768#define DMA12_Y_MODIFY 0xFFC05118 /* DMA12 Outer Loop Address Increment (2D only) */
1769#define DMA12_CURR_DESC_PTR 0xFFC05124 /* DMA12 Current Descriptor Pointer */
1770#define DMA12_PREV_DESC_PTR 0xFFC05128 /* DMA12 Previous Initial Descriptor Pointer */
1771#define DMA12_CURR_ADDR 0xFFC0512C /* DMA12 Current Address */
1772#define DMA12_IRQ_STATUS 0xFFC05130 /* DMA12 Status Register */
1773#define DMA12_CURR_X_COUNT 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
1774#define DMA12_CURR_Y_COUNT 0xFFC05138 /* DMA12 Current Row Count (2D only) */
1775#define DMA12_BWL_COUNT 0xFFC05140 /* DMA12 Bandwidth Limit Count */
1776#define DMA12_CURR_BWL_COUNT 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */
1777#define DMA12_BWM_COUNT 0xFFC05148 /* DMA12 Bandwidth Monitor Count */
1778#define DMA12_CURR_BWM_COUNT 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */
1779
1780/* =========================
1781 DMA13
1782 ========================= */
1783#define DMA13_NEXT_DESC_PTR 0xFFC07000 /* DMA13 Pointer to Next Initial Descriptor */
1784#define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */
1785#define DMA13_CONFIG 0xFFC07008 /* DMA13 Configuration Register */
1786#define DMA13_X_COUNT 0xFFC0700C /* DMA13 Inner Loop Count Start Value */
1787#define DMA13_X_MODIFY 0xFFC07010 /* DMA13 Inner Loop Address Increment */
1788#define DMA13_Y_COUNT 0xFFC07014 /* DMA13 Outer Loop Count Start Value (2D only) */
1789#define DMA13_Y_MODIFY 0xFFC07018 /* DMA13 Outer Loop Address Increment (2D only) */
1790#define DMA13_CURR_DESC_PTR 0xFFC07024 /* DMA13 Current Descriptor Pointer */
1791#define DMA13_PREV_DESC_PTR 0xFFC07028 /* DMA13 Previous Initial Descriptor Pointer */
1792#define DMA13_CURR_ADDR 0xFFC0702C /* DMA13 Current Address */
1793#define DMA13_IRQ_STATUS 0xFFC07030 /* DMA13 Status Register */
1794#define DMA13_CURR_X_COUNT 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
1795#define DMA13_CURR_Y_COUNT 0xFFC07038 /* DMA13 Current Row Count (2D only) */
1796#define DMA13_BWL_COUNT 0xFFC07040 /* DMA13 Bandwidth Limit Count */
1797#define DMA13_CURR_BWL_COUNT 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */
1798#define DMA13_BWM_COUNT 0xFFC07048 /* DMA13 Bandwidth Monitor Count */
1799#define DMA13_CURR_BWM_COUNT 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */
1800
1801/* =========================
1802 DMA14
1803 ========================= */
1804#define DMA14_NEXT_DESC_PTR 0xFFC07080 /* DMA14 Pointer to Next Initial Descriptor */
1805#define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */
1806#define DMA14_CONFIG 0xFFC07088 /* DMA14 Configuration Register */
1807#define DMA14_X_COUNT 0xFFC0708C /* DMA14 Inner Loop Count Start Value */
1808#define DMA14_X_MODIFY 0xFFC07090 /* DMA14 Inner Loop Address Increment */
1809#define DMA14_Y_COUNT 0xFFC07094 /* DMA14 Outer Loop Count Start Value (2D only) */
1810#define DMA14_Y_MODIFY 0xFFC07098 /* DMA14 Outer Loop Address Increment (2D only) */
1811#define DMA14_CURR_DESC_PTR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */
1812#define DMA14_PREV_DESC_PTR 0xFFC070A8 /* DMA14 Previous Initial Descriptor Pointer */
1813#define DMA14_CURR_ADDR 0xFFC070AC /* DMA14 Current Address */
1814#define DMA14_IRQ_STATUS 0xFFC070B0 /* DMA14 Status Register */
1815#define DMA14_CURR_X_COUNT 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
1816#define DMA14_CURR_Y_COUNT 0xFFC070B8 /* DMA14 Current Row Count (2D only) */
1817#define DMA14_BWL_COUNT 0xFFC070C0 /* DMA14 Bandwidth Limit Count */
1818#define DMA14_CURR_BWL_COUNT 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */
1819#define DMA14_BWM_COUNT 0xFFC070C8 /* DMA14 Bandwidth Monitor Count */
1820#define DMA14_CURR_BWM_COUNT 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */
1821
1822/* =========================
1823 DMA15
1824 ========================= */
1825#define DMA15_NEXT_DESC_PTR 0xFFC07100 /* DMA15 Pointer to Next Initial Descriptor */
1826#define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */
1827#define DMA15_CONFIG 0xFFC07108 /* DMA15 Configuration Register */
1828#define DMA15_X_COUNT 0xFFC0710C /* DMA15 Inner Loop Count Start Value */
1829#define DMA15_X_MODIFY 0xFFC07110 /* DMA15 Inner Loop Address Increment */
1830#define DMA15_Y_COUNT 0xFFC07114 /* DMA15 Outer Loop Count Start Value (2D only) */
1831#define DMA15_Y_MODIFY 0xFFC07118 /* DMA15 Outer Loop Address Increment (2D only) */
1832#define DMA15_CURR_DESC_PTR 0xFFC07124 /* DMA15 Current Descriptor Pointer */
1833#define DMA15_PREV_DESC_PTR 0xFFC07128 /* DMA15 Previous Initial Descriptor Pointer */
1834#define DMA15_CURR_ADDR 0xFFC0712C /* DMA15 Current Address */
1835#define DMA15_IRQ_STATUS 0xFFC07130 /* DMA15 Status Register */
1836#define DMA15_CURR_X_COUNT 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
1837#define DMA15_CURR_Y_COUNT 0xFFC07138 /* DMA15 Current Row Count (2D only) */
1838#define DMA15_BWL_COUNT 0xFFC07140 /* DMA15 Bandwidth Limit Count */
1839#define DMA15_CURR_BWL_COUNT 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */
1840#define DMA15_BWM_COUNT 0xFFC07148 /* DMA15 Bandwidth Monitor Count */
1841#define DMA15_CURR_BWM_COUNT 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */
1842
1843/* =========================
1844 DMA16
1845 ========================= */
1846#define DMA16_NEXT_DESC_PTR 0xFFC07180 /* DMA16 Pointer to Next Initial Descriptor */
1847#define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */
1848#define DMA16_CONFIG 0xFFC07188 /* DMA16 Configuration Register */
1849#define DMA16_X_COUNT 0xFFC0718C /* DMA16 Inner Loop Count Start Value */
1850#define DMA16_X_MODIFY 0xFFC07190 /* DMA16 Inner Loop Address Increment */
1851#define DMA16_Y_COUNT 0xFFC07194 /* DMA16 Outer Loop Count Start Value (2D only) */
1852#define DMA16_Y_MODIFY 0xFFC07198 /* DMA16 Outer Loop Address Increment (2D only) */
1853#define DMA16_CURR_DESC_PTR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */
1854#define DMA16_PREV_DESC_PTR 0xFFC071A8 /* DMA16 Previous Initial Descriptor Pointer */
1855#define DMA16_CURR_ADDR 0xFFC071AC /* DMA16 Current Address */
1856#define DMA16_IRQ_STATUS 0xFFC071B0 /* DMA16 Status Register */
1857#define DMA16_CURR_X_COUNT 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
1858#define DMA16_CURR_Y_COUNT 0xFFC071B8 /* DMA16 Current Row Count (2D only) */
1859#define DMA16_BWL_COUNT 0xFFC071C0 /* DMA16 Bandwidth Limit Count */
1860#define DMA16_CURR_BWL_COUNT 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */
1861#define DMA16_BWM_COUNT 0xFFC071C8 /* DMA16 Bandwidth Monitor Count */
1862#define DMA16_CURR_BWM_COUNT 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */
1863
1864/* =========================
1865 DMA17
1866 ========================= */
1867#define DMA17_NEXT_DESC_PTR 0xFFC07200 /* DMA17 Pointer to Next Initial Descriptor */
1868#define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */
1869#define DMA17_CONFIG 0xFFC07208 /* DMA17 Configuration Register */
1870#define DMA17_X_COUNT 0xFFC0720C /* DMA17 Inner Loop Count Start Value */
1871#define DMA17_X_MODIFY 0xFFC07210 /* DMA17 Inner Loop Address Increment */
1872#define DMA17_Y_COUNT 0xFFC07214 /* DMA17 Outer Loop Count Start Value (2D only) */
1873#define DMA17_Y_MODIFY 0xFFC07218 /* DMA17 Outer Loop Address Increment (2D only) */
1874#define DMA17_CURR_DESC_PTR 0xFFC07224 /* DMA17 Current Descriptor Pointer */
1875#define DMA17_PREV_DESC_PTR 0xFFC07228 /* DMA17 Previous Initial Descriptor Pointer */
1876#define DMA17_CURR_ADDR 0xFFC0722C /* DMA17 Current Address */
1877#define DMA17_IRQ_STATUS 0xFFC07230 /* DMA17 Status Register */
1878#define DMA17_CURR_X_COUNT 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
1879#define DMA17_CURR_Y_COUNT 0xFFC07238 /* DMA17 Current Row Count (2D only) */
1880#define DMA17_BWL_COUNT 0xFFC07240 /* DMA17 Bandwidth Limit Count */
1881#define DMA17_CURR_BWL_COUNT 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */
1882#define DMA17_BWM_COUNT 0xFFC07248 /* DMA17 Bandwidth Monitor Count */
1883#define DMA17_CURR_BWM_COUNT 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */
1884
1885/* =========================
1886 DMA18
1887 ========================= */
1888#define DMA18_NEXT_DESC_PTR 0xFFC07280 /* DMA18 Pointer to Next Initial Descriptor */
1889#define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */
1890#define DMA18_CONFIG 0xFFC07288 /* DMA18 Configuration Register */
1891#define DMA18_X_COUNT 0xFFC0728C /* DMA18 Inner Loop Count Start Value */
1892#define DMA18_X_MODIFY 0xFFC07290 /* DMA18 Inner Loop Address Increment */
1893#define DMA18_Y_COUNT 0xFFC07294 /* DMA18 Outer Loop Count Start Value (2D only) */
1894#define DMA18_Y_MODIFY 0xFFC07298 /* DMA18 Outer Loop Address Increment (2D only) */
1895#define DMA18_CURR_DESC_PTR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */
1896#define DMA18_PREV_DESC_PTR 0xFFC072A8 /* DMA18 Previous Initial Descriptor Pointer */
1897#define DMA18_CURR_ADDR 0xFFC072AC /* DMA18 Current Address */
1898#define DMA18_IRQ_STATUS 0xFFC072B0 /* DMA18 Status Register */
1899#define DMA18_CURR_X_COUNT 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
1900#define DMA18_CURR_Y_COUNT 0xFFC072B8 /* DMA18 Current Row Count (2D only) */
1901#define DMA18_BWL_COUNT 0xFFC072C0 /* DMA18 Bandwidth Limit Count */
1902#define DMA18_CURR_BWL_COUNT 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */
1903#define DMA18_BWM_COUNT 0xFFC072C8 /* DMA18 Bandwidth Monitor Count */
1904#define DMA18_CURR_BWM_COUNT 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */
1905
1906/* =========================
1907 DMA19
1908 ========================= */
1909#define DMA19_NEXT_DESC_PTR 0xFFC07300 /* DMA19 Pointer to Next Initial Descriptor */
1910#define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */
1911#define DMA19_CONFIG 0xFFC07308 /* DMA19 Configuration Register */
1912#define DMA19_X_COUNT 0xFFC0730C /* DMA19 Inner Loop Count Start Value */
1913#define DMA19_X_MODIFY 0xFFC07310 /* DMA19 Inner Loop Address Increment */
1914#define DMA19_Y_COUNT 0xFFC07314 /* DMA19 Outer Loop Count Start Value (2D only) */
1915#define DMA19_Y_MODIFY 0xFFC07318 /* DMA19 Outer Loop Address Increment (2D only) */
1916#define DMA19_CURR_DESC_PTR 0xFFC07324 /* DMA19 Current Descriptor Pointer */
1917#define DMA19_PREV_DESC_PTR 0xFFC07328 /* DMA19 Previous Initial Descriptor Pointer */
1918#define DMA19_CURR_ADDR 0xFFC0732C /* DMA19 Current Address */
1919#define DMA19_IRQ_STATUS 0xFFC07330 /* DMA19 Status Register */
1920#define DMA19_CURR_X_COUNT 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
1921#define DMA19_CURR_Y_COUNT 0xFFC07338 /* DMA19 Current Row Count (2D only) */
1922#define DMA19_BWL_COUNT 0xFFC07340 /* DMA19 Bandwidth Limit Count */
1923#define DMA19_CURR_BWL_COUNT 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */
1924#define DMA19_BWM_COUNT 0xFFC07348 /* DMA19 Bandwidth Monitor Count */
1925#define DMA19_CURR_BWM_COUNT 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */
1926
1927/* =========================
1928 DMA20
1929 ========================= */
1930#define DMA20_NEXT_DESC_PTR 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */
1931#define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */
1932#define DMA20_CONFIG 0xFFC07388 /* DMA20 Configuration Register */
1933#define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */
1934#define DMA20_X_MODIFY 0xFFC07390 /* DMA20 Inner Loop Address Increment */
1935#define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */
1936#define DMA20_Y_MODIFY 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */
1937#define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */
1938#define DMA20_PREV_DESC_PTR 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */
1939#define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */
1940#define DMA20_IRQ_STATUS 0xFFC073B0 /* DMA20 Status Register */
1941#define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
1942#define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */
1943#define DMA20_BWL_COUNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */
1944#define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */
1945#define DMA20_BWM_COUNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */
1946#define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */
1947
1948/* =========================
1949 DMA21
1950 ========================= */
1951#define DMA21_NEXT_DESC_PTR 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */
1952#define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */
1953#define DMA21_CONFIG 0xFFC09008 /* DMA21 Configuration Register */
1954#define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */
1955#define DMA21_X_MODIFY 0xFFC09010 /* DMA21 Inner Loop Address Increment */
1956#define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */
1957#define DMA21_Y_MODIFY 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */
1958#define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */
1959#define DMA21_PREV_DESC_PTR 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */
1960#define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */
1961#define DMA21_IRQ_STATUS 0xFFC09030 /* DMA21 Status Register */
1962#define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
1963#define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */
1964#define DMA21_BWL_COUNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */
1965#define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */
1966#define DMA21_BWM_COUNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */
1967#define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */
1968
1969/* =========================
1970 DMA22
1971 ========================= */
1972#define DMA22_NEXT_DESC_PTR 0xFFC09080 /* DMA22 Pointer to Next Initial Descriptor */
1973#define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */
1974#define DMA22_CONFIG 0xFFC09088 /* DMA22 Configuration Register */
1975#define DMA22_X_COUNT 0xFFC0908C /* DMA22 Inner Loop Count Start Value */
1976#define DMA22_X_MODIFY 0xFFC09090 /* DMA22 Inner Loop Address Increment */
1977#define DMA22_Y_COUNT 0xFFC09094 /* DMA22 Outer Loop Count Start Value (2D only) */
1978#define DMA22_Y_MODIFY 0xFFC09098 /* DMA22 Outer Loop Address Increment (2D only) */
1979#define DMA22_CURR_DESC_PTR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */
1980#define DMA22_PREV_DESC_PTR 0xFFC090A8 /* DMA22 Previous Initial Descriptor Pointer */
1981#define DMA22_CURR_ADDR 0xFFC090AC /* DMA22 Current Address */
1982#define DMA22_IRQ_STATUS 0xFFC090B0 /* DMA22 Status Register */
1983#define DMA22_CURR_X_COUNT 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
1984#define DMA22_CURR_Y_COUNT 0xFFC090B8 /* DMA22 Current Row Count (2D only) */
1985#define DMA22_BWL_COUNT 0xFFC090C0 /* DMA22 Bandwidth Limit Count */
1986#define DMA22_CURR_BWL_COUNT 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */
1987#define DMA22_BWM_COUNT 0xFFC090C8 /* DMA22 Bandwidth Monitor Count */
1988#define DMA22_CURR_BWM_COUNT 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */
1989
1990/* =========================
1991 DMA23
1992 ========================= */
1993#define DMA23_NEXT_DESC_PTR 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */
1994#define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */
1995#define DMA23_CONFIG 0xFFC09108 /* DMA23 Configuration Register */
1996#define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */
1997#define DMA23_X_MODIFY 0xFFC09110 /* DMA23 Inner Loop Address Increment */
1998#define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */
1999#define DMA23_Y_MODIFY 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */
2000#define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */
2001#define DMA23_PREV_DESC_PTR 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */
2002#define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */
2003#define DMA23_IRQ_STATUS 0xFFC09130 /* DMA23 Status Register */
2004#define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
2005#define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */
2006#define DMA23_BWL_COUNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */
2007#define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */
2008#define DMA23_BWM_COUNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */
2009#define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */
2010
2011/* =========================
2012 DMA24
2013 ========================= */
2014#define DMA24_NEXT_DESC_PTR 0xFFC09180 /* DMA24 Pointer to Next Initial Descriptor */
2015#define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */
2016#define DMA24_CONFIG 0xFFC09188 /* DMA24 Configuration Register */
2017#define DMA24_X_COUNT 0xFFC0918C /* DMA24 Inner Loop Count Start Value */
2018#define DMA24_X_MODIFY 0xFFC09190 /* DMA24 Inner Loop Address Increment */
2019#define DMA24_Y_COUNT 0xFFC09194 /* DMA24 Outer Loop Count Start Value (2D only) */
2020#define DMA24_Y_MODIFY 0xFFC09198 /* DMA24 Outer Loop Address Increment (2D only) */
2021#define DMA24_CURR_DESC_PTR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */
2022#define DMA24_PREV_DESC_PTR 0xFFC091A8 /* DMA24 Previous Initial Descriptor Pointer */
2023#define DMA24_CURR_ADDR 0xFFC091AC /* DMA24 Current Address */
2024#define DMA24_IRQ_STATUS 0xFFC091B0 /* DMA24 Status Register */
2025#define DMA24_CURR_X_COUNT 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
2026#define DMA24_CURR_Y_COUNT 0xFFC091B8 /* DMA24 Current Row Count (2D only) */
2027#define DMA24_BWL_COUNT 0xFFC091C0 /* DMA24 Bandwidth Limit Count */
2028#define DMA24_CURR_BWL_COUNT 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */
2029#define DMA24_BWM_COUNT 0xFFC091C8 /* DMA24 Bandwidth Monitor Count */
2030#define DMA24_CURR_BWM_COUNT 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */
2031
2032/* =========================
2033 DMA25
2034 ========================= */
2035#define DMA25_NEXT_DESC_PTR 0xFFC09200 /* DMA25 Pointer to Next Initial Descriptor */
2036#define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */
2037#define DMA25_CONFIG 0xFFC09208 /* DMA25 Configuration Register */
2038#define DMA25_X_COUNT 0xFFC0920C /* DMA25 Inner Loop Count Start Value */
2039#define DMA25_X_MODIFY 0xFFC09210 /* DMA25 Inner Loop Address Increment */
2040#define DMA25_Y_COUNT 0xFFC09214 /* DMA25 Outer Loop Count Start Value (2D only) */
2041#define DMA25_Y_MODIFY 0xFFC09218 /* DMA25 Outer Loop Address Increment (2D only) */
2042#define DMA25_CURR_DESC_PTR 0xFFC09224 /* DMA25 Current Descriptor Pointer */
2043#define DMA25_PREV_DESC_PTR 0xFFC09228 /* DMA25 Previous Initial Descriptor Pointer */
2044#define DMA25_CURR_ADDR 0xFFC0922C /* DMA25 Current Address */
2045#define DMA25_IRQ_STATUS 0xFFC09230 /* DMA25 Status Register */
2046#define DMA25_CURR_X_COUNT 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
2047#define DMA25_CURR_Y_COUNT 0xFFC09238 /* DMA25 Current Row Count (2D only) */
2048#define DMA25_BWL_COUNT 0xFFC09240 /* DMA25 Bandwidth Limit Count */
2049#define DMA25_CURR_BWL_COUNT 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */
2050#define DMA25_BWM_COUNT 0xFFC09248 /* DMA25 Bandwidth Monitor Count */
2051#define DMA25_CURR_BWM_COUNT 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */
2052
2053/* =========================
2054 DMA26
2055 ========================= */
2056#define DMA26_NEXT_DESC_PTR 0xFFC09280 /* DMA26 Pointer to Next Initial Descriptor */
2057#define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */
2058#define DMA26_CONFIG 0xFFC09288 /* DMA26 Configuration Register */
2059#define DMA26_X_COUNT 0xFFC0928C /* DMA26 Inner Loop Count Start Value */
2060#define DMA26_X_MODIFY 0xFFC09290 /* DMA26 Inner Loop Address Increment */
2061#define DMA26_Y_COUNT 0xFFC09294 /* DMA26 Outer Loop Count Start Value (2D only) */
2062#define DMA26_Y_MODIFY 0xFFC09298 /* DMA26 Outer Loop Address Increment (2D only) */
2063#define DMA26_CURR_DESC_PTR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */
2064#define DMA26_PREV_DESC_PTR 0xFFC092A8 /* DMA26 Previous Initial Descriptor Pointer */
2065#define DMA26_CURR_ADDR 0xFFC092AC /* DMA26 Current Address */
2066#define DMA26_IRQ_STATUS 0xFFC092B0 /* DMA26 Status Register */
2067#define DMA26_CURR_X_COUNT 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
2068#define DMA26_CURR_Y_COUNT 0xFFC092B8 /* DMA26 Current Row Count (2D only) */
2069#define DMA26_BWL_COUNT 0xFFC092C0 /* DMA26 Bandwidth Limit Count */
2070#define DMA26_CURR_BWL_COUNT 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */
2071#define DMA26_BWM_COUNT 0xFFC092C8 /* DMA26 Bandwidth Monitor Count */
2072#define DMA26_CURR_BWM_COUNT 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */
2073
2074/* =========================
2075 DMA27
2076 ========================= */
2077#define DMA27_NEXT_DESC_PTR 0xFFC09300 /* DMA27 Pointer to Next Initial Descriptor */
2078#define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */
2079#define DMA27_CONFIG 0xFFC09308 /* DMA27 Configuration Register */
2080#define DMA27_X_COUNT 0xFFC0930C /* DMA27 Inner Loop Count Start Value */
2081#define DMA27_X_MODIFY 0xFFC09310 /* DMA27 Inner Loop Address Increment */
2082#define DMA27_Y_COUNT 0xFFC09314 /* DMA27 Outer Loop Count Start Value (2D only) */
2083#define DMA27_Y_MODIFY 0xFFC09318 /* DMA27 Outer Loop Address Increment (2D only) */
2084#define DMA27_CURR_DESC_PTR 0xFFC09324 /* DMA27 Current Descriptor Pointer */
2085#define DMA27_PREV_DESC_PTR 0xFFC09328 /* DMA27 Previous Initial Descriptor Pointer */
2086#define DMA27_CURR_ADDR 0xFFC0932C /* DMA27 Current Address */
2087#define DMA27_IRQ_STATUS 0xFFC09330 /* DMA27 Status Register */
2088#define DMA27_CURR_X_COUNT 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
2089#define DMA27_CURR_Y_COUNT 0xFFC09338 /* DMA27 Current Row Count (2D only) */
2090#define DMA27_BWL_COUNT 0xFFC09340 /* DMA27 Bandwidth Limit Count */
2091#define DMA27_CURR_BWL_COUNT 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */
2092#define DMA27_BWM_COUNT 0xFFC09348 /* DMA27 Bandwidth Monitor Count */
2093#define DMA27_CURR_BWM_COUNT 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */
2094
2095/* =========================
2096 DMA28
2097 ========================= */
2098#define DMA28_NEXT_DESC_PTR 0xFFC09380 /* DMA28 Pointer to Next Initial Descriptor */
2099#define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */
2100#define DMA28_CONFIG 0xFFC09388 /* DMA28 Configuration Register */
2101#define DMA28_X_COUNT 0xFFC0938C /* DMA28 Inner Loop Count Start Value */
2102#define DMA28_X_MODIFY 0xFFC09390 /* DMA28 Inner Loop Address Increment */
2103#define DMA28_Y_COUNT 0xFFC09394 /* DMA28 Outer Loop Count Start Value (2D only) */
2104#define DMA28_Y_MODIFY 0xFFC09398 /* DMA28 Outer Loop Address Increment (2D only) */
2105#define DMA28_CURR_DESC_PTR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */
2106#define DMA28_PREV_DESC_PTR 0xFFC093A8 /* DMA28 Previous Initial Descriptor Pointer */
2107#define DMA28_CURR_ADDR 0xFFC093AC /* DMA28 Current Address */
2108#define DMA28_IRQ_STATUS 0xFFC093B0 /* DMA28 Status Register */
2109#define DMA28_CURR_X_COUNT 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
2110#define DMA28_CURR_Y_COUNT 0xFFC093B8 /* DMA28 Current Row Count (2D only) */
2111#define DMA28_BWL_COUNT 0xFFC093C0 /* DMA28 Bandwidth Limit Count */
2112#define DMA28_CURR_BWL_COUNT 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */
2113#define DMA28_BWM_COUNT 0xFFC093C8 /* DMA28 Bandwidth Monitor Count */
2114#define DMA28_CURR_BWM_COUNT 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */
2115
2116/* =========================
2117 DMA29
2118 ========================= */
2119#define DMA29_NEXT_DESC_PTR 0xFFC0B000 /* DMA29 Pointer to Next Initial Descriptor */
2120#define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */
2121#define DMA29_CONFIG 0xFFC0B008 /* DMA29 Configuration Register */
2122#define DMA29_X_COUNT 0xFFC0B00C /* DMA29 Inner Loop Count Start Value */
2123#define DMA29_X_MODIFY 0xFFC0B010 /* DMA29 Inner Loop Address Increment */
2124#define DMA29_Y_COUNT 0xFFC0B014 /* DMA29 Outer Loop Count Start Value (2D only) */
2125#define DMA29_Y_MODIFY 0xFFC0B018 /* DMA29 Outer Loop Address Increment (2D only) */
2126#define DMA29_CURR_DESC_PTR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */
2127#define DMA29_PREV_DESC_PTR 0xFFC0B028 /* DMA29 Previous Initial Descriptor Pointer */
2128#define DMA29_CURR_ADDR 0xFFC0B02C /* DMA29 Current Address */
2129#define DMA29_IRQ_STATUS 0xFFC0B030 /* DMA29 Status Register */
2130#define DMA29_CURR_X_COUNT 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
2131#define DMA29_CURR_Y_COUNT 0xFFC0B038 /* DMA29 Current Row Count (2D only) */
2132#define DMA29_BWL_COUNT 0xFFC0B040 /* DMA29 Bandwidth Limit Count */
2133#define DMA29_CURR_BWL_COUNT 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */
2134#define DMA29_BWM_COUNT 0xFFC0B048 /* DMA29 Bandwidth Monitor Count */
2135#define DMA29_CURR_BWM_COUNT 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */
2136
2137/* =========================
2138 DMA30
2139 ========================= */
2140#define DMA30_NEXT_DESC_PTR 0xFFC0B080 /* DMA30 Pointer to Next Initial Descriptor */
2141#define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */
2142#define DMA30_CONFIG 0xFFC0B088 /* DMA30 Configuration Register */
2143#define DMA30_X_COUNT 0xFFC0B08C /* DMA30 Inner Loop Count Start Value */
2144#define DMA30_X_MODIFY 0xFFC0B090 /* DMA30 Inner Loop Address Increment */
2145#define DMA30_Y_COUNT 0xFFC0B094 /* DMA30 Outer Loop Count Start Value (2D only) */
2146#define DMA30_Y_MODIFY 0xFFC0B098 /* DMA30 Outer Loop Address Increment (2D only) */
2147#define DMA30_CURR_DESC_PTR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */
2148#define DMA30_PREV_DESC_PTR 0xFFC0B0A8 /* DMA30 Previous Initial Descriptor Pointer */
2149#define DMA30_CURR_ADDR 0xFFC0B0AC /* DMA30 Current Address */
2150#define DMA30_IRQ_STATUS 0xFFC0B0B0 /* DMA30 Status Register */
2151#define DMA30_CURR_X_COUNT 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
2152#define DMA30_CURR_Y_COUNT 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */
2153#define DMA30_BWL_COUNT 0xFFC0B0C0 /* DMA30 Bandwidth Limit Count */
2154#define DMA30_CURR_BWL_COUNT 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */
2155#define DMA30_BWM_COUNT 0xFFC0B0C8 /* DMA30 Bandwidth Monitor Count */
2156#define DMA30_CURR_BWM_COUNT 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */
2157
2158/* =========================
2159 DMA31
2160 ========================= */
2161#define DMA31_NEXT_DESC_PTR 0xFFC0B100 /* DMA31 Pointer to Next Initial Descriptor */
2162#define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */
2163#define DMA31_CONFIG 0xFFC0B108 /* DMA31 Configuration Register */
2164#define DMA31_X_COUNT 0xFFC0B10C /* DMA31 Inner Loop Count Start Value */
2165#define DMA31_X_MODIFY 0xFFC0B110 /* DMA31 Inner Loop Address Increment */
2166#define DMA31_Y_COUNT 0xFFC0B114 /* DMA31 Outer Loop Count Start Value (2D only) */
2167#define DMA31_Y_MODIFY 0xFFC0B118 /* DMA31 Outer Loop Address Increment (2D only) */
2168#define DMA31_CURR_DESC_PTR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */
2169#define DMA31_PREV_DESC_PTR 0xFFC0B128 /* DMA31 Previous Initial Descriptor Pointer */
2170#define DMA31_CURR_ADDR 0xFFC0B12C /* DMA31 Current Address */
2171#define DMA31_IRQ_STATUS 0xFFC0B130 /* DMA31 Status Register */
2172#define DMA31_CURR_X_COUNT 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
2173#define DMA31_CURR_Y_COUNT 0xFFC0B138 /* DMA31 Current Row Count (2D only) */
2174#define DMA31_BWL_COUNT 0xFFC0B140 /* DMA31 Bandwidth Limit Count */
2175#define DMA31_CURR_BWL_COUNT 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */
2176#define DMA31_BWM_COUNT 0xFFC0B148 /* DMA31 Bandwidth Monitor Count */
2177#define DMA31_CURR_BWM_COUNT 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */
2178
2179/* =========================
2180 DMA32
2181 ========================= */
2182#define DMA32_NEXT_DESC_PTR 0xFFC0B180 /* DMA32 Pointer to Next Initial Descriptor */
2183#define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */
2184#define DMA32_CONFIG 0xFFC0B188 /* DMA32 Configuration Register */
2185#define DMA32_X_COUNT 0xFFC0B18C /* DMA32 Inner Loop Count Start Value */
2186#define DMA32_X_MODIFY 0xFFC0B190 /* DMA32 Inner Loop Address Increment */
2187#define DMA32_Y_COUNT 0xFFC0B194 /* DMA32 Outer Loop Count Start Value (2D only) */
2188#define DMA32_Y_MODIFY 0xFFC0B198 /* DMA32 Outer Loop Address Increment (2D only) */
2189#define DMA32_CURR_DESC_PTR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */
2190#define DMA32_PREV_DESC_PTR 0xFFC0B1A8 /* DMA32 Previous Initial Descriptor Pointer */
2191#define DMA32_CURR_ADDR 0xFFC0B1AC /* DMA32 Current Address */
2192#define DMA32_IRQ_STATUS 0xFFC0B1B0 /* DMA32 Status Register */
2193#define DMA32_CURR_X_COUNT 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
2194#define DMA32_CURR_Y_COUNT 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */
2195#define DMA32_BWL_COUNT 0xFFC0B1C0 /* DMA32 Bandwidth Limit Count */
2196#define DMA32_CURR_BWL_COUNT 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */
2197#define DMA32_BWM_COUNT 0xFFC0B1C8 /* DMA32 Bandwidth Monitor Count */
2198#define DMA32_CURR_BWM_COUNT 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */
2199
2200/* =========================
2201 DMA33
2202 ========================= */
2203#define DMA33_NEXT_DESC_PTR 0xFFC0D000 /* DMA33 Pointer to Next Initial Descriptor */
2204#define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */
2205#define DMA33_CONFIG 0xFFC0D008 /* DMA33 Configuration Register */
2206#define DMA33_X_COUNT 0xFFC0D00C /* DMA33 Inner Loop Count Start Value */
2207#define DMA33_X_MODIFY 0xFFC0D010 /* DMA33 Inner Loop Address Increment */
2208#define DMA33_Y_COUNT 0xFFC0D014 /* DMA33 Outer Loop Count Start Value (2D only) */
2209#define DMA33_Y_MODIFY 0xFFC0D018 /* DMA33 Outer Loop Address Increment (2D only) */
2210#define DMA33_CURR_DESC_PTR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */
2211#define DMA33_PREV_DESC_PTR 0xFFC0D028 /* DMA33 Previous Initial Descriptor Pointer */
2212#define DMA33_CURR_ADDR 0xFFC0D02C /* DMA33 Current Address */
2213#define DMA33_IRQ_STATUS 0xFFC0D030 /* DMA33 Status Register */
2214#define DMA33_CURR_X_COUNT 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
2215#define DMA33_CURR_Y_COUNT 0xFFC0D038 /* DMA33 Current Row Count (2D only) */
2216#define DMA33_BWL_COUNT 0xFFC0D040 /* DMA33 Bandwidth Limit Count */
2217#define DMA33_CURR_BWL_COUNT 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */
2218#define DMA33_BWM_COUNT 0xFFC0D048 /* DMA33 Bandwidth Monitor Count */
2219#define DMA33_CURR_BWM_COUNT 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */
2220
2221/* =========================
2222 DMA34
2223 ========================= */
2224#define DMA34_NEXT_DESC_PTR 0xFFC0D080 /* DMA34 Pointer to Next Initial Descriptor */
2225#define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */
2226#define DMA34_CONFIG 0xFFC0D088 /* DMA34 Configuration Register */
2227#define DMA34_X_COUNT 0xFFC0D08C /* DMA34 Inner Loop Count Start Value */
2228#define DMA34_X_MODIFY 0xFFC0D090 /* DMA34 Inner Loop Address Increment */
2229#define DMA34_Y_COUNT 0xFFC0D094 /* DMA34 Outer Loop Count Start Value (2D only) */
2230#define DMA34_Y_MODIFY 0xFFC0D098 /* DMA34 Outer Loop Address Increment (2D only) */
2231#define DMA34_CURR_DESC_PTR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */
2232#define DMA34_PREV_DESC_PTR 0xFFC0D0A8 /* DMA34 Previous Initial Descriptor Pointer */
2233#define DMA34_CURR_ADDR 0xFFC0D0AC /* DMA34 Current Address */
2234#define DMA34_IRQ_STATUS 0xFFC0D0B0 /* DMA34 Status Register */
2235#define DMA34_CURR_X_COUNT 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
2236#define DMA34_CURR_Y_COUNT 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */
2237#define DMA34_BWL_COUNT 0xFFC0D0C0 /* DMA34 Bandwidth Limit Count */
2238#define DMA34_CURR_BWL_COUNT 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */
2239#define DMA34_BWM_COUNT 0xFFC0D0C8 /* DMA34 Bandwidth Monitor Count */
2240#define DMA34_CURR_BWM_COUNT 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */
2241
2242/* =========================
2243 DMA35
2244 ========================= */
2245#define DMA35_NEXT_DESC_PTR 0xFFC10000 /* DMA35 Pointer to Next Initial Descriptor */
2246#define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */
2247#define DMA35_CONFIG 0xFFC10008 /* DMA35 Configuration Register */
2248#define DMA35_X_COUNT 0xFFC1000C /* DMA35 Inner Loop Count Start Value */
2249#define DMA35_X_MODIFY 0xFFC10010 /* DMA35 Inner Loop Address Increment */
2250#define DMA35_Y_COUNT 0xFFC10014 /* DMA35 Outer Loop Count Start Value (2D only) */
2251#define DMA35_Y_MODIFY 0xFFC10018 /* DMA35 Outer Loop Address Increment (2D only) */
2252#define DMA35_CURR_DESC_PTR 0xFFC10024 /* DMA35 Current Descriptor Pointer */
2253#define DMA35_PREV_DESC_PTR 0xFFC10028 /* DMA35 Previous Initial Descriptor Pointer */
2254#define DMA35_CURR_ADDR 0xFFC1002C /* DMA35 Current Address */
2255#define DMA35_IRQ_STATUS 0xFFC10030 /* DMA35 Status Register */
2256#define DMA35_CURR_X_COUNT 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
2257#define DMA35_CURR_Y_COUNT 0xFFC10038 /* DMA35 Current Row Count (2D only) */
2258#define DMA35_BWL_COUNT 0xFFC10040 /* DMA35 Bandwidth Limit Count */
2259#define DMA35_CURR_BWL_COUNT 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */
2260#define DMA35_BWM_COUNT 0xFFC10048 /* DMA35 Bandwidth Monitor Count */
2261#define DMA35_CURR_BWM_COUNT 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */
2262
2263/* =========================
2264 DMA36
2265 ========================= */
2266#define DMA36_NEXT_DESC_PTR 0xFFC10080 /* DMA36 Pointer to Next Initial Descriptor */
2267#define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */
2268#define DMA36_CONFIG 0xFFC10088 /* DMA36 Configuration Register */
2269#define DMA36_X_COUNT 0xFFC1008C /* DMA36 Inner Loop Count Start Value */
2270#define DMA36_X_MODIFY 0xFFC10090 /* DMA36 Inner Loop Address Increment */
2271#define DMA36_Y_COUNT 0xFFC10094 /* DMA36 Outer Loop Count Start Value (2D only) */
2272#define DMA36_Y_MODIFY 0xFFC10098 /* DMA36 Outer Loop Address Increment (2D only) */
2273#define DMA36_CURR_DESC_PTR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */
2274#define DMA36_PREV_DESC_PTR 0xFFC100A8 /* DMA36 Previous Initial Descriptor Pointer */
2275#define DMA36_CURR_ADDR 0xFFC100AC /* DMA36 Current Address */
2276#define DMA36_IRQ_STATUS 0xFFC100B0 /* DMA36 Status Register */
2277#define DMA36_CURR_X_COUNT 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
2278#define DMA36_CURR_Y_COUNT 0xFFC100B8 /* DMA36 Current Row Count (2D only) */
2279#define DMA36_BWL_COUNT 0xFFC100C0 /* DMA36 Bandwidth Limit Count */
2280#define DMA36_CURR_BWL_COUNT 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */
2281#define DMA36_BWM_COUNT 0xFFC100C8 /* DMA36 Bandwidth Monitor Count */
2282#define DMA36_CURR_BWM_COUNT 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */
2283
2284/* =========================
2285 DMA37
2286 ========================= */
2287#define DMA37_NEXT_DESC_PTR 0xFFC10100 /* DMA37 Pointer to Next Initial Descriptor */
2288#define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */
2289#define DMA37_CONFIG 0xFFC10108 /* DMA37 Configuration Register */
2290#define DMA37_X_COUNT 0xFFC1010C /* DMA37 Inner Loop Count Start Value */
2291#define DMA37_X_MODIFY 0xFFC10110 /* DMA37 Inner Loop Address Increment */
2292#define DMA37_Y_COUNT 0xFFC10114 /* DMA37 Outer Loop Count Start Value (2D only) */
2293#define DMA37_Y_MODIFY 0xFFC10118 /* DMA37 Outer Loop Address Increment (2D only) */
2294#define DMA37_CURR_DESC_PTR 0xFFC10124 /* DMA37 Current Descriptor Pointer */
2295#define DMA37_PREV_DESC_PTR 0xFFC10128 /* DMA37 Previous Initial Descriptor Pointer */
2296#define DMA37_CURR_ADDR 0xFFC1012C /* DMA37 Current Address */
2297#define DMA37_IRQ_STATUS 0xFFC10130 /* DMA37 Status Register */
2298#define DMA37_CURR_X_COUNT 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
2299#define DMA37_CURR_Y_COUNT 0xFFC10138 /* DMA37 Current Row Count (2D only) */
2300#define DMA37_BWL_COUNT 0xFFC10140 /* DMA37 Bandwidth Limit Count */
2301#define DMA37_CURR_BWL_COUNT 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */
2302#define DMA37_BWM_COUNT 0xFFC10148 /* DMA37 Bandwidth Monitor Count */
2303#define DMA37_CURR_BWM_COUNT 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */
2304
2305/* =========================
2306 DMA38
2307 ========================= */
2308#define DMA38_NEXT_DESC_PTR 0xFFC12000 /* DMA38 Pointer to Next Initial Descriptor */
2309#define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */
2310#define DMA38_CONFIG 0xFFC12008 /* DMA38 Configuration Register */
2311#define DMA38_X_COUNT 0xFFC1200C /* DMA38 Inner Loop Count Start Value */
2312#define DMA38_X_MODIFY 0xFFC12010 /* DMA38 Inner Loop Address Increment */
2313#define DMA38_Y_COUNT 0xFFC12014 /* DMA38 Outer Loop Count Start Value (2D only) */
2314#define DMA38_Y_MODIFY 0xFFC12018 /* DMA38 Outer Loop Address Increment (2D only) */
2315#define DMA38_CURR_DESC_PTR 0xFFC12024 /* DMA38 Current Descriptor Pointer */
2316#define DMA38_PREV_DESC_PTR 0xFFC12028 /* DMA38 Previous Initial Descriptor Pointer */
2317#define DMA38_CURR_ADDR 0xFFC1202C /* DMA38 Current Address */
2318#define DMA38_IRQ_STATUS 0xFFC12030 /* DMA38 Status Register */
2319#define DMA38_CURR_X_COUNT 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
2320#define DMA38_CURR_Y_COUNT 0xFFC12038 /* DMA38 Current Row Count (2D only) */
2321#define DMA38_BWL_COUNT 0xFFC12040 /* DMA38 Bandwidth Limit Count */
2322#define DMA38_CURR_BWL_COUNT 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */
2323#define DMA38_BWM_COUNT 0xFFC12048 /* DMA38 Bandwidth Monitor Count */
2324#define DMA38_CURR_BWM_COUNT 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */
2325
2326/* =========================
2327 DMA39
2328 ========================= */
2329#define DMA39_NEXT_DESC_PTR 0xFFC12080 /* DMA39 Pointer to Next Initial Descriptor */
2330#define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */
2331#define DMA39_CONFIG 0xFFC12088 /* DMA39 Configuration Register */
2332#define DMA39_X_COUNT 0xFFC1208C /* DMA39 Inner Loop Count Start Value */
2333#define DMA39_X_MODIFY 0xFFC12090 /* DMA39 Inner Loop Address Increment */
2334#define DMA39_Y_COUNT 0xFFC12094 /* DMA39 Outer Loop Count Start Value (2D only) */
2335#define DMA39_Y_MODIFY 0xFFC12098 /* DMA39 Outer Loop Address Increment (2D only) */
2336#define DMA39_CURR_DESC_PTR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */
2337#define DMA39_PREV_DESC_PTR 0xFFC120A8 /* DMA39 Previous Initial Descriptor Pointer */
2338#define DMA39_CURR_ADDR 0xFFC120AC /* DMA39 Current Address */
2339#define DMA39_IRQ_STATUS 0xFFC120B0 /* DMA39 Status Register */
2340#define DMA39_CURR_X_COUNT 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
2341#define DMA39_CURR_Y_COUNT 0xFFC120B8 /* DMA39 Current Row Count (2D only) */
2342#define DMA39_BWL_COUNT 0xFFC120C0 /* DMA39 Bandwidth Limit Count */
2343#define DMA39_CURR_BWL_COUNT 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */
2344#define DMA39_BWM_COUNT 0xFFC120C8 /* DMA39 Bandwidth Monitor Count */
2345#define DMA39_CURR_BWM_COUNT 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */
2346
2347/* =========================
2348 DMA40
2349 ========================= */
2350#define DMA40_NEXT_DESC_PTR 0xFFC12100 /* DMA40 Pointer to Next Initial Descriptor */
2351#define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */
2352#define DMA40_CONFIG 0xFFC12108 /* DMA40 Configuration Register */
2353#define DMA40_X_COUNT 0xFFC1210C /* DMA40 Inner Loop Count Start Value */
2354#define DMA40_X_MODIFY 0xFFC12110 /* DMA40 Inner Loop Address Increment */
2355#define DMA40_Y_COUNT 0xFFC12114 /* DMA40 Outer Loop Count Start Value (2D only) */
2356#define DMA40_Y_MODIFY 0xFFC12118 /* DMA40 Outer Loop Address Increment (2D only) */
2357#define DMA40_CURR_DESC_PTR 0xFFC12124 /* DMA40 Current Descriptor Pointer */
2358#define DMA40_PREV_DESC_PTR 0xFFC12128 /* DMA40 Previous Initial Descriptor Pointer */
2359#define DMA40_CURR_ADDR 0xFFC1212C /* DMA40 Current Address */
2360#define DMA40_IRQ_STATUS 0xFFC12130 /* DMA40 Status Register */
2361#define DMA40_CURR_X_COUNT 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
2362#define DMA40_CURR_Y_COUNT 0xFFC12138 /* DMA40 Current Row Count (2D only) */
2363#define DMA40_BWL_COUNT 0xFFC12140 /* DMA40 Bandwidth Limit Count */
2364#define DMA40_CURR_BWL_COUNT 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */
2365#define DMA40_BWM_COUNT 0xFFC12148 /* DMA40 Bandwidth Monitor Count */
2366#define DMA40_CURR_BWM_COUNT 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */
2367
2368/* =========================
2369 DMA41
2370 ========================= */
2371#define DMA41_NEXT_DESC_PTR 0xFFC12180 /* DMA41 Pointer to Next Initial Descriptor */
2372#define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */
2373#define DMA41_CONFIG 0xFFC12188 /* DMA41 Configuration Register */
2374#define DMA41_X_COUNT 0xFFC1218C /* DMA41 Inner Loop Count Start Value */
2375#define DMA41_X_MODIFY 0xFFC12190 /* DMA41 Inner Loop Address Increment */
2376#define DMA41_Y_COUNT 0xFFC12194 /* DMA41 Outer Loop Count Start Value (2D only) */
2377#define DMA41_Y_MODIFY 0xFFC12198 /* DMA41 Outer Loop Address Increment (2D only) */
2378#define DMA41_CURR_DESC_PTR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */
2379#define DMA41_PREV_DESC_PTR 0xFFC121A8 /* DMA41 Previous Initial Descriptor Pointer */
2380#define DMA41_CURR_ADDR 0xFFC121AC /* DMA41 Current Address */
2381#define DMA41_IRQ_STATUS 0xFFC121B0 /* DMA41 Status Register */
2382#define DMA41_CURR_X_COUNT 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
2383#define DMA41_CURR_Y_COUNT 0xFFC121B8 /* DMA41 Current Row Count (2D only) */
2384#define DMA41_BWL_COUNT 0xFFC121C0 /* DMA41 Bandwidth Limit Count */
2385#define DMA41_CURR_BWL_COUNT 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */
2386#define DMA41_BWM_COUNT 0xFFC121C8 /* DMA41 Bandwidth Monitor Count */
2387#define DMA41_CURR_BWM_COUNT 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */
2388
2389/* =========================
2390 DMA42
2391 ========================= */
2392#define DMA42_NEXT_DESC_PTR 0xFFC14000 /* DMA42 Pointer to Next Initial Descriptor */
2393#define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */
2394#define DMA42_CONFIG 0xFFC14008 /* DMA42 Configuration Register */
2395#define DMA42_X_COUNT 0xFFC1400C /* DMA42 Inner Loop Count Start Value */
2396#define DMA42_X_MODIFY 0xFFC14010 /* DMA42 Inner Loop Address Increment */
2397#define DMA42_Y_COUNT 0xFFC14014 /* DMA42 Outer Loop Count Start Value (2D only) */
2398#define DMA42_Y_MODIFY 0xFFC14018 /* DMA42 Outer Loop Address Increment (2D only) */
2399#define DMA42_CURR_DESC_PTR 0xFFC14024 /* DMA42 Current Descriptor Pointer */
2400#define DMA42_PREV_DESC_PTR 0xFFC14028 /* DMA42 Previous Initial Descriptor Pointer */
2401#define DMA42_CURR_ADDR 0xFFC1402C /* DMA42 Current Address */
2402#define DMA42_IRQ_STATUS 0xFFC14030 /* DMA42 Status Register */
2403#define DMA42_CURR_X_COUNT 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
2404#define DMA42_CURR_Y_COUNT 0xFFC14038 /* DMA42 Current Row Count (2D only) */
2405#define DMA42_BWL_COUNT 0xFFC14040 /* DMA42 Bandwidth Limit Count */
2406#define DMA42_CURR_BWL_COUNT 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */
2407#define DMA42_BWM_COUNT 0xFFC14048 /* DMA42 Bandwidth Monitor Count */
2408#define DMA42_CURR_BWM_COUNT 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */
2409
2410/* =========================
2411 DMA43
2412 ========================= */
2413#define DMA43_NEXT_DESC_PTR 0xFFC14080 /* DMA43 Pointer to Next Initial Descriptor */
2414#define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */
2415#define DMA43_CONFIG 0xFFC14088 /* DMA43 Configuration Register */
2416#define DMA43_X_COUNT 0xFFC1408C /* DMA43 Inner Loop Count Start Value */
2417#define DMA43_X_MODIFY 0xFFC14090 /* DMA43 Inner Loop Address Increment */
2418#define DMA43_Y_COUNT 0xFFC14094 /* DMA43 Outer Loop Count Start Value (2D only) */
2419#define DMA43_Y_MODIFY 0xFFC14098 /* DMA43 Outer Loop Address Increment (2D only) */
2420#define DMA43_CURR_DESC_PTR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */
2421#define DMA43_PREV_DESC_PTR 0xFFC140A8 /* DMA43 Previous Initial Descriptor Pointer */
2422#define DMA43_CURR_ADDR 0xFFC140AC /* DMA43 Current Address */
2423#define DMA43_IRQ_STATUS 0xFFC140B0 /* DMA43 Status Register */
2424#define DMA43_CURR_X_COUNT 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
2425#define DMA43_CURR_Y_COUNT 0xFFC140B8 /* DMA43 Current Row Count (2D only) */
2426#define DMA43_BWL_COUNT 0xFFC140C0 /* DMA43 Bandwidth Limit Count */
2427#define DMA43_CURR_BWL_COUNT 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */
2428#define DMA43_BWM_COUNT 0xFFC140C8 /* DMA43 Bandwidth Monitor Count */
2429#define DMA43_CURR_BWM_COUNT 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */
2430
2431/* =========================
2432 DMA44
2433 ========================= */
2434#define DMA44_NEXT_DESC_PTR 0xFFC14100 /* DMA44 Pointer to Next Initial Descriptor */
2435#define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */
2436#define DMA44_CONFIG 0xFFC14108 /* DMA44 Configuration Register */
2437#define DMA44_X_COUNT 0xFFC1410C /* DMA44 Inner Loop Count Start Value */
2438#define DMA44_X_MODIFY 0xFFC14110 /* DMA44 Inner Loop Address Increment */
2439#define DMA44_Y_COUNT 0xFFC14114 /* DMA44 Outer Loop Count Start Value (2D only) */
2440#define DMA44_Y_MODIFY 0xFFC14118 /* DMA44 Outer Loop Address Increment (2D only) */
2441#define DMA44_CURR_DESC_PTR 0xFFC14124 /* DMA44 Current Descriptor Pointer */
2442#define DMA44_PREV_DESC_PTR 0xFFC14128 /* DMA44 Previous Initial Descriptor Pointer */
2443#define DMA44_CURR_ADDR 0xFFC1412C /* DMA44 Current Address */
2444#define DMA44_IRQ_STATUS 0xFFC14130 /* DMA44 Status Register */
2445#define DMA44_CURR_X_COUNT 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
2446#define DMA44_CURR_Y_COUNT 0xFFC14138 /* DMA44 Current Row Count (2D only) */
2447#define DMA44_BWL_COUNT 0xFFC14140 /* DMA44 Bandwidth Limit Count */
2448#define DMA44_CURR_BWL_COUNT 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */
2449#define DMA44_BWM_COUNT 0xFFC14148 /* DMA44 Bandwidth Monitor Count */
2450#define DMA44_CURR_BWM_COUNT 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */
2451
2452/* =========================
2453 DMA45
2454 ========================= */
2455#define DMA45_NEXT_DESC_PTR 0xFFC14180 /* DMA45 Pointer to Next Initial Descriptor */
2456#define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */
2457#define DMA45_CONFIG 0xFFC14188 /* DMA45 Configuration Register */
2458#define DMA45_X_COUNT 0xFFC1418C /* DMA45 Inner Loop Count Start Value */
2459#define DMA45_X_MODIFY 0xFFC14190 /* DMA45 Inner Loop Address Increment */
2460#define DMA45_Y_COUNT 0xFFC14194 /* DMA45 Outer Loop Count Start Value (2D only) */
2461#define DMA45_Y_MODIFY 0xFFC14198 /* DMA45 Outer Loop Address Increment (2D only) */
2462#define DMA45_CURR_DESC_PTR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */
2463#define DMA45_PREV_DESC_PTR 0xFFC141A8 /* DMA45 Previous Initial Descriptor Pointer */
2464#define DMA45_CURR_ADDR 0xFFC141AC /* DMA45 Current Address */
2465#define DMA45_IRQ_STATUS 0xFFC141B0 /* DMA45 Status Register */
2466#define DMA45_CURR_X_COUNT 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
2467#define DMA45_CURR_Y_COUNT 0xFFC141B8 /* DMA45 Current Row Count (2D only) */
2468#define DMA45_BWL_COUNT 0xFFC141C0 /* DMA45 Bandwidth Limit Count */
2469#define DMA45_CURR_BWL_COUNT 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */
2470#define DMA45_BWM_COUNT 0xFFC141C8 /* DMA45 Bandwidth Monitor Count */
2471#define DMA45_CURR_BWM_COUNT 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */
2472
2473/* =========================
2474 DMA46
2475 ========================= */
2476#define DMA46_NEXT_DESC_PTR 0xFFC14200 /* DMA46 Pointer to Next Initial Descriptor */
2477#define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */
2478#define DMA46_CONFIG 0xFFC14208 /* DMA46 Configuration Register */
2479#define DMA46_X_COUNT 0xFFC1420C /* DMA46 Inner Loop Count Start Value */
2480#define DMA46_X_MODIFY 0xFFC14210 /* DMA46 Inner Loop Address Increment */
2481#define DMA46_Y_COUNT 0xFFC14214 /* DMA46 Outer Loop Count Start Value (2D only) */
2482#define DMA46_Y_MODIFY 0xFFC14218 /* DMA46 Outer Loop Address Increment (2D only) */
2483#define DMA46_CURR_DESC_PTR 0xFFC14224 /* DMA46 Current Descriptor Pointer */
2484#define DMA46_PREV_DESC_PTR 0xFFC14228 /* DMA46 Previous Initial Descriptor Pointer */
2485#define DMA46_CURR_ADDR 0xFFC1422C /* DMA46 Current Address */
2486#define DMA46_IRQ_STATUS 0xFFC14230 /* DMA46 Status Register */
2487#define DMA46_CURR_X_COUNT 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
2488#define DMA46_CURR_Y_COUNT 0xFFC14238 /* DMA46 Current Row Count (2D only) */
2489#define DMA46_BWL_COUNT 0xFFC14240 /* DMA46 Bandwidth Limit Count */
2490#define DMA46_CURR_BWL_COUNT 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */
2491#define DMA46_BWM_COUNT 0xFFC14248 /* DMA46 Bandwidth Monitor Count */
2492#define DMA46_CURR_BWM_COUNT 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */
2493
2494
2495/********************************************************************************
2496 DMA Alias Definitions
2497 ********************************************************************************/
2498#define MDMA0_DEST_CRC0_NEXT_DESC_PTR (DMA22_NEXT_DESC_PTR)
2499#define MDMA0_DEST_CRC0_START_ADDR (DMA22_START_ADDR)
2500#define MDMA0_DEST_CRC0_CONFIG (DMA22_CONFIG)
2501#define MDMA0_DEST_CRC0_X_COUNT (DMA22_X_COUNT)
2502#define MDMA0_DEST_CRC0_X_MODIFY (DMA22_X_MODIFY)
2503#define MDMA0_DEST_CRC0_Y_COUNT (DMA22_Y_COUNT)
2504#define MDMA0_DEST_CRC0_Y_MODIFY (DMA22_Y_MODIFY)
2505#define MDMA0_DEST_CRC0_CURR_DESC_PTR (DMA22_CURR_DESC_PTR)
2506#define MDMA0_DEST_CRC0_PREV_DESC_PTR (DMA22_PREV_DESC_PTR)
2507#define MDMA0_DEST_CRC0_CURR_ADDR (DMA22_CURR_ADDR)
2508#define MDMA0_DEST_CRC0_IRQ_STATUS (DMA22_IRQ_STATUS)
2509#define MDMA0_DEST_CRC0_CURR_X_COUNT (DMA22_CURR_X_COUNT)
2510#define MDMA0_DEST_CRC0_CURR_Y_COUNT (DMA22_CURR_Y_COUNT)
2511#define MDMA0_DEST_CRC0_BWL_COUNT (DMA22_BWL_COUNT)
2512#define MDMA0_DEST_CRC0_CURR_BWL_COUNT (DMA22_CURR_BWL_COUNT)
2513#define MDMA0_DEST_CRC0_BWM_COUNT (DMA22_BWM_COUNT)
2514#define MDMA0_DEST_CRC0_CURR_BWM_COUNT (DMA22_CURR_BWM_COUNT)
2515#define MDMA0_SRC_CRC0_NEXT_DESC_PTR (DMA21_NEXT_DESC_PTR)
2516#define MDMA0_SRC_CRC0_START_ADDR (DMA21_START_ADDR)
2517#define MDMA0_SRC_CRC0_CONFIG (DMA21_CONFIG)
2518#define MDMA0_SRC_CRC0_X_COUNT (DMA21_X_COUNT)
2519#define MDMA0_SRC_CRC0_X_MODIFY (DMA21_X_MODIFY)
2520#define MDMA0_SRC_CRC0_Y_COUNT (DMA21_Y_COUNT)
2521#define MDMA0_SRC_CRC0_Y_MODIFY (DMA21_Y_MODIFY)
2522#define MDMA0_SRC_CRC0_CURR_DESC_PTR (DMA21_CURR_DESC_PTR)
2523#define MDMA0_SRC_CRC0_PREV_DESC_PTR (DMA21_PREV_DESC_PTR)
2524#define MDMA0_SRC_CRC0_CURR_ADDR (DMA21_CURR_ADDR)
2525#define MDMA0_SRC_CRC0_IRQ_STATUS (DMA21_IRQ_STATUS)
2526#define MDMA0_SRC_CRC0_CURR_X_COUNT (DMA21_CURR_X_COUNT)
2527#define MDMA0_SRC_CRC0_CURR_Y_COUNT (DMA21_CURR_Y_COUNT)
2528#define MDMA0_SRC_CRC0_BWL_COUNT (DMA21_BWL_COUNT)
2529#define MDMA0_SRC_CRC0_CURR_BWL_COUNT (DMA21_CURR_BWL_COUNT)
2530#define MDMA0_SRC_CRC0_BWM_COUNT (DMA21_BWM_COUNT)
2531#define MDMA0_SRC_CRC0_CURR_BWM_COUNT (DMA21_CURR_BWM_COUNT)
2532#define MDMA1_DEST_CRC1_NEXT_DESC_PTR (DMA24_NEXT_DESC_PTR)
2533#define MDMA1_DEST_CRC1_START_ADDR (DMA24_START_ADDR)
2534#define MDMA1_DEST_CRC1_CONFIG (DMA24_CONFIG)
2535#define MDMA1_DEST_CRC1_X_COUNT (DMA24_X_COUNT)
2536#define MDMA1_DEST_CRC1_X_MODIFY (DMA24_X_MODIFY)
2537#define MDMA1_DEST_CRC1_Y_COUNT (DMA24_Y_COUNT)
2538#define MDMA1_DEST_CRC1_Y_MODIFY (DMA24_Y_MODIFY)
2539#define MDMA1_DEST_CRC1_CURR_DESC_PTR (DMA24_CURR_DESC_PTR)
2540#define MDMA1_DEST_CRC1_PREV_DESC_PTR (DMA24_PREV_DESC_PTR)
2541#define MDMA1_DEST_CRC1_CURR_ADDR (DMA24_CURR_ADDR)
2542#define MDMA1_DEST_CRC1_IRQ_STATUS (DMA24_IRQ_STATUS)
2543#define MDMA1_DEST_CRC1_CURR_X_COUNT (DMA24_CURR_X_COUNT)
2544#define MDMA1_DEST_CRC1_CURR_Y_COUNT (DMA24_CURR_Y_COUNT)
2545#define MDMA1_DEST_CRC1_BWL_COUNT (DMA24_BWL_COUNT)
2546#define MDMA1_DEST_CRC1_CURR_BWL_COUNT (DMA24_CURR_BWL_COUNT)
2547#define MDMA1_DEST_CRC1_BWM_COUNT (DMA24_BWM_COUNT)
2548#define MDMA1_DEST_CRC1_CURR_BWM_COUNT (DMA24_CURR_BWM_COUNT)
2549#define MDMA1_SRC_CRC1_NEXT_DESC_PTR (DMA23_NEXT_DESC_PTR)
2550#define MDMA1_SRC_CRC1_START_ADDR (DMA23_START_ADDR)
2551#define MDMA1_SRC_CRC1_CONFIG (DMA23_CONFIG)
2552#define MDMA1_SRC_CRC1_X_COUNT (DMA23_X_COUNT)
2553#define MDMA1_SRC_CRC1_X_MODIFY (DMA23_X_MODIFY)
2554#define MDMA1_SRC_CRC1_Y_COUNT (DMA23_Y_COUNT)
2555#define MDMA1_SRC_CRC1_Y_MODIFY (DMA23_Y_MODIFY)
2556#define MDMA1_SRC_CRC1_CURR_DESC_PTR (DMA23_CURR_DESC_PTR)
2557#define MDMA1_SRC_CRC1_PREV_DESC_PTR (DMA23_PREV_DESC_PTR)
2558#define MDMA1_SRC_CRC1_CURR_ADDR (DMA23_CURR_ADDR)
2559#define MDMA1_SRC_CRC1_IRQ_STATUS (DMA23_IRQ_STATUS)
2560#define MDMA1_SRC_CRC1_CURR_X_COUNT (DMA23_CURR_X_COUNT)
2561#define MDMA1_SRC_CRC1_CURR_Y_COUNT (DMA23_CURR_Y_COUNT)
2562#define MDMA1_SRC_CRC1_BWL_COUNT (DMA23_BWL_COUNT)
2563#define MDMA1_SRC_CRC1_CURR_BWL_COUNT (DMA23_CURR_BWL_COUNT)
2564#define MDMA1_SRC_CRC1_BWM_COUNT (DMA23_BWM_COUNT)
2565#define MDMA1_SRC_CRC1_CURR_BWM_COUNT (DMA23_CURR_BWM_COUNT)
2566#define MDMA2_DEST_NEXT_DESC_PTR (DMA26_NEXT_DESC_PTR)
2567#define MDMA2_DEST_START_ADDR (DMA26_START_ADDR)
2568#define MDMA2_DEST_CONFIG (DMA26_CONFIG)
2569#define MDMA2_DEST_X_COUNT (DMA26_X_COUNT)
2570#define MDMA2_DEST_X_MODIFY (DMA26_X_MODIFY)
2571#define MDMA2_DEST_Y_COUNT (DMA26_Y_COUNT)
2572#define MDMA2_DEST_Y_MODIFY (DMA26_Y_MODIFY)
2573#define MDMA2_DEST_CURR_DESC_PTR (DMA26_CURR_DESC_PTR)
2574#define MDMA2_DEST_PREV_DESC_PTR (DMA26_PREV_DESC_PTR)
2575#define MDMA2_DEST_CURR_ADDR (DMA26_CURR_ADDR)
2576#define MDMA2_DEST_IRQ_STATUS (DMA26_IRQ_STATUS)
2577#define MDMA2_DEST_CURR_X_COUNT (DMA26_CURR_X_COUNT)
2578#define MDMA2_DEST_CURR_Y_COUNT (DMA26_CURR_Y_COUNT)
2579#define MDMA2_DEST_BWL_COUNT (DMA26_BWL_COUNT)
2580#define MDMA2_DEST_CURR_BWL_COUNT (DMA26_CURR_BWL_COUNT)
2581#define MDMA2_DEST_BWM_COUNT (DMA26_BWM_COUNT)
2582#define MDMA2_DEST_CURR_BWM_COUNT (DMA26_CURR_BWM_COUNT)
2583#define MDMA2_SRC_NEXT_DESC_PTR (DMA25_NEXT_DESC_PTR)
2584#define MDMA2_SRC_START_ADDR (DMA25_START_ADDR)
2585#define MDMA2_SRC_CONFIG (DMA25_CONFIG)
2586#define MDMA2_SRC_X_COUNT (DMA25_X_COUNT)
2587#define MDMA2_SRC_X_MODIFY (DMA25_X_MODIFY)
2588#define MDMA2_SRC_Y_COUNT (DMA25_Y_COUNT)
2589#define MDMA2_SRC_Y_MODIFY (DMA25_Y_MODIFY)
2590#define MDMA2_SRC_CURR_DESC_PTR (DMA25_CURR_DESC_PTR)
2591#define MDMA2_SRC_PREV_DESC_PTR (DMA25_PREV_DESC_PTR)
2592#define MDMA2_SRC_CURR_ADDR (DMA25_CURR_ADDR)
2593#define MDMA2_SRC_IRQ_STATUS (DMA25_IRQ_STATUS)
2594#define MDMA2_SRC_CURR_X_COUNT (DMA25_CURR_X_COUNT)
2595#define MDMA2_SRC_CURR_Y_COUNT (DMA25_CURR_Y_COUNT)
2596#define MDMA2_SRC_BWL_COUNT (DMA25_BWL_COUNT)
2597#define MDMA2_SRC_CURR_BWL_COUNT (DMA25_CURR_BWL_COUNT)
2598#define MDMA2_SRC_BWM_COUNT (DMA25_BWM_COUNT)
2599#define MDMA2_SRC_CURR_BWM_COUNT (DMA25_CURR_BWM_COUNT)
2600#define MDMA3_DEST_NEXT_DESC_PTR (DMA28_NEXT_DESC_PTR)
2601#define MDMA3_DEST_START_ADDR (DMA28_START_ADDR)
2602#define MDMA3_DEST_CONFIG (DMA28_CONFIG)
2603#define MDMA3_DEST_X_COUNT (DMA28_X_COUNT)
2604#define MDMA3_DEST_X_MODIFY (DMA28_X_MODIFY)
2605#define MDMA3_DEST_Y_COUNT (DMA28_Y_COUNT)
2606#define MDMA3_DEST_Y_MODIFY (DMA28_Y_MODIFY)
2607#define MDMA3_DEST_CURR_DESC_PTR (DMA28_CURR_DESC_PTR)
2608#define MDMA3_DEST_PREV_DESC_PTR (DMA28_PREV_DESC_PTR)
2609#define MDMA3_DEST_CURR_ADDR (DMA28_CURR_ADDR)
2610#define MDMA3_DEST_IRQ_STATUS (DMA28_IRQ_STATUS)
2611#define MDMA3_DEST_CURR_X_COUNT (DMA28_CURR_X_COUNT)
2612#define MDMA3_DEST_CURR_Y_COUNT (DMA28_CURR_Y_COUNT)
2613#define MDMA3_DEST_BWL_COUNT (DMA28_BWL_COUNT)
2614#define MDMA3_DEST_CURR_BWL_COUNT (DMA28_CURR_BWL_COUNT)
2615#define MDMA3_DEST_BWM_COUNT (DMA28_BWM_COUNT)
2616#define MDMA3_DEST_CURR_BWM_COUNT (DMA28_CURR_BWM_COUNT)
2617#define MDMA3_SRC_NEXT_DESC_PTR (DMA27_NEXT_DESC_PTR)
2618#define MDMA3_SRC_START_ADDR (DMA27_START_ADDR)
2619#define MDMA3_SRC_CONFIG (DMA27_CONFIG)
2620#define MDMA3_SRC_X_COUNT (DMA27_X_COUNT)
2621#define MDMA3_SRC_X_MODIFY (DMA27_X_MODIFY)
2622#define MDMA3_SRC_Y_COUNT (DMA27_Y_COUNT)
2623#define MDMA3_SRC_Y_MODIFY (DMA27_Y_MODIFY)
2624#define MDMA3_SRC_CURR_DESC_PTR (DMA27_CURR_DESC_PTR)
2625#define MDMA3_SRC_PREV_DESC_PTR (DMA27_PREV_DESC_PTR)
2626#define MDMA3_SRC_CURR_ADDR (DMA27_CURR_ADDR)
2627#define MDMA3_SRC_IRQ_STATUS (DMA27_IRQ_STATUS)
2628#define MDMA3_SRC_CURR_X_COUNT (DMA27_CURR_X_COUNT)
2629#define MDMA3_SRC_CURR_Y_COUNT (DMA27_CURR_Y_COUNT)
2630#define MDMA3_SRC_BWL_COUNT (DMA27_BWL_COUNT)
2631#define MDMA3_SRC_CURR_BWL_COUNT (DMA27_CURR_BWL_COUNT)
2632#define MDMA3_SRC_BWM_COUNT (DMA27_BWM_COUNT)
2633#define MDMA3_SRC_CURR_BWM_COUNT (DMA27_CURR_BWM_COUNT)
2634
2635
2636/* =========================
2637 DMC Registers
2638 ========================= */
2639
2640/* =========================
2641 DMC0
2642 ========================= */
2643#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */
2644#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
2645#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
2646#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */
2647#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
2648#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */
2649#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */
2650#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */
2651#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */
2652#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */
2653#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */
2654#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */
2655#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */
2656#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */
2657#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */
2658#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
2659#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */
2660
2661#define DEVSZ_64 0x000 /* DMC External Bank Size = 64Mbit */
2662#define DEVSZ_128 0x100 /* DMC External Bank Size = 128Mbit */
2663#define DEVSZ_256 0x200 /* DMC External Bank Size = 256Mbit */
2664#define DEVSZ_512 0x300 /* DMC External Bank Size = 512Mbit */
2665#define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */
2666#define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */
2667
2668
2669/* =========================
2670 L2CTL Registers
2671 ========================= */
2672
2673/* =========================
2674 L2CTL0
2675 ========================= */
2676#define L2CTL0_CTL 0xFFCA3000 /* L2CTL0 L2 Control Register */
2677#define L2CTL0_ACTL_C0 0xFFCA3004 /* L2CTL0 L2 Core 0 Access Control Register */
2678#define L2CTL0_ACTL_C1 0xFFCA3008 /* L2CTL0 L2 Core 1 Access Control Register */
2679#define L2CTL0_ACTL_SYS 0xFFCA300C /* L2CTL0 L2 System Access Control Register */
2680#define L2CTL0_STAT 0xFFCA3010 /* L2CTL0 L2 Status Register */
2681#define L2CTL0_RPCR 0xFFCA3014 /* L2CTL0 L2 Read Priority Count Register */
2682#define L2CTL0_WPCR 0xFFCA3018 /* L2CTL0 L2 Write Priority Count Register */
2683#define L2CTL0_RFA 0xFFCA3024 /* L2CTL0 L2 Refresh Address Regsiter */
2684#define L2CTL0_ERRADDR0 0xFFCA3040 /* L2CTL0 L2 Bank 0 ECC Error Address Register */
2685#define L2CTL0_ERRADDR1 0xFFCA3044 /* L2CTL0 L2 Bank 1 ECC Error Address Register */
2686#define L2CTL0_ERRADDR2 0xFFCA3048 /* L2CTL0 L2 Bank 2 ECC Error Address Register */
2687#define L2CTL0_ERRADDR3 0xFFCA304C /* L2CTL0 L2 Bank 3 ECC Error Address Register */
2688#define L2CTL0_ERRADDR4 0xFFCA3050 /* L2CTL0 L2 Bank 4 ECC Error Address Register */
2689#define L2CTL0_ERRADDR5 0xFFCA3054 /* L2CTL0 L2 Bank 5 ECC Error Address Register */
2690#define L2CTL0_ERRADDR6 0xFFCA3058 /* L2CTL0 L2 Bank 6 ECC Error Address Register */
2691#define L2CTL0_ERRADDR7 0xFFCA305C /* L2CTL0 L2 Bank 7 ECC Error Address Register */
2692#define L2CTL0_ET0 0xFFCA3080 /* L2CTL0 L2 AXI Error 0 Type Register */
2693#define L2CTL0_EADDR0 0xFFCA3084 /* L2CTL0 L2 AXI Error 0 Address Register */
2694#define L2CTL0_ET1 0xFFCA3088 /* L2CTL0 L2 AXI Error 1 Type Register */
2695#define L2CTL0_EADDR1 0xFFCA308C /* L2CTL0 L2 AXI Error 1 Address Register */
2696
2697
2698/* =========================
2699 SEC Registers
2700 ========================= */
2701/* ------------------------------------------------------------------------------------------------------------------------
2702 SEC Core Interface (SCI) Register Definitions
2703 ------------------------------------------------------------------------------------------------------------------------ */
2704
2705#define SEC_SCI_BASE 0xFFCA4400
2706#define SEC_SCI_OFF 0x40
2707#define SEC_CCTL 0x0 /* SEC Core Control Register n */
2708#define SEC_CSTAT 0x4 /* SEC Core Status Register n */
2709#define SEC_CPND 0x8 /* SEC Core Pending IRQ Register n */
2710#define SEC_CACT 0xC /* SEC Core Active IRQ Register n */
2711#define SEC_CPMSK 0x10 /* SEC Core IRQ Priority Mask Register n */
2712#define SEC_CGMSK 0x14 /* SEC Core IRQ Group Mask Register n */
2713#define SEC_CPLVL 0x18 /* SEC Core IRQ Priority Level Register n */
2714#define SEC_CSID 0x1C /* SEC Core IRQ Source ID Register n */
2715
2716#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
2717#define bfin_write_SEC_SCI(n, reg, val) \
2718 bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
2719
2720/* ------------------------------------------------------------------------------------------------------------------------
2721 SEC Fault Management Interface (SFI) Register Definitions
2722 ------------------------------------------------------------------------------------------------------------------------ */
2723#define SEC_FCTL 0xFFCA4010 /* SEC Fault Control Register */
2724#define SEC_FSTAT 0xFFCA4014 /* SEC Fault Status Register */
2725#define SEC_FSID 0xFFCA4018 /* SEC Fault Source ID Register */
2726#define SEC_FEND 0xFFCA401C /* SEC Fault End Register */
2727#define SEC_FDLY 0xFFCA4020 /* SEC Fault Delay Register */
2728#define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */
2729#define SEC_FSRDLY 0xFFCA4028 /* SEC Fault System Reset Delay Register */
2730#define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */
2731#define SEC_FCOPP 0xFFCA4030 /* SEC Fault COP Period Register */
2732#define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */
2733
2734/* ------------------------------------------------------------------------------------------------------------------------
2735 SEC Global Register Definitions
2736 ------------------------------------------------------------------------------------------------------------------------ */
2737#define SEC_GCTL 0xFFCA4000 /* SEC Global Control Register */
2738#define SEC_GSTAT 0xFFCA4004 /* SEC Global Status Register */
2739#define SEC_RAISE 0xFFCA4008 /* SEC Global Raise Register */
2740#define SEC_END 0xFFCA400C /* SEC Global End Register */
2741
2742/* ------------------------------------------------------------------------------------------------------------------------
2743 SEC Source Interface (SSI) Register Definitions
2744 ------------------------------------------------------------------------------------------------------------------------ */
2745#define SEC_SCTL0 0xFFCA4800 /* SEC IRQ Source Control Register n */
2746#define SEC_SCTL1 0xFFCA4808 /* SEC IRQ Source Control Register n */
2747#define SEC_SCTL2 0xFFCA4810 /* SEC IRQ Source Control Register n */
2748#define SEC_SCTL3 0xFFCA4818 /* SEC IRQ Source Control Register n */
2749#define SEC_SCTL4 0xFFCA4820 /* SEC IRQ Source Control Register n */
2750#define SEC_SCTL5 0xFFCA4828 /* SEC IRQ Source Control Register n */
2751#define SEC_SCTL6 0xFFCA4830 /* SEC IRQ Source Control Register n */
2752#define SEC_SCTL7 0xFFCA4838 /* SEC IRQ Source Control Register n */
2753#define SEC_SCTL8 0xFFCA4840 /* SEC IRQ Source Control Register n */
2754#define SEC_SCTL9 0xFFCA4848 /* SEC IRQ Source Control Register n */
2755#define SEC_SCTL10 0xFFCA4850 /* SEC IRQ Source Control Register n */
2756#define SEC_SCTL11 0xFFCA4858 /* SEC IRQ Source Control Register n */
2757#define SEC_SCTL12 0xFFCA4860 /* SEC IRQ Source Control Register n */
2758#define SEC_SCTL13 0xFFCA4868 /* SEC IRQ Source Control Register n */
2759#define SEC_SCTL14 0xFFCA4870 /* SEC IRQ Source Control Register n */
2760#define SEC_SCTL15 0xFFCA4878 /* SEC IRQ Source Control Register n */
2761#define SEC_SCTL16 0xFFCA4880 /* SEC IRQ Source Control Register n */
2762#define SEC_SCTL17 0xFFCA4888 /* SEC IRQ Source Control Register n */
2763#define SEC_SCTL18 0xFFCA4890 /* SEC IRQ Source Control Register n */
2764#define SEC_SCTL19 0xFFCA4898 /* SEC IRQ Source Control Register n */
2765#define SEC_SCTL20 0xFFCA48A0 /* SEC IRQ Source Control Register n */
2766#define SEC_SCTL21 0xFFCA48A8 /* SEC IRQ Source Control Register n */
2767#define SEC_SCTL22 0xFFCA48B0 /* SEC IRQ Source Control Register n */
2768#define SEC_SCTL23 0xFFCA48B8 /* SEC IRQ Source Control Register n */
2769#define SEC_SCTL24 0xFFCA48C0 /* SEC IRQ Source Control Register n */
2770#define SEC_SCTL25 0xFFCA48C8 /* SEC IRQ Source Control Register n */
2771#define SEC_SCTL26 0xFFCA48D0 /* SEC IRQ Source Control Register n */
2772#define SEC_SCTL27 0xFFCA48D8 /* SEC IRQ Source Control Register n */
2773#define SEC_SCTL28 0xFFCA48E0 /* SEC IRQ Source Control Register n */
2774#define SEC_SCTL29 0xFFCA48E8 /* SEC IRQ Source Control Register n */
2775#define SEC_SCTL30 0xFFCA48F0 /* SEC IRQ Source Control Register n */
2776#define SEC_SCTL31 0xFFCA48F8 /* SEC IRQ Source Control Register n */
2777#define SEC_SCTL32 0xFFCA4900 /* SEC IRQ Source Control Register n */
2778#define SEC_SCTL33 0xFFCA4908 /* SEC IRQ Source Control Register n */
2779#define SEC_SCTL34 0xFFCA4910 /* SEC IRQ Source Control Register n */
2780#define SEC_SCTL35 0xFFCA4918 /* SEC IRQ Source Control Register n */
2781#define SEC_SCTL36 0xFFCA4920 /* SEC IRQ Source Control Register n */
2782#define SEC_SCTL37 0xFFCA4928 /* SEC IRQ Source Control Register n */
2783#define SEC_SCTL38 0xFFCA4930 /* SEC IRQ Source Control Register n */
2784#define SEC_SCTL39 0xFFCA4938 /* SEC IRQ Source Control Register n */
2785#define SEC_SCTL40 0xFFCA4940 /* SEC IRQ Source Control Register n */
2786#define SEC_SCTL41 0xFFCA4948 /* SEC IRQ Source Control Register n */
2787#define SEC_SCTL42 0xFFCA4950 /* SEC IRQ Source Control Register n */
2788#define SEC_SCTL43 0xFFCA4958 /* SEC IRQ Source Control Register n */
2789#define SEC_SCTL44 0xFFCA4960 /* SEC IRQ Source Control Register n */
2790#define SEC_SCTL45 0xFFCA4968 /* SEC IRQ Source Control Register n */
2791#define SEC_SCTL46 0xFFCA4970 /* SEC IRQ Source Control Register n */
2792#define SEC_SCTL47 0xFFCA4978 /* SEC IRQ Source Control Register n */
2793#define SEC_SCTL48 0xFFCA4980 /* SEC IRQ Source Control Register n */
2794#define SEC_SCTL49 0xFFCA4988 /* SEC IRQ Source Control Register n */
2795#define SEC_SCTL50 0xFFCA4990 /* SEC IRQ Source Control Register n */
2796#define SEC_SCTL51 0xFFCA4998 /* SEC IRQ Source Control Register n */
2797#define SEC_SCTL52 0xFFCA49A0 /* SEC IRQ Source Control Register n */
2798#define SEC_SCTL53 0xFFCA49A8 /* SEC IRQ Source Control Register n */
2799#define SEC_SCTL54 0xFFCA49B0 /* SEC IRQ Source Control Register n */
2800#define SEC_SCTL55 0xFFCA49B8 /* SEC IRQ Source Control Register n */
2801#define SEC_SCTL56 0xFFCA49C0 /* SEC IRQ Source Control Register n */
2802#define SEC_SCTL57 0xFFCA49C8 /* SEC IRQ Source Control Register n */
2803#define SEC_SCTL58 0xFFCA49D0 /* SEC IRQ Source Control Register n */
2804#define SEC_SCTL59 0xFFCA49D8 /* SEC IRQ Source Control Register n */
2805#define SEC_SCTL60 0xFFCA49E0 /* SEC IRQ Source Control Register n */
2806#define SEC_SCTL61 0xFFCA49E8 /* SEC IRQ Source Control Register n */
2807#define SEC_SCTL62 0xFFCA49F0 /* SEC IRQ Source Control Register n */
2808#define SEC_SCTL63 0xFFCA49F8 /* SEC IRQ Source Control Register n */
2809#define SEC_SCTL64 0xFFCA4A00 /* SEC IRQ Source Control Register n */
2810#define SEC_SCTL65 0xFFCA4A08 /* SEC IRQ Source Control Register n */
2811#define SEC_SCTL66 0xFFCA4A10 /* SEC IRQ Source Control Register n */
2812#define SEC_SCTL67 0xFFCA4A18 /* SEC IRQ Source Control Register n */
2813#define SEC_SCTL68 0xFFCA4A20 /* SEC IRQ Source Control Register n */
2814#define SEC_SCTL69 0xFFCA4A28 /* SEC IRQ Source Control Register n */
2815#define SEC_SCTL70 0xFFCA4A30 /* SEC IRQ Source Control Register n */
2816#define SEC_SCTL71 0xFFCA4A38 /* SEC IRQ Source Control Register n */
2817#define SEC_SCTL72 0xFFCA4A40 /* SEC IRQ Source Control Register n */
2818#define SEC_SCTL73 0xFFCA4A48 /* SEC IRQ Source Control Register n */
2819#define SEC_SCTL74 0xFFCA4A50 /* SEC IRQ Source Control Register n */
2820#define SEC_SCTL75 0xFFCA4A58 /* SEC IRQ Source Control Register n */
2821#define SEC_SCTL76 0xFFCA4A60 /* SEC IRQ Source Control Register n */
2822#define SEC_SCTL77 0xFFCA4A68 /* SEC IRQ Source Control Register n */
2823#define SEC_SCTL78 0xFFCA4A70 /* SEC IRQ Source Control Register n */
2824#define SEC_SCTL79 0xFFCA4A78 /* SEC IRQ Source Control Register n */
2825#define SEC_SCTL80 0xFFCA4A80 /* SEC IRQ Source Control Register n */
2826#define SEC_SCTL81 0xFFCA4A88 /* SEC IRQ Source Control Register n */
2827#define SEC_SCTL82 0xFFCA4A90 /* SEC IRQ Source Control Register n */
2828#define SEC_SCTL83 0xFFCA4A98 /* SEC IRQ Source Control Register n */
2829#define SEC_SCTL84 0xFFCA4AA0 /* SEC IRQ Source Control Register n */
2830#define SEC_SCTL85 0xFFCA4AA8 /* SEC IRQ Source Control Register n */
2831#define SEC_SCTL86 0xFFCA4AB0 /* SEC IRQ Source Control Register n */
2832#define SEC_SCTL87 0xFFCA4AB8 /* SEC IRQ Source Control Register n */
2833#define SEC_SCTL88 0xFFCA4AC0 /* SEC IRQ Source Control Register n */
2834#define SEC_SCTL89 0xFFCA4AC8 /* SEC IRQ Source Control Register n */
2835#define SEC_SCTL90 0xFFCA4AD0 /* SEC IRQ Source Control Register n */
2836#define SEC_SCTL91 0xFFCA4AD8 /* SEC IRQ Source Control Register n */
2837#define SEC_SCTL92 0xFFCA4AE0 /* SEC IRQ Source Control Register n */
2838#define SEC_SCTL93 0xFFCA4AE8 /* SEC IRQ Source Control Register n */
2839#define SEC_SCTL94 0xFFCA4AF0 /* SEC IRQ Source Control Register n */
2840#define SEC_SCTL95 0xFFCA4AF8 /* SEC IRQ Source Control Register n */
2841#define SEC_SCTL96 0xFFCA4B00 /* SEC IRQ Source Control Register n */
2842#define SEC_SCTL97 0xFFCA4B08 /* SEC IRQ Source Control Register n */
2843#define SEC_SCTL98 0xFFCA4B10 /* SEC IRQ Source Control Register n */
2844#define SEC_SCTL99 0xFFCA4B18 /* SEC IRQ Source Control Register n */
2845#define SEC_SCTL100 0xFFCA4B20 /* SEC IRQ Source Control Register n */
2846#define SEC_SCTL101 0xFFCA4B28 /* SEC IRQ Source Control Register n */
2847#define SEC_SCTL102 0xFFCA4B30 /* SEC IRQ Source Control Register n */
2848#define SEC_SCTL103 0xFFCA4B38 /* SEC IRQ Source Control Register n */
2849#define SEC_SCTL104 0xFFCA4B40 /* SEC IRQ Source Control Register n */
2850#define SEC_SCTL105 0xFFCA4B48 /* SEC IRQ Source Control Register n */
2851#define SEC_SCTL106 0xFFCA4B50 /* SEC IRQ Source Control Register n */
2852#define SEC_SCTL107 0xFFCA4B58 /* SEC IRQ Source Control Register n */
2853#define SEC_SCTL108 0xFFCA4B60 /* SEC IRQ Source Control Register n */
2854#define SEC_SCTL109 0xFFCA4B68 /* SEC IRQ Source Control Register n */
2855#define SEC_SCTL110 0xFFCA4B70 /* SEC IRQ Source Control Register n */
2856#define SEC_SCTL111 0xFFCA4B78 /* SEC IRQ Source Control Register n */
2857#define SEC_SCTL112 0xFFCA4B80 /* SEC IRQ Source Control Register n */
2858#define SEC_SCTL113 0xFFCA4B88 /* SEC IRQ Source Control Register n */
2859#define SEC_SCTL114 0xFFCA4B90 /* SEC IRQ Source Control Register n */
2860#define SEC_SCTL115 0xFFCA4B98 /* SEC IRQ Source Control Register n */
2861#define SEC_SCTL116 0xFFCA4BA0 /* SEC IRQ Source Control Register n */
2862#define SEC_SCTL117 0xFFCA4BA8 /* SEC IRQ Source Control Register n */
2863#define SEC_SCTL118 0xFFCA4BB0 /* SEC IRQ Source Control Register n */
2864#define SEC_SCTL119 0xFFCA4BB8 /* SEC IRQ Source Control Register n */
2865#define SEC_SCTL120 0xFFCA4BC0 /* SEC IRQ Source Control Register n */
2866#define SEC_SCTL121 0xFFCA4BC8 /* SEC IRQ Source Control Register n */
2867#define SEC_SCTL122 0xFFCA4BD0 /* SEC IRQ Source Control Register n */
2868#define SEC_SCTL123 0xFFCA4BD8 /* SEC IRQ Source Control Register n */
2869#define SEC_SCTL124 0xFFCA4BE0 /* SEC IRQ Source Control Register n */
2870#define SEC_SCTL125 0xFFCA4BE8 /* SEC IRQ Source Control Register n */
2871#define SEC_SCTL126 0xFFCA4BF0 /* SEC IRQ Source Control Register n */
2872#define SEC_SCTL127 0xFFCA4BF8 /* SEC IRQ Source Control Register n */
2873#define SEC_SCTL128 0xFFCA4C00 /* SEC IRQ Source Control Register n */
2874#define SEC_SCTL129 0xFFCA4C08 /* SEC IRQ Source Control Register n */
2875#define SEC_SCTL130 0xFFCA4C10 /* SEC IRQ Source Control Register n */
2876#define SEC_SCTL131 0xFFCA4C18 /* SEC IRQ Source Control Register n */
2877#define SEC_SCTL132 0xFFCA4C20 /* SEC IRQ Source Control Register n */
2878#define SEC_SCTL133 0xFFCA4C28 /* SEC IRQ Source Control Register n */
2879#define SEC_SCTL134 0xFFCA4C30 /* SEC IRQ Source Control Register n */
2880#define SEC_SCTL135 0xFFCA4C38 /* SEC IRQ Source Control Register n */
2881#define SEC_SCTL136 0xFFCA4C40 /* SEC IRQ Source Control Register n */
2882#define SEC_SCTL137 0xFFCA4C48 /* SEC IRQ Source Control Register n */
2883#define SEC_SCTL138 0xFFCA4C50 /* SEC IRQ Source Control Register n */
2884#define SEC_SCTL139 0xFFCA4C58 /* SEC IRQ Source Control Register n */
2885#define SEC_SSTAT0 0xFFCA4804 /* SEC IRQ Source Status Register n */
2886#define SEC_SSTAT1 0xFFCA480C /* SEC IRQ Source Status Register n */
2887#define SEC_SSTAT2 0xFFCA4814 /* SEC IRQ Source Status Register n */
2888#define SEC_SSTAT3 0xFFCA481C /* SEC IRQ Source Status Register n */
2889#define SEC_SSTAT4 0xFFCA4824 /* SEC IRQ Source Status Register n */
2890#define SEC_SSTAT5 0xFFCA482C /* SEC IRQ Source Status Register n */
2891#define SEC_SSTAT6 0xFFCA4834 /* SEC IRQ Source Status Register n */
2892#define SEC_SSTAT7 0xFFCA483C /* SEC IRQ Source Status Register n */
2893#define SEC_SSTAT8 0xFFCA4844 /* SEC IRQ Source Status Register n */
2894#define SEC_SSTAT9 0xFFCA484C /* SEC IRQ Source Status Register n */
2895#define SEC_SSTAT10 0xFFCA4854 /* SEC IRQ Source Status Register n */
2896#define SEC_SSTAT11 0xFFCA485C /* SEC IRQ Source Status Register n */
2897#define SEC_SSTAT12 0xFFCA4864 /* SEC IRQ Source Status Register n */
2898#define SEC_SSTAT13 0xFFCA486C /* SEC IRQ Source Status Register n */
2899#define SEC_SSTAT14 0xFFCA4874 /* SEC IRQ Source Status Register n */
2900#define SEC_SSTAT15 0xFFCA487C /* SEC IRQ Source Status Register n */
2901#define SEC_SSTAT16 0xFFCA4884 /* SEC IRQ Source Status Register n */
2902#define SEC_SSTAT17 0xFFCA488C /* SEC IRQ Source Status Register n */
2903#define SEC_SSTAT18 0xFFCA4894 /* SEC IRQ Source Status Register n */
2904#define SEC_SSTAT19 0xFFCA489C /* SEC IRQ Source Status Register n */
2905#define SEC_SSTAT20 0xFFCA48A4 /* SEC IRQ Source Status Register n */
2906#define SEC_SSTAT21 0xFFCA48AC /* SEC IRQ Source Status Register n */
2907#define SEC_SSTAT22 0xFFCA48B4 /* SEC IRQ Source Status Register n */
2908#define SEC_SSTAT23 0xFFCA48BC /* SEC IRQ Source Status Register n */
2909#define SEC_SSTAT24 0xFFCA48C4 /* SEC IRQ Source Status Register n */
2910#define SEC_SSTAT25 0xFFCA48CC /* SEC IRQ Source Status Register n */
2911#define SEC_SSTAT26 0xFFCA48D4 /* SEC IRQ Source Status Register n */
2912#define SEC_SSTAT27 0xFFCA48DC /* SEC IRQ Source Status Register n */
2913#define SEC_SSTAT28 0xFFCA48E4 /* SEC IRQ Source Status Register n */
2914#define SEC_SSTAT29 0xFFCA48EC /* SEC IRQ Source Status Register n */
2915#define SEC_SSTAT30 0xFFCA48F4 /* SEC IRQ Source Status Register n */
2916#define SEC_SSTAT31 0xFFCA48FC /* SEC IRQ Source Status Register n */
2917#define SEC_SSTAT32 0xFFCA4904 /* SEC IRQ Source Status Register n */
2918#define SEC_SSTAT33 0xFFCA490C /* SEC IRQ Source Status Register n */
2919#define SEC_SSTAT34 0xFFCA4914 /* SEC IRQ Source Status Register n */
2920#define SEC_SSTAT35 0xFFCA491C /* SEC IRQ Source Status Register n */
2921#define SEC_SSTAT36 0xFFCA4924 /* SEC IRQ Source Status Register n */
2922#define SEC_SSTAT37 0xFFCA492C /* SEC IRQ Source Status Register n */
2923#define SEC_SSTAT38 0xFFCA4934 /* SEC IRQ Source Status Register n */
2924#define SEC_SSTAT39 0xFFCA493C /* SEC IRQ Source Status Register n */
2925#define SEC_SSTAT40 0xFFCA4944 /* SEC IRQ Source Status Register n */
2926#define SEC_SSTAT41 0xFFCA494C /* SEC IRQ Source Status Register n */
2927#define SEC_SSTAT42 0xFFCA4954 /* SEC IRQ Source Status Register n */
2928#define SEC_SSTAT43 0xFFCA495C /* SEC IRQ Source Status Register n */
2929#define SEC_SSTAT44 0xFFCA4964 /* SEC IRQ Source Status Register n */
2930#define SEC_SSTAT45 0xFFCA496C /* SEC IRQ Source Status Register n */
2931#define SEC_SSTAT46 0xFFCA4974 /* SEC IRQ Source Status Register n */
2932#define SEC_SSTAT47 0xFFCA497C /* SEC IRQ Source Status Register n */
2933#define SEC_SSTAT48 0xFFCA4984 /* SEC IRQ Source Status Register n */
2934#define SEC_SSTAT49 0xFFCA498C /* SEC IRQ Source Status Register n */
2935#define SEC_SSTAT50 0xFFCA4994 /* SEC IRQ Source Status Register n */
2936#define SEC_SSTAT51 0xFFCA499C /* SEC IRQ Source Status Register n */
2937#define SEC_SSTAT52 0xFFCA49A4 /* SEC IRQ Source Status Register n */
2938#define SEC_SSTAT53 0xFFCA49AC /* SEC IRQ Source Status Register n */
2939#define SEC_SSTAT54 0xFFCA49B4 /* SEC IRQ Source Status Register n */
2940#define SEC_SSTAT55 0xFFCA49BC /* SEC IRQ Source Status Register n */
2941#define SEC_SSTAT56 0xFFCA49C4 /* SEC IRQ Source Status Register n */
2942#define SEC_SSTAT57 0xFFCA49CC /* SEC IRQ Source Status Register n */
2943#define SEC_SSTAT58 0xFFCA49D4 /* SEC IRQ Source Status Register n */
2944#define SEC_SSTAT59 0xFFCA49DC /* SEC IRQ Source Status Register n */
2945#define SEC_SSTAT60 0xFFCA49E4 /* SEC IRQ Source Status Register n */
2946#define SEC_SSTAT61 0xFFCA49EC /* SEC IRQ Source Status Register n */
2947#define SEC_SSTAT62 0xFFCA49F4 /* SEC IRQ Source Status Register n */
2948#define SEC_SSTAT63 0xFFCA49FC /* SEC IRQ Source Status Register n */
2949#define SEC_SSTAT64 0xFFCA4A04 /* SEC IRQ Source Status Register n */
2950#define SEC_SSTAT65 0xFFCA4A0C /* SEC IRQ Source Status Register n */
2951#define SEC_SSTAT66 0xFFCA4A14 /* SEC IRQ Source Status Register n */
2952#define SEC_SSTAT67 0xFFCA4A1C /* SEC IRQ Source Status Register n */
2953#define SEC_SSTAT68 0xFFCA4A24 /* SEC IRQ Source Status Register n */
2954#define SEC_SSTAT69 0xFFCA4A2C /* SEC IRQ Source Status Register n */
2955#define SEC_SSTAT70 0xFFCA4A34 /* SEC IRQ Source Status Register n */
2956#define SEC_SSTAT71 0xFFCA4A3C /* SEC IRQ Source Status Register n */
2957#define SEC_SSTAT72 0xFFCA4A44 /* SEC IRQ Source Status Register n */
2958#define SEC_SSTAT73 0xFFCA4A4C /* SEC IRQ Source Status Register n */
2959#define SEC_SSTAT74 0xFFCA4A54 /* SEC IRQ Source Status Register n */
2960#define SEC_SSTAT75 0xFFCA4A5C /* SEC IRQ Source Status Register n */
2961#define SEC_SSTAT76 0xFFCA4A64 /* SEC IRQ Source Status Register n */
2962#define SEC_SSTAT77 0xFFCA4A6C /* SEC IRQ Source Status Register n */
2963#define SEC_SSTAT78 0xFFCA4A74 /* SEC IRQ Source Status Register n */
2964#define SEC_SSTAT79 0xFFCA4A7C /* SEC IRQ Source Status Register n */
2965#define SEC_SSTAT80 0xFFCA4A84 /* SEC IRQ Source Status Register n */
2966#define SEC_SSTAT81 0xFFCA4A8C /* SEC IRQ Source Status Register n */
2967#define SEC_SSTAT82 0xFFCA4A94 /* SEC IRQ Source Status Register n */
2968#define SEC_SSTAT83 0xFFCA4A9C /* SEC IRQ Source Status Register n */
2969#define SEC_SSTAT84 0xFFCA4AA4 /* SEC IRQ Source Status Register n */
2970#define SEC_SSTAT85 0xFFCA4AAC /* SEC IRQ Source Status Register n */
2971#define SEC_SSTAT86 0xFFCA4AB4 /* SEC IRQ Source Status Register n */
2972#define SEC_SSTAT87 0xFFCA4ABC /* SEC IRQ Source Status Register n */
2973#define SEC_SSTAT88 0xFFCA4AC4 /* SEC IRQ Source Status Register n */
2974#define SEC_SSTAT89 0xFFCA4ACC /* SEC IRQ Source Status Register n */
2975#define SEC_SSTAT90 0xFFCA4AD4 /* SEC IRQ Source Status Register n */
2976#define SEC_SSTAT91 0xFFCA4ADC /* SEC IRQ Source Status Register n */
2977#define SEC_SSTAT92 0xFFCA4AE4 /* SEC IRQ Source Status Register n */
2978#define SEC_SSTAT93 0xFFCA4AEC /* SEC IRQ Source Status Register n */
2979#define SEC_SSTAT94 0xFFCA4AF4 /* SEC IRQ Source Status Register n */
2980#define SEC_SSTAT95 0xFFCA4AFC /* SEC IRQ Source Status Register n */
2981#define SEC_SSTAT96 0xFFCA4B04 /* SEC IRQ Source Status Register n */
2982#define SEC_SSTAT97 0xFFCA4B0C /* SEC IRQ Source Status Register n */
2983#define SEC_SSTAT98 0xFFCA4B14 /* SEC IRQ Source Status Register n */
2984#define SEC_SSTAT99 0xFFCA4B1C /* SEC IRQ Source Status Register n */
2985#define SEC_SSTAT100 0xFFCA4B24 /* SEC IRQ Source Status Register n */
2986#define SEC_SSTAT101 0xFFCA4B2C /* SEC IRQ Source Status Register n */
2987#define SEC_SSTAT102 0xFFCA4B34 /* SEC IRQ Source Status Register n */
2988#define SEC_SSTAT103 0xFFCA4B3C /* SEC IRQ Source Status Register n */
2989#define SEC_SSTAT104 0xFFCA4B44 /* SEC IRQ Source Status Register n */
2990#define SEC_SSTAT105 0xFFCA4B4C /* SEC IRQ Source Status Register n */
2991#define SEC_SSTAT106 0xFFCA4B54 /* SEC IRQ Source Status Register n */
2992#define SEC_SSTAT107 0xFFCA4B5C /* SEC IRQ Source Status Register n */
2993#define SEC_SSTAT108 0xFFCA4B64 /* SEC IRQ Source Status Register n */
2994#define SEC_SSTAT109 0xFFCA4B6C /* SEC IRQ Source Status Register n */
2995#define SEC_SSTAT110 0xFFCA4B74 /* SEC IRQ Source Status Register n */
2996#define SEC_SSTAT111 0xFFCA4B7C /* SEC IRQ Source Status Register n */
2997#define SEC_SSTAT112 0xFFCA4B84 /* SEC IRQ Source Status Register n */
2998#define SEC_SSTAT113 0xFFCA4B8C /* SEC IRQ Source Status Register n */
2999#define SEC_SSTAT114 0xFFCA4B94 /* SEC IRQ Source Status Register n */
3000#define SEC_SSTAT115 0xFFCA4B9C /* SEC IRQ Source Status Register n */
3001#define SEC_SSTAT116 0xFFCA4BA4 /* SEC IRQ Source Status Register n */
3002#define SEC_SSTAT117 0xFFCA4BAC /* SEC IRQ Source Status Register n */
3003#define SEC_SSTAT118 0xFFCA4BB4 /* SEC IRQ Source Status Register n */
3004#define SEC_SSTAT119 0xFFCA4BBC /* SEC IRQ Source Status Register n */
3005#define SEC_SSTAT120 0xFFCA4BC4 /* SEC IRQ Source Status Register n */
3006#define SEC_SSTAT121 0xFFCA4BCC /* SEC IRQ Source Status Register n */
3007#define SEC_SSTAT122 0xFFCA4BD4 /* SEC IRQ Source Status Register n */
3008#define SEC_SSTAT123 0xFFCA4BDC /* SEC IRQ Source Status Register n */
3009#define SEC_SSTAT124 0xFFCA4BE4 /* SEC IRQ Source Status Register n */
3010#define SEC_SSTAT125 0xFFCA4BEC /* SEC IRQ Source Status Register n */
3011#define SEC_SSTAT126 0xFFCA4BF4 /* SEC IRQ Source Status Register n */
3012#define SEC_SSTAT127 0xFFCA4BFC /* SEC IRQ Source Status Register n */
3013#define SEC_SSTAT128 0xFFCA4C04 /* SEC IRQ Source Status Register n */
3014#define SEC_SSTAT129 0xFFCA4C0C /* SEC IRQ Source Status Register n */
3015#define SEC_SSTAT130 0xFFCA4C14 /* SEC IRQ Source Status Register n */
3016#define SEC_SSTAT131 0xFFCA4C1C /* SEC IRQ Source Status Register n */
3017#define SEC_SSTAT132 0xFFCA4C24 /* SEC IRQ Source Status Register n */
3018#define SEC_SSTAT133 0xFFCA4C2C /* SEC IRQ Source Status Register n */
3019#define SEC_SSTAT134 0xFFCA4C34 /* SEC IRQ Source Status Register n */
3020#define SEC_SSTAT135 0xFFCA4C3C /* SEC IRQ Source Status Register n */
3021#define SEC_SSTAT136 0xFFCA4C44 /* SEC IRQ Source Status Register n */
3022#define SEC_SSTAT137 0xFFCA4C4C /* SEC IRQ Source Status Register n */
3023#define SEC_SSTAT138 0xFFCA4C54 /* SEC IRQ Source Status Register n */
3024#define SEC_SSTAT139 0xFFCA4C5C /* SEC IRQ Source Status Register n */
3025
3026/* ------------------------------------------------------------------------------------------------------------------------
3027 SEC_CCTL Pos/Masks Description
3028 ------------------------------------------------------------------------------------------------------------------------ */
3029#define SEC_CCTL_LOCK 0x80000000 /* LOCK: Lock */
3030#define SEC_CCTL_NMI_EN 0x00010000 /* NMIEN: Enable */
3031#define SEC_CCTL_WAITIDLE 0x00001000 /* WFI: Wait for Idle */
3032#define SEC_CCTL_RESET 0x00000002 /* RESET: Reset */
3033#define SEC_CCTL_EN 0x00000001 /* EN: Enable */
3034
3035/* ------------------------------------------------------------------------------------------------------------------------
3036 SEC_CSTAT Pos/Masks Description
3037 ------------------------------------------------------------------------------------------------------------------------ */
3038#define SEC_CSTAT_NMI 0x00010000 /* NMI Status */
3039#define SEC_CSTAT_WAITING 0x00001000 /* WFI: Waiting */
3040#define SEC_CSTAT_VALID_SID 0x00000400 /* SIDV: Valid */
3041#define SEC_CSTAT_VALID_ACT 0x00000200 /* ACTV: Valid */
3042#define SEC_CSTAT_VALID_PND 0x00000100 /* PNDV: Valid */
3043#define SEC_CSTAT_ERRC 0x00000030 /* Error Cause */
3044#define SEC_CSTAT_ACKERR 0x00000010 /* ERRC: Acknowledge Error */
3045#define SEC_CSTAT_ERR 0x00000002 /* ERR: Error Occurred */
3046
3047/* ------------------------------------------------------------------------------------------------------------------------
3048 SEC_CPND Pos/Masks Description
3049 ------------------------------------------------------------------------------------------------------------------------ */
3050#define SEC_CPND_PRIO 0x0000FF00 /* Highest Pending IRQ Priority */
3051#define SEC_CPND_SID 0x000000FF /* Highest Pending IRQ Source ID */
3052
3053/* ------------------------------------------------------------------------------------------------------------------------
3054 SEC_CACT Pos/Masks Description
3055 ------------------------------------------------------------------------------------------------------------------------ */
3056#define SEC_CACT_PRIO 0x0000FF00 /* Highest Active IRQ Priority */
3057#define SEC_CACT_SID 0x000000FF /* Highest Active IRQ Source ID */
3058
3059/* ------------------------------------------------------------------------------------------------------------------------
3060 SEC_CPMSK Pos/Masks Description
3061 ------------------------------------------------------------------------------------------------------------------------ */
3062#define SEC_CPMSK_LOCK 0x80000000 /* LOCK: Lock */
3063#define SEC_CPMSK_PRIO 0x000000FF /* IRQ Priority Mask */
3064
3065/* ------------------------------------------------------------------------------------------------------------------------
3066 SEC_CGMSK Pos/Masks Description
3067 ------------------------------------------------------------------------------------------------------------------------ */
3068#define SEC_CGMSK_LOCK 0x80000000 /* LOCK: Lock */
3069#define SEC_CGMSK_MASK 0x00000100 /* UGRP: Mask Ungrouped Sources */
3070#define SEC_CGMSK_GRP 0x0000000F /* Grouped Mask */
3071
3072/* ------------------------------------------------------------------------------------------------------------------------
3073 SEC_CPLVL Pos/Masks Description
3074 ------------------------------------------------------------------------------------------------------------------------ */
3075#define SEC_CPLVL_LOCK 0x80000000 /* LOCK: Lock */
3076#define SEC_CPLVL_PLVL 0x00000007 /* Priority Levels */
3077
3078/* ------------------------------------------------------------------------------------------------------------------------
3079 SEC_CSID Pos/Masks Description
3080 ------------------------------------------------------------------------------------------------------------------------ */
3081#define SEC_CSID_SID 0x000000FF /* Source ID */
3082
3083
3084/* ------------------------------------------------------------------------------------------------------------------------
3085 SEC_FCTL Pos/Masks Description
3086 ------------------------------------------------------------------------------------------------------------------------ */
3087#define SEC_FCTL_LOCK 0x80000000 /* LOCK: Lock */
3088#define SEC_FCTL_FLTPND_MODE 0x00002000 /* TES: Fault Pending Mode */
3089#define SEC_FCTL_COP_MODE 0x00001000 /* CMS: COP Mode */
3090#define SEC_FCTL_FLTIN_EN 0x00000080 /* FIEN: Enable */
3091#define SEC_FCTL_SYSRST_EN 0x00000040 /* SREN: Enable */
3092#define SEC_FCTL_TRGOUT_EN 0x00000020 /* TOEN: Enable */
3093#define SEC_FCTL_FLTOUT_EN 0x00000010 /* FOEN: Enable */
3094#define SEC_FCTL_RESET 0x00000002 /* RESET: Reset */
3095#define SEC_FCTL_EN 0x00000001 /* EN: Enable */
3096
3097/* ------------------------------------------------------------------------------------------------------------------------
3098 SEC_FSTAT Pos/Masks Description
3099 ------------------------------------------------------------------------------------------------------------------------ */
3100#define SEC_FSTAT_NXTFLT 0x00000400 /* NPND: Pending */
3101#define SEC_FSTAT_FLTACT 0x00000200 /* ACT: Active Fault */
3102#define SEC_FSTAT_FLTPND 0x00000100 /* PND: Pending */
3103#define SEC_FSTAT_ERRC 0x00000030 /* Error Cause */
3104#define SEC_FSTAT_ENDERR 0x00000020 /* ERRC: End Error */
3105#define SEC_FSTAT_ERR 0x00000002 /* ERR: Error Occurred */
3106
3107/* ------------------------------------------------------------------------------------------------------------------------
3108 SEC_FSID Pos/Masks Description
3109 ------------------------------------------------------------------------------------------------------------------------ */
3110#define SEC_FSID_SRC_EXTFLT 0x00010000 /* FEXT: Fault External */
3111#define SEC_FSID_SID 0x000000FF /* Source ID */
3112
3113/* ------------------------------------------------------------------------------------------------------------------------
3114 SEC_FEND Pos/Masks Description
3115 ------------------------------------------------------------------------------------------------------------------------ */
3116#define SEC_FEND_END_EXTFLT 0x00010000 /* FEXT: Fault External */
3117#define SEC_FEND_SID 0x000000FF /* Source ID */
3118
3119
3120/* ------------------------------------------------------------------------------------------------------------------------
3121 SEC_GCTL Pos/Masks Description
3122 ------------------------------------------------------------------------------------------------------------------------ */
3123#define SEC_GCTL_LOCK 0x80000000 /* Lock */
3124#define SEC_GCTL_RESET 0x00000002 /* Reset */
3125#define SEC_GCTL_EN 0x00000001 /* Enable */
3126
3127/* ------------------------------------------------------------------------------------------------------------------------
3128 SEC_GSTAT Pos/Masks Description
3129 ------------------------------------------------------------------------------------------------------------------------ */
3130#define SEC_GSTAT_LWERR 0x80000000 /* LWERR: Error Occurred */
3131#define SEC_GSTAT_ADRERR 0x40000000 /* ADRERR: Error Occurred */
3132#define SEC_GSTAT_SID 0x00FF0000 /* Source ID for SSI Error */
3133#define SEC_GSTAT_SCI 0x00000F00 /* SCI ID for SCI Error */
3134#define SEC_GSTAT_ERRC 0x00000030 /* Error Cause */
3135#define SEC_GSTAT_SCIERR 0x00000010 /* ERRC: SCI Error */
3136#define SEC_GSTAT_SSIERR 0x00000020 /* ERRC: SSI Error */
3137#define SEC_GSTAT_ERR 0x00000002 /* ERR: Error Occurred */
3138
3139/* ------------------------------------------------------------------------------------------------------------------------
3140 SEC_RAISE Pos/Masks Description
3141 ------------------------------------------------------------------------------------------------------------------------ */
3142#define SEC_RAISE_SID 0x000000FF /* Source ID IRQ Set to Pending */
3143
3144/* ------------------------------------------------------------------------------------------------------------------------
3145 SEC_END Pos/Masks Description
3146 ------------------------------------------------------------------------------------------------------------------------ */
3147#define SEC_END_SID 0x000000FF /* Source ID IRQ to End */
3148
3149
3150/* ------------------------------------------------------------------------------------------------------------------------
3151 SEC_SCTL Pos/Masks Description
3152 ------------------------------------------------------------------------------------------------------------------------ */
3153#define SEC_SCTL_LOCK 0x80000000 /* Lock */
3154#define SEC_SCTL_CTG 0x0F000000 /* Core Target Select */
3155#define SEC_SCTL_GRP 0x000F0000 /* Group Select */
3156#define SEC_SCTL_PRIO 0x0000FF00 /* Priority Level Select */
3157#define SEC_SCTL_ERR_EN 0x00000010 /* ERREN: Enable */
3158#define SEC_SCTL_EDGE 0x00000008 /* ES: Edge Sensitive */
3159#define SEC_SCTL_SRC_EN 0x00000004 /* SEN: Enable */
3160#define SEC_SCTL_FAULT_EN 0x00000002 /* FEN: Enable */
3161#define SEC_SCTL_INT_EN 0x00000001 /* IEN: Enable */
3162
3163/* ------------------------------------------------------------------------------------------------------------------------
3164 SEC_SSTAT Pos/Masks Description
3165 ------------------------------------------------------------------------------------------------------------------------ */
3166#define SEC_SSTAT_CHID 0x00FF0000 /* Channel ID */
3167#define SEC_SSTAT_ACTIVE_SRC 0x00000200 /* ACT: Active Source */
3168#define SEC_SSTAT_PENDING 0x00000100 /* PND: Pending */
3169#define SEC_SSTAT_ERRC 0x00000030 /* Error Cause */
3170#define SEC_SSTAT_ENDERR 0x00000020 /* ERRC: End Error */
3171#define SEC_SSTAT_ERR 0x00000002 /* Error */
3172
3173
3174/* =========================
3175 RCU Registers
3176 ========================= */
3177
3178/* =========================
3179 RCU0
3180 ========================= */
3181#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
3182#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
3183#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
3184#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
3185#define RCU0_SIDIS 0xFFCA6010 /* RCU0 System Interface Disable Register */
3186#define RCU0_SISTAT 0xFFCA6014 /* RCU0 System Interface Status Register */
3187#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
3188#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
3189#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
3190#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
3191
3192
3193/* =========================
3194 CGU0
3195 ========================= */
3196#define CGU0_CTL 0xFFCA8000 /* CGU0 Control Register */
3197#define CGU0_STAT 0xFFCA8004 /* CGU0 Status Register */
3198#define CGU0_DIV 0xFFCA8008 /* CGU0 Divisor Register */
3199#define CGU0_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
3200
3201
3202/* =========================
3203 DPM Registers
3204 ========================= */
3205
3206/* =========================
3207 DPM0
3208 ========================= */
3209#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
3210#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
3211#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable Register */
3212#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable Register */
3213#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status Register */
3214#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Status Sticky Register */
3215#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable Register */
3216#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
3217#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
3218#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
3219#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
3220#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
3221#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */
3222#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */
3223#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */
3224#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */
3225#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */
3226#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */
3227#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */
3228#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */
3229#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */
3230#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */
3231#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */
3232#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */
3233#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */
3234#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */
3235#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */
3236#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */
3237
3238
3239/* =========================
3240 DBG Registers
3241 ========================= */
3242
3243/* USB register */
3244#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode */
3245#define USB_POWER 0xFFCC1001 /* USB Power and Device Control */
3246#define USB_INTRTX 0xFFCC1002 /* USB Transmit Interrupt */
3247#define USB_INTRRX 0xFFCC1004 /* USB Receive Interrupts */
3248#define USB_INTRTXE 0xFFCC1006 /* USB Transmit Interrupt Enable */
3249#define USB_INTRRXE 0xFFCC1008 /* USB Receive Interrupt Enable */
3250#define USB_INTRUSB 0xFFCC100A /* USB USB Interrupts */
3251#define USB_INTRUSBE 0xFFCC100B /* USB USB Interrupt Enable */
3252#define USB_FRAME 0xFFCC100C /* USB Frame Number */
3253#define USB_INDEX 0xFFCC100E /* USB Index */
3254#define USB_TESTMODE 0xFFCC100F /* USB Testmodes */
3255#define USB_EPI_TXMAXP0 0xFFCC1010 /* USB Transmit Maximum Packet Length */
3256#define USB_EP_NI0_TXMAXP 0xFFCC1010
3257#define USB_EP0I_CSR0_H 0xFFCC1012 /* USB Config and Status EP0 */
3258#define USB_EPI_TXCSR0_H 0xFFCC1012 /* USB Transmit Configuration and Status */
3259#define USB_EP0I_CSR0_P 0xFFCC1012 /* USB Config and Status EP0 */
3260#define USB_EPI_TXCSR0_P 0xFFCC1012 /* USB Transmit Configuration and Status */
3261#define USB_EPI_RXMAXP0 0xFFCC1014 /* USB Receive Maximum Packet Length */
3262#define USB_EPI_RXCSR0_H 0xFFCC1016 /* USB Receive Configuration and Status Register */
3263#define USB_EPI_RXCSR0_P 0xFFCC1016 /* USB Receive Configuration and Status Register */
3264#define USB_EP0I_CNT0 0xFFCC1018 /* USB Number of Received Bytes for Endpoint 0 */
3265#define USB_EPI_RXCNT0 0xFFCC1018 /* USB Number of Byte Received */
3266#define USB_EP0I_TYPE0 0xFFCC101A /* USB Speed for Endpoint 0 */
3267#define USB_EPI_TXTYPE0 0xFFCC101A /* USB Transmit Type */
3268#define USB_EP0I_NAKLIMIT0 0xFFCC101B /* USB NAK Response Timeout for Endpoint 0 */
3269#define USB_EPI_TXINTERVAL0 0xFFCC101B /* USB Transmit Polling Interval */
3270#define USB_EPI_RXTYPE0 0xFFCC101C /* USB Receive Type */
3271#define USB_EPI_RXINTERVAL0 0xFFCC101D /* USB Receive Polling Interval */
3272#define USB_EP0I_CFGDATA0 0xFFCC101F /* USB Configuration Information */
3273#define USB_FIFOB0 0xFFCC1020 /* USB FIFO Data */
3274#define USB_FIFOB1 0xFFCC1024 /* USB FIFO Data */
3275#define USB_FIFOB2 0xFFCC1028 /* USB FIFO Data */
3276#define USB_FIFOB3 0xFFCC102C /* USB FIFO Data */
3277#define USB_FIFOB4 0xFFCC1030 /* USB FIFO Data */
3278#define USB_FIFOB5 0xFFCC1034 /* USB FIFO Data */
3279#define USB_FIFOB6 0xFFCC1038 /* USB FIFO Data */
3280#define USB_FIFOB7 0xFFCC103C /* USB FIFO Data */
3281#define USB_FIFOB8 0xFFCC1040 /* USB FIFO Data */
3282#define USB_FIFOB9 0xFFCC1044 /* USB FIFO Data */
3283#define USB_FIFOB10 0xFFCC1048 /* USB FIFO Data */
3284#define USB_FIFOB11 0xFFCC104C /* USB FIFO Data */
3285#define USB_FIFOH0 0xFFCC1020 /* USB FIFO Data */
3286#define USB_FIFOH1 0xFFCC1024 /* USB FIFO Data */
3287#define USB_FIFOH2 0xFFCC1028 /* USB FIFO Data */
3288#define USB_FIFOH3 0xFFCC102C /* USB FIFO Data */
3289#define USB_FIFOH4 0xFFCC1030 /* USB FIFO Data */
3290#define USB_FIFOH5 0xFFCC1034 /* USB FIFO Data */
3291#define USB_FIFOH6 0xFFCC1038 /* USB FIFO Data */
3292#define USB_FIFOH7 0xFFCC103C /* USB FIFO Data */
3293#define USB_FIFOH8 0xFFCC1040 /* USB FIFO Data */
3294#define USB_FIFOH9 0xFFCC1044 /* USB FIFO Data */
3295#define USB_FIFOH10 0xFFCC1048 /* USB FIFO Data */
3296#define USB_FIFOH11 0xFFCC104C /* USB FIFO Data */
3297#define USB_FIFO0 0xFFCC1020 /* USB FIFO Data */
3298#define USB_EP0_FIFO 0xFFCC1020
3299#define USB_FIFO1 0xFFCC1024 /* USB FIFO Data */
3300#define USB_FIFO2 0xFFCC1028 /* USB FIFO Data */
3301#define USB_FIFO3 0xFFCC102C /* USB FIFO Data */
3302#define USB_FIFO4 0xFFCC1030 /* USB FIFO Data */
3303#define USB_FIFO5 0xFFCC1034 /* USB FIFO Data */
3304#define USB_FIFO6 0xFFCC1038 /* USB FIFO Data */
3305#define USB_FIFO7 0xFFCC103C /* USB FIFO Data */
3306#define USB_FIFO8 0xFFCC1040 /* USB FIFO Data */
3307#define USB_FIFO9 0xFFCC1044 /* USB FIFO Data */
3308#define USB_FIFO10 0xFFCC1048 /* USB FIFO Data */
3309#define USB_FIFO11 0xFFCC104C /* USB FIFO Data */
3310#define USB_OTG_DEV_CTL 0xFFCC1060 /* USB Device Control */
3311#define USB_TXFIFOSZ 0xFFCC1062 /* USB Transmit FIFO Size */
3312#define USB_RXFIFOSZ 0xFFCC1063 /* USB Receive FIFO Size */
3313#define USB_TXFIFOADDR 0xFFCC1064 /* USB Transmit FIFO Address */
3314#define USB_RXFIFOADDR 0xFFCC1066 /* USB Receive FIFO Address */
3315#define USB_VENDSTAT 0xFFCC1068 /* USB Vendor Status */
3316#define USB_HWVERS 0xFFCC106C /* USB Hardware Version */
3317#define USB_EPINFO 0xFFCC1078 /* USB Endpoint Info */
3318#define USB_RAMINFO 0xFFCC1079 /* USB Ram Information */
3319#define USB_LINKINFO 0xFFCC107A /* USB Programmable Delay Values */
3320#define USB_VPLEN 0xFFCC107B /* USB VBus Pulse Duration */
3321#define USB_HS_EOF1 0xFFCC107C /* USB High Speed End of Frame Remaining */
3322#define USB_FS_EOF1 0xFFCC107D /* USB Full Speed End of Frame Remaining */
3323#define USB_LS_EOF1 0xFFCC107E /* USB Low Speed End of Frame Remaining */
3324#define USB_SOFT_RST 0xFFCC107F /* USB Software Reset */
3325#define USB_TXFUNCADDR0 0xFFCC1080 /* USB Transmit Function Address */
3326#define USB_TXFUNCADDR1 0xFFCC1088 /* USB Transmit Function Address */
3327#define USB_TXFUNCADDR2 0xFFCC1090 /* USB Transmit Function Address */
3328#define USB_TXFUNCADDR3 0xFFCC1098 /* USB Transmit Function Address */
3329#define USB_TXFUNCADDR4 0xFFCC10A0 /* USB Transmit Function Address */
3330#define USB_TXFUNCADDR5 0xFFCC10A8 /* USB Transmit Function Address */
3331#define USB_TXFUNCADDR6 0xFFCC10B0 /* USB Transmit Function Address */
3332#define USB_TXFUNCADDR7 0xFFCC10B8 /* USB Transmit Function Address */
3333#define USB_TXFUNCADDR8 0xFFCC10C0 /* USB Transmit Function Address */
3334#define USB_TXFUNCADDR9 0xFFCC10C8 /* USB Transmit Function Address */
3335#define USB_TXFUNCADDR10 0xFFCC10D0 /* USB Transmit Function Address */
3336#define USB_TXFUNCADDR11 0xFFCC10D8 /* USB Transmit Function Address */
3337#define USB_TXHUBADDR0 0xFFCC1082 /* USB Transmit Hub Address */
3338#define USB_TXHUBADDR1 0xFFCC108A /* USB Transmit Hub Address */
3339#define USB_TXHUBADDR2 0xFFCC1092 /* USB Transmit Hub Address */
3340#define USB_TXHUBADDR3 0xFFCC109A /* USB Transmit Hub Address */
3341#define USB_TXHUBADDR4 0xFFCC10A2 /* USB Transmit Hub Address */
3342#define USB_TXHUBADDR5 0xFFCC10AA /* USB Transmit Hub Address */
3343#define USB_TXHUBADDR6 0xFFCC10B2 /* USB Transmit Hub Address */
3344#define USB_TXHUBADDR7 0xFFCC10BA /* USB Transmit Hub Address */
3345#define USB_TXHUBADDR8 0xFFCC10C2 /* USB Transmit Hub Address */
3346#define USB_TXHUBADDR9 0xFFCC10CA /* USB Transmit Hub Address */
3347#define USB_TXHUBADDR10 0xFFCC10D2 /* USB Transmit Hub Address */
3348#define USB_TXHUBADDR11 0xFFCC10DA /* USB Transmit Hub Address */
3349#define USB_TXHUBPORT0 0xFFCC1083 /* USB Transmit Hub Port */
3350#define USB_TXHUBPORT1 0xFFCC108B /* USB Transmit Hub Port */
3351#define USB_TXHUBPORT2 0xFFCC1093 /* USB Transmit Hub Port */
3352#define USB_TXHUBPORT3 0xFFCC109B /* USB Transmit Hub Port */
3353#define USB_TXHUBPORT4 0xFFCC10A3 /* USB Transmit Hub Port */
3354#define USB_TXHUBPORT5 0xFFCC10AB /* USB Transmit Hub Port */
3355#define USB_TXHUBPORT6 0xFFCC10B3 /* USB Transmit Hub Port */
3356#define USB_TXHUBPORT7 0xFFCC10BB /* USB Transmit Hub Port */
3357#define USB_TXHUBPORT8 0xFFCC10C3 /* USB Transmit Hub Port */
3358#define USB_TXHUBPORT9 0xFFCC10CB /* USB Transmit Hub Port */
3359#define USB_TXHUBPORT10 0xFFCC10D3 /* USB Transmit Hub Port */
3360#define USB_TXHUBPORT11 0xFFCC10DB /* USB Transmit Hub Port */
3361#define USB_RXFUNCADDR0 0xFFCC1084 /* USB Receive Function Address */
3362#define USB_RXFUNCADDR1 0xFFCC108C /* USB Receive Function Address */
3363#define USB_RXFUNCADDR2 0xFFCC1094 /* USB Receive Function Address */
3364#define USB_RXFUNCADDR3 0xFFCC109C /* USB Receive Function Address */
3365#define USB_RXFUNCADDR4 0xFFCC10A4 /* USB Receive Function Address */
3366#define USB_RXFUNCADDR5 0xFFCC10AC /* USB Receive Function Address */
3367#define USB_RXFUNCADDR6 0xFFCC10B4 /* USB Receive Function Address */
3368#define USB_RXFUNCADDR7 0xFFCC10BC /* USB Receive Function Address */
3369#define USB_RXFUNCADDR8 0xFFCC10C4 /* USB Receive Function Address */
3370#define USB_RXFUNCADDR9 0xFFCC10CC /* USB Receive Function Address */
3371#define USB_RXFUNCADDR10 0xFFCC10D4 /* USB Receive Function Address */
3372#define USB_RXFUNCADDR11 0xFFCC10DC /* USB Receive Function Address */
3373#define USB_RXHUBADDR0 0xFFCC1086 /* USB Receive Hub Address */
3374#define USB_RXHUBADDR1 0xFFCC108E /* USB Receive Hub Address */
3375#define USB_RXHUBADDR2 0xFFCC1096 /* USB Receive Hub Address */
3376#define USB_RXHUBADDR3 0xFFCC109E /* USB Receive Hub Address */
3377#define USB_RXHUBADDR4 0xFFCC10A6 /* USB Receive Hub Address */
3378#define USB_RXHUBADDR5 0xFFCC10AE /* USB Receive Hub Address */
3379#define USB_RXHUBADDR6 0xFFCC10B6 /* USB Receive Hub Address */
3380#define USB_RXHUBADDR7 0xFFCC10BE /* USB Receive Hub Address */
3381#define USB_RXHUBADDR8 0xFFCC10C6 /* USB Receive Hub Address */
3382#define USB_RXHUBADDR9 0xFFCC10CE /* USB Receive Hub Address */
3383#define USB_RXHUBADDR10 0xFFCC10D6 /* USB Receive Hub Address */
3384#define USB_RXHUBADDR11 0xFFCC10DE /* USB Receive Hub Address */
3385#define USB_RXHUBPORT0 0xFFCC1087 /* USB Receive Hub Port */
3386#define USB_RXHUBPORT1 0xFFCC108F /* USB Receive Hub Port */
3387#define USB_RXHUBPORT2 0xFFCC1097 /* USB Receive Hub Port */
3388#define USB_RXHUBPORT3 0xFFCC109F /* USB Receive Hub Port */
3389#define USB_RXHUBPORT4 0xFFCC10A7 /* USB Receive Hub Port */
3390#define USB_RXHUBPORT5 0xFFCC10AF /* USB Receive Hub Port */
3391#define USB_RXHUBPORT6 0xFFCC10B7 /* USB Receive Hub Port */
3392#define USB_RXHUBPORT7 0xFFCC10BF /* USB Receive Hub Port */
3393#define USB_RXHUBPORT8 0xFFCC10C7 /* USB Receive Hub Port */
3394#define USB_RXHUBPORT9 0xFFCC10CF /* USB Receive Hub Port */
3395#define USB_RXHUBPORT10 0xFFCC10D7 /* USB Receive Hub Port */
3396#define USB_RXHUBPORT11 0xFFCC10DF /* USB Receive Hub Port */
3397#define USB_EP0_CSR0_H 0xFFCC1102 /* USB Config and Status EP0 */
3398#define USB_EP0_CSR0_P 0xFFCC1102 /* USB Config and Status EP0 */
3399#define USB_EP0_CNT0 0xFFCC1108 /* USB Number of Received Bytes for Endpoint 0 */
3400#define USB_EP0_TYPE0 0xFFCC110A /* USB Speed for Endpoint 0 */
3401#define USB_EP0_NAKLIMIT0 0xFFCC110B /* USB NAK Response Timeout for Endpoint 0 */
3402#define USB_EP0_CFGDATA0 0xFFCC110F /* USB Configuration Information */
3403#define USB_EP_TXMAXP0 0xFFCC1110 /* USB Transmit Maximum Packet Length */
3404#define USB_EP_TXMAXP1 0xFFCC1120 /* USB Transmit Maximum Packet Length */
3405#define USB_EP_TXMAXP2 0xFFCC1130 /* USB Transmit Maximum Packet Length */
3406#define USB_EP_TXMAXP3 0xFFCC1140 /* USB Transmit Maximum Packet Length */
3407#define USB_EP_TXMAXP4 0xFFCC1150 /* USB Transmit Maximum Packet Length */
3408#define USB_EP_TXMAXP5 0xFFCC1160 /* USB Transmit Maximum Packet Length */
3409#define USB_EP_TXMAXP6 0xFFCC1170 /* USB Transmit Maximum Packet Length */
3410#define USB_EP_TXMAXP7 0xFFCC1180 /* USB Transmit Maximum Packet Length */
3411#define USB_EP_TXMAXP8 0xFFCC1190 /* USB Transmit Maximum Packet Length */
3412#define USB_EP_TXMAXP9 0xFFCC11A0 /* USB Transmit Maximum Packet Length */
3413#define USB_EP_TXMAXP10 0xFFCC11B0 /* USB Transmit Maximum Packet Length */
3414#define USB_EP_TXCSR0_H 0xFFCC1112 /* USB Transmit Configuration and Status */
3415#define USB_EP_TXCSR1_H 0xFFCC1122 /* USB Transmit Configuration and Status */
3416#define USB_EP_TXCSR2_H 0xFFCC1132 /* USB Transmit Configuration and Status */
3417#define USB_EP_TXCSR3_H 0xFFCC1142 /* USB Transmit Configuration and Status */
3418#define USB_EP_TXCSR4_H 0xFFCC1152 /* USB Transmit Configuration and Status */
3419#define USB_EP_TXCSR5_H 0xFFCC1162 /* USB Transmit Configuration and Status */
3420#define USB_EP_TXCSR6_H 0xFFCC1172 /* USB Transmit Configuration and Status */
3421#define USB_EP_TXCSR7_H 0xFFCC1182 /* USB Transmit Configuration and Status */
3422#define USB_EP_TXCSR8_H 0xFFCC1192 /* USB Transmit Configuration and Status */
3423#define USB_EP_TXCSR9_H 0xFFCC11A2 /* USB Transmit Configuration and Status */
3424#define USB_EP_TXCSR10_H 0xFFCC11B2 /* USB Transmit Configuration and Status */
3425#define USB_EP_TXCSR0_P 0xFFCC1112 /* USB Transmit Configuration and Status */
3426#define USB_EP_TXCSR1_P 0xFFCC1122 /* USB Transmit Configuration and Status */
3427#define USB_EP_TXCSR2_P 0xFFCC1132 /* USB Transmit Configuration and Status */
3428#define USB_EP_TXCSR3_P 0xFFCC1142 /* USB Transmit Configuration and Status */
3429#define USB_EP_TXCSR4_P 0xFFCC1152 /* USB Transmit Configuration and Status */
3430#define USB_EP_TXCSR5_P 0xFFCC1162 /* USB Transmit Configuration and Status */
3431#define USB_EP_TXCSR6_P 0xFFCC1172 /* USB Transmit Configuration and Status */
3432#define USB_EP_TXCSR7_P 0xFFCC1182 /* USB Transmit Configuration and Status */
3433#define USB_EP_TXCSR8_P 0xFFCC1192 /* USB Transmit Configuration and Status */
3434#define USB_EP_TXCSR9_P 0xFFCC11A2 /* USB Transmit Configuration and Status */
3435#define USB_EP_TXCSR10_P 0xFFCC11B2 /* USB Transmit Configuration and Status */
3436#define USB_EP_RXMAXP0 0xFFCC1114 /* USB Receive Maximum Packet Length */
3437#define USB_EP_RXMAXP1 0xFFCC1124 /* USB Receive Maximum Packet Length */
3438#define USB_EP_RXMAXP2 0xFFCC1134 /* USB Receive Maximum Packet Length */
3439#define USB_EP_RXMAXP3 0xFFCC1144 /* USB Receive Maximum Packet Length */
3440#define USB_EP_RXMAXP4 0xFFCC1154 /* USB Receive Maximum Packet Length */
3441#define USB_EP_RXMAXP5 0xFFCC1164 /* USB Receive Maximum Packet Length */
3442#define USB_EP_RXMAXP6 0xFFCC1174 /* USB Receive Maximum Packet Length */
3443#define USB_EP_RXMAXP7 0xFFCC1184 /* USB Receive Maximum Packet Length */
3444#define USB_EP_RXMAXP8 0xFFCC1194 /* USB Receive Maximum Packet Length */
3445#define USB_EP_RXMAXP9 0xFFCC11A4 /* USB Receive Maximum Packet Length */
3446#define USB_EP_RXMAXP10 0xFFCC11B4 /* USB Receive Maximum Packet Length */
3447#define USB_EP_RXCSR0_H 0xFFCC1116 /* USB Receive Configuration and Status Register */
3448#define USB_EP_RXCSR1_H 0xFFCC1126 /* USB Receive Configuration and Status Register */
3449#define USB_EP_RXCSR2_H 0xFFCC1136 /* USB Receive Configuration and Status Register */
3450#define USB_EP_RXCSR3_H 0xFFCC1146 /* USB Receive Configuration and Status Register */
3451#define USB_EP_RXCSR4_H 0xFFCC1156 /* USB Receive Configuration and Status Register */
3452#define USB_EP_RXCSR5_H 0xFFCC1166 /* USB Receive Configuration and Status Register */
3453#define USB_EP_RXCSR6_H 0xFFCC1176 /* USB Receive Configuration and Status Register */
3454#define USB_EP_RXCSR7_H 0xFFCC1186 /* USB Receive Configuration and Status Register */
3455#define USB_EP_RXCSR8_H 0xFFCC1196 /* USB Receive Configuration and Status Register */
3456#define USB_EP_RXCSR9_H 0xFFCC11A6 /* USB Receive Configuration and Status Register */
3457#define USB_EP_RXCSR10_H 0xFFCC11B6 /* USB Receive Configuration and Status Register */
3458#define USB_EP_RXCSR0_P 0xFFCC1116 /* USB Receive Configuration and Status Register */
3459#define USB_EP_RXCSR1_P 0xFFCC1126 /* USB Receive Configuration and Status Register */
3460#define USB_EP_RXCSR2_P 0xFFCC1136 /* USB Receive Configuration and Status Register */
3461#define USB_EP_RXCSR3_P 0xFFCC1146 /* USB Receive Configuration and Status Register */
3462#define USB_EP_RXCSR4_P 0xFFCC1156 /* USB Receive Configuration and Status Register */
3463#define USB_EP_RXCSR5_P 0xFFCC1166 /* USB Receive Configuration and Status Register */
3464#define USB_EP_RXCSR6_P 0xFFCC1176 /* USB Receive Configuration and Status Register */
3465#define USB_EP_RXCSR7_P 0xFFCC1186 /* USB Receive Configuration and Status Register */
3466#define USB_EP_RXCSR8_P 0xFFCC1196 /* USB Receive Configuration and Status Register */
3467#define USB_EP_RXCSR9_P 0xFFCC11A6 /* USB Receive Configuration and Status Register */
3468#define USB_EP_RXCSR10_P 0xFFCC11B6 /* USB Receive Configuration and Status Register */
3469#define USB_EP_RXCNT0 0xFFCC1118 /* USB Number of Byte Received */
3470#define USB_EP_RXCNT1 0xFFCC1128 /* USB Number of Byte Received */
3471#define USB_EP_RXCNT2 0xFFCC1138 /* USB Number of Byte Received */
3472#define USB_EP_RXCNT3 0xFFCC1148 /* USB Number of Byte Received */
3473#define USB_EP_RXCNT4 0xFFCC1158 /* USB Number of Byte Received */
3474#define USB_EP_RXCNT5 0xFFCC1168 /* USB Number of Byte Received */
3475#define USB_EP_RXCNT6 0xFFCC1178 /* USB Number of Byte Received */
3476#define USB_EP_RXCNT7 0xFFCC1188 /* USB Number of Byte Received */
3477#define USB_EP_RXCNT8 0xFFCC1198 /* USB Number of Byte Received */
3478#define USB_EP_RXCNT9 0xFFCC11A8 /* USB Number of Byte Received */
3479#define USB_EP_RXCNT10 0xFFCC11B8 /* USB Number of Byte Received */
3480#define USB_EP_TXTYPE0 0xFFCC111A /* USB Transmit Type */
3481#define USB_EP_TXTYPE1 0xFFCC112A /* USB Transmit Type */
3482#define USB_EP_TXTYPE2 0xFFCC113A /* USB Transmit Type */
3483#define USB_EP_TXTYPE3 0xFFCC114A /* USB Transmit Type */
3484#define USB_EP_TXTYPE4 0xFFCC115A /* USB Transmit Type */
3485#define USB_EP_TXTYPE5 0xFFCC116A /* USB Transmit Type */
3486#define USB_EP_TXTYPE6 0xFFCC117A /* USB Transmit Type */
3487#define USB_EP_TXTYPE7 0xFFCC118A /* USB Transmit Type */
3488#define USB_EP_TXTYPE8 0xFFCC119A /* USB Transmit Type */
3489#define USB_EP_TXTYPE9 0xFFCC11AA /* USB Transmit Type */
3490#define USB_EP_TXTYPE10 0xFFCC11BA /* USB Transmit Type */
3491#define USB_EP_TXINTERVAL0 0xFFCC111B /* USB Transmit Polling Interval */
3492#define USB_EP_TXINTERVAL1 0xFFCC112B /* USB Transmit Polling Interval */
3493#define USB_EP_TXINTERVAL2 0xFFCC113B /* USB Transmit Polling Interval */
3494#define USB_EP_TXINTERVAL3 0xFFCC114B /* USB Transmit Polling Interval */
3495#define USB_EP_TXINTERVAL4 0xFFCC115B /* USB Transmit Polling Interval */
3496#define USB_EP_TXINTERVAL5 0xFFCC116B /* USB Transmit Polling Interval */
3497#define USB_EP_TXINTERVAL6 0xFFCC117B /* USB Transmit Polling Interval */
3498#define USB_EP_TXINTERVAL7 0xFFCC118B /* USB Transmit Polling Interval */
3499#define USB_EP_TXINTERVAL8 0xFFCC119B /* USB Transmit Polling Interval */
3500#define USB_EP_TXINTERVAL9 0xFFCC11AB /* USB Transmit Polling Interval */
3501#define USB_EP_TXINTERVAL10 0xFFCC11BB /* USB Transmit Polling Interval */
3502#define USB_EP_RXTYPE0 0xFFCC111C /* USB Receive Type */
3503#define USB_EP_RXTYPE1 0xFFCC112C /* USB Receive Type */
3504#define USB_EP_RXTYPE2 0xFFCC113C /* USB Receive Type */
3505#define USB_EP_RXTYPE3 0xFFCC114C /* USB Receive Type */
3506#define USB_EP_RXTYPE4 0xFFCC115C /* USB Receive Type */
3507#define USB_EP_RXTYPE5 0xFFCC116C /* USB Receive Type */
3508#define USB_EP_RXTYPE6 0xFFCC117C /* USB Receive Type */
3509#define USB_EP_RXTYPE7 0xFFCC118C /* USB Receive Type */
3510#define USB_EP_RXTYPE8 0xFFCC119C /* USB Receive Type */
3511#define USB_EP_RXTYPE9 0xFFCC11AC /* USB Receive Type */
3512#define USB_EP_RXTYPE10 0xFFCC11BC /* USB Receive Type */
3513#define USB_EP_RXINTERVAL0 0xFFCC111D /* USB Receive Polling Interval */
3514#define USB_EP_RXINTERVAL1 0xFFCC112D /* USB Receive Polling Interval */
3515#define USB_EP_RXINTERVAL2 0xFFCC113D /* USB Receive Polling Interval */
3516#define USB_EP_RXINTERVAL3 0xFFCC114D /* USB Receive Polling Interval */
3517#define USB_EP_RXINTERVAL4 0xFFCC115D /* USB Receive Polling Interval */
3518#define USB_EP_RXINTERVAL5 0xFFCC116D /* USB Receive Polling Interval */
3519#define USB_EP_RXINTERVAL6 0xFFCC117D /* USB Receive Polling Interval */
3520#define USB_EP_RXINTERVAL7 0xFFCC118D /* USB Receive Polling Interval */
3521#define USB_EP_RXINTERVAL8 0xFFCC119D /* USB Receive Polling Interval */
3522#define USB_EP_RXINTERVAL9 0xFFCC11AD /* USB Receive Polling Interval */
3523#define USB_EP_RXINTERVAL10 0xFFCC11BD /* USB Receive Polling Interval */
3524#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */
3525#define USB_DMA_CTL0 0xFFCC1204 /* USB DMA Control */
3526#define USB_DMA_CTL1 0xFFCC1214 /* USB DMA Control */
3527#define USB_DMA_CTL2 0xFFCC1224 /* USB DMA Control */
3528#define USB_DMA_CTL3 0xFFCC1234 /* USB DMA Control */
3529#define USB_DMA_CTL4 0xFFCC1244 /* USB DMA Control */
3530#define USB_DMA_CTL5 0xFFCC1254 /* USB DMA Control */
3531#define USB_DMA_CTL6 0xFFCC1264 /* USB DMA Control */
3532#define USB_DMA_CTL7 0xFFCC1274 /* USB DMA Control */
3533#define USB_DMA_ADDR0 0xFFCC1208 /* USB DMA Address */
3534#define USB_DMA_ADDR1 0xFFCC1218 /* USB DMA Address */
3535#define USB_DMA_ADDR2 0xFFCC1228 /* USB DMA Address */
3536#define USB_DMA_ADDR3 0xFFCC1238 /* USB DMA Address */
3537#define USB_DMA_ADDR4 0xFFCC1248 /* USB DMA Address */
3538#define USB_DMA_ADDR5 0xFFCC1258 /* USB DMA Address */
3539#define USB_DMA_ADDR6 0xFFCC1268 /* USB DMA Address */
3540#define USB_DMA_ADDR7 0xFFCC1278 /* USB DMA Address */
3541#define USB_DMA_CNT0 0xFFCC120C /* USB DMA Count */
3542#define USB_DMA_CNT1 0xFFCC121C /* USB DMA Count */
3543#define USB_DMA_CNT2 0xFFCC122C /* USB DMA Count */
3544#define USB_DMA_CNT3 0xFFCC123C /* USB DMA Count */
3545#define USB_DMA_CNT4 0xFFCC124C /* USB DMA Count */
3546#define USB_DMA_CNT5 0xFFCC125C /* USB DMA Count */
3547#define USB_DMA_CNT6 0xFFCC126C /* USB DMA Count */
3548#define USB_DMA_CNT7 0xFFCC127C /* USB DMA Count */
3549#define USB_RQPKTCNT0 0xFFCC1300 /* USB Request Packet Count */
3550#define USB_RQPKTCNT1 0xFFCC1304 /* USB Request Packet Count */
3551#define USB_RQPKTCNT2 0xFFCC1308 /* USB Request Packet Count */
3552#define USB_RQPKTCNT3 0xFFCC130C /* USB Request Packet Count */
3553#define USB_RQPKTCNT4 0xFFCC1310 /* USB Request Packet Count */
3554#define USB_RQPKTCNT5 0xFFCC1314 /* USB Request Packet Count */
3555#define USB_RQPKTCNT6 0xFFCC1318 /* USB Request Packet Count */
3556#define USB_RQPKTCNT7 0xFFCC131C /* USB Request Packet Count */
3557#define USB_RQPKTCNT8 0xFFCC1320 /* USB Request Packet Count */
3558#define USB_RQPKTCNT9 0xFFCC1324 /* USB Request Packet Count */
3559#define USB_RQPKTCNT10 0xFFCC1328 /* USB Request Packet Count */
3560#define USB_CT_UCH 0xFFCC1344 /* USB Chirp Timeout */
3561#define USB_CT_HHSRTN 0xFFCC1346 /* USB High Speed Resume Return to Normal */
3562#define USB_CT_HSBT 0xFFCC1348 /* USB High Speed Timeout */
3563#define USB_LPM_ATTR 0xFFCC1360 /* USB LPM Attribute */
3564#define USB_LPM_CTL 0xFFCC1362 /* USB LPM Control */
3565#define USB_LPM_IEN 0xFFCC1363 /* USB LPM Interrupt Enable */
3566#define USB_LPM_IRQ 0xFFCC1364 /* USB LPM Interrupt */
3567#define USB_LPM_FADDR 0xFFCC1365 /* USB LPM Function Address */
3568#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */
3569#define USB_BAT_CHG 0xFFCC1381 /* USB Battery Charging */
3570#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */
3571#define USB_TESTCTL 0xFFCC1397 /* USB Test Control */
3572#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */
3573
3574
3575
3576/* =========================
3577 CHIPID
3578 ========================= */
3579
3580#define CHIPID 0xffc00014
3581/* CHIPID Masks */
3582#define CHIPID_VERSION 0xF0000000
3583#define CHIPID_FAMILY 0x0FFFF000
3584#define CHIPID_MANUFACTURE 0x00000FFE
3585
3586
3587#endif /* _DEF_BF60X_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/dma.h b/arch/blackfin/mach-bf609/include/mach/dma.h
new file mode 100644
index 000000000000..872d141ca119
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/dma.h
@@ -0,0 +1,116 @@
1/* mach/dma.h - arch-specific DMA defines
2 *
3 * Copyright 2011 Analog Devices Inc.
4 *
5 * Licensed under the GPL-2 or later.
6 */
7
8#ifndef _MACH_DMA_H_
9#define _MACH_DMA_H_
10
11#define CH_SPORT0_TX 0
12#define CH_SPORT0_RX 1
13#define CH_SPORT1_TX 2
14#define CH_SPORT1_RX 3
15#define CH_SPORT2_TX 4
16#define CH_SPORT2_RX 5
17#define CH_SPI0_TX 6
18#define CH_SPI0_RX 7
19#define CH_SPI1_TX 8
20#define CH_SPI1_RX 9
21#define CH_RSI 10
22#define CH_SDU 11
23#define CH_LP0 13
24#define CH_LP1 14
25#define CH_LP2 15
26#define CH_LP3 16
27#define CH_UART0_TX 17
28#define CH_UART0_RX 18
29#define CH_UART1_TX 19
30#define CH_UART1_RX 20
31#define CH_MEM_STREAM0_SRC_CRC0 21
32#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0
33#define CH_MEM_STREAM0_DEST_CRC0 22
34#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0
35#define CH_MEM_STREAM1_SRC_CRC1 23
36#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1
37#define CH_MEM_STREAM1_DEST_CRC1 24
38#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1
39#define CH_MEM_STREAM2_SRC 25
40#define CH_MEM_STREAM2_DEST 26
41#define CH_MEM_STREAM3_SRC 27
42#define CH_MEM_STREAM3_DEST 28
43#define CH_EPPI0_CH0 29
44#define CH_EPPI0_CH1 30
45#define CH_EPPI1_CH0 31
46#define CH_EPPI1_CH1 32
47#define CH_EPPI2_CH0 33
48#define CH_EPPI2_CH1 34
49#define CH_PIXC_CH0 35
50#define CH_PIXC_CH1 36
51#define CH_PIXC_CH2 37
52#define CH_PVP_CPDOB 38
53#define CH_PVP_CPDOC 39
54#define CH_PVP_CPSTAT 40
55#define CH_PVP_CPCI 41
56#define CH_PVP_MPDO 42
57#define CH_PVP_MPDI 43
58#define CH_PVP_MPSTAT 44
59#define CH_PVP_MPCI 45
60#define CH_PVP_CPDOA 46
61
62#define MAX_DMA_CHANNELS 47
63#define MAX_DMA_SUSPEND_CHANNELS 0
64#define DMA_MMR_SIZE_32
65
66#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
67#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
68#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
69#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
70#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
71#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
72#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
73#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
74#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
75#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
76#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
77#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
78#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
79#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
80#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
81#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
82#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
83#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
84
85#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
86#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
87#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
88#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
89#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
90#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
91
92#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
93#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
94#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
95#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
96#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
97#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
98#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
99#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
100#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
101#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
102#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
103#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
104#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
105#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
106#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
107#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
108#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
109#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
110
111#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
112#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
113#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
114#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
115
116#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
new file mode 100644
index 000000000000..127586b1e04a
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/gpio.h
@@ -0,0 +1,171 @@
1/*
2 * Copyright 2007-2009 Analog Devices Inc.
3 * Licensed under the GPL-2 or later.
4 */
5
6#ifndef _MACH_GPIO_H_
7#define _MACH_GPIO_H_
8
9#define MAX_BLACKFIN_GPIOS 112
10
11#define GPIO_PA0 0
12#define GPIO_PA1 1
13#define GPIO_PA2 2
14#define GPIO_PA3 3
15#define GPIO_PA4 4
16#define GPIO_PA5 5
17#define GPIO_PA6 6
18#define GPIO_PA7 7
19#define GPIO_PA8 8
20#define GPIO_PA9 9
21#define GPIO_PA10 10
22#define GPIO_PA11 11
23#define GPIO_PA12 12
24#define GPIO_PA13 13
25#define GPIO_PA14 14
26#define GPIO_PA15 15
27#define GPIO_PB0 16
28#define GPIO_PB1 17
29#define GPIO_PB2 18
30#define GPIO_PB3 19
31#define GPIO_PB4 20
32#define GPIO_PB5 21
33#define GPIO_PB6 22
34#define GPIO_PB7 23
35#define GPIO_PB8 24
36#define GPIO_PB9 25
37#define GPIO_PB10 26
38#define GPIO_PB11 27
39#define GPIO_PB12 28
40#define GPIO_PB13 29
41#define GPIO_PB14 30
42#define GPIO_PB15 31
43#define GPIO_PC0 32
44#define GPIO_PC1 33
45#define GPIO_PC2 34
46#define GPIO_PC3 35
47#define GPIO_PC4 36
48#define GPIO_PC5 37
49#define GPIO_PC6 38
50#define GPIO_PC7 39
51#define GPIO_PC8 40
52#define GPIO_PC9 41
53#define GPIO_PC10 42
54#define GPIO_PC11 43
55#define GPIO_PC12 44
56#define GPIO_PC13 45
57#define GPIO_PC14 46
58#define GPIO_PC15 47
59#define GPIO_PD0 48
60#define GPIO_PD1 49
61#define GPIO_PD2 50
62#define GPIO_PD3 51
63#define GPIO_PD4 52
64#define GPIO_PD5 53
65#define GPIO_PD6 54
66#define GPIO_PD7 55
67#define GPIO_PD8 56
68#define GPIO_PD9 57
69#define GPIO_PD10 58
70#define GPIO_PD11 59
71#define GPIO_PD12 60
72#define GPIO_PD13 61
73#define GPIO_PD14 62
74#define GPIO_PD15 63
75#define GPIO_PE0 64
76#define GPIO_PE1 65
77#define GPIO_PE2 66
78#define GPIO_PE3 67
79#define GPIO_PE4 68
80#define GPIO_PE5 69
81#define GPIO_PE6 70
82#define GPIO_PE7 71
83#define GPIO_PE8 72
84#define GPIO_PE9 73
85#define GPIO_PE10 74
86#define GPIO_PE11 75
87#define GPIO_PE12 76
88#define GPIO_PE13 77
89#define GPIO_PE14 78
90#define GPIO_PE15 79
91#define GPIO_PF0 80
92#define GPIO_PF1 81
93#define GPIO_PF2 82
94#define GPIO_PF3 83
95#define GPIO_PF4 84
96#define GPIO_PF5 85
97#define GPIO_PF6 86
98#define GPIO_PF7 87
99#define GPIO_PF8 88
100#define GPIO_PF9 89
101#define GPIO_PF10 90
102#define GPIO_PF11 91
103#define GPIO_PF12 92
104#define GPIO_PF13 93
105#define GPIO_PF14 94
106#define GPIO_PF15 95
107#define GPIO_PG0 96
108#define GPIO_PG1 97
109#define GPIO_PG2 98
110#define GPIO_PG3 99
111#define GPIO_PG4 100
112#define GPIO_PG5 101
113#define GPIO_PG6 102
114#define GPIO_PG7 103
115#define GPIO_PG8 104
116#define GPIO_PG9 105
117#define GPIO_PG10 106
118#define GPIO_PG11 107
119#define GPIO_PG12 108
120#define GPIO_PG13 109
121#define GPIO_PG14 110
122#define GPIO_PG15 111
123
124
125#define BFIN_GPIO_PINT 1
126
127
128#ifndef __ASSEMBLY__
129
130struct gpio_port_t {
131 unsigned long port_fer;
132 unsigned long port_fer_set;
133 unsigned long port_fer_clear;
134 unsigned long data;
135 unsigned long data_set;
136 unsigned long data_clear;
137 unsigned long dir;
138 unsigned long dir_set;
139 unsigned long dir_clear;
140 unsigned long inen;
141 unsigned long inen_set;
142 unsigned long inen_clear;
143 unsigned long port_mux;
144 unsigned long toggle;
145 unsigned long polar;
146 unsigned long polar_set;
147 unsigned long polar_clear;
148 unsigned long lock;
149 unsigned long spare;
150 unsigned long revid;
151};
152
153struct gpio_port_s {
154 unsigned short fer;
155 unsigned short data;
156 unsigned short dir;
157 unsigned short inen;
158 unsigned int mux;
159};
160
161#endif
162
163#include <mach-common/ports-a.h>
164#include <mach-common/ports-b.h>
165#include <mach-common/ports-c.h>
166#include <mach-common/ports-d.h>
167#include <mach-common/ports-e.h>
168#include <mach-common/ports-f.h>
169#include <mach-common/ports-g.h>
170
171#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
new file mode 100644
index 000000000000..0004552433b2
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/irq.h
@@ -0,0 +1,318 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#ifndef _BF60x_IRQ_H_
8#define _BF60x_IRQ_H_
9
10#include <mach-common/irq.h>
11
12#undef BFIN_IRQ
13#define BFIN_IRQ(x) ((x) + IVG15)
14
15#define NR_PERI_INTS (5 * 32)
16
17#define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */
18#define IRQ_CGU_EVT BFIN_IRQ(1) /* CGU Event */
19#define IRQ_WATCH0 BFIN_IRQ(2) /* Watchdog0 Interrupt */
20#define IRQ_WATCH1 BFIN_IRQ(3) /* Watchdog1 Interrupt */
21#define IRQ_L2CTL0_ECC_ERR BFIN_IRQ(4) /* L2 ECC Error */
22#define IRQ_L2CTL0_ECC_WARN BFIN_IRQ(5) /* L2 ECC Waring */
23#define IRQ_C0_DBL_FAULT BFIN_IRQ(6) /* Core 0 Double Fault */
24#define IRQ_C1_DBL_FAULT BFIN_IRQ(7) /* Core 1 Double Fault */
25#define IRQ_C0_HW_ERR BFIN_IRQ(8) /* Core 0 Hardware Error */
26#define IRQ_C1_HW_ERR BFIN_IRQ(9) /* Core 1 Hardware Error */
27#define IRQ_C0_NMI_L1_PARITY_ERR BFIN_IRQ(10) /* Core 0 Unhandled NMI or L1 Memory Parity Error */
28#define IRQ_C1_NMI_L1_PARITY_ERR BFIN_IRQ(11) /* Core 1 Unhandled NMI or L1 Memory Parity Error */
29#define CORE_IRQS (IRQ_C1_NMI_L1_PARITY_ERR + 1)
30
31#define IRQ_TIMER0 BFIN_IRQ(12) /* Timer 0 Interrupt */
32#define IRQ_TIMER1 BFIN_IRQ(13) /* Timer 1 Interrupt */
33#define IRQ_TIMER2 BFIN_IRQ(14) /* Timer 2 Interrupt */
34#define IRQ_TIMER3 BFIN_IRQ(15) /* Timer 3 Interrupt */
35#define IRQ_TIMER4 BFIN_IRQ(16) /* Timer 4 Interrupt */
36#define IRQ_TIMER5 BFIN_IRQ(17) /* Timer 5 Interrupt */
37#define IRQ_TIMER6 BFIN_IRQ(18) /* Timer 6 Interrupt */
38#define IRQ_TIMER7 BFIN_IRQ(19) /* Timer 7 Interrupt */
39#define IRQ_TIMER_STAT BFIN_IRQ(20) /* Timer Block Status */
40#define IRQ_PINT0 BFIN_IRQ(21) /* PINT0 Interrupt */
41#define IRQ_PINT1 BFIN_IRQ(22) /* PINT1 Interrupt */
42#define IRQ_PINT2 BFIN_IRQ(23) /* PINT2 Interrupt */
43#define IRQ_PINT3 BFIN_IRQ(24) /* PINT3 Interrupt */
44#define IRQ_PINT4 BFIN_IRQ(25) /* PINT4 Interrupt */
45#define IRQ_PINT5 BFIN_IRQ(26) /* PINT5 Interrupt */
46#define IRQ_CNT BFIN_IRQ(27) /* CNT Interrupt */
47#define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */
48#define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */
49#define IRQ_PWM1_TRIP BFIN_IRQ(30) /* PWM1 Trip Interrupt */
50#define IRQ_PWM1_SYNC BFIN_IRQ(31) /* PWM1 Sync Interrupt */
51#define IRQ_TWI0 BFIN_IRQ(32) /* TWI0 Interrupt */
52#define IRQ_TWI1 BFIN_IRQ(33) /* TWI1 Interrupt */
53#define IRQ_SOFT0 BFIN_IRQ(34) /* Software-Driven Interrupt 0 */
54#define IRQ_SOFT1 BFIN_IRQ(35) /* Software-Driven Interrupt 1 */
55#define IRQ_SOFT2 BFIN_IRQ(36) /* Software-Driven Interrupt 2 */
56#define IRQ_SOFT3 BFIN_IRQ(37) /* Software-Driven Interrupt 3 */
57#define IRQ_ACM_EVT_MISS BFIN_IRQ(38) /* ACM Event Miss */
58#define IRQ_ACM_EVT_COMPLETE BFIN_IRQ(39) /* ACM Event Complete */
59#define IRQ_CAN0_RX BFIN_IRQ(40) /* CAN0 Receive Interrupt */
60#define IRQ_CAN0_TX BFIN_IRQ(41) /* CAN0 Transmit Interrupt */
61#define IRQ_CAN0_STAT BFIN_IRQ(42) /* CAN0 Status */
62#define IRQ_SPORT0_TX BFIN_IRQ(43) /* SPORT0 TX Interrupt (DMA0) */
63#define IRQ_SPORT0_TX_STAT BFIN_IRQ(44) /* SPORT0 TX Status Interrupt */
64#define IRQ_SPORT0_RX BFIN_IRQ(45) /* SPORT0 RX Interrupt (DMA1) */
65#define IRQ_SPORT0_RX_STAT BFIN_IRQ(46) /* SPORT0 RX Status Interrupt */
66#define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */
67#define IRQ_SPORT1_TX_STAT BFIN_IRQ(48) /* SPORT1 TX Status Interrupt */
68#define IRQ_SPORT1_RX BFIN_IRQ(49) /* SPORT1 RX Interrupt (DMA3) */
69#define IRQ_SPORT1_RX_STAT BFIN_IRQ(50) /* SPORT1 RX Status Interrupt */
70#define IRQ_SPORT2_TX BFIN_IRQ(51) /* SPORT2 TX Interrupt (DMA4) */
71#define IRQ_SPORT2_TX_STAT BFIN_IRQ(52) /* SPORT2 TX Status Interrupt */
72#define IRQ_SPORT2_RX BFIN_IRQ(53) /* SPORT2 RX Interrupt (DMA5) */
73#define IRQ_SPORT2_RX_STAT BFIN_IRQ(54) /* SPORT2 RX Status Interrupt */
74#define IRQ_SPI0_TX BFIN_IRQ(55) /* SPI0 TX Interrupt (DMA6) */
75#define IRQ_SPI0_RX BFIN_IRQ(56) /* SPI0 RX Interrupt (DMA7) */
76#define IRQ_SPI0_STAT BFIN_IRQ(57) /* SPI0 Status Interrupt */
77#define IRQ_SPI1_TX BFIN_IRQ(58) /* SPI1 TX Interrupt (DMA8) */
78#define IRQ_SPI1_RX BFIN_IRQ(59) /* SPI1 RX Interrupt (DMA9) */
79#define IRQ_SPI1_STAT BFIN_IRQ(60) /* SPI1 Status Interrupt */
80#define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */
81#define IRQ_RSI_INT0 BFIN_IRQ(62) /* RSI Interrupt0 */
82#define IRQ_RSI_INT1 BFIN_IRQ(63) /* RSI Interrupt1 */
83#define IRQ_SDU BFIN_IRQ(64) /* DMA11 Data (SDU) */
84/* -- RESERVED -- 65 DMA12 Data (Reserved) */
85/* -- RESERVED -- 66 Reserved */
86/* -- RESERVED -- 67 Reserved */
87#define IRQ_EMAC0_STAT BFIN_IRQ(68) /* EMAC0 Status */
88/* -- RESERVED -- 69 EMAC0 Power (Reserved) */
89#define IRQ_EMAC1_STAT BFIN_IRQ(70) /* EMAC1 Status */
90/* -- RESERVED -- 71 EMAC1 Power (Reserved) */
91#define IRQ_LP0 BFIN_IRQ(72) /* DMA13 Data (Link Port 0) */
92#define IRQ_LP0_STAT BFIN_IRQ(73) /* Link Port 0 Status */
93#define IRQ_LP1 BFIN_IRQ(74) /* DMA14 Data (Link Port 1) */
94#define IRQ_LP1_STAT BFIN_IRQ(75) /* Link Port 1 Status */
95#define IRQ_LP2 BFIN_IRQ(76) /* DMA15 Data (Link Port 2) */
96#define IRQ_LP2_STAT BFIN_IRQ(77) /* Link Port 2 Status */
97#define IRQ_LP3 BFIN_IRQ(78) /* DMA16 Data(Link Port 3) */
98#define IRQ_LP3_STAT BFIN_IRQ(79) /* Link Port 3 Status */
99#define IRQ_UART0_TX BFIN_IRQ(80) /* UART0 TX Interrupt (DMA17) */
100#define IRQ_UART0_RX BFIN_IRQ(81) /* UART0 RX Interrupt (DMA18) */
101#define IRQ_UART0_STAT BFIN_IRQ(82) /* UART0 Status(Error) Interrupt */
102#define IRQ_UART1_TX BFIN_IRQ(83) /* UART1 TX Interrupt (DMA19) */
103#define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */
104#define IRQ_UART1_STAT BFIN_IRQ(85) /* UART1 Status(Error) Interrupt */
105#define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
106#define IRQ_MDMA0_DEST_CRC0 BFIN_IRQ(87) /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
107#define IRQ_MDMAS0 IRQ_MDMA0_DEST_CRC0
108#define IRQ_CRC0_DCNTEXP BFIN_IRQ(88) /* CRC0 DATACOUNT Expiration */
109#define IRQ_CRC0_ERR BFIN_IRQ(89) /* CRC0 Error */
110#define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
111#define IRQ_MDMA1_DEST_CRC1 BFIN_IRQ(91) /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
112#define IRQ_MDMAS1 IRQ_MDMA1_DEST_CRC1
113#define IRQ_CRC1_DCNTEXP BFIN_IRQ(92) /* CRC1 DATACOUNT Expiration */
114#define IRQ_CRC1_ERR BFIN_IRQ(93) /* CRC1 Error */
115#define IRQ_MDMA2_SRC BFIN_IRQ(94) /* DMA25 Data (MDMA Stream 2 Source Channel) */
116#define IRQ_MDMA2_DEST BFIN_IRQ(95) /* DMA26 Data (MDMA Stream 2 Destination Channel) */
117#define IRQ_MDMAS2 IRQ_MDMA2_DEST
118#define IRQ_MDMA3_SRC BFIN_IRQ(96) /* DMA27 Data (MDMA Stream 3 Source Channel) */
119#define IRQ_MDMA3_DEST BFIN_IRQ(97) /* DMA28 Data (MDMA Stream 3 Destination Channel) */
120#define IRQ_MDMAS3 IRQ_MDMA3_DEST
121#define IRQ_EPPI0_CH0 BFIN_IRQ(98) /* DMA29 Data (EPPI0 Channel 0) */
122#define IRQ_EPPI0_CH1 BFIN_IRQ(99) /* DMA30 Data (EPPI0 Channel 1) */
123#define IRQ_EPPI0_STAT BFIN_IRQ(100) /* EPPI0 Status */
124#define IRQ_EPPI2_CH0 BFIN_IRQ(101) /* DMA31 Data (EPPI2 Channel 0) */
125#define IRQ_EPPI2_CH1 BFIN_IRQ(102) /* DMA32 Data (EPPI2 Channel 1) */
126#define IRQ_EPPI2_STAT BFIN_IRQ(103) /* EPPI2 Status */
127#define IRQ_EPPI1_CH0 BFIN_IRQ(104) /* DMA33 Data (EPPI1 Channel 0) */
128#define IRQ_EPPI1_CH1 BFIN_IRQ(105) /* DMA34 Data (EPPI1 Channel 1) */
129#define IRQ_EPPI1_STAT BFIN_IRQ(106) /* EPPI1 Status */
130#define IRQ_PIXC_CH0 BFIN_IRQ(107) /* DMA35 Data (PIXC Channel 0) */
131#define IRQ_PIXC_CH1 BFIN_IRQ(108) /* DMA36 Data (PIXC Channel 1) */
132#define IRQ_PIXC_CH2 BFIN_IRQ(109) /* DMA37 Data (PIXC Channel 2) */
133#define IRQ_PIXC_STAT BFIN_IRQ(110) /* PIXC Status */
134#define IRQ_PVP_CPDOB BFIN_IRQ(111) /* DMA38 Data (PVP0 Camera Pipe Data Out B) */
135#define IRQ_PVP_CPDOC BFIN_IRQ(112) /* DMA39 Data (PVP0 Camera Pipe Data Out C) */
136#define IRQ_PVP_CPSTAT BFIN_IRQ(113) /* DMA40 Data (PVP0 Camera Pipe Status Out) */
137#define IRQ_PVP_CPCI BFIN_IRQ(114) /* DMA41 Data (PVP0 Camera Pipe Control In) */
138#define IRQ_PVP_STAT0 BFIN_IRQ(115) /* PVP0 Status 0 */
139#define IRQ_PVP_MPDO BFIN_IRQ(116) /* DMA42 Data (PVP0 Memory Pipe Data Out) */
140#define IRQ_PVP_MPDI BFIN_IRQ(117) /* DMA43 Data (PVP0 Memory Pipe Data In) */
141#define IRQ_PVP_MPSTAT BFIN_IRQ(118) /* DMA44 Data (PVP0 Memory Pipe Status Out) */
142#define IRQ_PVP_MPCI BFIN_IRQ(119) /* DMA45 Data (PVP0 Memory Pipe Control In) */
143#define IRQ_PVP_CPDOA BFIN_IRQ(120) /* DMA46 Data (PVP0 Camera Pipe Data Out A) */
144#define IRQ_PVP_STAT1 BFIN_IRQ(121) /* PVP0 Status 1 */
145#define IRQ_USB_STAT BFIN_IRQ(122) /* USB Status Interrupt */
146#define IRQ_USB_DMA BFIN_IRQ(123) /* USB DMA Interrupt */
147#define IRQ_TRU_INT0 BFIN_IRQ(124) /* TRU0 Interrupt 0 */
148#define IRQ_TRU_INT1 BFIN_IRQ(125) /* TRU0 Interrupt 1 */
149#define IRQ_TRU_INT2 BFIN_IRQ(126) /* TRU0 Interrupt 2 */
150#define IRQ_TRU_INT3 BFIN_IRQ(127) /* TRU0 Interrupt 3 */
151#define IRQ_DMAC0_ERROR BFIN_IRQ(128) /* DMAC0 Status Interrupt */
152#define IRQ_CGU0_ERROR BFIN_IRQ(129) /* CGU0 Error */
153/* -- RESERVED -- 130 Reserved */
154#define IRQ_DPM BFIN_IRQ(131) /* DPM0 Event */
155/* -- RESERVED -- 132 Reserved */
156#define IRQ_SWU0 BFIN_IRQ(133) /* SWU0 */
157#define IRQ_SWU1 BFIN_IRQ(134) /* SWU1 */
158#define IRQ_SWU2 BFIN_IRQ(135) /* SWU2 */
159#define IRQ_SWU3 BFIN_IRQ(136) /* SWU3 */
160#define IRQ_SWU4 BFIN_IRQ(137) /* SWU4 */
161#define IRQ_SWU5 BFIN_IRQ(138) /* SWU5 */
162#define IRQ_SWU6 BFIN_IRQ(139) /* SWU6 */
163
164#define SYS_IRQS IRQ_SWU6
165
166#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
167#define IRQ_PA0 BFIN_PA_IRQ(0)
168#define IRQ_PA1 BFIN_PA_IRQ(1)
169#define IRQ_PA2 BFIN_PA_IRQ(2)
170#define IRQ_PA3 BFIN_PA_IRQ(3)
171#define IRQ_PA4 BFIN_PA_IRQ(4)
172#define IRQ_PA5 BFIN_PA_IRQ(5)
173#define IRQ_PA6 BFIN_PA_IRQ(6)
174#define IRQ_PA7 BFIN_PA_IRQ(7)
175#define IRQ_PA8 BFIN_PA_IRQ(8)
176#define IRQ_PA9 BFIN_PA_IRQ(9)
177#define IRQ_PA10 BFIN_PA_IRQ(10)
178#define IRQ_PA11 BFIN_PA_IRQ(11)
179#define IRQ_PA12 BFIN_PA_IRQ(12)
180#define IRQ_PA13 BFIN_PA_IRQ(13)
181#define IRQ_PA14 BFIN_PA_IRQ(14)
182#define IRQ_PA15 BFIN_PA_IRQ(15)
183
184#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
185#define IRQ_PB0 BFIN_PB_IRQ(0)
186#define IRQ_PB1 BFIN_PB_IRQ(1)
187#define IRQ_PB2 BFIN_PB_IRQ(2)
188#define IRQ_PB3 BFIN_PB_IRQ(3)
189#define IRQ_PB4 BFIN_PB_IRQ(4)
190#define IRQ_PB5 BFIN_PB_IRQ(5)
191#define IRQ_PB6 BFIN_PB_IRQ(6)
192#define IRQ_PB7 BFIN_PB_IRQ(7)
193#define IRQ_PB8 BFIN_PB_IRQ(8)
194#define IRQ_PB9 BFIN_PB_IRQ(9)
195#define IRQ_PB10 BFIN_PB_IRQ(10)
196#define IRQ_PB11 BFIN_PB_IRQ(11)
197#define IRQ_PB12 BFIN_PB_IRQ(12)
198#define IRQ_PB13 BFIN_PB_IRQ(13)
199#define IRQ_PB14 BFIN_PB_IRQ(14)
200#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
201
202#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
203#define IRQ_PC0 BFIN_PC_IRQ(0)
204#define IRQ_PC1 BFIN_PC_IRQ(1)
205#define IRQ_PC2 BFIN_PC_IRQ(2)
206#define IRQ_PC3 BFIN_PC_IRQ(3)
207#define IRQ_PC4 BFIN_PC_IRQ(4)
208#define IRQ_PC5 BFIN_PC_IRQ(5)
209#define IRQ_PC6 BFIN_PC_IRQ(6)
210#define IRQ_PC7 BFIN_PC_IRQ(7)
211#define IRQ_PC8 BFIN_PC_IRQ(8)
212#define IRQ_PC9 BFIN_PC_IRQ(9)
213#define IRQ_PC10 BFIN_PC_IRQ(10)
214#define IRQ_PC11 BFIN_PC_IRQ(11)
215#define IRQ_PC12 BFIN_PC_IRQ(12)
216#define IRQ_PC13 BFIN_PC_IRQ(13)
217#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
218#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
219
220#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
221#define IRQ_PD0 BFIN_PD_IRQ(0)
222#define IRQ_PD1 BFIN_PD_IRQ(1)
223#define IRQ_PD2 BFIN_PD_IRQ(2)
224#define IRQ_PD3 BFIN_PD_IRQ(3)
225#define IRQ_PD4 BFIN_PD_IRQ(4)
226#define IRQ_PD5 BFIN_PD_IRQ(5)
227#define IRQ_PD6 BFIN_PD_IRQ(6)
228#define IRQ_PD7 BFIN_PD_IRQ(7)
229#define IRQ_PD8 BFIN_PD_IRQ(8)
230#define IRQ_PD9 BFIN_PD_IRQ(9)
231#define IRQ_PD10 BFIN_PD_IRQ(10)
232#define IRQ_PD11 BFIN_PD_IRQ(11)
233#define IRQ_PD12 BFIN_PD_IRQ(12)
234#define IRQ_PD13 BFIN_PD_IRQ(13)
235#define IRQ_PD14 BFIN_PD_IRQ(14)
236#define IRQ_PD15 BFIN_PD_IRQ(15)
237
238#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
239#define IRQ_PE0 BFIN_PE_IRQ(0)
240#define IRQ_PE1 BFIN_PE_IRQ(1)
241#define IRQ_PE2 BFIN_PE_IRQ(2)
242#define IRQ_PE3 BFIN_PE_IRQ(3)
243#define IRQ_PE4 BFIN_PE_IRQ(4)
244#define IRQ_PE5 BFIN_PE_IRQ(5)
245#define IRQ_PE6 BFIN_PE_IRQ(6)
246#define IRQ_PE7 BFIN_PE_IRQ(7)
247#define IRQ_PE8 BFIN_PE_IRQ(8)
248#define IRQ_PE9 BFIN_PE_IRQ(9)
249#define IRQ_PE10 BFIN_PE_IRQ(10)
250#define IRQ_PE11 BFIN_PE_IRQ(11)
251#define IRQ_PE12 BFIN_PE_IRQ(12)
252#define IRQ_PE13 BFIN_PE_IRQ(13)
253#define IRQ_PE14 BFIN_PE_IRQ(14)
254#define IRQ_PE15 BFIN_PE_IRQ(15)
255
256#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
257#define IRQ_PF0 BFIN_PF_IRQ(0)
258#define IRQ_PF1 BFIN_PF_IRQ(1)
259#define IRQ_PF2 BFIN_PF_IRQ(2)
260#define IRQ_PF3 BFIN_PF_IRQ(3)
261#define IRQ_PF4 BFIN_PF_IRQ(4)
262#define IRQ_PF5 BFIN_PF_IRQ(5)
263#define IRQ_PF6 BFIN_PF_IRQ(6)
264#define IRQ_PF7 BFIN_PF_IRQ(7)
265#define IRQ_PF8 BFIN_PF_IRQ(8)
266#define IRQ_PF9 BFIN_PF_IRQ(9)
267#define IRQ_PF10 BFIN_PF_IRQ(10)
268#define IRQ_PF11 BFIN_PF_IRQ(11)
269#define IRQ_PF12 BFIN_PF_IRQ(12)
270#define IRQ_PF13 BFIN_PF_IRQ(13)
271#define IRQ_PF14 BFIN_PF_IRQ(14)
272#define IRQ_PF15 BFIN_PF_IRQ(15)
273
274#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
275#define IRQ_PG0 BFIN_PG_IRQ(0)
276#define IRQ_PG1 BFIN_PG_IRQ(1)
277#define IRQ_PG2 BFIN_PG_IRQ(2)
278#define IRQ_PG3 BFIN_PG_IRQ(3)
279#define IRQ_PG4 BFIN_PG_IRQ(4)
280#define IRQ_PG5 BFIN_PG_IRQ(5)
281#define IRQ_PG6 BFIN_PG_IRQ(6)
282#define IRQ_PG7 BFIN_PG_IRQ(7)
283#define IRQ_PG8 BFIN_PG_IRQ(8)
284#define IRQ_PG9 BFIN_PG_IRQ(9)
285#define IRQ_PG10 BFIN_PG_IRQ(10)
286#define IRQ_PG11 BFIN_PG_IRQ(11)
287#define IRQ_PG12 BFIN_PG_IRQ(12)
288#define IRQ_PG13 BFIN_PG_IRQ(13)
289#define IRQ_PG14 BFIN_PG_IRQ(14)
290#define IRQ_PG15 BFIN_PG_IRQ(15)
291
292#define GPIO_IRQ_BASE IRQ_PA0
293
294#define NR_MACH_IRQS (IRQ_PG15 + 1)
295
296#ifndef __ASSEMBLY__
297#include <linux/types.h>
298
299/*
300 * bfin pint registers layout
301 */
302struct bfin_pint_regs {
303 u32 mask_set;
304 u32 mask_clear;
305 u32 request;
306 u32 assign;
307 u32 edge_set;
308 u32 edge_clear;
309 u32 invert_set;
310 u32 invert_clear;
311 u32 pinstate;
312 u32 latch;
313 u32 __pad0[2];
314};
315
316#endif
317
318#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/mem_map.h b/arch/blackfin/mach-bf609/include/mach/mem_map.h
new file mode 100644
index 000000000000..20b65bfc5311
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/mem_map.h
@@ -0,0 +1,86 @@
1/*
2 * BF60x memory map
3 *
4 * Copyright 2011 Analog Devices Inc.
5 * Licensed under the GPL-2 or later.
6 */
7
8#ifndef __BFIN_MACH_MEM_MAP_H__
9#define __BFIN_MACH_MEM_MAP_H__
10
11#ifndef __BFIN_MEM_MAP_H__
12# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
13#endif
14
15/* Async Memory Banks */
16#define ASYNC_BANK3_BASE 0xBC000000 /* Async Bank 3 */
17#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
18#define ASYNC_BANK2_BASE 0xB8000000 /* Async Bank 2 */
19#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
20#define ASYNC_BANK1_BASE 0xB4000000 /* Async Bank 1 */
21#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
22#define ASYNC_BANK0_BASE 0xB0000000 /* Async Bank 0 */
23#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
24
25/* Boot ROM Memory */
26
27#define BOOT_ROM_START 0xC8000000
28#define BOOT_ROM_LENGTH 0x8000
29
30/* Level 1 Memory */
31
32/* Memory Map for ADSP-BF60x processors */
33#ifdef CONFIG_BFIN_ICACHE
34#define BFIN_ICACHESIZE (16*1024)
35#define L1_CODE_LENGTH 0x10000
36#else
37#define BFIN_ICACHESIZE (0*1024)
38#define L1_CODE_LENGTH 0x14000
39#endif
40
41#define L1_CODE_START 0xFFA00000
42#define L1_DATA_A_START 0xFF800000
43#define L1_DATA_B_START 0xFF900000
44
45
46#define COREA_L1_SCRATCH_START 0xFFB00000
47#define COREB_L1_SCRATCH_START 0xFF700000
48
49#define COREB_L1_CODE_START 0xFF600000
50#define COREB_L1_DATA_A_START 0xFF400000
51#define COREB_L1_DATA_B_START 0xFF500000
52
53#define COREB_L1_CODE_LENGTH 0x14000
54#define COREB_L1_DATA_A_LENGTH 0x8000
55#define COREB_L1_DATA_B_LENGTH 0x8000
56
57
58#ifdef CONFIG_BFIN_DCACHE
59
60#ifdef CONFIG_BFIN_DCACHE_BANKA
61#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
62#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
63#define L1_DATA_B_LENGTH 0x8000
64#define BFIN_DCACHESIZE (16*1024)
65#define BFIN_DSUPBANKS 1
66#else
67#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
68#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
69#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
70#define BFIN_DCACHESIZE (32*1024)
71#define BFIN_DSUPBANKS 2
72#endif
73
74#else
75#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
76#define L1_DATA_A_LENGTH 0x8000
77#define L1_DATA_B_LENGTH 0x8000
78#define BFIN_DCACHESIZE (0*1024)
79#define BFIN_DSUPBANKS 0
80#endif /*CONFIG_BFIN_DCACHE*/
81
82/* Level 2 Memory */
83#define L2_START 0xC8080000
84#define L2_LENGTH 0x40000
85
86#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/pll.h b/arch/blackfin/mach-bf609/include/mach/pll.h
new file mode 100644
index 000000000000..1857a4a0f262
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/pll.h
@@ -0,0 +1 @@
/* #include <mach-common/pll.h> */
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h
new file mode 100644
index 000000000000..036d9bdc889e
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/pm.h
@@ -0,0 +1,21 @@
1/*
2 * Blackfin bf609 power management
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2
7 */
8
9#ifndef __MACH_BF609_PM_H__
10#define __MACH_BF609_PM_H__
11
12#include <linux/suspend.h>
13
14int bfin609_pm_enter(suspend_state_t state);
15int bf609_pm_prepare(void);
16void bf609_pm_finish(void);
17
18void bf609_hibernate(void);
19void bfin_sec_raise_irq(unsigned int sid);
20void coreb_enable(void);
21#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
new file mode 100644
index 000000000000..2e1a51c25098
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/portmux.h
@@ -0,0 +1,347 @@
1/*
2 * Copyright 2011 Analog Devices Inc.
3 *
4 * Licensed under the GPL-2 or later
5 */
6
7#ifndef _MACH_PORTMUX_H_
8#define _MACH_PORTMUX_H_
9
10#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
11
12/* EMAC RMII Port Mux */
13#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
14#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
15#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
16#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
17#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
18#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
19#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
20#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
21#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
22#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
23#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
24
25#define P_RMII0 {\
26 P_MII0_ETxD0, \
27 P_MII0_ETxD1, \
28 P_MII0_ETxEN, \
29 P_MII0_ERxD0, \
30 P_MII0_ERxD1, \
31 P_MII0_ERxER, \
32 P_MII0_TxCLK, \
33 P_MII0_PHYINT, \
34 P_MII0_CRS, \
35 P_MII0_MDC, \
36 P_MII0_MDIO, 0}
37
38#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
39#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
40#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
41#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
42#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
43#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
44#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
45#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
46#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
47#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
48#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
49
50#define P_RMII1 {\
51 P_MII1_ETxD0, \
52 P_MII1_ETxD1, \
53 P_MII1_ETxEN, \
54 P_MII1_ERxD0, \
55 P_MII1_ERxD1, \
56 P_MII1_ERxER, \
57 P_MII1_TxCLK, \
58 P_MII1_PHYINT, \
59 P_MII1_CRS, \
60 P_MII1_MDC, \
61 P_MII1_MDIO, 0}
62
63/* PPI Port Mux */
64#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
65#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
66#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
67#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
68#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
69#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
70#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
71#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
72#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
73#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
74#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
75#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
76#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
77#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
78#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
79#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
80#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
81#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
82#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
83#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
84#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
85#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
86#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
87#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
88#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
89#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
90#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
91#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
92
93#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
94#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
95#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
96#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
97#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
98#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
99#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
100#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
101#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
102#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
103#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
104#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
105#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
106#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
107#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
108#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
109#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
110#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
111#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
112#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
113#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
114#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
115
116#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
117#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
118#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
119#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
120#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
121#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
122#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
123#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
124#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
125#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
126#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
127#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
128#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
129#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
130#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
131#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
132#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
133#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
134#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
135#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
136#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
137#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
138
139/* SPI Port Mux */
140#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
141#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
142#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
143#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
144#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
145#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
146#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
147
148#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
149#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
150#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
151#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
152#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
153#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
154#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
155
156#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
157#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
158#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
159#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
160#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
161#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
162#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
163
164#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
165#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
166#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
167#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
168#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
169#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
170#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
171
172#define GPIO_DEFAULT_BOOT_SPI_CS
173#define P_DEFAULT_BOOT_SPI_CS
174
175/* CORE IDLE */
176#define P_IDLEA (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
177#define P_IDLEB (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
178#define P_SLEEP (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
179
180/* UART Port Mux */
181#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
182#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
183#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
184#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
185
186#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
187#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
188#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
189#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
190
191/* Timer */
192#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
193#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
194#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
195#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
196#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
197#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
198#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
199#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
200#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
201
202/* RSI */
203#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
204#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
205#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
206#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
207#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
208#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
209#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
210#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
211#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
212#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
213
214/* PTP */
215#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
216#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
217#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
218
219#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
220#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
221#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
222
223/* SMC Port Mux */
224#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
225#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
226#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
227#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
228#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
229#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
230#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
231#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
232#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
233#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
234#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
235#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
236#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
237#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
238#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
239#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
240#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
241#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
242#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
243#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
244#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
245#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
246#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
247#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
248
249#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
250#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
251#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
252
253/* CAN */
254#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
255#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
256
257/* SPORT */
258#define P_SPORT0_ACLK (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2))
259#define P_SPORT0_AFS (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2))
260#define P_SPORT0_AD0 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2))
261#define P_SPORT0_AD1 (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2))
262#define P_SPORT0_ATDV (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1))
263#define P_SPORT0_BCLK (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2))
264#define P_SPORT0_BFS (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2))
265#define P_SPORT0_BD0 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2))
266#define P_SPORT0_BD1 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2))
267#define P_SPORT0_BTDV (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1))
268
269#define P_SPORT1_ACLK (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2))
270#define P_SPORT1_AFS (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2))
271#define P_SPORT1_AD0 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
272#define P_SPORT1_AD1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
273#define P_SPORT1_ATDV (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
274#define P_SPORT1_BCLK (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2))
275#define P_SPORT1_BFS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2))
276#define P_SPORT1_BD0 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2))
277#define P_SPORT1_BD1 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2))
278#define P_SPORT1_BTDV (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
279
280#define P_SPORT2_ACLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
281#define P_SPORT2_AFS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
282#define P_SPORT2_AD0 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
283#define P_SPORT2_AD1 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
284#define P_SPORT2_ATDV (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1))
285#define P_SPORT2_BCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
286#define P_SPORT2_BFS (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
287#define P_SPORT2_BD0 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
288#define P_SPORT2_BD1 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
289#define P_SPORT2_BTDV (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
290
291/* LINK PORT */
292#define P_LP0_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2))
293#define P_LP0_ACK (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2))
294#define P_LP0_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2))
295#define P_LP0_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2))
296#define P_LP0_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2))
297#define P_LP0_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2))
298#define P_LP0_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2))
299#define P_LP0_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2))
300#define P_LP0_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2))
301#define P_LP0_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2))
302
303#define P_LP1_CLK (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2))
304#define P_LP1_ACK (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2))
305#define P_LP1_D0 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2))
306#define P_LP1_D1 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2))
307#define P_LP1_D2 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2))
308#define P_LP1_D3 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2))
309#define P_LP1_D4 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2))
310#define P_LP1_D5 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2))
311#define P_LP1_D6 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2))
312#define P_LP1_D7 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2))
313
314#define P_LP2_CLK (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2))
315#define P_LP2_ACK (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2))
316#define P_LP2_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
317#define P_LP2_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
318#define P_LP2_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
319#define P_LP2_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
320#define P_LP2_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
321#define P_LP2_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
322#define P_LP2_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
323#define P_LP2_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
324
325#define P_LP3_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2))
326#define P_LP3_ACK (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2))
327#define P_LP3_D0 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
328#define P_LP3_D1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
329#define P_LP3_D2 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
330#define P_LP3_D3 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
331#define P_LP3_D4 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
332#define P_LP3_D5 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
333#define P_LP3_D6 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
334#define P_LP3_D7 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
335
336/* TWI */
337#define P_TWI0_SCL (P_DONTCARE)
338#define P_TWI0_SDA (P_DONTCARE)
339#define P_TWI1_SCL (P_DONTCARE)
340#define P_TWI1_SDA (P_DONTCARE)
341
342/* Rotary Encoder */
343#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3))
344#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3))
345#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3))
346
347#endif /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
new file mode 100644
index 000000000000..b76966eb16ad
--- /dev/null
+++ b/arch/blackfin/mach-bf609/pm.c
@@ -0,0 +1,362 @@
1/*
2 * Blackfin bf609 power management
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2
7 */
8
9#include <linux/suspend.h>
10#include <linux/io.h>
11#include <linux/interrupt.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14
15#include <linux/delay.h>
16
17#include <asm/dpmc.h>
18#include <asm/pm.h>
19#include <mach/pm.h>
20#include <asm/blackfin.h>
21
22/***********************************************************/
23/* */
24/* Wakeup Actions for DPM_RESTORE */
25/* */
26/***********************************************************/
27#define BITP_ROM_WUA_CHKHDR 24
28#define BITP_ROM_WUA_DDRLOCK 7
29#define BITP_ROM_WUA_DDRDLLEN 6
30#define BITP_ROM_WUA_DDR 5
31#define BITP_ROM_WUA_CGU 4
32#define BITP_ROM_WUA_MEMBOOT 2
33#define BITP_ROM_WUA_EN 1
34
35#define BITM_ROM_WUA_CHKHDR (0xFF000000)
36#define ENUM_ROM_WUA_CHKHDR_AD 0xAD000000
37
38#define BITM_ROM_WUA_DDRLOCK (0x00000080)
39#define BITM_ROM_WUA_DDRDLLEN (0x00000040)
40#define BITM_ROM_WUA_DDR (0x00000020)
41#define BITM_ROM_WUA_CGU (0x00000010)
42#define BITM_ROM_WUA_MEMBOOT (0x00000002)
43#define BITM_ROM_WUA_EN (0x00000001)
44
45/***********************************************************/
46/* */
47/* Syscontrol */
48/* */
49/***********************************************************/
50#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN 28 /* unlocks CGU_CTL register */
51#define BITP_ROM_SYSCTRL_WUA_OVERRIDE 24
52#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN 20 /* Saves the DDR DLL and PADS registers to the DPM registers */
53#define BITP_ROM_SYSCTRL_WUA_DDR 19 /* Saves the DDR registers to the DPM registers */
54#define BITP_ROM_SYSCTRL_WUA_CGU 18 /* Saves the CGU registers into DPM registers */
55#define BITP_ROM_SYSCTRL_WUA_DPMWRITE 17 /* Saves the Syscontrol structure structure contents into DPM registers */
56#define BITP_ROM_SYSCTRL_WUA_EN 16 /* reads current PLL and DDR configuration into structure */
57#define BITP_ROM_SYSCTRL_DDR_WRITE 13 /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
58#define BITP_ROM_SYSCTRL_DDR_READ 12 /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
59#define BITP_ROM_SYSCTRL_CGU_AUTODIS 11 /* Disables auto handling of UPDT and ALGN fields */
60#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL 7 /* access CGU_CLKOUTSEL register */
61#define BITP_ROM_SYSCTRL_CGU_DIV 6 /* access CGU_DIV register */
62#define BITP_ROM_SYSCTRL_CGU_STAT 5 /* access CGU_STAT register */
63#define BITP_ROM_SYSCTRL_CGU_CTL 4 /* access CGU_CTL register */
64#define BITP_ROM_SYSCTRL_CGU_RTNSTAT 2 /* Update structure STAT field upon error */
65#define BITP_ROM_SYSCTRL_WRITE 1 /* write registers */
66#define BITP_ROM_SYSCTRL_READ 0 /* read registers */
67
68#define BITM_ROM_SYSCTRL_CGU_READ (0x00000001) /* Read CGU registers */
69#define BITM_ROM_SYSCTRL_CGU_WRITE (0x00000002) /* Write registers */
70#define BITM_ROM_SYSCTRL_CGU_RTNSTAT (0x00000004) /* Update structure STAT field upon error or after a write operation */
71#define BITM_ROM_SYSCTRL_CGU_CTL (0x00000010) /* Access CGU_CTL register */
72#define BITM_ROM_SYSCTRL_CGU_STAT (0x00000020) /* Access CGU_STAT register */
73#define BITM_ROM_SYSCTRL_CGU_DIV (0x00000040) /* Access CGU_DIV register */
74#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL (0x00000080) /* Access CGU_CLKOUTSEL register */
75#define BITM_ROM_SYSCTRL_CGU_AUTODIS (0x00000800) /* Disables auto handling of UPDT and ALGN fields */
76#define BITM_ROM_SYSCTRL_DDR_READ (0x00001000) /* Reads the contents of the DDR registers and stores them into the structure */
77#define BITM_ROM_SYSCTRL_DDR_WRITE (0x00002000) /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
78#define BITM_ROM_SYSCTRL_WUA_EN (0x00010000) /* Wakeup entry or exit opertation enable */
79#define BITM_ROM_SYSCTRL_WUA_DPMWRITE (0x00020000) /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
80#define BITM_ROM_SYSCTRL_WUA_CGU (0x00040000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
81#define BITM_ROM_SYSCTRL_WUA_DDR (0x00080000) /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
82#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN (0x00100000) /* Enables saving/restoring of the DDR DLLCTL register */
83#define BITM_ROM_SYSCTRL_WUA_OVERRIDE (0x01000000)
84#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN (0x10000000) /* Unlocks the CGU_CTL register */
85
86
87/* Structures for the syscontrol() function */
88struct STRUCT_ROM_SYSCTRL {
89 uint32_t ulCGU_CTL;
90 uint32_t ulCGU_STAT;
91 uint32_t ulCGU_DIV;
92 uint32_t ulCGU_CLKOUTSEL;
93 uint32_t ulWUA_Flags;
94 uint32_t ulWUA_BootAddr;
95 uint32_t ulWUA_User;
96 uint32_t ulDDR_CTL;
97 uint32_t ulDDR_CFG;
98 uint32_t ulDDR_TR0;
99 uint32_t ulDDR_TR1;
100 uint32_t ulDDR_TR2;
101 uint32_t ulDDR_MR;
102 uint32_t ulDDR_EMR1;
103 uint32_t ulDDR_EMR2;
104 uint32_t ulDDR_PADCTL;
105 uint32_t ulDDR_DLLCTL;
106 uint32_t ulReserved;
107};
108
109struct bfin_pm_data {
110 uint32_t magic;
111 uint32_t resume_addr;
112 uint32_t sp;
113};
114
115struct bfin_pm_data bf609_pm_data;
116
117struct STRUCT_ROM_SYSCTRL configvalues;
118uint32_t dactionflags;
119
120#define FUNC_ROM_SYSCONTROL 0xC8000080
121__attribute__((l1_data))
122static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
123
124__attribute__((l1_text))
125void bfin_cpu_suspend(void)
126{
127 __asm__ __volatile__( \
128 ".align 8;" \
129 "idle;" \
130 : : \
131 );
132}
133
134__attribute__((l1_text))
135void bfin_deepsleep(unsigned long mask)
136{
137 uint32_t dpm0_ctl;
138
139 bfin_write32(DPM0_WAKE_EN, 0x10);
140 bfin_write32(DPM0_WAKE_POL, 0x10);
141 dpm0_ctl = 0x00000008;
142 bfin_write32(DPM0_CTL, dpm0_ctl);
143 SSYNC();
144 __asm__ __volatile__( \
145 ".align 8;" \
146 "idle;" \
147 : : \
148 );
149#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
150 __asm__ __volatile__(
151 "R0 = 0;"
152 "CYCLES = R0;"
153 "CYCLES2 = R0;"
154 "R0 = SYSCFG;"
155 "BITSET(R0, 1);"
156 "SYSCFG = R0;"
157 : : : "R0"
158 );
159#endif
160
161}
162
163__attribute__((l1_text))
164void bf609_ddr_sr(void)
165{
166 uint32_t reg;
167
168 reg = bfin_read_DMC0_CTL();
169 reg |= 0x8;
170 bfin_write_DMC0_CTL(reg);
171
172 while (!(bfin_read_DMC0_STAT() & 0x8))
173 continue;
174}
175
176__attribute__((l1_text))
177void bf609_ddr_sr_exit(void)
178{
179 uint32_t reg;
180 while (!(bfin_read_DMC0_STAT() & 0x1))
181 continue;
182
183 reg = bfin_read_DMC0_CTL();
184 reg &= ~0x8;
185 bfin_write_DMC0_CTL(reg);
186
187 while ((bfin_read_DMC0_STAT() & 0x8))
188 continue;
189}
190
191__attribute__((l1_text))
192void bfin_hibernate_syscontrol(void)
193{
194 configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
195 | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
196
197 dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
198 | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
199 | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
200
201 bfrom_SysControl(dactionflags, &configvalues, NULL);
202
203 bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
204}
205
206#ifndef CONFIG_BF60x
207# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
208#else
209# define SIC_SYSIRQ(irq) ((irq) - IVG15)
210#endif
211void bfin_hibernate(unsigned long mask)
212{
213 bfin_write32(DPM0_WAKE_EN, 0x10);
214 bfin_write32(DPM0_WAKE_POL, 0x10);
215 bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
216 bfin_write32(DPM0_HIB_DIS, 0xFFFF);
217
218 printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR));
219
220 bf609_hibernate();
221}
222
223void bf609_cpu_pm_enter(suspend_state_t state)
224{
225 int error;
226 unsigned long wakeup = 0;
227 unsigned long wakeup_pol = 0;
228
229#ifdef CONFIG_PM_BFIN_WAKE_PA15
230 wakeup |= PA15WE;
231# if CONFIG_PM_BFIN_WAKE_PA15_POL
232 wakeup_pol |= PA15WE;
233# endif
234#endif
235
236#ifdef CONFIG_PM_BFIN_WAKE_PB15
237 wakeup |= PB15WE;
238# if CONFIG_PM_BFIN_WAKE_PA15_POL
239 wakeup_pol |= PB15WE;
240# endif
241#endif
242
243#ifdef CONFIG_PM_BFIN_WAKE_PC15
244 wakeup |= PC15WE;
245# if CONFIG_PM_BFIN_WAKE_PC15_POL
246 wakeup_pol |= PC15WE;
247# endif
248#endif
249
250#ifdef CONFIG_PM_BFIN_WAKE_PD06
251 wakeup |= PD06WE;
252# if CONFIG_PM_BFIN_WAKE_PD06_POL
253 wakeup_pol |= PD06WE;
254# endif
255#endif
256
257#ifdef CONFIG_PM_BFIN_WAKE_PE12
258 wakeup |= PE12WE;
259# if CONFIG_PM_BFIN_WAKE_PE12_POL
260 wakeup_pol |= PE12WE;
261# endif
262#endif
263
264#ifdef CONFIG_PM_BFIN_WAKE_PG04
265 wakeup |= PG04WE;
266# if CONFIG_PM_BFIN_WAKE_PG04_POL
267 wakeup_pol |= PG04WE;
268# endif
269#endif
270
271#ifdef CONFIG_PM_BFIN_WAKE_PG13
272 wakeup |= PG13WE;
273# if CONFIG_PM_BFIN_WAKE_PG13_POL
274 wakeup_pol |= PG13WE;
275# endif
276#endif
277
278#ifdef CONFIG_PM_BFIN_WAKE_USB
279 wakeup |= USBWE;
280# if CONFIG_PM_BFIN_WAKE_USB_POL
281 wakeup_pol |= USBWE;
282# endif
283#endif
284
285 error = irq_set_irq_wake(255, 1);
286 if(error < 0)
287 printk(KERN_DEBUG "Unable to get irq wake\n");
288 error = irq_set_irq_wake(231, 1);
289 if (error < 0)
290 printk(KERN_DEBUG "Unable to get irq wake\n");
291
292 if (state == PM_SUSPEND_STANDBY)
293 bfin_deepsleep(wakeup);
294 else {
295 bfin_hibernate(wakeup);
296 }
297}
298
299int bf609_cpu_pm_prepare(void)
300{
301 return 0;
302}
303
304void bf609_cpu_pm_finish(void)
305{
306
307}
308
309static struct bfin_cpu_pm_fns bf609_cpu_pm = {
310 .enter = bf609_cpu_pm_enter,
311 .prepare = bf609_cpu_pm_prepare,
312 .finish = bf609_cpu_pm_finish,
313};
314
315static irqreturn_t test_isr(int irq, void *dev_id)
316{
317 printk(KERN_DEBUG "gpio irq %d\n", irq);
318 return IRQ_HANDLED;
319}
320
321static irqreturn_t dpm0_isr(int irq, void *dev_id)
322{
323 uint32_t wake_stat;
324
325 wake_stat = bfin_read32(DPM0_WAKE_STAT);
326 printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat);
327
328 bfin_write32(DPM0_WAKE_STAT, wake_stat);
329 return IRQ_HANDLED;
330}
331
332static int __init bf609_init_pm(void)
333{
334 int irq;
335 int error;
336
337#if CONFIG_PM_BFIN_WAKE_PE12
338 irq = gpio_to_irq(GPIO_PE12);
339 if (irq < 0) {
340 error = irq;
341 printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
342 GPIO_PE12, error);
343 }
344
345 error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL);
346 if(error < 0)
347 printk(KERN_DEBUG "Unable to get irq\n");
348#endif
349
350 error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
351 if(error < 0)
352 printk(KERN_DEBUG "Unable to get irq\n");
353
354 error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
355 if (error < 0)
356 printk(KERN_DEBUG "Unable to get irq\n");
357
358 bfin_cpu_pm = &bf609_cpu_pm;
359 return 0;
360}
361
362late_initcall(bf609_init_pm);
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index ff299f24aba0..75f0ba29ebb9 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -6,7 +6,10 @@ obj-y := \
6 cache.o cache-c.o entry.o head.o \ 6 cache.o cache-c.o entry.o head.o \
7 interrupt.o arch_checks.o ints-priority.o 7 interrupt.o arch_checks.o ints-priority.o
8 8
9obj-$(CONFIG_PM) += pm.o dpmc_modes.o 9obj-$(CONFIG_PM) += pm.o
10ifneq ($(CONFIG_BF60x),y)
11obj-$(CONFIG_PM) += dpmc_modes.o
12endif
10obj-$(CONFIG_CPU_FREQ) += cpufreq.o 13obj-$(CONFIG_CPU_FREQ) += cpufreq.o
11obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o 14obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
12obj-$(CONFIG_SMP) += smp.o 15obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h
new file mode 100644
index 000000000000..645ff460a1f2
--- /dev/null
+++ b/arch/blackfin/mach-common/clock.h
@@ -0,0 +1,27 @@
1#ifndef __MACH_COMMON_CLKDEV_H
2#define __MACH_COMMON_CLKDEV_H
3
4#include <linux/clk.h>
5
6struct clk_ops {
7 unsigned long (*get_rate)(struct clk *clk);
8 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
9 int (*set_rate)(struct clk *clk, unsigned long rate);
10 int (*enable)(struct clk *clk);
11 int (*disable)(struct clk *clk);
12};
13
14struct clk {
15 const char *name;
16 unsigned long rate;
17 spinlock_t lock;
18 u32 flags;
19 const struct clk_ops *ops;
20 const struct params *params;
21 void __iomem *reg;
22 u32 mask;
23 u32 shift;
24};
25
26#endif
27
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index d5cfe611b778..7ad2407d1571 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -15,10 +15,121 @@
15#include <asm/mem_init.h> 15#include <asm/mem_init.h>
16#include <asm/dpmc.h> 16#include <asm/dpmc.h>
17 17
18#ifdef CONFIG_BF60x
19#define CSEL_P 0
20#define S0SEL_P 5
21#define SYSSEL_P 8
22#define S1SEL_P 13
23#define DSEL_P 16
24#define OSEL_P 22
25#define ALGN_P 29
26#define UPDT_P 30
27#define LOCK_P 31
28
29#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
30#define CGU_DIV_VAL \
31 ((CONFIG_CCLK_DIV << CSEL_P) | \
32 (CONFIG_SCLK_DIV << SYSSEL_P) | \
33 (CONFIG_SCLK0_DIV << S0SEL_P) | \
34 (CONFIG_SCLK1_DIV << S1SEL_P) | \
35 (CONFIG_DCLK_DIV << DSEL_P))
36
37#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
38#if ((CONFIG_BFIN_DCLK != 125) && \
39 (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
40 (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
41 (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
42#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
43#endif
44struct ddr_config {
45 u32 ddr_clk;
46 u32 dmc_ddrctl;
47 u32 dmc_ddrcfg;
48 u32 dmc_ddrtr0;
49 u32 dmc_ddrtr1;
50 u32 dmc_ddrtr2;
51 u32 dmc_ddrmr;
52 u32 dmc_ddrmr1;
53};
54
55struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
56 [0] = {
57 .ddr_clk = 125,
58 .dmc_ddrctl = 0x00000904,
59 .dmc_ddrcfg = 0x00000422,
60 .dmc_ddrtr0 = 0x20705212,
61 .dmc_ddrtr1 = 0x201003CF,
62 .dmc_ddrtr2 = 0x00320107,
63 .dmc_ddrmr = 0x00000422,
64 .dmc_ddrmr1 = 0x4,
65 },
66 [1] = {
67 .ddr_clk = 133,
68 .dmc_ddrctl = 0x00000904,
69 .dmc_ddrcfg = 0x00000422,
70 .dmc_ddrtr0 = 0x20806313,
71 .dmc_ddrtr1 = 0x2013040D,
72 .dmc_ddrtr2 = 0x00320108,
73 .dmc_ddrmr = 0x00000632,
74 .dmc_ddrmr1 = 0x4,
75 },
76 [2] = {
77 .ddr_clk = 150,
78 .dmc_ddrctl = 0x00000904,
79 .dmc_ddrcfg = 0x00000422,
80 .dmc_ddrtr0 = 0x20A07323,
81 .dmc_ddrtr1 = 0x20160492,
82 .dmc_ddrtr2 = 0x00320209,
83 .dmc_ddrmr = 0x00000632,
84 .dmc_ddrmr1 = 0x4,
85 },
86 [3] = {
87 .ddr_clk = 166,
88 .dmc_ddrctl = 0x00000904,
89 .dmc_ddrcfg = 0x00000422,
90 .dmc_ddrtr0 = 0x20A07323,
91 .dmc_ddrtr1 = 0x2016050E,
92 .dmc_ddrtr2 = 0x00320209,
93 .dmc_ddrmr = 0x00000632,
94 .dmc_ddrmr1 = 0x4,
95 },
96 [4] = {
97 .ddr_clk = 200,
98 .dmc_ddrctl = 0x00000904,
99 .dmc_ddrcfg = 0x00000422,
100 .dmc_ddrtr0 = 0x20a07323,
101 .dmc_ddrtr1 = 0x2016050f,
102 .dmc_ddrtr2 = 0x00320509,
103 .dmc_ddrmr = 0x00000632,
104 .dmc_ddrmr1 = 0x4,
105 },
106 [5] = {
107 .ddr_clk = 225,
108 .dmc_ddrctl = 0x00000904,
109 .dmc_ddrcfg = 0x00000422,
110 .dmc_ddrtr0 = 0x20E0A424,
111 .dmc_ddrtr1 = 0x302006DB,
112 .dmc_ddrtr2 = 0x0032020D,
113 .dmc_ddrmr = 0x00000842,
114 .dmc_ddrmr1 = 0x4,
115 },
116 [6] = {
117 .ddr_clk = 250,
118 .dmc_ddrctl = 0x00000904,
119 .dmc_ddrcfg = 0x00000422,
120 .dmc_ddrtr0 = 0x20E0A424,
121 .dmc_ddrtr1 = 0x3020079E,
122 .dmc_ddrtr2 = 0x0032020D,
123 .dmc_ddrmr = 0x00000842,
124 .dmc_ddrmr1 = 0x4,
125 },
126};
127#else
18#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ 128#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
19#define PLL_CTL_VAL \ 129#define PLL_CTL_VAL \
20 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ 130 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
21 (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) 131 (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
132#endif
22 133
23__attribute__((l1_text)) 134__attribute__((l1_text))
24static void do_sync(void) 135static void do_sync(void)
@@ -33,6 +144,44 @@ void init_clocks(void)
33 * in the middle of reprogramming things, and that'll screw us up. 144 * in the middle of reprogramming things, and that'll screw us up.
34 * For example, any automatic DMAs left by U-Boot for splash screens. 145 * For example, any automatic DMAs left by U-Boot for splash screens.
35 */ 146 */
147
148#ifdef CONFIG_BF60x
149 int i, dlldatacycle, dll_ctl;
150 bfin_write32(CGU0_DIV, CGU_DIV_VAL);
151 bfin_write32(CGU0_CTL, CGU_CTL_VAL);
152 while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4))
153 continue;
154
155 bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P));
156 while (bfin_read32(CGU0_STAT) & (1 << 3))
157 continue;
158
159 for (i = 0; i < 7; i++) {
160 if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) {
161 bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg);
162 bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0);
163 bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1);
164 bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2);
165 bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr);
166 bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1);
167 bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl);
168 break;
169 }
170 }
171
172 do_sync();
173 while (!(bfin_read_DDR0_STAT() & 0x4))
174 continue;
175
176 dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20;
177 dll_ctl = bfin_read_DDR0_DLLCTL();
178 dll_ctl &= 0x0ff;
179 bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8));
180
181 do_sync();
182 while (!(bfin_read_DDR0_STAT() & 0x2000))
183 continue;
184#else
36 size_t i; 185 size_t i;
37 for (i = 0; i < MAX_DMA_CHANNELS; ++i) { 186 for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
38 struct dma_register *dma = dma_io_base_addr[i]; 187 struct dma_register *dma = dma_io_base_addr[i];
@@ -91,6 +240,8 @@ void init_clocks(void)
91 bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE); 240 bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
92#endif 241#endif
93#endif 242#endif
243#endif
94 do_sync(); 244 do_sync();
95 bfin_read16(0); 245 bfin_read16(0);
246
96} 247}
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 2e6eefd812f4..6e87dc13f6bf 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -10,6 +10,7 @@
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/types.h> 11#include <linux/types.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/clk.h>
13#include <linux/cpufreq.h> 14#include <linux/cpufreq.h>
14#include <linux/fs.h> 15#include <linux/fs.h>
15#include <linux/delay.h> 16#include <linux/delay.h>
@@ -17,6 +18,7 @@
17#include <asm/time.h> 18#include <asm/time.h>
18#include <asm/dpmc.h> 19#include <asm/dpmc.h>
19 20
21
20/* this is the table of CCLK frequencies, in Hz */ 22/* this is the table of CCLK frequencies, in Hz */
21/* .index is the entry in the auxiliary dpm_state_table[] */ 23/* .index is the entry in the auxiliary dpm_state_table[] */
22static struct cpufreq_frequency_table bfin_freq_table[] = { 24static struct cpufreq_frequency_table bfin_freq_table[] = {
@@ -67,12 +69,22 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
67#else 69#else
68 min_cclk = sclk; 70 min_cclk = sclk;
69#endif 71#endif
72
73#ifndef CONFIG_BF60x
70 csel = ((bfin_read_PLL_DIV() & CSEL) >> 4); 74 csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
75#else
76 csel = bfin_read32(CGU0_DIV) & 0x1F;
77#endif
71 78
72 for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { 79 for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
73 bfin_freq_table[index].frequency = cclk >> index; 80 bfin_freq_table[index].frequency = cclk >> index;
81#ifndef CONFIG_BF60x
74 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ 82 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
75 dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1; 83 dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1;
84#else
85 dpm_state_table[index].csel = csel;
86 dpm_state_table[index].tscale = TIME_SCALE >> index;
87#endif
76 88
77 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", 89 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
78 bfin_freq_table[index].frequency, 90 bfin_freq_table[index].frequency,
@@ -99,14 +111,34 @@ static unsigned int bfin_getfreq_khz(unsigned int cpu)
99 return get_cclk() / 1000; 111 return get_cclk() / 1000;
100} 112}
101 113
114#ifdef CONFIG_BF60x
115unsigned long cpu_set_cclk(int cpu, unsigned long new)
116{
117 struct clk *clk;
118 int ret;
119
120 clk = clk_get(NULL, "CCLK");
121 if (IS_ERR(clk))
122 return -ENODEV;
123
124 ret = clk_set_rate(clk, new);
125 clk_put(clk);
126 return ret;
127}
128#endif
129
102static int bfin_target(struct cpufreq_policy *poli, 130static int bfin_target(struct cpufreq_policy *poli,
103 unsigned int target_freq, unsigned int relation) 131 unsigned int target_freq, unsigned int relation)
104{ 132{
105 unsigned int index, plldiv, cpu; 133#ifndef CONFIG_BF60x
134 unsigned int plldiv;
135#endif
136 unsigned int index, cpu;
106 unsigned long flags, cclk_hz; 137 unsigned long flags, cclk_hz;
107 struct cpufreq_freqs freqs; 138 struct cpufreq_freqs freqs;
108 static unsigned long lpj_ref; 139 static unsigned long lpj_ref;
109 static unsigned int lpj_ref_freq; 140 static unsigned int lpj_ref_freq;
141 int ret = 0;
110 142
111#if defined(CONFIG_CYCLES_CLOCKSOURCE) 143#if defined(CONFIG_CYCLES_CLOCKSOURCE)
112 cycles_t cycles; 144 cycles_t cycles;
@@ -134,9 +166,17 @@ static int bfin_target(struct cpufreq_policy *poli,
134 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 166 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
135 if (cpu == CPUFREQ_CPU) { 167 if (cpu == CPUFREQ_CPU) {
136 flags = hard_local_irq_save(); 168 flags = hard_local_irq_save();
169#ifndef CONFIG_BF60x
137 plldiv = (bfin_read_PLL_DIV() & SSEL) | 170 plldiv = (bfin_read_PLL_DIV() & SSEL) |
138 dpm_state_table[index].csel; 171 dpm_state_table[index].csel;
139 bfin_write_PLL_DIV(plldiv); 172 bfin_write_PLL_DIV(plldiv);
173#else
174 ret = cpu_set_cclk(cpu, freqs.new * 1000);
175 if (ret != 0) {
176 pr_debug("cpufreq set freq failed %d\n", ret);
177 break;
178 }
179#endif
140 on_each_cpu(bfin_adjust_core_timer, &index, 1); 180 on_each_cpu(bfin_adjust_core_timer, &index, 1);
141#if defined(CONFIG_CYCLES_CLOCKSOURCE) 181#if defined(CONFIG_CYCLES_CLOCKSOURCE)
142 cycles = get_cycles(); 182 cycles = get_cycles();
@@ -161,7 +201,7 @@ static int bfin_target(struct cpufreq_policy *poli,
161 } 201 }
162 202
163 pr_debug("cpufreq: done\n"); 203 pr_debug("cpufreq: done\n");
164 return 0; 204 return ret;
165} 205}
166 206
167static int bfin_verify_speed(struct cpufreq_policy *policy) 207static int bfin_verify_speed(struct cpufreq_policy *policy)
@@ -169,7 +209,7 @@ static int bfin_verify_speed(struct cpufreq_policy *policy)
169 return cpufreq_frequency_table_verify(policy, bfin_freq_table); 209 return cpufreq_frequency_table_verify(policy, bfin_freq_table);
170} 210}
171 211
172static int __init __bfin_cpu_init(struct cpufreq_policy *policy) 212static int __bfin_cpu_init(struct cpufreq_policy *policy)
173{ 213{
174 214
175 unsigned long cclk, sclk; 215 unsigned long cclk, sclk;
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 1c534d298de4..de99f3aac2c5 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -10,7 +10,6 @@
10#include <asm/dpmc.h> 10#include <asm/dpmc.h>
11 11
12.section .l1.text 12.section .l1.text
13
14ENTRY(_sleep_mode) 13ENTRY(_sleep_mode)
15 [--SP] = (R7:4, P5:3); 14 [--SP] = (R7:4, P5:3);
16 [--SP] = RETS; 15 [--SP] = RETS;
@@ -43,6 +42,9 @@ ENTRY(_sleep_mode)
43 BITCLR (R7, 5); 42 BITCLR (R7, 5);
44 w[p0] = R7.L; 43 w[p0] = R7.L;
45 IDLE; 44 IDLE;
45
46 bfin_init_pm_bench_cycles;
47
46 call _test_pll_locked; 48 call _test_pll_locked;
47 49
48 RETS = [SP++]; 50 RETS = [SP++];
@@ -58,12 +60,13 @@ ENDPROC(_sleep_mode)
58 * 60 *
59 * We accept just one argument -- the value to write to VR_CTL. 61 * We accept just one argument -- the value to write to VR_CTL.
60 */ 62 */
63
61ENTRY(_hibernate_mode) 64ENTRY(_hibernate_mode)
62 /* Save/setup the regs we need early for minor pipeline optimization */ 65 /* Save/setup the regs we need early for minor pipeline optimization */
63 R4 = R0; 66 R4 = R0;
67
64 P3.H = hi(VR_CTL); 68 P3.H = hi(VR_CTL);
65 P3.L = lo(VR_CTL); 69 P3.L = lo(VR_CTL);
66
67 /* Disable all wakeup sources */ 70 /* Disable all wakeup sources */
68 R0 = IWR_DISABLE_ALL; 71 R0 = IWR_DISABLE_ALL;
69 R1 = IWR_DISABLE_ALL; 72 R1 = IWR_DISABLE_ALL;
@@ -74,6 +77,9 @@ ENTRY(_hibernate_mode)
74 77
75 /* Finally, we climb into our cave to hibernate */ 78 /* Finally, we climb into our cave to hibernate */
76 W[P3] = R4.L; 79 W[P3] = R4.L;
80
81 bfin_init_pm_bench_cycles;
82
77 CLI R2; 83 CLI R2;
78 IDLE; 84 IDLE;
79.Lforever: 85.Lforever:
@@ -158,6 +164,8 @@ ENTRY(_sleep_deeper)
158 SSYNC; 164 SSYNC;
159 IDLE; 165 IDLE;
160 166
167 bfin_init_pm_bench_cycles;
168
161 call _test_pll_locked; 169 call _test_pll_locked;
162 170
163 P0.H = hi(PLL_DIV); 171 P0.H = hi(PLL_DIV);
@@ -276,327 +284,10 @@ ENTRY(_test_pll_locked)
276ENDPROC(_test_pll_locked) 284ENDPROC(_test_pll_locked)
277 285
278.section .text 286.section .text
279
280#define PM_REG0 R7
281#define PM_REG1 R6
282#define PM_REG2 R5
283#define PM_REG3 R4
284#define PM_REG4 R3
285#define PM_REG5 R2
286#define PM_REG6 R1
287#define PM_REG7 R0
288#define PM_REG8 P5
289#define PM_REG9 P4
290#define PM_REG10 P3
291#define PM_REG11 P2
292#define PM_REG12 P1
293#define PM_REG13 P0
294
295#define PM_REGSET0 R7:7
296#define PM_REGSET1 R7:6
297#define PM_REGSET2 R7:5
298#define PM_REGSET3 R7:4
299#define PM_REGSET4 R7:3
300#define PM_REGSET5 R7:2
301#define PM_REGSET6 R7:1
302#define PM_REGSET7 R7:0
303#define PM_REGSET8 R7:0, P5:5
304#define PM_REGSET9 R7:0, P5:4
305#define PM_REGSET10 R7:0, P5:3
306#define PM_REGSET11 R7:0, P5:2
307#define PM_REGSET12 R7:0, P5:1
308#define PM_REGSET13 R7:0, P5:0
309
310#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
311#define _PM_POP(n, x, w, base) w[FP + ((x) - (base))] = PM_REG##n;
312#define PM_PUSH_SYNC(n) [--sp] = (PM_REGSET##n);
313#define PM_POP_SYNC(n) (PM_REGSET##n) = [sp++];
314#define PM_PUSH(n, x) PM_REG##n = [FP++];
315#define PM_POP(n, x) [FP--] = PM_REG##n;
316#define PM_CORE_PUSH(n, x) _PM_PUSH(n, x, , COREMMR_BASE)
317#define PM_CORE_POP(n, x) _PM_POP(n, x, , COREMMR_BASE)
318#define PM_SYS_PUSH(n, x) _PM_PUSH(n, x, , SYSMMR_BASE)
319#define PM_SYS_POP(n, x) _PM_POP(n, x, , SYSMMR_BASE)
320#define PM_SYS_PUSH16(n, x) _PM_PUSH(n, x, w, SYSMMR_BASE)
321#define PM_SYS_POP16(n, x) _PM_POP(n, x, w, SYSMMR_BASE)
322
323ENTRY(_do_hibernate) 287ENTRY(_do_hibernate)
324 /* 288 bfin_cpu_reg_save;
325 * Save the core regs early so we can blow them away when 289 bfin_sys_mmr_save;
326 * saving/restoring MMR states 290 bfin_core_mmr_save;
327 */
328 [--sp] = (R7:0, P5:0);
329 [--sp] = fp;
330 [--sp] = usp;
331
332 [--sp] = i0;
333 [--sp] = i1;
334 [--sp] = i2;
335 [--sp] = i3;
336
337 [--sp] = m0;
338 [--sp] = m1;
339 [--sp] = m2;
340 [--sp] = m3;
341
342 [--sp] = l0;
343 [--sp] = l1;
344 [--sp] = l2;
345 [--sp] = l3;
346
347 [--sp] = b0;
348 [--sp] = b1;
349 [--sp] = b2;
350 [--sp] = b3;
351 [--sp] = a0.x;
352 [--sp] = a0.w;
353 [--sp] = a1.x;
354 [--sp] = a1.w;
355
356 [--sp] = LC0;
357 [--sp] = LC1;
358 [--sp] = LT0;
359 [--sp] = LT1;
360 [--sp] = LB0;
361 [--sp] = LB1;
362
363 /* We can't push RETI directly as that'll change IPEND[4] */
364 r7 = RETI;
365 [--sp] = RETS;
366 [--sp] = ASTAT;
367 [--sp] = CYCLES;
368 [--sp] = CYCLES2;
369 [--sp] = SYSCFG;
370 [--sp] = RETX;
371 [--sp] = SEQSTAT;
372 [--sp] = r7;
373
374 /* Save first func arg in M3 */
375 M3 = R0;
376
377 /* Save system MMRs */
378 FP.H = hi(SYSMMR_BASE);
379 FP.L = lo(SYSMMR_BASE);
380
381#ifdef SIC_IMASK0
382 PM_SYS_PUSH(0, SIC_IMASK0)
383 PM_SYS_PUSH(1, SIC_IMASK1)
384# ifdef SIC_IMASK2
385 PM_SYS_PUSH(2, SIC_IMASK2)
386# endif
387#else
388 PM_SYS_PUSH(0, SIC_IMASK)
389#endif
390#ifdef SIC_IAR0
391 PM_SYS_PUSH(3, SIC_IAR0)
392 PM_SYS_PUSH(4, SIC_IAR1)
393 PM_SYS_PUSH(5, SIC_IAR2)
394#endif
395#ifdef SIC_IAR3
396 PM_SYS_PUSH(6, SIC_IAR3)
397#endif
398#ifdef SIC_IAR4
399 PM_SYS_PUSH(7, SIC_IAR4)
400 PM_SYS_PUSH(8, SIC_IAR5)
401 PM_SYS_PUSH(9, SIC_IAR6)
402#endif
403#ifdef SIC_IAR7
404 PM_SYS_PUSH(10, SIC_IAR7)
405#endif
406#ifdef SIC_IAR8
407 PM_SYS_PUSH(11, SIC_IAR8)
408 PM_SYS_PUSH(12, SIC_IAR9)
409 PM_SYS_PUSH(13, SIC_IAR10)
410#endif
411 PM_PUSH_SYNC(13)
412#ifdef SIC_IAR11
413 PM_SYS_PUSH(0, SIC_IAR11)
414#endif
415
416#ifdef SIC_IWR
417 PM_SYS_PUSH(1, SIC_IWR)
418#endif
419#ifdef SIC_IWR0
420 PM_SYS_PUSH(1, SIC_IWR0)
421#endif
422#ifdef SIC_IWR1
423 PM_SYS_PUSH(2, SIC_IWR1)
424#endif
425#ifdef SIC_IWR2
426 PM_SYS_PUSH(3, SIC_IWR2)
427#endif
428
429#ifdef PINT0_ASSIGN
430 PM_SYS_PUSH(4, PINT0_MASK_SET)
431 PM_SYS_PUSH(5, PINT1_MASK_SET)
432 PM_SYS_PUSH(6, PINT2_MASK_SET)
433 PM_SYS_PUSH(7, PINT3_MASK_SET)
434 PM_SYS_PUSH(8, PINT0_ASSIGN)
435 PM_SYS_PUSH(9, PINT1_ASSIGN)
436 PM_SYS_PUSH(10, PINT2_ASSIGN)
437 PM_SYS_PUSH(11, PINT3_ASSIGN)
438 PM_SYS_PUSH(12, PINT0_INVERT_SET)
439 PM_SYS_PUSH(13, PINT1_INVERT_SET)
440 PM_PUSH_SYNC(13)
441 PM_SYS_PUSH(0, PINT2_INVERT_SET)
442 PM_SYS_PUSH(1, PINT3_INVERT_SET)
443 PM_SYS_PUSH(2, PINT0_EDGE_SET)
444 PM_SYS_PUSH(3, PINT1_EDGE_SET)
445 PM_SYS_PUSH(4, PINT2_EDGE_SET)
446 PM_SYS_PUSH(5, PINT3_EDGE_SET)
447#endif
448
449 PM_SYS_PUSH16(6, SYSCR)
450
451 PM_SYS_PUSH16(7, EBIU_AMGCTL)
452 PM_SYS_PUSH(8, EBIU_AMBCTL0)
453 PM_SYS_PUSH(9, EBIU_AMBCTL1)
454#ifdef EBIU_FCTL
455 PM_SYS_PUSH(10, EBIU_MBSCTL)
456 PM_SYS_PUSH(11, EBIU_MODE)
457 PM_SYS_PUSH(12, EBIU_FCTL)
458 PM_PUSH_SYNC(12)
459#else
460 PM_PUSH_SYNC(9)
461#endif
462
463 /* Save Core MMRs */
464 I0.H = hi(COREMMR_BASE);
465 I0.L = lo(COREMMR_BASE);
466 I1 = I0;
467 I2 = I0;
468 I3 = I0;
469 B0 = I0;
470 B1 = I0;
471 B2 = I0;
472 B3 = I0;
473 I1.L = lo(DCPLB_ADDR0);
474 I2.L = lo(DCPLB_DATA0);
475 I3.L = lo(ICPLB_ADDR0);
476 B0.L = lo(ICPLB_DATA0);
477 B1.L = lo(EVT2);
478 B2.L = lo(IMASK);
479 B3.L = lo(TCNTL);
480
481 /* DCPLB Addr */
482 FP = I1;
483 PM_PUSH(0, DCPLB_ADDR0)
484 PM_PUSH(1, DCPLB_ADDR1)
485 PM_PUSH(2, DCPLB_ADDR2)
486 PM_PUSH(3, DCPLB_ADDR3)
487 PM_PUSH(4, DCPLB_ADDR4)
488 PM_PUSH(5, DCPLB_ADDR5)
489 PM_PUSH(6, DCPLB_ADDR6)
490 PM_PUSH(7, DCPLB_ADDR7)
491 PM_PUSH(8, DCPLB_ADDR8)
492 PM_PUSH(9, DCPLB_ADDR9)
493 PM_PUSH(10, DCPLB_ADDR10)
494 PM_PUSH(11, DCPLB_ADDR11)
495 PM_PUSH(12, DCPLB_ADDR12)
496 PM_PUSH(13, DCPLB_ADDR13)
497 PM_PUSH_SYNC(13)
498 PM_PUSH(0, DCPLB_ADDR14)
499 PM_PUSH(1, DCPLB_ADDR15)
500
501 /* DCPLB Data */
502 FP = I2;
503 PM_PUSH(2, DCPLB_DATA0)
504 PM_PUSH(3, DCPLB_DATA1)
505 PM_PUSH(4, DCPLB_DATA2)
506 PM_PUSH(5, DCPLB_DATA3)
507 PM_PUSH(6, DCPLB_DATA4)
508 PM_PUSH(7, DCPLB_DATA5)
509 PM_PUSH(8, DCPLB_DATA6)
510 PM_PUSH(9, DCPLB_DATA7)
511 PM_PUSH(10, DCPLB_DATA8)
512 PM_PUSH(11, DCPLB_DATA9)
513 PM_PUSH(12, DCPLB_DATA10)
514 PM_PUSH(13, DCPLB_DATA11)
515 PM_PUSH_SYNC(13)
516 PM_PUSH(0, DCPLB_DATA12)
517 PM_PUSH(1, DCPLB_DATA13)
518 PM_PUSH(2, DCPLB_DATA14)
519 PM_PUSH(3, DCPLB_DATA15)
520
521 /* ICPLB Addr */
522 FP = I3;
523 PM_PUSH(4, ICPLB_ADDR0)
524 PM_PUSH(5, ICPLB_ADDR1)
525 PM_PUSH(6, ICPLB_ADDR2)
526 PM_PUSH(7, ICPLB_ADDR3)
527 PM_PUSH(8, ICPLB_ADDR4)
528 PM_PUSH(9, ICPLB_ADDR5)
529 PM_PUSH(10, ICPLB_ADDR6)
530 PM_PUSH(11, ICPLB_ADDR7)
531 PM_PUSH(12, ICPLB_ADDR8)
532 PM_PUSH(13, ICPLB_ADDR9)
533 PM_PUSH_SYNC(13)
534 PM_PUSH(0, ICPLB_ADDR10)
535 PM_PUSH(1, ICPLB_ADDR11)
536 PM_PUSH(2, ICPLB_ADDR12)
537 PM_PUSH(3, ICPLB_ADDR13)
538 PM_PUSH(4, ICPLB_ADDR14)
539 PM_PUSH(5, ICPLB_ADDR15)
540
541 /* ICPLB Data */
542 FP = B0;
543 PM_PUSH(6, ICPLB_DATA0)
544 PM_PUSH(7, ICPLB_DATA1)
545 PM_PUSH(8, ICPLB_DATA2)
546 PM_PUSH(9, ICPLB_DATA3)
547 PM_PUSH(10, ICPLB_DATA4)
548 PM_PUSH(11, ICPLB_DATA5)
549 PM_PUSH(12, ICPLB_DATA6)
550 PM_PUSH(13, ICPLB_DATA7)
551 PM_PUSH_SYNC(13)
552 PM_PUSH(0, ICPLB_DATA8)
553 PM_PUSH(1, ICPLB_DATA9)
554 PM_PUSH(2, ICPLB_DATA10)
555 PM_PUSH(3, ICPLB_DATA11)
556 PM_PUSH(4, ICPLB_DATA12)
557 PM_PUSH(5, ICPLB_DATA13)
558 PM_PUSH(6, ICPLB_DATA14)
559 PM_PUSH(7, ICPLB_DATA15)
560
561 /* Event Vectors */
562 FP = B1;
563 PM_PUSH(8, EVT2)
564 PM_PUSH(9, EVT3)
565 FP += 4; /* EVT4 */
566 PM_PUSH(10, EVT5)
567 PM_PUSH(11, EVT6)
568 PM_PUSH(12, EVT7)
569 PM_PUSH(13, EVT8)
570 PM_PUSH_SYNC(13)
571 PM_PUSH(0, EVT9)
572 PM_PUSH(1, EVT10)
573 PM_PUSH(2, EVT11)
574 PM_PUSH(3, EVT12)
575 PM_PUSH(4, EVT13)
576 PM_PUSH(5, EVT14)
577 PM_PUSH(6, EVT15)
578
579 /* CEC */
580 FP = B2;
581 PM_PUSH(7, IMASK)
582 FP += 4; /* IPEND */
583 PM_PUSH(8, ILAT)
584 PM_PUSH(9, IPRIO)
585
586 /* Core Timer */
587 FP = B3;
588 PM_PUSH(10, TCNTL)
589 PM_PUSH(11, TPERIOD)
590 PM_PUSH(12, TSCALE)
591 PM_PUSH(13, TCOUNT)
592 PM_PUSH_SYNC(13)
593
594 /* Misc non-contiguous registers */
595 FP = I0;
596 PM_CORE_PUSH(0, DMEM_CONTROL);
597 PM_CORE_PUSH(1, IMEM_CONTROL);
598 PM_CORE_PUSH(2, TBUFCTL);
599 PM_PUSH_SYNC(2)
600 291
601 /* Setup args to hibernate mode early for pipeline optimization */ 292 /* Setup args to hibernate mode early for pipeline optimization */
602 R0 = M3; 293 R0 = M3;
@@ -618,274 +309,9 @@ ENTRY(_do_hibernate)
618 309
619.Lpm_resume_here: 310.Lpm_resume_here:
620 311
621 /* Restore Core MMRs */ 312 bfin_core_mmr_restore;
622 I0.H = hi(COREMMR_BASE); 313 bfin_sys_mmr_restore;
623 I0.L = lo(COREMMR_BASE); 314 bfin_cpu_reg_restore;
624 I1 = I0;
625 I2 = I0;
626 I3 = I0;
627 B0 = I0;
628 B1 = I0;
629 B2 = I0;
630 B3 = I0;
631 I1.L = lo(DCPLB_ADDR15);
632 I2.L = lo(DCPLB_DATA15);
633 I3.L = lo(ICPLB_ADDR15);
634 B0.L = lo(ICPLB_DATA15);
635 B1.L = lo(EVT15);
636 B2.L = lo(IPRIO);
637 B3.L = lo(TCOUNT);
638
639 /* Misc non-contiguous registers */
640 FP = I0;
641 PM_POP_SYNC(2)
642 PM_CORE_POP(2, TBUFCTL)
643 PM_CORE_POP(1, IMEM_CONTROL)
644 PM_CORE_POP(0, DMEM_CONTROL)
645
646 /* Core Timer */
647 PM_POP_SYNC(13)
648 FP = B3;
649 PM_POP(13, TCOUNT)
650 PM_POP(12, TSCALE)
651 PM_POP(11, TPERIOD)
652 PM_POP(10, TCNTL)
653
654 /* CEC */
655 FP = B2;
656 PM_POP(9, IPRIO)
657 PM_POP(8, ILAT)
658 FP += -4; /* IPEND */
659 PM_POP(7, IMASK)
660
661 /* Event Vectors */
662 FP = B1;
663 PM_POP(6, EVT15)
664 PM_POP(5, EVT14)
665 PM_POP(4, EVT13)
666 PM_POP(3, EVT12)
667 PM_POP(2, EVT11)
668 PM_POP(1, EVT10)
669 PM_POP(0, EVT9)
670 PM_POP_SYNC(13)
671 PM_POP(13, EVT8)
672 PM_POP(12, EVT7)
673 PM_POP(11, EVT6)
674 PM_POP(10, EVT5)
675 FP += -4; /* EVT4 */
676 PM_POP(9, EVT3)
677 PM_POP(8, EVT2)
678
679 /* ICPLB Data */
680 FP = B0;
681 PM_POP(7, ICPLB_DATA15)
682 PM_POP(6, ICPLB_DATA14)
683 PM_POP(5, ICPLB_DATA13)
684 PM_POP(4, ICPLB_DATA12)
685 PM_POP(3, ICPLB_DATA11)
686 PM_POP(2, ICPLB_DATA10)
687 PM_POP(1, ICPLB_DATA9)
688 PM_POP(0, ICPLB_DATA8)
689 PM_POP_SYNC(13)
690 PM_POP(13, ICPLB_DATA7)
691 PM_POP(12, ICPLB_DATA6)
692 PM_POP(11, ICPLB_DATA5)
693 PM_POP(10, ICPLB_DATA4)
694 PM_POP(9, ICPLB_DATA3)
695 PM_POP(8, ICPLB_DATA2)
696 PM_POP(7, ICPLB_DATA1)
697 PM_POP(6, ICPLB_DATA0)
698
699 /* ICPLB Addr */
700 FP = I3;
701 PM_POP(5, ICPLB_ADDR15)
702 PM_POP(4, ICPLB_ADDR14)
703 PM_POP(3, ICPLB_ADDR13)
704 PM_POP(2, ICPLB_ADDR12)
705 PM_POP(1, ICPLB_ADDR11)
706 PM_POP(0, ICPLB_ADDR10)
707 PM_POP_SYNC(13)
708 PM_POP(13, ICPLB_ADDR9)
709 PM_POP(12, ICPLB_ADDR8)
710 PM_POP(11, ICPLB_ADDR7)
711 PM_POP(10, ICPLB_ADDR6)
712 PM_POP(9, ICPLB_ADDR5)
713 PM_POP(8, ICPLB_ADDR4)
714 PM_POP(7, ICPLB_ADDR3)
715 PM_POP(6, ICPLB_ADDR2)
716 PM_POP(5, ICPLB_ADDR1)
717 PM_POP(4, ICPLB_ADDR0)
718
719 /* DCPLB Data */
720 FP = I2;
721 PM_POP(3, DCPLB_DATA15)
722 PM_POP(2, DCPLB_DATA14)
723 PM_POP(1, DCPLB_DATA13)
724 PM_POP(0, DCPLB_DATA12)
725 PM_POP_SYNC(13)
726 PM_POP(13, DCPLB_DATA11)
727 PM_POP(12, DCPLB_DATA10)
728 PM_POP(11, DCPLB_DATA9)
729 PM_POP(10, DCPLB_DATA8)
730 PM_POP(9, DCPLB_DATA7)
731 PM_POP(8, DCPLB_DATA6)
732 PM_POP(7, DCPLB_DATA5)
733 PM_POP(6, DCPLB_DATA4)
734 PM_POP(5, DCPLB_DATA3)
735 PM_POP(4, DCPLB_DATA2)
736 PM_POP(3, DCPLB_DATA1)
737 PM_POP(2, DCPLB_DATA0)
738
739 /* DCPLB Addr */
740 FP = I1;
741 PM_POP(1, DCPLB_ADDR15)
742 PM_POP(0, DCPLB_ADDR14)
743 PM_POP_SYNC(13)
744 PM_POP(13, DCPLB_ADDR13)
745 PM_POP(12, DCPLB_ADDR12)
746 PM_POP(11, DCPLB_ADDR11)
747 PM_POP(10, DCPLB_ADDR10)
748 PM_POP(9, DCPLB_ADDR9)
749 PM_POP(8, DCPLB_ADDR8)
750 PM_POP(7, DCPLB_ADDR7)
751 PM_POP(6, DCPLB_ADDR6)
752 PM_POP(5, DCPLB_ADDR5)
753 PM_POP(4, DCPLB_ADDR4)
754 PM_POP(3, DCPLB_ADDR3)
755 PM_POP(2, DCPLB_ADDR2)
756 PM_POP(1, DCPLB_ADDR1)
757 PM_POP(0, DCPLB_ADDR0)
758
759 /* Restore System MMRs */
760 FP.H = hi(SYSMMR_BASE);
761 FP.L = lo(SYSMMR_BASE);
762
763#ifdef EBIU_FCTL
764 PM_POP_SYNC(12)
765 PM_SYS_POP(12, EBIU_FCTL)
766 PM_SYS_POP(11, EBIU_MODE)
767 PM_SYS_POP(10, EBIU_MBSCTL)
768#else
769 PM_POP_SYNC(9)
770#endif
771 PM_SYS_POP(9, EBIU_AMBCTL1)
772 PM_SYS_POP(8, EBIU_AMBCTL0)
773 PM_SYS_POP16(7, EBIU_AMGCTL)
774
775 PM_SYS_POP16(6, SYSCR)
776
777#ifdef PINT0_ASSIGN
778 PM_SYS_POP(5, PINT3_EDGE_SET)
779 PM_SYS_POP(4, PINT2_EDGE_SET)
780 PM_SYS_POP(3, PINT1_EDGE_SET)
781 PM_SYS_POP(2, PINT0_EDGE_SET)
782 PM_SYS_POP(1, PINT3_INVERT_SET)
783 PM_SYS_POP(0, PINT2_INVERT_SET)
784 PM_POP_SYNC(13)
785 PM_SYS_POP(13, PINT1_INVERT_SET)
786 PM_SYS_POP(12, PINT0_INVERT_SET)
787 PM_SYS_POP(11, PINT3_ASSIGN)
788 PM_SYS_POP(10, PINT2_ASSIGN)
789 PM_SYS_POP(9, PINT1_ASSIGN)
790 PM_SYS_POP(8, PINT0_ASSIGN)
791 PM_SYS_POP(7, PINT3_MASK_SET)
792 PM_SYS_POP(6, PINT2_MASK_SET)
793 PM_SYS_POP(5, PINT1_MASK_SET)
794 PM_SYS_POP(4, PINT0_MASK_SET)
795#endif
796
797#ifdef SIC_IWR2
798 PM_SYS_POP(3, SIC_IWR2)
799#endif
800#ifdef SIC_IWR1
801 PM_SYS_POP(2, SIC_IWR1)
802#endif
803#ifdef SIC_IWR0
804 PM_SYS_POP(1, SIC_IWR0)
805#endif
806#ifdef SIC_IWR
807 PM_SYS_POP(1, SIC_IWR)
808#endif
809
810#ifdef SIC_IAR11
811 PM_SYS_POP(0, SIC_IAR11)
812#endif
813 PM_POP_SYNC(13)
814#ifdef SIC_IAR8
815 PM_SYS_POP(13, SIC_IAR10)
816 PM_SYS_POP(12, SIC_IAR9)
817 PM_SYS_POP(11, SIC_IAR8)
818#endif
819#ifdef SIC_IAR7
820 PM_SYS_POP(10, SIC_IAR7)
821#endif
822#ifdef SIC_IAR6
823 PM_SYS_POP(9, SIC_IAR6)
824 PM_SYS_POP(8, SIC_IAR5)
825 PM_SYS_POP(7, SIC_IAR4)
826#endif
827#ifdef SIC_IAR3
828 PM_SYS_POP(6, SIC_IAR3)
829#endif
830#ifdef SIC_IAR0
831 PM_SYS_POP(5, SIC_IAR2)
832 PM_SYS_POP(4, SIC_IAR1)
833 PM_SYS_POP(3, SIC_IAR0)
834#endif
835#ifdef SIC_IMASK0
836# ifdef SIC_IMASK2
837 PM_SYS_POP(2, SIC_IMASK2)
838# endif
839 PM_SYS_POP(1, SIC_IMASK1)
840 PM_SYS_POP(0, SIC_IMASK0)
841#else
842 PM_SYS_POP(0, SIC_IMASK)
843#endif
844
845 /* Restore Core Registers */
846 RETI = [sp++];
847 SEQSTAT = [sp++];
848 RETX = [sp++];
849 SYSCFG = [sp++];
850 CYCLES2 = [sp++];
851 CYCLES = [sp++];
852 ASTAT = [sp++];
853 RETS = [sp++];
854
855 LB1 = [sp++];
856 LB0 = [sp++];
857 LT1 = [sp++];
858 LT0 = [sp++];
859 LC1 = [sp++];
860 LC0 = [sp++];
861
862 a1.w = [sp++];
863 a1.x = [sp++];
864 a0.w = [sp++];
865 a0.x = [sp++];
866 b3 = [sp++];
867 b2 = [sp++];
868 b1 = [sp++];
869 b0 = [sp++];
870
871 l3 = [sp++];
872 l2 = [sp++];
873 l1 = [sp++];
874 l0 = [sp++];
875
876 m3 = [sp++];
877 m2 = [sp++];
878 m1 = [sp++];
879 m0 = [sp++];
880
881 i3 = [sp++];
882 i2 = [sp++];
883 i1 = [sp++];
884 i0 = [sp++];
885
886 usp = [sp++];
887 fp = [sp++];
888 (R7:0, P5:0) = [sp++];
889 315
890 [--sp] = RETI; /* Clear Global Interrupt Disable */ 316 [--sp] = RETI; /* Clear Global Interrupt Disable */
891 SP += 4; 317 SP += 4;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 4698a9800522..80aa2535e2c9 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -1141,7 +1141,8 @@ ENTRY(_schedule_and_signal_from_int)
1141 sti r0; 1141 sti r0;
1142 1142
1143 /* finish the userspace "atomic" functions for it */ 1143 /* finish the userspace "atomic" functions for it */
1144 r1 = FIXED_CODE_END; 1144 r1.l = lo(FIXED_CODE_END);
1145 r1.h = hi(FIXED_CODE_END);
1145 r2 = [sp + PT_PC]; 1146 r2 = [sp + PT_PC];
1146 cc = r1 <= r2; 1147 cc = r1 <= r2;
1147 if cc jump .Lresume_userspace (bp); 1148 if cc jump .Lresume_userspace (bp);
@@ -1376,7 +1377,7 @@ END(_ex_table)
1376ENTRY(_sys_call_table) 1377ENTRY(_sys_call_table)
1377 .long _sys_restart_syscall /* 0 */ 1378 .long _sys_restart_syscall /* 0 */
1378 .long _sys_exit 1379 .long _sys_exit
1379 .long _sys_fork 1380 .long _sys_ni_syscall /* fork */
1380 .long _sys_read 1381 .long _sys_read
1381 .long _sys_write 1382 .long _sys_write
1382 .long _sys_open /* 5 */ 1383 .long _sys_open /* 5 */
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index 8b4d98854403..31515f0146f9 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -210,14 +210,12 @@ ENDPROC(__start)
210ENTRY(_real_start) 210ENTRY(_real_start)
211 /* Enable nested interrupts */ 211 /* Enable nested interrupts */
212 [--sp] = reti; 212 [--sp] = reti;
213
214 /* watchdog off for now */ 213 /* watchdog off for now */
215 p0.l = lo(WDOG_CTL); 214 p0.l = lo(WDOG_CTL);
216 p0.h = hi(WDOG_CTL); 215 p0.h = hi(WDOG_CTL);
217 r0 = 0xAD6(z); 216 r0 = 0xAD6(z);
218 w[p0] = r0; 217 w[p0] = r0;
219 ssync; 218 ssync;
220
221 /* Pass the u-boot arguments to the global value command line */ 219 /* Pass the u-boot arguments to the global value command line */
222 R0 = R7; 220 R0 = R7;
223 call _cmdline_init; 221 call _cmdline_init;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 332dace6af34..2729cba715b0 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -16,6 +16,8 @@
16#include <linux/seq_file.h> 16#include <linux/seq_file.h>
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/sched.h> 18#include <linux/sched.h>
19#include <linux/syscore_ops.h>
20#include <asm/delay.h>
19#ifdef CONFIG_IPIPE 21#ifdef CONFIG_IPIPE
20#include <linux/ipipe.h> 22#include <linux/ipipe.h>
21#endif 23#endif
@@ -25,7 +27,11 @@
25#include <asm/irq_handler.h> 27#include <asm/irq_handler.h>
26#include <asm/dpmc.h> 28#include <asm/dpmc.h>
27 29
28#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) 30#ifndef CONFIG_BF60x
31# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
32#else
33# define SIC_SYSIRQ(irq) ((irq) - IVG15)
34#endif
29 35
30/* 36/*
31 * NOTES: 37 * NOTES:
@@ -50,6 +56,7 @@ unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
50unsigned vr_wakeup; 56unsigned vr_wakeup;
51#endif 57#endif
52 58
59#ifndef CONFIG_BF60x
53static struct ivgx { 60static struct ivgx {
54 /* irq number for request_irq, available in mach-bf5xx/irq.h */ 61 /* irq number for request_irq, available in mach-bf5xx/irq.h */
55 unsigned int irqno; 62 unsigned int irqno;
@@ -78,7 +85,8 @@ static void __init search_IAR(void)
78 85
79 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) { 86 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
80 int irqn; 87 int irqn;
81 u32 iar = bfin_read32((unsigned long *)SIC_IAR0 + 88 u32 iar =
89 bfin_read32((unsigned long *)SIC_IAR0 +
82#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \ 90#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
83 defined(CONFIG_BF538) || defined(CONFIG_BF539) 91 defined(CONFIG_BF538) || defined(CONFIG_BF539)
84 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4)) 92 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
@@ -86,7 +94,6 @@ static void __init search_IAR(void)
86 (irqN >> 3) 94 (irqN >> 3)
87#endif 95#endif
88 ); 96 );
89
90 for (irqn = irqN; irqn < irqN + 4; ++irqn) { 97 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
91 int iar_shift = (irqn & 7) * 4; 98 int iar_shift = (irqn & 7) * 4;
92 if (ivg == (0xf & (iar >> iar_shift))) { 99 if (ivg == (0xf & (iar >> iar_shift))) {
@@ -99,11 +106,11 @@ static void __init search_IAR(void)
99 } 106 }
100 } 107 }
101} 108}
109#endif
102 110
103/* 111/*
104 * This is for core internal IRQs 112 * This is for core internal IRQs
105 */ 113 */
106
107void bfin_ack_noop(struct irq_data *d) 114void bfin_ack_noop(struct irq_data *d)
108{ 115{
109 /* Dummy function. */ 116 /* Dummy function. */
@@ -136,21 +143,21 @@ static void bfin_core_unmask_irq(struct irq_data *d)
136void bfin_internal_mask_irq(unsigned int irq) 143void bfin_internal_mask_irq(unsigned int irq)
137{ 144{
138 unsigned long flags = hard_local_irq_save(); 145 unsigned long flags = hard_local_irq_save();
139 146#ifndef CONFIG_BF60x
140#ifdef SIC_IMASK0 147#ifdef SIC_IMASK0
141 unsigned mask_bank = SIC_SYSIRQ(irq) / 32; 148 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
142 unsigned mask_bit = SIC_SYSIRQ(irq) % 32; 149 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
143 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 150 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
144 ~(1 << mask_bit)); 151 ~(1 << mask_bit));
145# ifdef CONFIG_SMP 152# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
146 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & 153 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
147 ~(1 << mask_bit)); 154 ~(1 << mask_bit));
148# endif 155# endif
149#else 156#else
150 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 157 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
151 ~(1 << SIC_SYSIRQ(irq))); 158 ~(1 << SIC_SYSIRQ(irq)));
159#endif /* end of SIC_IMASK0 */
152#endif 160#endif
153
154 hard_local_irq_restore(flags); 161 hard_local_irq_restore(flags);
155} 162}
156 163
@@ -160,7 +167,7 @@ static void bfin_internal_mask_irq_chip(struct irq_data *d)
160} 167}
161 168
162#ifdef CONFIG_SMP 169#ifdef CONFIG_SMP
163static void bfin_internal_unmask_irq_affinity(unsigned int irq, 170void bfin_internal_unmask_irq_affinity(unsigned int irq,
164 const struct cpumask *affinity) 171 const struct cpumask *affinity)
165#else 172#else
166void bfin_internal_unmask_irq(unsigned int irq) 173void bfin_internal_unmask_irq(unsigned int irq)
@@ -168,6 +175,7 @@ void bfin_internal_unmask_irq(unsigned int irq)
168{ 175{
169 unsigned long flags = hard_local_irq_save(); 176 unsigned long flags = hard_local_irq_save();
170 177
178#ifndef CONFIG_BF60x
171#ifdef SIC_IMASK0 179#ifdef SIC_IMASK0
172 unsigned mask_bank = SIC_SYSIRQ(irq) / 32; 180 unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
173 unsigned mask_bit = SIC_SYSIRQ(irq) % 32; 181 unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
@@ -175,22 +183,239 @@ void bfin_internal_unmask_irq(unsigned int irq)
175 if (cpumask_test_cpu(0, affinity)) 183 if (cpumask_test_cpu(0, affinity))
176# endif 184# endif
177 bfin_write_SIC_IMASK(mask_bank, 185 bfin_write_SIC_IMASK(mask_bank,
178 bfin_read_SIC_IMASK(mask_bank) | 186 bfin_read_SIC_IMASK(mask_bank) |
179 (1 << mask_bit)); 187 (1 << mask_bit));
180# ifdef CONFIG_SMP 188# ifdef CONFIG_SMP
181 if (cpumask_test_cpu(1, affinity)) 189 if (cpumask_test_cpu(1, affinity))
182 bfin_write_SICB_IMASK(mask_bank, 190 bfin_write_SICB_IMASK(mask_bank,
183 bfin_read_SICB_IMASK(mask_bank) | 191 bfin_read_SICB_IMASK(mask_bank) |
184 (1 << mask_bit)); 192 (1 << mask_bit));
185# endif 193# endif
186#else 194#else
187 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 195 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
188 (1 << SIC_SYSIRQ(irq))); 196 (1 << SIC_SYSIRQ(irq)));
197#endif
189#endif 198#endif
199 hard_local_irq_restore(flags);
200}
201
202#ifdef CONFIG_BF60x
203static void bfin_sec_preflow_handler(struct irq_data *d)
204{
205 unsigned long flags = hard_local_irq_save();
206 unsigned int sid = SIC_SYSIRQ(d->irq);
207
208 bfin_write_SEC_SCI(0, SEC_CSID, sid);
209
210 hard_local_irq_restore(flags);
211}
212
213static void bfin_sec_mask_ack_irq(struct irq_data *d)
214{
215 unsigned long flags = hard_local_irq_save();
216 unsigned int sid = SIC_SYSIRQ(d->irq);
217
218 bfin_write_SEC_SCI(0, SEC_CSID, sid);
190 219
191 hard_local_irq_restore(flags); 220 hard_local_irq_restore(flags);
192} 221}
193 222
223static void bfin_sec_unmask_irq(struct irq_data *d)
224{
225 unsigned long flags = hard_local_irq_save();
226 unsigned int sid = SIC_SYSIRQ(d->irq);
227
228 bfin_write32(SEC_END, sid);
229
230 hard_local_irq_restore(flags);
231}
232
233static void bfin_sec_enable_ssi(unsigned int sid)
234{
235 unsigned long flags = hard_local_irq_save();
236 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
237
238 reg_sctl |= SEC_SCTL_SRC_EN;
239 bfin_write_SEC_SCTL(sid, reg_sctl);
240
241 hard_local_irq_restore(flags);
242}
243
244static void bfin_sec_disable_ssi(unsigned int sid)
245{
246 unsigned long flags = hard_local_irq_save();
247 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
248
249 reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
250 bfin_write_SEC_SCTL(sid, reg_sctl);
251
252 hard_local_irq_restore(flags);
253}
254
255static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
256{
257 unsigned long flags = hard_local_irq_save();
258 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
259
260 reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
261 bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
262
263 hard_local_irq_restore(flags);
264}
265
266static void bfin_sec_enable_sci(unsigned int sid)
267{
268 unsigned long flags = hard_local_irq_save();
269 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
270
271 if (sid == SIC_SYSIRQ(IRQ_WATCH0))
272 reg_sctl |= SEC_SCTL_FAULT_EN;
273 else
274 reg_sctl |= SEC_SCTL_INT_EN;
275 bfin_write_SEC_SCTL(sid, reg_sctl);
276
277 hard_local_irq_restore(flags);
278}
279
280static void bfin_sec_disable_sci(unsigned int sid)
281{
282 unsigned long flags = hard_local_irq_save();
283 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
284
285 reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
286 bfin_write_SEC_SCTL(sid, reg_sctl);
287
288 hard_local_irq_restore(flags);
289}
290
291static void bfin_sec_enable(struct irq_data *d)
292{
293 unsigned long flags = hard_local_irq_save();
294 unsigned int sid = SIC_SYSIRQ(d->irq);
295
296 bfin_sec_enable_sci(sid);
297 bfin_sec_enable_ssi(sid);
298
299 hard_local_irq_restore(flags);
300}
301
302static void bfin_sec_disable(struct irq_data *d)
303{
304 unsigned long flags = hard_local_irq_save();
305 unsigned int sid = SIC_SYSIRQ(d->irq);
306
307 bfin_sec_disable_sci(sid);
308 bfin_sec_disable_ssi(sid);
309
310 hard_local_irq_restore(flags);
311}
312
313static void bfin_sec_raise_irq(unsigned int sid)
314{
315 unsigned long flags = hard_local_irq_save();
316
317 bfin_write32(SEC_RAISE, sid);
318
319 hard_local_irq_restore(flags);
320}
321
322static void init_software_driven_irq(void)
323{
324 bfin_sec_set_ssi_coreid(34, 0);
325 bfin_sec_set_ssi_coreid(35, 1);
326 bfin_sec_set_ssi_coreid(36, 0);
327 bfin_sec_set_ssi_coreid(37, 1);
328}
329
330void bfin_sec_resume(void)
331{
332 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
333 udelay(100);
334 bfin_write_SEC_GCTL(SEC_GCTL_EN);
335 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
336}
337
338void handle_sec_sfi_fault(uint32_t gstat)
339{
340
341}
342
343void handle_sec_sci_fault(uint32_t gstat)
344{
345 uint32_t core_id;
346 uint32_t cstat;
347
348 core_id = gstat & SEC_GSTAT_SCI;
349 cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
350 if (cstat & SEC_CSTAT_ERR) {
351 switch (cstat & SEC_CSTAT_ERRC) {
352 case SEC_CSTAT_ACKERR:
353 printk(KERN_DEBUG "sec ack err\n");
354 break;
355 default:
356 printk(KERN_DEBUG "sec sci unknow err\n");
357 }
358 }
359
360}
361
362void handle_sec_ssi_fault(uint32_t gstat)
363{
364 uint32_t sid;
365 uint32_t sstat;
366
367 sid = gstat & SEC_GSTAT_SID;
368 sstat = bfin_read_SEC_SSTAT(sid);
369
370}
371
372void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
373{
374 uint32_t sec_gstat;
375
376 raw_spin_lock(&desc->lock);
377
378 sec_gstat = bfin_read32(SEC_GSTAT);
379 if (sec_gstat & SEC_GSTAT_ERR) {
380
381 switch (sec_gstat & SEC_GSTAT_ERRC) {
382 case 0:
383 handle_sec_sfi_fault(sec_gstat);
384 break;
385 case SEC_GSTAT_SCIERR:
386 handle_sec_sci_fault(sec_gstat);
387 break;
388 case SEC_GSTAT_SSIERR:
389 handle_sec_ssi_fault(sec_gstat);
390 break;
391 }
392
393
394 }
395
396 raw_spin_unlock(&desc->lock);
397}
398
399static int sec_suspend(void)
400{
401 return 0;
402}
403
404static void sec_resume(void)
405{
406 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
407 udelay(100);
408 bfin_write_SEC_GCTL(SEC_GCTL_EN);
409 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
410}
411
412static struct syscore_ops sec_pm_syscore_ops = {
413 .suspend = sec_suspend,
414 .resume = sec_resume,
415};
416
417#endif
418
194#ifdef CONFIG_SMP 419#ifdef CONFIG_SMP
195static void bfin_internal_unmask_irq_chip(struct irq_data *d) 420static void bfin_internal_unmask_irq_chip(struct irq_data *d)
196{ 421{
@@ -212,7 +437,7 @@ static void bfin_internal_unmask_irq_chip(struct irq_data *d)
212} 437}
213#endif 438#endif
214 439
215#ifdef CONFIG_PM 440#if defined(CONFIG_PM) && !defined(CONFIG_BF60x)
216int bfin_internal_set_wake(unsigned int irq, unsigned int state) 441int bfin_internal_set_wake(unsigned int irq, unsigned int state)
217{ 442{
218 u32 bank, bit, wakeup = 0; 443 u32 bank, bit, wakeup = 0;
@@ -271,22 +496,20 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
271 return bfin_internal_set_wake(d->irq, state); 496 return bfin_internal_set_wake(d->irq, state);
272} 497}
273#else 498#else
499# define bfin_internal_set_wake(irq, state)
274# define bfin_internal_set_wake_chip NULL 500# define bfin_internal_set_wake_chip NULL
275#endif 501#endif
276 502
277static struct irq_chip bfin_core_irqchip = { 503static struct irq_chip bfin_core_irqchip = {
278 .name = "CORE", 504 .name = "CORE",
279 .irq_ack = bfin_ack_noop,
280 .irq_mask = bfin_core_mask_irq, 505 .irq_mask = bfin_core_mask_irq,
281 .irq_unmask = bfin_core_unmask_irq, 506 .irq_unmask = bfin_core_unmask_irq,
282}; 507};
283 508
284static struct irq_chip bfin_internal_irqchip = { 509static struct irq_chip bfin_internal_irqchip = {
285 .name = "INTN", 510 .name = "INTN",
286 .irq_ack = bfin_ack_noop,
287 .irq_mask = bfin_internal_mask_irq_chip, 511 .irq_mask = bfin_internal_mask_irq_chip,
288 .irq_unmask = bfin_internal_unmask_irq_chip, 512 .irq_unmask = bfin_internal_unmask_irq_chip,
289 .irq_mask_ack = bfin_internal_mask_irq_chip,
290 .irq_disable = bfin_internal_mask_irq_chip, 513 .irq_disable = bfin_internal_mask_irq_chip,
291 .irq_enable = bfin_internal_unmask_irq_chip, 514 .irq_enable = bfin_internal_unmask_irq_chip,
292#ifdef CONFIG_SMP 515#ifdef CONFIG_SMP
@@ -295,6 +518,18 @@ static struct irq_chip bfin_internal_irqchip = {
295 .irq_set_wake = bfin_internal_set_wake_chip, 518 .irq_set_wake = bfin_internal_set_wake_chip,
296}; 519};
297 520
521#ifdef CONFIG_BF60x
522static struct irq_chip bfin_sec_irqchip = {
523 .name = "SEC",
524 .irq_mask_ack = bfin_sec_mask_ack_irq,
525 .irq_mask = bfin_sec_mask_ack_irq,
526 .irq_unmask = bfin_sec_unmask_irq,
527 .irq_eoi = bfin_sec_unmask_irq,
528 .irq_disable = bfin_sec_disable,
529 .irq_enable = bfin_sec_enable,
530};
531#endif
532
298void bfin_handle_irq(unsigned irq) 533void bfin_handle_irq(unsigned irq)
299{ 534{
300#ifdef CONFIG_IPIPE 535#ifdef CONFIG_IPIPE
@@ -396,8 +631,6 @@ int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
396 631
397static struct irq_chip bfin_mac_status_irqchip = { 632static struct irq_chip bfin_mac_status_irqchip = {
398 .name = "MACST", 633 .name = "MACST",
399 .irq_ack = bfin_ack_noop,
400 .irq_mask_ack = bfin_mac_status_mask_irq,
401 .irq_mask = bfin_mac_status_mask_irq, 634 .irq_mask = bfin_mac_status_mask_irq,
402 .irq_unmask = bfin_mac_status_unmask_irq, 635 .irq_unmask = bfin_mac_status_unmask_irq,
403 .irq_set_wake = bfin_mac_status_set_wake, 636 .irq_set_wake = bfin_mac_status_set_wake,
@@ -421,15 +654,15 @@ void bfin_demux_mac_status_irq(unsigned int int_err_irq,
421 } else { 654 } else {
422 bfin_mac_status_ack_irq(irq); 655 bfin_mac_status_ack_irq(irq);
423 pr_debug("IRQ %d:" 656 pr_debug("IRQ %d:"
424 " MASKED MAC ERROR INTERRUPT ASSERTED\n", 657 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
425 irq); 658 irq);
426 } 659 }
427 } else 660 } else
428 printk(KERN_ERR 661 printk(KERN_ERR
429 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" 662 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
430 " INTERRUPT ASSERTED BUT NO SOURCE FOUND" 663 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
431 "(EMAC_SYSTAT=0x%X)\n", 664 "(EMAC_SYSTAT=0x%X)\n",
432 __func__, __FILE__, __LINE__, status); 665 __func__, __FILE__, __LINE__, status);
433} 666}
434#endif 667#endif
435 668
@@ -583,7 +816,7 @@ static void bfin_demux_gpio_block(unsigned int irq)
583} 816}
584 817
585void bfin_demux_gpio_irq(unsigned int inta_irq, 818void bfin_demux_gpio_irq(unsigned int inta_irq,
586 struct irq_desc *desc) 819 struct irq_desc *desc)
587{ 820{
588 unsigned int irq; 821 unsigned int irq;
589 822
@@ -635,9 +868,15 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
635 868
636#else 869#else
637 870
871# ifndef CONFIG_BF60x
638#define NR_PINT_SYS_IRQS 4 872#define NR_PINT_SYS_IRQS 4
639#define NR_PINT_BITS 32
640#define NR_PINTS 160 873#define NR_PINTS 160
874# else
875#define NR_PINT_SYS_IRQS 6
876#define NR_PINTS 112
877#endif
878
879#define NR_PINT_BITS 32
641#define IRQ_NOT_AVAIL 0xFF 880#define IRQ_NOT_AVAIL 0xFF
642 881
643#define PINT_2_BANK(x) ((x) >> 5) 882#define PINT_2_BANK(x) ((x) >> 5)
@@ -652,8 +891,13 @@ static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
652 (struct bfin_pint_regs *)PINT1_MASK_SET, 891 (struct bfin_pint_regs *)PINT1_MASK_SET,
653 (struct bfin_pint_regs *)PINT2_MASK_SET, 892 (struct bfin_pint_regs *)PINT2_MASK_SET,
654 (struct bfin_pint_regs *)PINT3_MASK_SET, 893 (struct bfin_pint_regs *)PINT3_MASK_SET,
894#ifdef CONFIG_BF60x
895 (struct bfin_pint_regs *)PINT4_MASK_SET,
896 (struct bfin_pint_regs *)PINT5_MASK_SET,
897#endif
655}; 898};
656 899
900#ifndef CONFIG_BF60x
657inline unsigned int get_irq_base(u32 bank, u8 bmap) 901inline unsigned int get_irq_base(u32 bank, u8 bmap)
658{ 902{
659 unsigned int irq_base; 903 unsigned int irq_base;
@@ -666,6 +910,16 @@ inline unsigned int get_irq_base(u32 bank, u8 bmap)
666 910
667 return irq_base; 911 return irq_base;
668} 912}
913#else
914inline unsigned int get_irq_base(u32 bank, u8 bmap)
915{
916 unsigned int irq_base;
917
918 irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
919
920 return irq_base;
921}
922#endif
669 923
670 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ 924 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
671void init_pint_lut(void) 925void init_pint_lut(void)
@@ -854,6 +1108,14 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
854 case 1: 1108 case 1:
855 pint_irq = IRQ_PINT1; 1109 pint_irq = IRQ_PINT1;
856 break; 1110 break;
1111#ifdef CONFIG_BF60x
1112 case 4:
1113 pint_irq = IRQ_PINT4;
1114 break;
1115 case 5:
1116 pint_irq = IRQ_PINT5;
1117 break;
1118#endif
857 default: 1119 default:
858 return -EINVAL; 1120 return -EINVAL;
859 } 1121 }
@@ -867,10 +1129,21 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
867#endif 1129#endif
868 1130
869void bfin_demux_gpio_irq(unsigned int inta_irq, 1131void bfin_demux_gpio_irq(unsigned int inta_irq,
870 struct irq_desc *desc) 1132 struct irq_desc *desc)
871{ 1133{
872 u32 bank, pint_val; 1134 u32 bank, pint_val;
873 u32 request, irq; 1135 u32 request, irq;
1136 u32 level_mask;
1137 int umask = 0;
1138 struct irq_chip *chip = irq_desc_get_chip(desc);
1139
1140 if (chip->irq_mask_ack) {
1141 chip->irq_mask_ack(&desc->irq_data);
1142 } else {
1143 chip->irq_mask(&desc->irq_data);
1144 if (chip->irq_ack)
1145 chip->irq_ack(&desc->irq_data);
1146 }
874 1147
875 switch (inta_irq) { 1148 switch (inta_irq) {
876 case IRQ_PINT0: 1149 case IRQ_PINT0:
@@ -885,6 +1158,14 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
885 case IRQ_PINT1: 1158 case IRQ_PINT1:
886 bank = 1; 1159 bank = 1;
887 break; 1160 break;
1161#ifdef CONFIG_BF60x
1162 case IRQ_PINT4:
1163 bank = 4;
1164 break;
1165 case IRQ_PINT5:
1166 bank = 5;
1167 break;
1168#endif
888 default: 1169 default:
889 return; 1170 return;
890 } 1171 }
@@ -893,15 +1174,23 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
893 1174
894 request = pint[bank]->request; 1175 request = pint[bank]->request;
895 1176
1177 level_mask = pint[bank]->edge_set & request;
1178
896 while (request) { 1179 while (request) {
897 if (request & 1) { 1180 if (request & 1) {
898 irq = pint2irq_lut[pint_val] + SYS_IRQS; 1181 irq = pint2irq_lut[pint_val] + SYS_IRQS;
1182 if (level_mask & PINT_BIT(pint_val)) {
1183 umask = 1;
1184 chip->irq_unmask(&desc->irq_data);
1185 }
899 bfin_handle_irq(irq); 1186 bfin_handle_irq(irq);
900 } 1187 }
901 pint_val++; 1188 pint_val++;
902 request >>= 1; 1189 request >>= 1;
903 } 1190 }
904 1191
1192 if (!umask)
1193 chip->irq_unmask(&desc->irq_data);
905} 1194}
906#endif 1195#endif
907 1196
@@ -951,6 +1240,7 @@ int __init init_arch_irq(void)
951 int irq; 1240 int irq;
952 unsigned long ilat = 0; 1241 unsigned long ilat = 0;
953 1242
1243#ifndef CONFIG_BF60x
954 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 1244 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
955#ifdef SIC_IMASK0 1245#ifdef SIC_IMASK0
956 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); 1246 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
@@ -958,13 +1248,16 @@ int __init init_arch_irq(void)
958# ifdef SIC_IMASK2 1248# ifdef SIC_IMASK2
959 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); 1249 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
960# endif 1250# endif
961# ifdef CONFIG_SMP 1251# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
962 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL); 1252 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
963 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL); 1253 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
964# endif 1254# endif
965#else 1255#else
966 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 1256 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
967#endif 1257#endif
1258#else /* CONFIG_BF60x */
1259 bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1260#endif
968 1261
969 local_irq_disable(); 1262 local_irq_disable();
970 1263
@@ -974,6 +1267,10 @@ int __init init_arch_irq(void)
974 pint[1]->assign = CONFIG_PINT1_ASSIGN; 1267 pint[1]->assign = CONFIG_PINT1_ASSIGN;
975 pint[2]->assign = CONFIG_PINT2_ASSIGN; 1268 pint[2]->assign = CONFIG_PINT2_ASSIGN;
976 pint[3]->assign = CONFIG_PINT3_ASSIGN; 1269 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1270# ifdef CONFIG_BF60x
1271 pint[4]->assign = CONFIG_PINT4_ASSIGN;
1272 pint[5]->assign = CONFIG_PINT5_ASSIGN;
1273# endif
977# endif 1274# endif
978 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ 1275 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
979 init_pint_lut(); 1276 init_pint_lut();
@@ -986,6 +1283,7 @@ int __init init_arch_irq(void)
986 irq_set_chip(irq, &bfin_internal_irqchip); 1283 irq_set_chip(irq, &bfin_internal_irqchip);
987 1284
988 switch (irq) { 1285 switch (irq) {
1286#ifndef CONFIG_BF60x
989#if BFIN_GPIO_PINT 1287#if BFIN_GPIO_PINT
990 case IRQ_PINT0: 1288 case IRQ_PINT0:
991 case IRQ_PINT1: 1289 case IRQ_PINT1:
@@ -1015,12 +1313,13 @@ int __init init_arch_irq(void)
1015 bfin_demux_mac_status_irq); 1313 bfin_demux_mac_status_irq);
1016 break; 1314 break;
1017#endif 1315#endif
1018#ifdef CONFIG_SMP 1316#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1019 case IRQ_SUPPLE_0: 1317 case IRQ_SUPPLE_0:
1020 case IRQ_SUPPLE_1: 1318 case IRQ_SUPPLE_1:
1021 irq_set_handler(irq, handle_percpu_irq); 1319 irq_set_handler(irq, handle_percpu_irq);
1022 break; 1320 break;
1023#endif 1321#endif
1322#endif
1024 1323
1025#ifdef CONFIG_TICKSOURCE_CORETMR 1324#ifdef CONFIG_TICKSOURCE_CORETMR
1026 case IRQ_CORETMR: 1325 case IRQ_CORETMR:
@@ -1050,7 +1349,8 @@ int __init init_arch_irq(void)
1050 1349
1051 init_mach_irq(); 1350 init_mach_irq();
1052 1351
1053#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 1352#ifndef CONFIG_BF60x
1353#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) && !defined(CONFIG_BF60x)
1054 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) 1354 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1055 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, 1355 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1056 handle_level_irq); 1356 handle_level_irq);
@@ -1060,7 +1360,28 @@ int __init init_arch_irq(void)
1060 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) 1360 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1061 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, 1361 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1062 handle_level_irq); 1362 handle_level_irq);
1063 1363#else
1364 for (irq = BFIN_IRQ(0); irq <= SYS_IRQS; irq++) {
1365 if (irq < CORE_IRQS) {
1366 irq_set_chip(irq, &bfin_sec_irqchip);
1367 __irq_set_handler(irq, handle_sec_fault, 0, NULL);
1368 } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
1369 irq_set_chip(irq, &bfin_sec_irqchip);
1370 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1371 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1372 irq_set_chip(irq, &bfin_sec_irqchip);
1373 irq_set_handler(irq, handle_percpu_irq);
1374 } else {
1375 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1376 handle_fasteoi_irq);
1377 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1378 }
1379 }
1380 for (irq = GPIO_IRQ_BASE;
1381 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1382 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1383 handle_level_irq);
1384#endif
1064 bfin_write_IMASK(0); 1385 bfin_write_IMASK(0);
1065 CSYNC(); 1386 CSYNC();
1066 ilat = bfin_read_ILAT(); 1387 ilat = bfin_read_ILAT();
@@ -1072,14 +1393,17 @@ int __init init_arch_irq(void)
1072 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, 1393 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1073 * local_irq_enable() 1394 * local_irq_enable()
1074 */ 1395 */
1396#ifndef CONFIG_BF60x
1075 program_IAR(); 1397 program_IAR();
1076 /* Therefore it's better to setup IARs before interrupts enabled */ 1398 /* Therefore it's better to setup IARs before interrupts enabled */
1077 search_IAR(); 1399 search_IAR();
1078 1400
1079 /* Enable interrupts IVG7-15 */ 1401 /* Enable interrupts IVG7-15 */
1080 bfin_irq_flags |= IMASK_IVG15 | 1402 bfin_irq_flags |= IMASK_IVG15 |
1081 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | 1403 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1082 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; 1404 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1405
1406 bfin_sti(bfin_irq_flags);
1083 1407
1084 /* This implicitly covers ANOMALY_05000171 1408 /* This implicitly covers ANOMALY_05000171
1085 * Boot-ROM code modifies SICA_IWRx wakeup registers 1409 * Boot-ROM code modifies SICA_IWRx wakeup registers
@@ -1103,7 +1427,23 @@ int __init init_arch_irq(void)
1103#else 1427#else
1104 bfin_write_SIC_IWR(IWR_DISABLE_ALL); 1428 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1105#endif 1429#endif
1430#else /* CONFIG_BF60x */
1431 /* Enable interrupts IVG7-15 */
1432 bfin_irq_flags |= IMASK_IVG15 |
1433 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1434 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1106 1435
1436
1437 bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1438 bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
1439 bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
1440 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1441 udelay(100);
1442 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1443 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1444 init_software_driven_irq();
1445 register_syscore_ops(&sec_pm_syscore_ops);
1446#endif
1107 return 0; 1447 return 0;
1108} 1448}
1109 1449
@@ -1112,13 +1452,14 @@ __attribute__((l1_text))
1112#endif 1452#endif
1113static int vec_to_irq(int vec) 1453static int vec_to_irq(int vec)
1114{ 1454{
1455#ifndef CONFIG_BF60x
1115 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 1456 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1116 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 1457 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1117 unsigned long sic_status[3]; 1458 unsigned long sic_status[3];
1118 1459#endif
1119 if (likely(vec == EVT_IVTMR_P)) 1460 if (likely(vec == EVT_IVTMR_P))
1120 return IRQ_CORETMR; 1461 return IRQ_CORETMR;
1121 1462#ifndef CONFIG_BF60x
1122#ifdef SIC_ISR 1463#ifdef SIC_ISR
1123 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); 1464 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1124#else 1465#else
@@ -1147,6 +1488,10 @@ static int vec_to_irq(int vec)
1147#endif 1488#endif
1148 return ivg->irqno; 1489 return ivg->irqno;
1149 } 1490 }
1491#else
1492 /* for bf60x read */
1493 return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1494#endif /* end of CONFIG_BF60x */
1150} 1495}
1151 1496
1152#ifdef CONFIG_DO_IRQ_L1 1497#ifdef CONFIG_DO_IRQ_L1
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 3c648a077e75..ca6655e0d653 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -19,20 +19,33 @@
19#include <asm/gpio.h> 19#include <asm/gpio.h>
20#include <asm/dma.h> 20#include <asm/dma.h>
21#include <asm/dpmc.h> 21#include <asm/dpmc.h>
22#include <asm/pm.h>
22 23
24#ifdef CONFIG_BF60x
25struct bfin_cpu_pm_fns *bfin_cpu_pm;
26#endif
23 27
24void bfin_pm_suspend_standby_enter(void) 28void bfin_pm_suspend_standby_enter(void)
25{ 29{
30#ifndef CONFIG_BF60x
26 bfin_pm_standby_setup(); 31 bfin_pm_standby_setup();
32#endif
27 33
28#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER 34#ifdef CONFIG_BF60x
29 sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); 35 bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
30#else 36#else
37# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
38 sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
39# else
31 sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]); 40 sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
41# endif
32#endif 42#endif
33 43
44#ifndef CONFIG_BF60x
34 bfin_pm_standby_restore(); 45 bfin_pm_standby_restore();
46#endif
35 47
48#ifndef CONFIG_BF60x
36#ifdef SIC_IWR0 49#ifdef SIC_IWR0
37 bfin_write_SIC_IWR0(IWR_DISABLE_ALL); 50 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
38# ifdef SIC_IWR1 51# ifdef SIC_IWR1
@@ -52,6 +65,8 @@ void bfin_pm_suspend_standby_enter(void)
52#else 65#else
53 bfin_write_SIC_IWR(IWR_DISABLE_ALL); 66 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
54#endif 67#endif
68
69#endif
55} 70}
56 71
57int bf53x_suspend_l1_mem(unsigned char *memptr) 72int bf53x_suspend_l1_mem(unsigned char *memptr)
@@ -83,10 +98,13 @@ int bf53x_resume_l1_mem(unsigned char *memptr)
83} 98}
84 99
85#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK) 100#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
101# ifdef CONFIG_BF60x
102__attribute__((l1_text))
103# endif
86static void flushinv_all_dcache(void) 104static void flushinv_all_dcache(void)
87{ 105{
88 u32 way, bank, subbank, set; 106 register u32 way, bank, subbank, set;
89 u32 status, addr; 107 register u32 status, addr;
90 u32 dmem_ctl = bfin_read_DMEM_CONTROL(); 108 u32 dmem_ctl = bfin_read_DMEM_CONTROL();
91 109
92 for (bank = 0; bank < 2; ++bank) { 110 for (bank = 0; bank < 2; ++bank) {
@@ -133,6 +151,7 @@ int bfin_pm_suspend_mem_enter(void)
133 return -ENOMEM; 151 return -ENOMEM;
134 } 152 }
135 153
154#ifndef CONFIG_BF60x
136 wakeup = bfin_read_VR_CTL() & ~FREQ; 155 wakeup = bfin_read_VR_CTL() & ~FREQ;
137 wakeup |= SCKELOW; 156 wakeup |= SCKELOW;
138 157
@@ -142,6 +161,7 @@ int bfin_pm_suspend_mem_enter(void)
142#ifdef CONFIG_PM_BFIN_WAKE_GP 161#ifdef CONFIG_PM_BFIN_WAKE_GP
143 wakeup |= GPWE; 162 wakeup |= GPWE;
144#endif 163#endif
164#endif
145 165
146 ret = blackfin_dma_suspend(); 166 ret = blackfin_dma_suspend();
147 167
@@ -159,7 +179,11 @@ int bfin_pm_suspend_mem_enter(void)
159 _disable_icplb(); 179 _disable_icplb();
160 bf53x_suspend_l1_mem(memptr); 180 bf53x_suspend_l1_mem(memptr);
161 181
182#ifndef CONFIG_BF60x
162 do_hibernate(wakeup | vr_wakeup); /* See you later! */ 183 do_hibernate(wakeup | vr_wakeup); /* See you later! */
184#else
185 bfin_cpu_pm->enter(PM_SUSPEND_MEM);
186#endif
163 187
164 bf53x_resume_l1_mem(memptr); 188 bf53x_resume_l1_mem(memptr);
165 189
@@ -223,9 +247,39 @@ static int bfin_pm_enter(suspend_state_t state)
223 return 0; 247 return 0;
224} 248}
225 249
250#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
251void bfin_pm_end(void)
252{
253 u32 cycle, cycle2;
254 u64 usec64;
255 u32 usec;
256
257 __asm__ __volatile__ (
258 "1: %0 = CYCLES2\n"
259 "%1 = CYCLES\n"
260 "%2 = CYCLES2\n"
261 "CC = %2 == %0\n"
262 "if ! CC jump 1b\n"
263 : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
264 );
265
266 usec64 = ((u64)cycle2 << 32) + cycle;
267 do_div(usec64, get_cclk() / USEC_PER_SEC);
268 usec = usec64;
269 if (usec == 0)
270 usec = 1;
271
272 pr_info("PM: resume of kernel completes after %ld msec %03ld usec\n",
273 usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
274}
275#endif
276
226static const struct platform_suspend_ops bfin_pm_ops = { 277static const struct platform_suspend_ops bfin_pm_ops = {
227 .enter = bfin_pm_enter, 278 .enter = bfin_pm_enter,
228 .valid = bfin_pm_valid, 279 .valid = bfin_pm_valid,
280#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
281 .end = bfin_pm_end,
282#endif
229}; 283};
230 284
231static int __init bfin_pm_init(void) 285static int __init bfin_pm_init(void)
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 78daae084915..9cb85537bd2b 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -48,7 +48,7 @@ void __init paging_init(void)
48 48
49 unsigned long zones_size[MAX_NR_ZONES] = { 49 unsigned long zones_size[MAX_NR_ZONES] = {
50 [0] = 0, 50 [0] = 0,
51 [ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT, 51 [ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT,
52 [ZONE_NORMAL] = 0, 52 [ZONE_NORMAL] = 0,
53#ifdef CONFIG_HIGHMEM 53#ifdef CONFIG_HIGHMEM
54 [ZONE_HIGHMEM] = 0, 54 [ZONE_HIGHMEM] = 0,
@@ -60,7 +60,8 @@ void __init paging_init(void)
60 60
61 pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n", 61 pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
62 PAGE_ALIGN(memory_start), end_mem); 62 PAGE_ALIGN(memory_start), end_mem);
63 free_area_init(zones_size); 63 free_area_init_node(0, zones_size,
64 CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL);
64} 65}
65 66
66asmlinkage void __init init_pda(void) 67asmlinkage void __init init_pda(void)
@@ -75,9 +76,6 @@ asmlinkage void __init init_pda(void)
75 valid pointers to it. */ 76 valid pointers to it. */
76 memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu])); 77 memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu]));
77 78
78 cpu_pda[0].next = &cpu_pda[1];
79 cpu_pda[1].next = &cpu_pda[0];
80
81#ifdef CONFIG_EXCEPTION_L1_SCRATCH 79#ifdef CONFIG_EXCEPTION_L1_SCRATCH
82 cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \ 80 cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \
83 L1_SCRATCH_LENGTH); 81 L1_SCRATCH_LENGTH);
@@ -109,10 +107,10 @@ void __init mem_init(void)
109 totalram_pages = free_all_bootmem(); 107 totalram_pages = free_all_bootmem();
110 108
111 reservedpages = 0; 109 reservedpages = 0;
112 for (tmp = 0; tmp < max_mapnr; tmp++) 110 for (tmp = ARCH_PFN_OFFSET; tmp < max_mapnr; tmp++)
113 if (PageReserved(pfn_to_page(tmp))) 111 if (PageReserved(pfn_to_page(tmp)))
114 reservedpages++; 112 reservedpages++;
115 freepages = max_mapnr - reservedpages; 113 freepages = max_mapnr - ARCH_PFN_OFFSET - reservedpages;
116 114
117 /* do not count in kernel image between _rambase and _ramstart */ 115 /* do not count in kernel image between _rambase and _ramstart */
118 reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT; 116 reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
@@ -127,7 +125,7 @@ void __init mem_init(void)
127 printk(KERN_INFO 125 printk(KERN_INFO
128 "Memory available: %luk/%luk RAM, " 126 "Memory available: %luk/%luk RAM, "
129 "(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n", 127 "(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n",
130 (unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10, 128 (unsigned long) freepages << (PAGE_SHIFT-10), (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 10,
131 initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10))); 129 initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10)));
132} 130}
133 131
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index 29d98faa1efd..342e378da1ec 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -186,9 +186,45 @@ static void __init l1_inst_sram_init(void)
186#endif 186#endif
187} 187}
188 188
189#ifdef __ADSPBF60x__
190static irqreturn_t l2_ecc_err(int irq, void *dev_id)
191{
192 int status;
193
194 printk(KERN_ERR "L2 ecc error happend\n");
195 status = bfin_read32(L2CTL0_STAT);
196 if (status & 0x1)
197 printk(KERN_ERR "Core channel error type:0x%x, addr:0x%x\n",
198 bfin_read32(L2CTL0_ET0), bfin_read32(L2CTL0_EADDR0));
199 if (status & 0x2)
200 printk(KERN_ERR "System channel error type:0x%x, addr:0x%x\n",
201 bfin_read32(L2CTL0_ET1), bfin_read32(L2CTL0_EADDR1));
202
203 status = status >> 8;
204 if (status)
205 printk(KERN_ERR "L2 Bank%d error, addr:0x%x\n",
206 status, bfin_read32(L2CTL0_ERRADDR0 + status));
207
208 panic("L2 Ecc error");
209 return IRQ_HANDLED;
210}
211#endif
212
189static void __init l2_sram_init(void) 213static void __init l2_sram_init(void)
190{ 214{
191#if L2_LENGTH != 0 215#if L2_LENGTH != 0
216
217#ifdef __ADSPBF60x__
218 int ret;
219
220 ret = request_irq(IRQ_L2CTL0_ECC_ERR, l2_ecc_err, 0, "l2-ecc-err",
221 NULL);
222 if (unlikely(ret < 0)) {
223 printk(KERN_INFO "Fail to request l2 ecc error interrupt");
224 return;
225 }
226#endif
227
192 free_l2_sram_head.next = 228 free_l2_sram_head.next =
193 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); 229 kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
194 if (!free_l2_sram_head.next) { 230 if (!free_l2_sram_head.next) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 13:23:41 -0500