diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-08-07 06:01:22 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-08-09 14:24:32 -0400 |
commit | 6f392d548658a17600da7faaf8a5df25ee5f01f6 (patch) | |
tree | f71098d2faa94ca6525862a0ea50e831abcba75a | |
parent | 0108a3edd5c2e3b150a550d565b6aa1a67c0edbe (diff) |
drm/i915: Use a common seqno for all rings.
This will be used by the eviction logic to maintain fairness between the
rings.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 46 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.h | 1 |
4 files changed, 29 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 151056501a5f..def6ee0a3524 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -244,6 +244,7 @@ typedef struct drm_i915_private { | |||
244 | struct pci_dev *bridge_dev; | 244 | struct pci_dev *bridge_dev; |
245 | struct intel_ring_buffer render_ring; | 245 | struct intel_ring_buffer render_ring; |
246 | struct intel_ring_buffer bsd_ring; | 246 | struct intel_ring_buffer bsd_ring; |
247 | uint32_t next_seqno; | ||
247 | 248 | ||
248 | drm_dma_handle_t *status_page_dmah; | 249 | drm_dma_handle_t *status_page_dmah; |
249 | void *seqno_page; | 250 | void *seqno_page; |
@@ -573,8 +574,6 @@ typedef struct drm_i915_private { | |||
573 | */ | 574 | */ |
574 | struct delayed_work retire_work; | 575 | struct delayed_work retire_work; |
575 | 576 | ||
576 | uint32_t next_gem_seqno; | ||
577 | |||
578 | /** | 577 | /** |
579 | * Waiting sequence number, if any | 578 | * Waiting sequence number, if any |
580 | */ | 579 | */ |
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f150bfd2c851..45b998218d0c 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -4714,6 +4714,8 @@ i915_gem_init_ringbuffer(struct drm_device *dev) | |||
4714 | goto cleanup_render_ring; | 4714 | goto cleanup_render_ring; |
4715 | } | 4715 | } |
4716 | 4716 | ||
4717 | dev_priv->next_seqno = 1; | ||
4718 | |||
4717 | return 0; | 4719 | return 0; |
4718 | 4720 | ||
4719 | cleanup_render_ring: | 4721 | cleanup_render_ring: |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a5d664e0b176..3a0242557220 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -33,18 +33,35 @@ | |||
33 | #include "i915_drm.h" | 33 | #include "i915_drm.h" |
34 | #include "i915_trace.h" | 34 | #include "i915_trace.h" |
35 | 35 | ||
36 | static u32 i915_gem_get_seqno(struct drm_device *dev) | ||
37 | { | ||
38 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
39 | u32 seqno; | ||
40 | |||
41 | seqno = dev_priv->next_seqno; | ||
42 | |||
43 | /* reserve 0 for non-seqno */ | ||
44 | if (++dev_priv->next_seqno == 0) | ||
45 | dev_priv->next_seqno = 1; | ||
46 | |||
47 | return seqno; | ||
48 | } | ||
49 | |||
36 | static void | 50 | static void |
37 | render_ring_flush(struct drm_device *dev, | 51 | render_ring_flush(struct drm_device *dev, |
38 | struct intel_ring_buffer *ring, | 52 | struct intel_ring_buffer *ring, |
39 | u32 invalidate_domains, | 53 | u32 invalidate_domains, |
40 | u32 flush_domains) | 54 | u32 flush_domains) |
41 | { | 55 | { |
56 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
57 | u32 cmd; | ||
58 | |||
42 | #if WATCH_EXEC | 59 | #if WATCH_EXEC |
43 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | 60 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, |
44 | invalidate_domains, flush_domains); | 61 | invalidate_domains, flush_domains); |
45 | #endif | 62 | #endif |
46 | u32 cmd; | 63 | |
47 | trace_i915_gem_request_flush(dev, ring->next_seqno, | 64 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, |
48 | invalidate_domains, flush_domains); | 65 | invalidate_domains, flush_domains); |
49 | 66 | ||
50 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { | 67 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
@@ -233,9 +250,10 @@ render_ring_add_request(struct drm_device *dev, | |||
233 | struct drm_file *file_priv, | 250 | struct drm_file *file_priv, |
234 | u32 flush_domains) | 251 | u32 flush_domains) |
235 | { | 252 | { |
236 | u32 seqno; | ||
237 | drm_i915_private_t *dev_priv = dev->dev_private; | 253 | drm_i915_private_t *dev_priv = dev->dev_private; |
238 | seqno = intel_ring_get_seqno(dev, ring); | 254 | u32 seqno; |
255 | |||
256 | seqno = i915_gem_get_seqno(dev); | ||
239 | 257 | ||
240 | if (IS_GEN6(dev)) { | 258 | if (IS_GEN6(dev)) { |
241 | BEGIN_LP_RING(6); | 259 | BEGIN_LP_RING(6); |
@@ -405,7 +423,9 @@ bsd_ring_add_request(struct drm_device *dev, | |||
405 | u32 flush_domains) | 423 | u32 flush_domains) |
406 | { | 424 | { |
407 | u32 seqno; | 425 | u32 seqno; |
408 | seqno = intel_ring_get_seqno(dev, ring); | 426 | |
427 | seqno = i915_gem_get_seqno(dev); | ||
428 | |||
409 | intel_ring_begin(dev, ring, 4); | 429 | intel_ring_begin(dev, ring, 4); |
410 | intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX); | 430 | intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX); |
411 | intel_ring_emit(dev, ring, | 431 | intel_ring_emit(dev, ring, |
@@ -479,7 +499,7 @@ render_ring_dispatch_gem_execbuffer(struct drm_device *dev, | |||
479 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | 499 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
480 | exec_len = (uint32_t) exec->batch_len; | 500 | exec_len = (uint32_t) exec->batch_len; |
481 | 501 | ||
482 | trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1); | 502 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
483 | 503 | ||
484 | count = nbox ? nbox : 1; | 504 | count = nbox ? nbox : 1; |
485 | 505 | ||
@@ -757,18 +777,6 @@ void intel_fill_struct(struct drm_device *dev, | |||
757 | intel_ring_advance(dev, ring); | 777 | intel_ring_advance(dev, ring); |
758 | } | 778 | } |
759 | 779 | ||
760 | u32 intel_ring_get_seqno(struct drm_device *dev, | ||
761 | struct intel_ring_buffer *ring) | ||
762 | { | ||
763 | u32 seqno; | ||
764 | seqno = ring->next_seqno; | ||
765 | |||
766 | /* reserve 0 for non-seqno */ | ||
767 | if (++ring->next_seqno == 0) | ||
768 | ring->next_seqno = 1; | ||
769 | return seqno; | ||
770 | } | ||
771 | |||
772 | struct intel_ring_buffer render_ring = { | 780 | struct intel_ring_buffer render_ring = { |
773 | .name = "render ring", | 781 | .name = "render ring", |
774 | .regs = { | 782 | .regs = { |
@@ -786,7 +794,6 @@ struct intel_ring_buffer render_ring = { | |||
786 | .head = 0, | 794 | .head = 0, |
787 | .tail = 0, | 795 | .tail = 0, |
788 | .space = 0, | 796 | .space = 0, |
789 | .next_seqno = 1, | ||
790 | .user_irq_refcount = 0, | 797 | .user_irq_refcount = 0, |
791 | .irq_gem_seqno = 0, | 798 | .irq_gem_seqno = 0, |
792 | .waiting_gem_seqno = 0, | 799 | .waiting_gem_seqno = 0, |
@@ -825,7 +832,6 @@ struct intel_ring_buffer bsd_ring = { | |||
825 | .head = 0, | 832 | .head = 0, |
826 | .tail = 0, | 833 | .tail = 0, |
827 | .space = 0, | 834 | .space = 0, |
828 | .next_seqno = 1, | ||
829 | .user_irq_refcount = 0, | 835 | .user_irq_refcount = 0, |
830 | .irq_gem_seqno = 0, | 836 | .irq_gem_seqno = 0, |
831 | .waiting_gem_seqno = 0, | 837 | .waiting_gem_seqno = 0, |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 9b67eead187e..525e7d3edda8 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h | |||
@@ -26,7 +26,6 @@ struct intel_ring_buffer { | |||
26 | unsigned int head; | 26 | unsigned int head; |
27 | unsigned int tail; | 27 | unsigned int tail; |
28 | unsigned int space; | 28 | unsigned int space; |
29 | u32 next_seqno; | ||
30 | struct intel_hw_status_page status_page; | 29 | struct intel_hw_status_page status_page; |
31 | 30 | ||
32 | u32 irq_gem_seqno; /* last seq seem at irq time */ | 31 | u32 irq_gem_seqno; /* last seq seem at irq time */ |