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authorakeemting <akeem@jmicron.com>2008-12-04 00:19:16 -0500
committerDavid S. Miller <davem@davemloft.net>2008-12-04 00:19:16 -0500
commit4f40bf46897ddb57f149c0758f0cef0cc7782f7f (patch)
tree98a0e6000bf92f26b0a2f75afbe8daf8f6f602d5
parent59e4220a1112bf65924bc2e47b5757911b6f349b (diff)
jme: GHC register control fix for new hardware
Due to the hardware design, except the first chip on the market, other chips needs to setup the clock source for MAC processor implicitly through Global Host Control Register(GHC). (Strange design huh?) 10/100M uses the PCI-E as clock source, and 1G uses GPHY. And I reordered the code a little, to make it easier to read. Found-by: "Ethan" <ethanhsiao@jmicron.com> Fixed-by: "akeemting" <akeem@jmicron.com> Signed-off-by: "Guo-Fu Tseng" <cooldavid@cooldavid.org> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/jme.c27
-rw-r--r--drivers/net/jme.h28
2 files changed, 35 insertions, 20 deletions
diff --git a/drivers/net/jme.c b/drivers/net/jme.c
index c3873879003b..e10d9f38662c 100644
--- a/drivers/net/jme.c
+++ b/drivers/net/jme.c
@@ -435,15 +435,18 @@ jme_check_link(struct net_device *netdev, int testonly)
435 GHC_DPX); 435 GHC_DPX);
436 switch (phylink & PHY_LINK_SPEED_MASK) { 436 switch (phylink & PHY_LINK_SPEED_MASK) {
437 case PHY_LINK_SPEED_10M: 437 case PHY_LINK_SPEED_10M:
438 ghc |= GHC_SPEED_10M; 438 ghc |= GHC_SPEED_10M |
439 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
439 strcat(linkmsg, "10 Mbps, "); 440 strcat(linkmsg, "10 Mbps, ");
440 break; 441 break;
441 case PHY_LINK_SPEED_100M: 442 case PHY_LINK_SPEED_100M:
442 ghc |= GHC_SPEED_100M; 443 ghc |= GHC_SPEED_100M |
444 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
443 strcat(linkmsg, "100 Mbps, "); 445 strcat(linkmsg, "100 Mbps, ");
444 break; 446 break;
445 case PHY_LINK_SPEED_1000M: 447 case PHY_LINK_SPEED_1000M:
446 ghc |= GHC_SPEED_1000M; 448 ghc |= GHC_SPEED_1000M |
449 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
447 strcat(linkmsg, "1000 Mbps, "); 450 strcat(linkmsg, "1000 Mbps, ");
448 break; 451 break;
449 default: 452 default:
@@ -463,14 +466,6 @@ jme_check_link(struct net_device *netdev, int testonly)
463 TXTRHD_TXREN | 466 TXTRHD_TXREN |
464 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL)); 467 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
465 } 468 }
466 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
467 "Full-Duplex, " :
468 "Half-Duplex, ");
469
470 if (phylink & PHY_LINK_MDI_STAT)
471 strcat(linkmsg, "MDI-X");
472 else
473 strcat(linkmsg, "MDI");
474 469
475 gpreg1 = GPREG1_DEFAULT; 470 gpreg1 = GPREG1_DEFAULT;
476 if (is_buggy250(jme->pdev->device, jme->chiprev)) { 471 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
@@ -492,11 +487,17 @@ jme_check_link(struct net_device *netdev, int testonly)
492 break; 487 break;
493 } 488 }
494 } 489 }
495 jwrite32(jme, JME_GPREG1, gpreg1);
496 490
497 jme->reg_ghc = ghc; 491 jwrite32(jme, JME_GPREG1, gpreg1);
498 jwrite32(jme, JME_GHC, ghc); 492 jwrite32(jme, JME_GHC, ghc);
493 jme->reg_ghc = ghc;
499 494
495 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
496 "Full-Duplex, " :
497 "Half-Duplex, ");
498 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
499 "MDI-X" :
500 "MDI");
500 msg_link(jme, "Link is up at %s.\n", linkmsg); 501 msg_link(jme, "Link is up at %s.\n", linkmsg);
501 netif_carrier_on(netdev); 502 netif_carrier_on(netdev);
502 } else { 503 } else {
diff --git a/drivers/net/jme.h b/drivers/net/jme.h
index f863aee6648b..adaf3ddbf783 100644
--- a/drivers/net/jme.h
+++ b/drivers/net/jme.h
@@ -815,16 +815,30 @@ static inline u32 smi_phy_addr(int x)
815 * Global Host Control 815 * Global Host Control
816 */ 816 */
817enum jme_ghc_bit_mask { 817enum jme_ghc_bit_mask {
818 GHC_SWRST = 0x40000000, 818 GHC_SWRST = 0x40000000,
819 GHC_DPX = 0x00000040, 819 GHC_DPX = 0x00000040,
820 GHC_SPEED = 0x00000030, 820 GHC_SPEED = 0x00000030,
821 GHC_LINK_POLL = 0x00000001, 821 GHC_LINK_POLL = 0x00000001,
822}; 822};
823 823
824enum jme_ghc_speed_val { 824enum jme_ghc_speed_val {
825 GHC_SPEED_10M = 0x00000010, 825 GHC_SPEED_10M = 0x00000010,
826 GHC_SPEED_100M = 0x00000020, 826 GHC_SPEED_100M = 0x00000020,
827 GHC_SPEED_1000M = 0x00000030, 827 GHC_SPEED_1000M = 0x00000030,
828};
829
830enum jme_ghc_to_clk {
831 GHC_TO_CLK_OFF = 0x00000000,
832 GHC_TO_CLK_GPHY = 0x00400000,
833 GHC_TO_CLK_PCIE = 0x00800000,
834 GHC_TO_CLK_INVALID = 0x00C00000,
835};
836
837enum jme_ghc_txmac_clk {
838 GHC_TXMAC_CLK_OFF = 0x00000000,
839 GHC_TXMAC_CLK_GPHY = 0x00100000,
840 GHC_TXMAC_CLK_PCIE = 0x00200000,
841 GHC_TXMAC_CLK_INVALID = 0x00300000,
828}; 842};
829 843
830/* 844/*