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authorJoe Perches <joe@perches.com>2010-11-29 02:41:56 -0500
committerDavid S. Miller <davem@davemloft.net>2010-11-29 14:44:53 -0500
commit294a554e274f961ac33c7d739d5b912bd0005f5b (patch)
treea1d8af440477c5c6e0c085cc9ccb2dc3358c1a9a
parentf52dafc1a67c98baa9b6fa1866a4caa4be4831fb (diff)
forcedeth: Use pr_fmt and pr_<level>
Convert printks to pr_<level>. Remove "forcedeth: " from some calls as it's now added by pr_fmt. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/forcedeth.c256
1 files changed, 142 insertions, 114 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index b30a5992e332..1c6f4ef9f928 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -39,6 +39,9 @@
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few 39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic. 40 * superfluous timer interrupts from the nic.
41 */ 41 */
42
43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
42#define FORCEDETH_VERSION "0.64" 45#define FORCEDETH_VERSION "0.64"
43#define DRV_NAME "forcedeth" 46#define DRV_NAME "forcedeth"
44 47
@@ -1189,7 +1192,8 @@ static int phy_init(struct net_device *dev)
1189 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); 1192 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1190 reg &= ~PHY_MARVELL_E3016_INITMASK; 1193 reg &= ~PHY_MARVELL_E3016_INITMASK;
1191 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { 1194 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1192 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev)); 1195 pr_info("%s: phy write to errata reg failed\n",
1196 pci_name(np->pci_dev));
1193 return PHY_ERROR; 1197 return PHY_ERROR;
1194 } 1198 }
1195 } 1199 }
@@ -1197,31 +1201,38 @@ static int phy_init(struct net_device *dev)
1197 if (np->phy_model == PHY_MODEL_REALTEK_8211 && 1201 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1198 np->phy_rev == PHY_REV_REALTEK_8211B) { 1202 np->phy_rev == PHY_REV_REALTEK_8211B) {
1199 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1203 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1200 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1204 pr_info("%s: phy init failed\n",
1205 pci_name(np->pci_dev));
1201 return PHY_ERROR; 1206 return PHY_ERROR;
1202 } 1207 }
1203 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { 1208 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1204 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1209 pr_info("%s: phy init failed\n",
1210 pci_name(np->pci_dev));
1205 return PHY_ERROR; 1211 return PHY_ERROR;
1206 } 1212 }
1207 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { 1213 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1208 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1214 pr_info("%s: phy init failed\n",
1215 pci_name(np->pci_dev));
1209 return PHY_ERROR; 1216 return PHY_ERROR;
1210 } 1217 }
1211 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { 1218 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1212 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1219 pr_info("%s: phy init failed\n",
1220 pci_name(np->pci_dev));
1213 return PHY_ERROR; 1221 return PHY_ERROR;
1214 } 1222 }
1215 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { 1223 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1216 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1224 pr_info("%s: phy init failed\n",
1225 pci_name(np->pci_dev));
1217 return PHY_ERROR; 1226 return PHY_ERROR;
1218 } 1227 }
1219 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { 1228 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1220 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1229 pr_info("%s: phy init failed\n",
1230 pci_name(np->pci_dev));
1221 return PHY_ERROR; 1231 return PHY_ERROR;
1222 } 1232 }
1223 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1233 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1224 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1234 pr_info("%s: phy init failed\n",
1235 pci_name(np->pci_dev));
1225 return PHY_ERROR; 1236 return PHY_ERROR;
1226 } 1237 }
1227 } 1238 }
@@ -1241,23 +1252,27 @@ static int phy_init(struct net_device *dev)
1241 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); 1252 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1242 reg |= PHY_REALTEK_INIT9; 1253 reg |= PHY_REALTEK_INIT9;
1243 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) { 1254 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1244 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1255 pr_info("%s: phy init failed\n",
1256 pci_name(np->pci_dev));
1245 return PHY_ERROR; 1257 return PHY_ERROR;
1246 } 1258 }
1247 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) { 1259 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1248 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1260 pr_info("%s: phy init failed\n",
1261 pci_name(np->pci_dev));
1249 return PHY_ERROR; 1262 return PHY_ERROR;
1250 } 1263 }
1251 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); 1264 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1252 if (!(reg & PHY_REALTEK_INIT11)) { 1265 if (!(reg & PHY_REALTEK_INIT11)) {
1253 reg |= PHY_REALTEK_INIT11; 1266 reg |= PHY_REALTEK_INIT11;
1254 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) { 1267 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1255 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1268 pr_info("%s: phy init failed\n",
1269 pci_name(np->pci_dev));
1256 return PHY_ERROR; 1270 return PHY_ERROR;
1257 } 1271 }
1258 } 1272 }
1259 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1273 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1260 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1274 pr_info("%s: phy init failed\n",
1275 pci_name(np->pci_dev));
1261 return PHY_ERROR; 1276 return PHY_ERROR;
1262 } 1277 }
1263 } 1278 }
@@ -1266,7 +1281,8 @@ static int phy_init(struct net_device *dev)
1266 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); 1281 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1267 phy_reserved |= PHY_REALTEK_INIT7; 1282 phy_reserved |= PHY_REALTEK_INIT7;
1268 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { 1283 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1269 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1284 pr_info("%s: phy init failed\n",
1285 pci_name(np->pci_dev));
1270 return PHY_ERROR; 1286 return PHY_ERROR;
1271 } 1287 }
1272 } 1288 }
@@ -1277,7 +1293,8 @@ static int phy_init(struct net_device *dev)
1277 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); 1293 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1278 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP); 1294 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1279 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { 1295 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1280 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev)); 1296 pr_info("%s: phy write to advertise failed\n",
1297 pci_name(np->pci_dev));
1281 return PHY_ERROR; 1298 return PHY_ERROR;
1282 } 1299 }
1283 1300
@@ -1296,7 +1313,7 @@ static int phy_init(struct net_device *dev)
1296 mii_control_1000 &= ~ADVERTISE_1000FULL; 1313 mii_control_1000 &= ~ADVERTISE_1000FULL;
1297 1314
1298 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { 1315 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1299 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1316 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1300 return PHY_ERROR; 1317 return PHY_ERROR;
1301 } 1318 }
1302 } else 1319 } else
@@ -1311,7 +1328,7 @@ static int phy_init(struct net_device *dev)
1311 /* start autoneg since we already performed hw reset above */ 1328 /* start autoneg since we already performed hw reset above */
1312 mii_control |= BMCR_ANRESTART; 1329 mii_control |= BMCR_ANRESTART;
1313 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { 1330 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1314 printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev)); 1331 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1315 return PHY_ERROR; 1332 return PHY_ERROR;
1316 } 1333 }
1317 } else { 1334 } else {
@@ -1319,7 +1336,7 @@ static int phy_init(struct net_device *dev)
1319 * (certain phys need bmcr to be setup with reset) 1336 * (certain phys need bmcr to be setup with reset)
1320 */ 1337 */
1321 if (phy_reset(dev, mii_control)) { 1338 if (phy_reset(dev, mii_control)) {
1322 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); 1339 pr_info("%s: phy reset failed\n", pci_name(np->pci_dev));
1323 return PHY_ERROR; 1340 return PHY_ERROR;
1324 } 1341 }
1325 } 1342 }
@@ -1330,13 +1347,13 @@ static int phy_init(struct net_device *dev)
1330 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); 1347 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1331 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); 1348 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1332 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) { 1349 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1333 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1350 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1334 return PHY_ERROR; 1351 return PHY_ERROR;
1335 } 1352 }
1336 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); 1353 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1337 phy_reserved |= PHY_CICADA_INIT5; 1354 phy_reserved |= PHY_CICADA_INIT5;
1338 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) { 1355 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1339 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1356 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1340 return PHY_ERROR; 1357 return PHY_ERROR;
1341 } 1358 }
1342 } 1359 }
@@ -1344,77 +1361,77 @@ static int phy_init(struct net_device *dev)
1344 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); 1361 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1345 phy_reserved |= PHY_CICADA_INIT6; 1362 phy_reserved |= PHY_CICADA_INIT6;
1346 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) { 1363 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1347 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1364 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1348 return PHY_ERROR; 1365 return PHY_ERROR;
1349 } 1366 }
1350 } 1367 }
1351 if (np->phy_oui == PHY_OUI_VITESSE) { 1368 if (np->phy_oui == PHY_OUI_VITESSE) {
1352 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) { 1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1353 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1370 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1354 return PHY_ERROR; 1371 return PHY_ERROR;
1355 } 1372 }
1356 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) { 1373 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1357 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1374 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1358 return PHY_ERROR; 1375 return PHY_ERROR;
1359 } 1376 }
1360 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); 1377 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1361 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { 1378 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1362 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1379 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1363 return PHY_ERROR; 1380 return PHY_ERROR;
1364 } 1381 }
1365 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); 1382 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1366 phy_reserved &= ~PHY_VITESSE_INIT_MSK1; 1383 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1367 phy_reserved |= PHY_VITESSE_INIT3; 1384 phy_reserved |= PHY_VITESSE_INIT3;
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { 1385 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1369 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1386 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1370 return PHY_ERROR; 1387 return PHY_ERROR;
1371 } 1388 }
1372 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) { 1389 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1373 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1390 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1374 return PHY_ERROR; 1391 return PHY_ERROR;
1375 } 1392 }
1376 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) { 1393 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1377 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1394 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1378 return PHY_ERROR; 1395 return PHY_ERROR;
1379 } 1396 }
1380 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); 1397 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1381 phy_reserved &= ~PHY_VITESSE_INIT_MSK1; 1398 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1382 phy_reserved |= PHY_VITESSE_INIT3; 1399 phy_reserved |= PHY_VITESSE_INIT3;
1383 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { 1400 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1384 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1401 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1385 return PHY_ERROR; 1402 return PHY_ERROR;
1386 } 1403 }
1387 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); 1404 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1388 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { 1405 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1389 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1406 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1390 return PHY_ERROR; 1407 return PHY_ERROR;
1391 } 1408 }
1392 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) { 1409 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1393 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1410 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1394 return PHY_ERROR; 1411 return PHY_ERROR;
1395 } 1412 }
1396 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) { 1413 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1397 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1414 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1398 return PHY_ERROR; 1415 return PHY_ERROR;
1399 } 1416 }
1400 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ); 1417 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1401 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) { 1418 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1402 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1419 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1403 return PHY_ERROR; 1420 return PHY_ERROR;
1404 } 1421 }
1405 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ); 1422 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1406 phy_reserved &= ~PHY_VITESSE_INIT_MSK2; 1423 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1407 phy_reserved |= PHY_VITESSE_INIT8; 1424 phy_reserved |= PHY_VITESSE_INIT8;
1408 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) { 1425 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1409 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1426 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1410 return PHY_ERROR; 1427 return PHY_ERROR;
1411 } 1428 }
1412 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) { 1429 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1413 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1430 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1414 return PHY_ERROR; 1431 return PHY_ERROR;
1415 } 1432 }
1416 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) { 1433 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1417 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1434 pr_info("%s: phy init failed\n", pci_name(np->pci_dev));
1418 return PHY_ERROR; 1435 return PHY_ERROR;
1419 } 1436 }
1420 } 1437 }
@@ -1423,31 +1440,38 @@ static int phy_init(struct net_device *dev)
1423 np->phy_rev == PHY_REV_REALTEK_8211B) { 1440 np->phy_rev == PHY_REV_REALTEK_8211B) {
1424 /* reset could have cleared these out, set them back */ 1441 /* reset could have cleared these out, set them back */
1425 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1442 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1426 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1443 pr_info("%s: phy init failed\n",
1444 pci_name(np->pci_dev));
1427 return PHY_ERROR; 1445 return PHY_ERROR;
1428 } 1446 }
1429 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) { 1447 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1430 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1448 pr_info("%s: phy init failed\n",
1449 pci_name(np->pci_dev));
1431 return PHY_ERROR; 1450 return PHY_ERROR;
1432 } 1451 }
1433 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { 1452 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1434 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1453 pr_info("%s: phy init failed\n",
1454 pci_name(np->pci_dev));
1435 return PHY_ERROR; 1455 return PHY_ERROR;
1436 } 1456 }
1437 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) { 1457 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1438 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1458 pr_info("%s: phy init failed\n",
1459 pci_name(np->pci_dev));
1439 return PHY_ERROR; 1460 return PHY_ERROR;
1440 } 1461 }
1441 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) { 1462 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
1442 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1463 pr_info("%s: phy init failed\n",
1464 pci_name(np->pci_dev));
1443 return PHY_ERROR; 1465 return PHY_ERROR;
1444 } 1466 }
1445 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) { 1467 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
1446 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1468 pr_info("%s: phy init failed\n",
1469 pci_name(np->pci_dev));
1447 return PHY_ERROR; 1470 return PHY_ERROR;
1448 } 1471 }
1449 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1472 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1450 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1473 pr_info("%s: phy init failed\n",
1474 pci_name(np->pci_dev));
1451 return PHY_ERROR; 1475 return PHY_ERROR;
1452 } 1476 }
1453 } 1477 }
@@ -1456,24 +1480,28 @@ static int phy_init(struct net_device *dev)
1456 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); 1480 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1457 phy_reserved |= PHY_REALTEK_INIT7; 1481 phy_reserved |= PHY_REALTEK_INIT7;
1458 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) { 1482 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
1459 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1483 pr_info("%s: phy init failed\n",
1484 pci_name(np->pci_dev));
1460 return PHY_ERROR; 1485 return PHY_ERROR;
1461 } 1486 }
1462 } 1487 }
1463 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { 1488 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1464 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) { 1489 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1465 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1490 pr_info("%s: phy init failed\n",
1491 pci_name(np->pci_dev));
1466 return PHY_ERROR; 1492 return PHY_ERROR;
1467 } 1493 }
1468 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); 1494 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
1469 phy_reserved &= ~PHY_REALTEK_INIT_MSK1; 1495 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1470 phy_reserved |= PHY_REALTEK_INIT3; 1496 phy_reserved |= PHY_REALTEK_INIT3;
1471 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) { 1497 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
1472 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1498 pr_info("%s: phy init failed\n",
1499 pci_name(np->pci_dev));
1473 return PHY_ERROR; 1500 return PHY_ERROR;
1474 } 1501 }
1475 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) { 1502 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1476 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev)); 1503 pr_info("%s: phy init failed\n",
1504 pci_name(np->pci_dev));
1477 return PHY_ERROR; 1505 return PHY_ERROR;
1478 } 1506 }
1479 } 1507 }
@@ -1532,7 +1560,7 @@ static void nv_stop_rx(struct net_device *dev)
1532 writel(rx_ctrl, base + NvRegReceiverControl); 1560 writel(rx_ctrl, base + NvRegReceiverControl);
1533 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, 1561 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1534 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX)) 1562 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1535 printk(KERN_INFO "nv_stop_rx: ReceiverStatus remained busy"); 1563 pr_info("%s: ReceiverStatus remained busy\n", __func__);
1536 1564
1537 udelay(NV_RXSTOP_DELAY2); 1565 udelay(NV_RXSTOP_DELAY2);
1538 if (!np->mac_in_use) 1566 if (!np->mac_in_use)
@@ -1567,7 +1595,7 @@ static void nv_stop_tx(struct net_device *dev)
1567 writel(tx_ctrl, base + NvRegTransmitterControl); 1595 writel(tx_ctrl, base + NvRegTransmitterControl);
1568 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, 1596 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1569 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX)) 1597 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1570 printk(KERN_INFO "nv_stop_tx: TransmitterStatus remained busy"); 1598 pr_info("%s: TransmitterStatus remained busy\n", __func__);
1571 1599
1572 udelay(NV_TXSTOP_DELAY2); 1600 udelay(NV_TXSTOP_DELAY2);
1573 if (!np->mac_in_use) 1601 if (!np->mac_in_use)
@@ -2485,57 +2513,53 @@ static void nv_tx_timeout(struct net_device *dev)
2485 u32 status; 2513 u32 status;
2486 union ring_type put_tx; 2514 union ring_type put_tx;
2487 int saved_tx_limit; 2515 int saved_tx_limit;
2516 int i;
2488 2517
2489 if (np->msi_flags & NV_MSI_X_ENABLED) 2518 if (np->msi_flags & NV_MSI_X_ENABLED)
2490 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; 2519 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2491 else 2520 else
2492 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; 2521 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2493 2522
2494 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status); 2523 pr_info("%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2495 2524
2496 { 2525 pr_info("%s: Ring at %lx\n", dev->name, (unsigned long)np->ring_addr);
2497 int i; 2526 pr_info("%s: Dumping tx registers\n", dev->name);
2498 2527 for (i = 0; i <= np->register_size; i += 32) {
2499 printk(KERN_INFO "%s: Ring at %lx\n", 2528 pr_info("%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2500 dev->name, (unsigned long)np->ring_addr); 2529 i,
2501 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name); 2530 readl(base + i + 0), readl(base + i + 4),
2502 for (i = 0; i <= np->register_size; i += 32) { 2531 readl(base + i + 8), readl(base + i + 12),
2503 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n", 2532 readl(base + i + 16), readl(base + i + 20),
2504 i, 2533 readl(base + i + 24), readl(base + i + 28));
2505 readl(base + i + 0), readl(base + i + 4), 2534 }
2506 readl(base + i + 8), readl(base + i + 12), 2535 pr_info("%s: Dumping tx ring\n", dev->name);
2507 readl(base + i + 16), readl(base + i + 20), 2536 for (i = 0; i < np->tx_ring_size; i += 4) {
2508 readl(base + i + 24), readl(base + i + 28)); 2537 if (!nv_optimized(np)) {
2509 } 2538 pr_info("%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2510 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name); 2539 i,
2511 for (i = 0; i < np->tx_ring_size; i += 4) { 2540 le32_to_cpu(np->tx_ring.orig[i].buf),
2512 if (!nv_optimized(np)) { 2541 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2513 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n", 2542 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2514 i, 2543 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2515 le32_to_cpu(np->tx_ring.orig[i].buf), 2544 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2516 le32_to_cpu(np->tx_ring.orig[i].flaglen), 2545 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2517 le32_to_cpu(np->tx_ring.orig[i+1].buf), 2546 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2518 le32_to_cpu(np->tx_ring.orig[i+1].flaglen), 2547 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2519 le32_to_cpu(np->tx_ring.orig[i+2].buf), 2548 } else {
2520 le32_to_cpu(np->tx_ring.orig[i+2].flaglen), 2549 pr_info("%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2521 le32_to_cpu(np->tx_ring.orig[i+3].buf), 2550 i,
2522 le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); 2551 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2523 } else { 2552 le32_to_cpu(np->tx_ring.ex[i].buflow),
2524 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n", 2553 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2525 i, 2554 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2526 le32_to_cpu(np->tx_ring.ex[i].bufhigh), 2555 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2527 le32_to_cpu(np->tx_ring.ex[i].buflow), 2556 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2528 le32_to_cpu(np->tx_ring.ex[i].flaglen), 2557 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2529 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), 2558 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2530 le32_to_cpu(np->tx_ring.ex[i+1].buflow), 2559 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2531 le32_to_cpu(np->tx_ring.ex[i+1].flaglen), 2560 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2532 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), 2561 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2533 le32_to_cpu(np->tx_ring.ex[i+2].buflow), 2562 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2534 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2535 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2536 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2537 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2538 }
2539 } 2563 }
2540 } 2564 }
2541 2565
@@ -3308,14 +3332,14 @@ static void nv_linkchange(struct net_device *dev)
3308 if (nv_update_linkspeed(dev)) { 3332 if (nv_update_linkspeed(dev)) {
3309 if (!netif_carrier_ok(dev)) { 3333 if (!netif_carrier_ok(dev)) {
3310 netif_carrier_on(dev); 3334 netif_carrier_on(dev);
3311 printk(KERN_INFO "%s: link up.\n", dev->name); 3335 pr_info("%s: link up\n", dev->name);
3312 nv_txrx_gate(dev, false); 3336 nv_txrx_gate(dev, false);
3313 nv_start_rx(dev); 3337 nv_start_rx(dev);
3314 } 3338 }
3315 } else { 3339 } else {
3316 if (netif_carrier_ok(dev)) { 3340 if (netif_carrier_ok(dev)) {
3317 netif_carrier_off(dev); 3341 netif_carrier_off(dev);
3318 printk(KERN_INFO "%s: link down.\n", dev->name); 3342 pr_info("%s: link down\n", dev->name);
3319 nv_txrx_gate(dev, true); 3343 nv_txrx_gate(dev, true);
3320 nv_stop_rx(dev); 3344 nv_stop_rx(dev);
3321 } 3345 }
@@ -3764,7 +3788,8 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3764 sprintf(np->name_rx, "%s-rx", dev->name); 3788 sprintf(np->name_rx, "%s-rx", dev->name);
3765 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, 3789 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3766 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) { 3790 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3767 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret); 3791 pr_info("request_irq failed for rx %d\n",
3792 ret);
3768 pci_disable_msix(np->pci_dev); 3793 pci_disable_msix(np->pci_dev);
3769 np->msi_flags &= ~NV_MSI_X_ENABLED; 3794 np->msi_flags &= ~NV_MSI_X_ENABLED;
3770 goto out_err; 3795 goto out_err;
@@ -3773,7 +3798,8 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3773 sprintf(np->name_tx, "%s-tx", dev->name); 3798 sprintf(np->name_tx, "%s-tx", dev->name);
3774 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, 3799 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3775 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) { 3800 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3776 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret); 3801 pr_info("request_irq failed for tx %d\n",
3802 ret);
3777 pci_disable_msix(np->pci_dev); 3803 pci_disable_msix(np->pci_dev);
3778 np->msi_flags &= ~NV_MSI_X_ENABLED; 3804 np->msi_flags &= ~NV_MSI_X_ENABLED;
3779 goto out_free_rx; 3805 goto out_free_rx;
@@ -3782,7 +3808,8 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3782 sprintf(np->name_other, "%s-other", dev->name); 3808 sprintf(np->name_other, "%s-other", dev->name);
3783 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, 3809 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3784 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) { 3810 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3785 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret); 3811 pr_info("request_irq failed for link %d\n",
3812 ret);
3786 pci_disable_msix(np->pci_dev); 3813 pci_disable_msix(np->pci_dev);
3787 np->msi_flags &= ~NV_MSI_X_ENABLED; 3814 np->msi_flags &= ~NV_MSI_X_ENABLED;
3788 goto out_free_tx; 3815 goto out_free_tx;
@@ -3796,7 +3823,7 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3796 } else { 3823 } else {
3797 /* Request irq for all interrupts */ 3824 /* Request irq for all interrupts */
3798 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) { 3825 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3799 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); 3826 pr_info("request_irq failed %d\n", ret);
3800 pci_disable_msix(np->pci_dev); 3827 pci_disable_msix(np->pci_dev);
3801 np->msi_flags &= ~NV_MSI_X_ENABLED; 3828 np->msi_flags &= ~NV_MSI_X_ENABLED;
3802 goto out_err; 3829 goto out_err;
@@ -3814,7 +3841,7 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
3814 np->msi_flags |= NV_MSI_ENABLED; 3841 np->msi_flags |= NV_MSI_ENABLED;
3815 dev->irq = np->pci_dev->irq; 3842 dev->irq = np->pci_dev->irq;
3816 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) { 3843 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3817 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret); 3844 pr_info("request_irq failed %d\n", ret);
3818 pci_disable_msi(np->pci_dev); 3845 pci_disable_msi(np->pci_dev);
3819 np->msi_flags &= ~NV_MSI_ENABLED; 3846 np->msi_flags &= ~NV_MSI_ENABLED;
3820 dev->irq = np->pci_dev->irq; 3847 dev->irq = np->pci_dev->irq;
@@ -3899,7 +3926,7 @@ static void nv_do_nic_poll(unsigned long data)
3899 3926
3900 if (np->recover_error) { 3927 if (np->recover_error) {
3901 np->recover_error = 0; 3928 np->recover_error = 0;
3902 printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name); 3929 pr_info("%s: MAC in recoverable error state\n", dev->name);
3903 if (netif_running(dev)) { 3930 if (netif_running(dev)) {
3904 netif_tx_lock_bh(dev); 3931 netif_tx_lock_bh(dev);
3905 netif_addr_lock(dev); 3932 netif_addr_lock(dev);
@@ -4195,14 +4222,14 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4195 } 4222 }
4196 4223
4197 if (netif_running(dev)) 4224 if (netif_running(dev))
4198 printk(KERN_INFO "%s: link down.\n", dev->name); 4225 pr_info("%s: link down\n", dev->name);
4199 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 4226 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4200 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { 4227 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4201 bmcr |= BMCR_ANENABLE; 4228 bmcr |= BMCR_ANENABLE;
4202 /* reset the phy in order for settings to stick, 4229 /* reset the phy in order for settings to stick,
4203 * and cause autoneg to start */ 4230 * and cause autoneg to start */
4204 if (phy_reset(dev, bmcr)) { 4231 if (phy_reset(dev, bmcr)) {
4205 printk(KERN_INFO "%s: phy reset failed\n", dev->name); 4232 pr_info("%s: phy reset failed\n", dev->name);
4206 return -EINVAL; 4233 return -EINVAL;
4207 } 4234 }
4208 } else { 4235 } else {
@@ -4251,7 +4278,7 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4251 if (np->phy_oui == PHY_OUI_MARVELL) { 4278 if (np->phy_oui == PHY_OUI_MARVELL) {
4252 /* reset the phy in order for forced mode settings to stick */ 4279 /* reset the phy in order for forced mode settings to stick */
4253 if (phy_reset(dev, bmcr)) { 4280 if (phy_reset(dev, bmcr)) {
4254 printk(KERN_INFO "%s: phy reset failed\n", dev->name); 4281 pr_info("%s: phy reset failed\n", dev->name);
4255 return -EINVAL; 4282 return -EINVAL;
4256 } 4283 }
4257 } else { 4284 } else {
@@ -4313,7 +4340,7 @@ static int nv_nway_reset(struct net_device *dev)
4313 spin_unlock(&np->lock); 4340 spin_unlock(&np->lock);
4314 netif_addr_unlock(dev); 4341 netif_addr_unlock(dev);
4315 netif_tx_unlock_bh(dev); 4342 netif_tx_unlock_bh(dev);
4316 printk(KERN_INFO "%s: link down.\n", dev->name); 4343 pr_info("%s: link down\n", dev->name);
4317 } 4344 }
4318 4345
4319 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 4346 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
@@ -4321,7 +4348,7 @@ static int nv_nway_reset(struct net_device *dev)
4321 bmcr |= BMCR_ANENABLE; 4348 bmcr |= BMCR_ANENABLE;
4322 /* reset the phy in order for settings to stick*/ 4349 /* reset the phy in order for settings to stick*/
4323 if (phy_reset(dev, bmcr)) { 4350 if (phy_reset(dev, bmcr)) {
4324 printk(KERN_INFO "%s: phy reset failed\n", dev->name); 4351 pr_info("%s: phy reset failed\n", dev->name);
4325 return -EINVAL; 4352 return -EINVAL;
4326 } 4353 }
4327 } else { 4354 } else {
@@ -4494,12 +4521,13 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam*
4494 4521
4495 if ((!np->autoneg && np->duplex == 0) || 4522 if ((!np->autoneg && np->duplex == 0) ||
4496 (np->autoneg && !pause->autoneg && np->duplex == 0)) { 4523 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4497 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n", 4524 pr_info("%s: can not set pause settings when forced link is in half duplex\n",
4498 dev->name); 4525 dev->name);
4499 return -EINVAL; 4526 return -EINVAL;
4500 } 4527 }
4501 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { 4528 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4502 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name); 4529 pr_info("%s: hardware does not support tx pause frames\n",
4530 dev->name);
4503 return -EINVAL; 4531 return -EINVAL;
4504 } 4532 }
4505 4533
@@ -4534,7 +4562,7 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam*
4534 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); 4562 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4535 4563
4536 if (netif_running(dev)) 4564 if (netif_running(dev))
4537 printk(KERN_INFO "%s: link down.\n", dev->name); 4565 pr_info("%s: link down\n", dev->name);
4538 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 4566 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4539 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 4567 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4540 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); 4568 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
@@ -4796,8 +4824,8 @@ static int nv_loopback_test(struct net_device *dev)
4796 pkt_len = ETH_DATA_LEN; 4824 pkt_len = ETH_DATA_LEN;
4797 tx_skb = dev_alloc_skb(pkt_len); 4825 tx_skb = dev_alloc_skb(pkt_len);
4798 if (!tx_skb) { 4826 if (!tx_skb) {
4799 printk(KERN_ERR "dev_alloc_skb() failed during loopback test" 4827 pr_err("dev_alloc_skb() failed during loopback test of %s\n",
4800 " of %s\n", dev->name); 4828 dev->name);
4801 ret = 0; 4829 ret = 0;
4802 goto out; 4830 goto out;
4803 } 4831 }
@@ -5160,7 +5188,7 @@ static int nv_open(struct net_device *dev)
5160 if (reg_delay(dev, NvRegUnknownSetupReg5, 5188 if (reg_delay(dev, NvRegUnknownSetupReg5,
5161 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, 5189 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5162 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX)) 5190 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5163 printk(KERN_INFO "open: SetupReg5, Bit 31 remained off\n"); 5191 pr_info("%s: SetupReg5, Bit 31 remained off\n", __func__);
5164 5192
5165 writel(0, base + NvRegMIIMask); 5193 writel(0, base + NvRegMIIMask);
5166 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); 5194 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
@@ -5249,7 +5277,7 @@ static int nv_open(struct net_device *dev)
5249 if (ret) { 5277 if (ret) {
5250 netif_carrier_on(dev); 5278 netif_carrier_on(dev);
5251 } else { 5279 } else {
5252 printk(KERN_INFO "%s: no link during initialization.\n", dev->name); 5280 pr_info("%s: no link during initialization\n", dev->name);
5253 netif_carrier_off(dev); 5281 netif_carrier_off(dev);
5254 } 5282 }
5255 if (oom) 5283 if (oom)
@@ -5361,8 +5389,8 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
5361 static int printed_version; 5389 static int printed_version;
5362 5390
5363 if (!printed_version++) 5391 if (!printed_version++)
5364 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet" 5392 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5365 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION); 5393 FORCEDETH_VERSION);
5366 5394
5367 dev = alloc_etherdev(sizeof(struct fe_priv)); 5395 dev = alloc_etherdev(sizeof(struct fe_priv));
5368 err = -ENOMEM; 5396 err = -ENOMEM;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 08:57:44 -0500