diff options
author | Joe Perches <joe@perches.com> | 2010-03-28 04:35:45 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-03-31 02:42:26 -0400 |
commit | dd4683daed6be3fd71105a8289257b75e151288c (patch) | |
tree | 83e691e0da3efd4bc378e458f3f5a765fe79df1b | |
parent | 02cdce53f3d0d3eee8188944c96150ee8c97100d (diff) |
drivers/net/ipg: Remove invalid IPG_DDEBUG_MSG uses, neaten
Some no longer valid IPG_DDEBUG_MSG uses are removed
Validate IPG_DDEBUG_MSG arguments when not #defined
Neaten #defines
marco/macro typo correction
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ipg.c | 5 | ||||
-rw-r--r-- | drivers/net/ipg.h | 109 |
2 files changed, 61 insertions, 53 deletions
diff --git a/drivers/net/ipg.c b/drivers/net/ipg.c index 150415e83f61..0d7ad3f2d0f3 100644 --- a/drivers/net/ipg.c +++ b/drivers/net/ipg.c | |||
@@ -1547,8 +1547,6 @@ static void ipg_reset_after_host_error(struct work_struct *work) | |||
1547 | container_of(work, struct ipg_nic_private, task.work); | 1547 | container_of(work, struct ipg_nic_private, task.work); |
1548 | struct net_device *dev = sp->dev; | 1548 | struct net_device *dev = sp->dev; |
1549 | 1549 | ||
1550 | IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL)); | ||
1551 | |||
1552 | /* | 1550 | /* |
1553 | * Acknowledge HostError interrupt by resetting | 1551 | * Acknowledge HostError interrupt by resetting |
1554 | * IPG DMA and HOST. | 1552 | * IPG DMA and HOST. |
@@ -1825,9 +1823,6 @@ static int ipg_nic_stop(struct net_device *dev) | |||
1825 | 1823 | ||
1826 | netif_stop_queue(dev); | 1824 | netif_stop_queue(dev); |
1827 | 1825 | ||
1828 | IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount); | ||
1829 | IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount); | ||
1830 | IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount); | ||
1831 | IPG_DUMPTFDLIST(dev); | 1826 | IPG_DUMPTFDLIST(dev); |
1832 | 1827 | ||
1833 | do { | 1828 | do { |
diff --git a/drivers/net/ipg.h b/drivers/net/ipg.h index dfc2541bb556..6ce027355fcf 100644 --- a/drivers/net/ipg.h +++ b/drivers/net/ipg.h | |||
@@ -29,7 +29,7 @@ | |||
29 | /* GMII based PHY IDs */ | 29 | /* GMII based PHY IDs */ |
30 | #define NS 0x2000 | 30 | #define NS 0x2000 |
31 | #define MARVELL 0x0141 | 31 | #define MARVELL 0x0141 |
32 | #define ICPLUS_PHY 0x243 | 32 | #define ICPLUS_PHY 0x243 |
33 | 33 | ||
34 | /* NIC Physical Layer Device MII register fields. */ | 34 | /* NIC Physical Layer Device MII register fields. */ |
35 | #define MII_PHY_SELECTOR_IEEE8023 0x0001 | 35 | #define MII_PHY_SELECTOR_IEEE8023 0x0001 |
@@ -96,31 +96,31 @@ enum ipg_regs { | |||
96 | }; | 96 | }; |
97 | 97 | ||
98 | /* Ethernet MIB statistic register offsets. */ | 98 | /* Ethernet MIB statistic register offsets. */ |
99 | #define IPG_OCTETRCVOK 0xA8 | 99 | #define IPG_OCTETRCVOK 0xA8 |
100 | #define IPG_MCSTOCTETRCVDOK 0xAC | 100 | #define IPG_MCSTOCTETRCVDOK 0xAC |
101 | #define IPG_BCSTOCTETRCVOK 0xB0 | 101 | #define IPG_BCSTOCTETRCVOK 0xB0 |
102 | #define IPG_FRAMESRCVDOK 0xB4 | 102 | #define IPG_FRAMESRCVDOK 0xB4 |
103 | #define IPG_MCSTFRAMESRCVDOK 0xB8 | 103 | #define IPG_MCSTFRAMESRCVDOK 0xB8 |
104 | #define IPG_BCSTFRAMESRCVDOK 0xBE | 104 | #define IPG_BCSTFRAMESRCVDOK 0xBE |
105 | #define IPG_MACCONTROLFRAMESRCVD 0xC6 | 105 | #define IPG_MACCONTROLFRAMESRCVD 0xC6 |
106 | #define IPG_FRAMETOOLONGERRRORS 0xC8 | 106 | #define IPG_FRAMETOOLONGERRRORS 0xC8 |
107 | #define IPG_INRANGELENGTHERRORS 0xCA | 107 | #define IPG_INRANGELENGTHERRORS 0xCA |
108 | #define IPG_FRAMECHECKSEQERRORS 0xCC | 108 | #define IPG_FRAMECHECKSEQERRORS 0xCC |
109 | #define IPG_FRAMESLOSTRXERRORS 0xCE | 109 | #define IPG_FRAMESLOSTRXERRORS 0xCE |
110 | #define IPG_OCTETXMTOK 0xD0 | 110 | #define IPG_OCTETXMTOK 0xD0 |
111 | #define IPG_MCSTOCTETXMTOK 0xD4 | 111 | #define IPG_MCSTOCTETXMTOK 0xD4 |
112 | #define IPG_BCSTOCTETXMTOK 0xD8 | 112 | #define IPG_BCSTOCTETXMTOK 0xD8 |
113 | #define IPG_FRAMESXMTDOK 0xDC | 113 | #define IPG_FRAMESXMTDOK 0xDC |
114 | #define IPG_MCSTFRAMESXMTDOK 0xE0 | 114 | #define IPG_MCSTFRAMESXMTDOK 0xE0 |
115 | #define IPG_FRAMESWDEFERREDXMT 0xE4 | 115 | #define IPG_FRAMESWDEFERREDXMT 0xE4 |
116 | #define IPG_LATECOLLISIONS 0xE8 | 116 | #define IPG_LATECOLLISIONS 0xE8 |
117 | #define IPG_MULTICOLFRAMES 0xEC | 117 | #define IPG_MULTICOLFRAMES 0xEC |
118 | #define IPG_SINGLECOLFRAMES 0xF0 | 118 | #define IPG_SINGLECOLFRAMES 0xF0 |
119 | #define IPG_BCSTFRAMESXMTDOK 0xF6 | 119 | #define IPG_BCSTFRAMESXMTDOK 0xF6 |
120 | #define IPG_CARRIERSENSEERRORS 0xF8 | 120 | #define IPG_CARRIERSENSEERRORS 0xF8 |
121 | #define IPG_MACCONTROLFRAMESXMTDOK 0xFA | 121 | #define IPG_MACCONTROLFRAMESXMTDOK 0xFA |
122 | #define IPG_FRAMESABORTXSCOLLS 0xFC | 122 | #define IPG_FRAMESABORTXSCOLLS 0xFC |
123 | #define IPG_FRAMESWEXDEFERRAL 0xFE | 123 | #define IPG_FRAMESWEXDEFERRAL 0xFE |
124 | 124 | ||
125 | /* RMON statistic register offsets. */ | 125 | /* RMON statistic register offsets. */ |
126 | #define IPG_ETHERSTATSCOLLISIONS 0x100 | 126 | #define IPG_ETHERSTATSCOLLISIONS 0x100 |
@@ -134,8 +134,8 @@ enum ipg_regs { | |||
134 | #define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT 0x120 | 134 | #define IPG_ETHERSTATSPKTS1024TO1518OCTESTSTRANSMIT 0x120 |
135 | #define IPG_ETHERSTATSCRCALIGNERRORS 0x124 | 135 | #define IPG_ETHERSTATSCRCALIGNERRORS 0x124 |
136 | #define IPG_ETHERSTATSUNDERSIZEPKTS 0x128 | 136 | #define IPG_ETHERSTATSUNDERSIZEPKTS 0x128 |
137 | #define IPG_ETHERSTATSFRAGMENTS 0x12C | 137 | #define IPG_ETHERSTATSFRAGMENTS 0x12C |
138 | #define IPG_ETHERSTATSJABBERS 0x130 | 138 | #define IPG_ETHERSTATSJABBERS 0x130 |
139 | #define IPG_ETHERSTATSOCTETS 0x134 | 139 | #define IPG_ETHERSTATSOCTETS 0x134 |
140 | #define IPG_ETHERSTATSPKTS 0x138 | 140 | #define IPG_ETHERSTATSPKTS 0x138 |
141 | #define IPG_ETHERSTATSPKTS64OCTESTS 0x13C | 141 | #define IPG_ETHERSTATSPKTS64OCTESTS 0x13C |
@@ -154,10 +154,10 @@ enum ipg_regs { | |||
154 | #define IPG_ETHERSTATSDROPEVENTS 0xCE | 154 | #define IPG_ETHERSTATSDROPEVENTS 0xCE |
155 | 155 | ||
156 | /* Serial EEPROM offsets */ | 156 | /* Serial EEPROM offsets */ |
157 | #define IPG_EEPROM_CONFIGPARAM 0x00 | 157 | #define IPG_EEPROM_CONFIGPARAM 0x00 |
158 | #define IPG_EEPROM_ASICCTRL 0x01 | 158 | #define IPG_EEPROM_ASICCTRL 0x01 |
159 | #define IPG_EEPROM_SUBSYSTEMVENDORID 0x02 | 159 | #define IPG_EEPROM_SUBSYSTEMVENDORID 0x02 |
160 | #define IPG_EEPROM_SUBSYSTEMID 0x03 | 160 | #define IPG_EEPROM_SUBSYSTEMID 0x03 |
161 | #define IPG_EEPROM_STATIONADDRESS0 0x10 | 161 | #define IPG_EEPROM_STATIONADDRESS0 0x10 |
162 | #define IPG_EEPROM_STATIONADDRESS1 0x11 | 162 | #define IPG_EEPROM_STATIONADDRESS1 0x11 |
163 | #define IPG_EEPROM_STATIONADDRESS2 0x12 | 163 | #define IPG_EEPROM_STATIONADDRESS2 0x12 |
@@ -168,16 +168,16 @@ enum ipg_regs { | |||
168 | 168 | ||
169 | /* IOBaseAddress */ | 169 | /* IOBaseAddress */ |
170 | #define IPG_PIB_RSVD_MASK 0xFFFFFE01 | 170 | #define IPG_PIB_RSVD_MASK 0xFFFFFE01 |
171 | #define IPG_PIB_IOBASEADDRESS 0xFFFFFF00 | 171 | #define IPG_PIB_IOBASEADDRESS 0xFFFFFF00 |
172 | #define IPG_PIB_IOBASEADDRIND 0x00000001 | 172 | #define IPG_PIB_IOBASEADDRIND 0x00000001 |
173 | 173 | ||
174 | /* MemBaseAddress */ | 174 | /* MemBaseAddress */ |
175 | #define IPG_PMB_RSVD_MASK 0xFFFFFE07 | 175 | #define IPG_PMB_RSVD_MASK 0xFFFFFE07 |
176 | #define IPG_PMB_MEMBASEADDRIND 0x00000001 | 176 | #define IPG_PMB_MEMBASEADDRIND 0x00000001 |
177 | #define IPG_PMB_MEMMAPTYPE 0x00000006 | 177 | #define IPG_PMB_MEMMAPTYPE 0x00000006 |
178 | #define IPG_PMB_MEMMAPTYPE0 0x00000002 | 178 | #define IPG_PMB_MEMMAPTYPE0 0x00000002 |
179 | #define IPG_PMB_MEMMAPTYPE1 0x00000004 | 179 | #define IPG_PMB_MEMMAPTYPE1 0x00000004 |
180 | #define IPG_PMB_MEMBASEADDRESS 0xFFFFFE00 | 180 | #define IPG_PMB_MEMBASEADDRESS 0xFFFFFE00 |
181 | 181 | ||
182 | /* ConfigStatus */ | 182 | /* ConfigStatus */ |
183 | #define IPG_CS_RSVD_MASK 0xFFB0 | 183 | #define IPG_CS_RSVD_MASK 0xFFB0 |
@@ -196,20 +196,20 @@ enum ipg_regs { | |||
196 | 196 | ||
197 | /* TFDList, TFC */ | 197 | /* TFDList, TFC */ |
198 | #define IPG_TFC_RSVD_MASK 0x0000FFFF9FFFFFFF | 198 | #define IPG_TFC_RSVD_MASK 0x0000FFFF9FFFFFFF |
199 | #define IPG_TFC_FRAMEID 0x000000000000FFFF | 199 | #define IPG_TFC_FRAMEID 0x000000000000FFFF |
200 | #define IPG_TFC_WORDALIGN 0x0000000000030000 | 200 | #define IPG_TFC_WORDALIGN 0x0000000000030000 |
201 | #define IPG_TFC_WORDALIGNTODWORD 0x0000000000000000 | 201 | #define IPG_TFC_WORDALIGNTODWORD 0x0000000000000000 |
202 | #define IPG_TFC_WORDALIGNTOWORD 0x0000000000020000 | 202 | #define IPG_TFC_WORDALIGNTOWORD 0x0000000000020000 |
203 | #define IPG_TFC_WORDALIGNDISABLED 0x0000000000030000 | 203 | #define IPG_TFC_WORDALIGNDISABLED 0x0000000000030000 |
204 | #define IPG_TFC_TCPCHECKSUMENABLE 0x0000000000040000 | 204 | #define IPG_TFC_TCPCHECKSUMENABLE 0x0000000000040000 |
205 | #define IPG_TFC_UDPCHECKSUMENABLE 0x0000000000080000 | 205 | #define IPG_TFC_UDPCHECKSUMENABLE 0x0000000000080000 |
206 | #define IPG_TFC_IPCHECKSUMENABLE 0x0000000000100000 | 206 | #define IPG_TFC_IPCHECKSUMENABLE 0x0000000000100000 |
207 | #define IPG_TFC_FCSAPPENDDISABLE 0x0000000000200000 | 207 | #define IPG_TFC_FCSAPPENDDISABLE 0x0000000000200000 |
208 | #define IPG_TFC_TXINDICATE 0x0000000000400000 | 208 | #define IPG_TFC_TXINDICATE 0x0000000000400000 |
209 | #define IPG_TFC_TXDMAINDICATE 0x0000000000800000 | 209 | #define IPG_TFC_TXDMAINDICATE 0x0000000000800000 |
210 | #define IPG_TFC_FRAGCOUNT 0x000000000F000000 | 210 | #define IPG_TFC_FRAGCOUNT 0x000000000F000000 |
211 | #define IPG_TFC_VLANTAGINSERT 0x0000000010000000 | 211 | #define IPG_TFC_VLANTAGINSERT 0x0000000010000000 |
212 | #define IPG_TFC_TFDDONE 0x0000000080000000 | 212 | #define IPG_TFC_TFDDONE 0x0000000080000000 |
213 | #define IPG_TFC_VID 0x00000FFF00000000 | 213 | #define IPG_TFC_VID 0x00000FFF00000000 |
214 | #define IPG_TFC_CFI 0x0000100000000000 | 214 | #define IPG_TFC_CFI 0x0000100000000000 |
215 | #define IPG_TFC_USERPRIORITY 0x0000E00000000000 | 215 | #define IPG_TFC_USERPRIORITY 0x0000E00000000000 |
@@ -217,35 +217,35 @@ enum ipg_regs { | |||
217 | /* TFDList, FragInfo */ | 217 | /* TFDList, FragInfo */ |
218 | #define IPG_TFI_RSVD_MASK 0xFFFF00FFFFFFFFFF | 218 | #define IPG_TFI_RSVD_MASK 0xFFFF00FFFFFFFFFF |
219 | #define IPG_TFI_FRAGADDR 0x000000FFFFFFFFFF | 219 | #define IPG_TFI_FRAGADDR 0x000000FFFFFFFFFF |
220 | #define IPG_TFI_FRAGLEN 0xFFFF000000000000LL | 220 | #define IPG_TFI_FRAGLEN 0xFFFF000000000000LL |
221 | 221 | ||
222 | /* RFD data structure masks. */ | 222 | /* RFD data structure masks. */ |
223 | 223 | ||
224 | /* RFDList, RFS */ | 224 | /* RFDList, RFS */ |
225 | #define IPG_RFS_RSVD_MASK 0x0000FFFFFFFFFFFF | 225 | #define IPG_RFS_RSVD_MASK 0x0000FFFFFFFFFFFF |
226 | #define IPG_RFS_RXFRAMELEN 0x000000000000FFFF | 226 | #define IPG_RFS_RXFRAMELEN 0x000000000000FFFF |
227 | #define IPG_RFS_RXFIFOOVERRUN 0x0000000000010000 | 227 | #define IPG_RFS_RXFIFOOVERRUN 0x0000000000010000 |
228 | #define IPG_RFS_RXRUNTFRAME 0x0000000000020000 | 228 | #define IPG_RFS_RXRUNTFRAME 0x0000000000020000 |
229 | #define IPG_RFS_RXALIGNMENTERROR 0x0000000000040000 | 229 | #define IPG_RFS_RXALIGNMENTERROR 0x0000000000040000 |
230 | #define IPG_RFS_RXFCSERROR 0x0000000000080000 | 230 | #define IPG_RFS_RXFCSERROR 0x0000000000080000 |
231 | #define IPG_RFS_RXOVERSIZEDFRAME 0x0000000000100000 | 231 | #define IPG_RFS_RXOVERSIZEDFRAME 0x0000000000100000 |
232 | #define IPG_RFS_RXLENGTHERROR 0x0000000000200000 | 232 | #define IPG_RFS_RXLENGTHERROR 0x0000000000200000 |
233 | #define IPG_RFS_VLANDETECTED 0x0000000000400000 | 233 | #define IPG_RFS_VLANDETECTED 0x0000000000400000 |
234 | #define IPG_RFS_TCPDETECTED 0x0000000000800000 | 234 | #define IPG_RFS_TCPDETECTED 0x0000000000800000 |
235 | #define IPG_RFS_TCPERROR 0x0000000001000000 | 235 | #define IPG_RFS_TCPERROR 0x0000000001000000 |
236 | #define IPG_RFS_UDPDETECTED 0x0000000002000000 | 236 | #define IPG_RFS_UDPDETECTED 0x0000000002000000 |
237 | #define IPG_RFS_UDPERROR 0x0000000004000000 | 237 | #define IPG_RFS_UDPERROR 0x0000000004000000 |
238 | #define IPG_RFS_IPDETECTED 0x0000000008000000 | 238 | #define IPG_RFS_IPDETECTED 0x0000000008000000 |
239 | #define IPG_RFS_IPERROR 0x0000000010000000 | 239 | #define IPG_RFS_IPERROR 0x0000000010000000 |
240 | #define IPG_RFS_FRAMESTART 0x0000000020000000 | 240 | #define IPG_RFS_FRAMESTART 0x0000000020000000 |
241 | #define IPG_RFS_FRAMEEND 0x0000000040000000 | 241 | #define IPG_RFS_FRAMEEND 0x0000000040000000 |
242 | #define IPG_RFS_RFDDONE 0x0000000080000000 | 242 | #define IPG_RFS_RFDDONE 0x0000000080000000 |
243 | #define IPG_RFS_TCI 0x0000FFFF00000000 | 243 | #define IPG_RFS_TCI 0x0000FFFF00000000 |
244 | 244 | ||
245 | /* RFDList, FragInfo */ | 245 | /* RFDList, FragInfo */ |
246 | #define IPG_RFI_RSVD_MASK 0xFFFF00FFFFFFFFFF | 246 | #define IPG_RFI_RSVD_MASK 0xFFFF00FFFFFFFFFF |
247 | #define IPG_RFI_FRAGADDR 0x000000FFFFFFFFFF | 247 | #define IPG_RFI_FRAGADDR 0x000000FFFFFFFFFF |
248 | #define IPG_RFI_FRAGLEN 0xFFFF000000000000LL | 248 | #define IPG_RFI_FRAGLEN 0xFFFF000000000000LL |
249 | 249 | ||
250 | /* I/O Register masks. */ | 250 | /* I/O Register masks. */ |
251 | 251 | ||
@@ -254,37 +254,37 @@ enum ipg_regs { | |||
254 | 254 | ||
255 | /* Statistics Mask */ | 255 | /* Statistics Mask */ |
256 | #define IPG_SM_ALL 0x0FFFFFFF | 256 | #define IPG_SM_ALL 0x0FFFFFFF |
257 | #define IPG_SM_OCTETRCVOK_FRAMESRCVDOK 0x00000001 | 257 | #define IPG_SM_OCTETRCVOK_FRAMESRCVDOK 0x00000001 |
258 | #define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002 | 258 | #define IPG_SM_MCSTOCTETRCVDOK_MCSTFRAMESRCVDOK 0x00000002 |
259 | #define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004 | 259 | #define IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK 0x00000004 |
260 | #define IPG_SM_RXJUMBOFRAMES 0x00000008 | 260 | #define IPG_SM_RXJUMBOFRAMES 0x00000008 |
261 | #define IPG_SM_TCPCHECKSUMERRORS 0x00000010 | 261 | #define IPG_SM_TCPCHECKSUMERRORS 0x00000010 |
262 | #define IPG_SM_IPCHECKSUMERRORS 0x00000020 | 262 | #define IPG_SM_IPCHECKSUMERRORS 0x00000020 |
263 | #define IPG_SM_UDPCHECKSUMERRORS 0x00000040 | 263 | #define IPG_SM_UDPCHECKSUMERRORS 0x00000040 |
264 | #define IPG_SM_MACCONTROLFRAMESRCVD 0x00000080 | 264 | #define IPG_SM_MACCONTROLFRAMESRCVD 0x00000080 |
265 | #define IPG_SM_FRAMESTOOLONGERRORS 0x00000100 | 265 | #define IPG_SM_FRAMESTOOLONGERRORS 0x00000100 |
266 | #define IPG_SM_INRANGELENGTHERRORS 0x00000200 | 266 | #define IPG_SM_INRANGELENGTHERRORS 0x00000200 |
267 | #define IPG_SM_FRAMECHECKSEQERRORS 0x00000400 | 267 | #define IPG_SM_FRAMECHECKSEQERRORS 0x00000400 |
268 | #define IPG_SM_FRAMESLOSTRXERRORS 0x00000800 | 268 | #define IPG_SM_FRAMESLOSTRXERRORS 0x00000800 |
269 | #define IPG_SM_OCTETXMTOK_FRAMESXMTOK 0x00001000 | 269 | #define IPG_SM_OCTETXMTOK_FRAMESXMTOK 0x00001000 |
270 | #define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK 0x00002000 | 270 | #define IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK 0x00002000 |
271 | #define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK 0x00004000 | 271 | #define IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK 0x00004000 |
272 | #define IPG_SM_FRAMESWDEFERREDXMT 0x00008000 | 272 | #define IPG_SM_FRAMESWDEFERREDXMT 0x00008000 |
273 | #define IPG_SM_LATECOLLISIONS 0x00010000 | 273 | #define IPG_SM_LATECOLLISIONS 0x00010000 |
274 | #define IPG_SM_MULTICOLFRAMES 0x00020000 | 274 | #define IPG_SM_MULTICOLFRAMES 0x00020000 |
275 | #define IPG_SM_SINGLECOLFRAMES 0x00040000 | 275 | #define IPG_SM_SINGLECOLFRAMES 0x00040000 |
276 | #define IPG_SM_TXJUMBOFRAMES 0x00080000 | 276 | #define IPG_SM_TXJUMBOFRAMES 0x00080000 |
277 | #define IPG_SM_CARRIERSENSEERRORS 0x00100000 | 277 | #define IPG_SM_CARRIERSENSEERRORS 0x00100000 |
278 | #define IPG_SM_MACCONTROLFRAMESXMTD 0x00200000 | 278 | #define IPG_SM_MACCONTROLFRAMESXMTD 0x00200000 |
279 | #define IPG_SM_FRAMESABORTXSCOLLS 0x00400000 | 279 | #define IPG_SM_FRAMESABORTXSCOLLS 0x00400000 |
280 | #define IPG_SM_FRAMESWEXDEFERAL 0x00800000 | 280 | #define IPG_SM_FRAMESWEXDEFERAL 0x00800000 |
281 | 281 | ||
282 | /* Countdown */ | 282 | /* Countdown */ |
283 | #define IPG_CD_RSVD_MASK 0x0700FFFF | 283 | #define IPG_CD_RSVD_MASK 0x0700FFFF |
284 | #define IPG_CD_COUNT 0x0000FFFF | 284 | #define IPG_CD_COUNT 0x0000FFFF |
285 | #define IPG_CD_COUNTDOWNSPEED 0x01000000 | 285 | #define IPG_CD_COUNTDOWNSPEED 0x01000000 |
286 | #define IPG_CD_COUNTDOWNMODE 0x02000000 | 286 | #define IPG_CD_COUNTDOWNMODE 0x02000000 |
287 | #define IPG_CD_COUNTINTENABLED 0x04000000 | 287 | #define IPG_CD_COUNTINTENABLED 0x04000000 |
288 | 288 | ||
289 | /* TxDMABurstThresh */ | 289 | /* TxDMABurstThresh */ |
290 | #define IPG_TB_RSVD_MASK 0xFF | 290 | #define IPG_TB_RSVD_MASK 0xFF |
@@ -653,15 +653,28 @@ enum ipg_regs { | |||
653 | * Miscellaneous macros. | 653 | * Miscellaneous macros. |
654 | */ | 654 | */ |
655 | 655 | ||
656 | /* Marco for printing debug statements. */ | 656 | /* Macros for printing debug statements. */ |
657 | #ifdef IPG_DEBUG | 657 | #ifdef IPG_DEBUG |
658 | # define IPG_DEBUG_MSG(args...) | 658 | # define IPG_DEBUG_MSG(fmt, args...) \ |
659 | # define IPG_DDEBUG_MSG(args...) printk(KERN_DEBUG "IPG: " args) | 659 | do { \ |
660 | if (0) \ | ||
661 | printk(KERN_DEBUG "IPG: " fmt, ##args); \ | ||
662 | } while (0) | ||
663 | # define IPG_DDEBUG_MSG(fmt, args...) \ | ||
664 | printk(KERN_DEBUG "IPG: " fmt, ##args) | ||
660 | # define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args) | 665 | # define IPG_DUMPRFDLIST(args) ipg_dump_rfdlist(args) |
661 | # define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args) | 666 | # define IPG_DUMPTFDLIST(args) ipg_dump_tfdlist(args) |
662 | #else | 667 | #else |
663 | # define IPG_DEBUG_MSG(args...) | 668 | # define IPG_DEBUG_MSG(fmt, args...) \ |
664 | # define IPG_DDEBUG_MSG(args...) | 669 | do { \ |
670 | if (0) \ | ||
671 | printk(KERN_DEBUG "IPG: " fmt, ##args); \ | ||
672 | } while (0) | ||
673 | # define IPG_DDEBUG_MSG(fmt, args...) \ | ||
674 | do { \ | ||
675 | if (0) \ | ||
676 | printk(KERN_DEBUG "IPG: " fmt, ##args); \ | ||
677 | } while (0) | ||
665 | # define IPG_DUMPRFDLIST(args) | 678 | # define IPG_DUMPRFDLIST(args) |
666 | # define IPG_DUMPTFDLIST(args) | 679 | # define IPG_DUMPTFDLIST(args) |
667 | #endif | 680 | #endif |