aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2012-06-25 06:43:19 -0400
committerRafael J. Wysocki <rjw@sisk.pl>2012-06-30 09:16:46 -0400
commitc317fc594064b3e6a53502a985b44416a5ef1e91 (patch)
tree3571ef85cf0eab861e6e50bf2332c012a69f6566
parent13bb340d636285014ff2f6ce68965889eb24bf30 (diff)
ARM: shmobile: use common DMAEngine definitions on sh7372
This patch switch over to use common DMAEngine definitions, and reduced a waste of code. It is easy to understand if sh_dmae_pdata / sh_dmae_slave_config settings are used defined value instead of direct value. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Diffstat
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c131
1 files changed, 47 insertions, 84 deletions
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 6a4bd582c028..4f473320f921 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -33,6 +33,7 @@
33#include <linux/sh_timer.h> 33#include <linux/sh_timer.h>
34#include <linux/pm_domain.h> 34#include <linux/pm_domain.h>
35#include <linux/dma-mapping.h> 35#include <linux/dma-mapping.h>
36#include <mach/dma-register.h>
36#include <mach/hardware.h> 37#include <mach/hardware.h>
37#include <mach/irqs.h> 38#include <mach/irqs.h>
38#include <mach/sh7372.h> 39#include <mach/sh7372.h>
@@ -335,151 +336,126 @@ static struct platform_device iic1_device = {
335}; 336};
336 337
337/* DMA */ 338/* DMA */
338/* Transmit sizes and respective CHCR register values */
339enum {
340 XMIT_SZ_8BIT = 0,
341 XMIT_SZ_16BIT = 1,
342 XMIT_SZ_32BIT = 2,
343 XMIT_SZ_64BIT = 7,
344 XMIT_SZ_128BIT = 3,
345 XMIT_SZ_256BIT = 4,
346 XMIT_SZ_512BIT = 5,
347};
348
349/* log2(size / 8) - used to calculate number of transfers */
350#define TS_SHIFT { \
351 [XMIT_SZ_8BIT] = 0, \
352 [XMIT_SZ_16BIT] = 1, \
353 [XMIT_SZ_32BIT] = 2, \
354 [XMIT_SZ_64BIT] = 3, \
355 [XMIT_SZ_128BIT] = 4, \
356 [XMIT_SZ_256BIT] = 5, \
357 [XMIT_SZ_512BIT] = 6, \
358}
359
360#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
361 (((i) & 0xc) << (20 - 2)))
362
363static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = { 339static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
364 { 340 {
365 .slave_id = SHDMA_SLAVE_SCIF0_TX, 341 .slave_id = SHDMA_SLAVE_SCIF0_TX,
366 .addr = 0xe6c40020, 342 .addr = 0xe6c40020,
367 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 343 .chcr = CHCR_TX(XMIT_SZ_8BIT),
368 .mid_rid = 0x21, 344 .mid_rid = 0x21,
369 }, { 345 }, {
370 .slave_id = SHDMA_SLAVE_SCIF0_RX, 346 .slave_id = SHDMA_SLAVE_SCIF0_RX,
371 .addr = 0xe6c40024, 347 .addr = 0xe6c40024,
372 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 348 .chcr = CHCR_RX(XMIT_SZ_8BIT),
373 .mid_rid = 0x22, 349 .mid_rid = 0x22,
374 }, { 350 }, {
375 .slave_id = SHDMA_SLAVE_SCIF1_TX, 351 .slave_id = SHDMA_SLAVE_SCIF1_TX,
376 .addr = 0xe6c50020, 352 .addr = 0xe6c50020,
377 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 353 .chcr = CHCR_TX(XMIT_SZ_8BIT),
378 .mid_rid = 0x25, 354 .mid_rid = 0x25,
379 }, { 355 }, {
380 .slave_id = SHDMA_SLAVE_SCIF1_RX, 356 .slave_id = SHDMA_SLAVE_SCIF1_RX,
381 .addr = 0xe6c50024, 357 .addr = 0xe6c50024,
382 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 358 .chcr = CHCR_RX(XMIT_SZ_8BIT),
383 .mid_rid = 0x26, 359 .mid_rid = 0x26,
384 }, { 360 }, {
385 .slave_id = SHDMA_SLAVE_SCIF2_TX, 361 .slave_id = SHDMA_SLAVE_SCIF2_TX,
386 .addr = 0xe6c60020, 362 .addr = 0xe6c60020,
387 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 363 .chcr = CHCR_TX(XMIT_SZ_8BIT),
388 .mid_rid = 0x29, 364 .mid_rid = 0x29,
389 }, { 365 }, {
390 .slave_id = SHDMA_SLAVE_SCIF2_RX, 366 .slave_id = SHDMA_SLAVE_SCIF2_RX,
391 .addr = 0xe6c60024, 367 .addr = 0xe6c60024,
392 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 368 .chcr = CHCR_RX(XMIT_SZ_8BIT),
393 .mid_rid = 0x2a, 369 .mid_rid = 0x2a,
394 }, { 370 }, {
395 .slave_id = SHDMA_SLAVE_SCIF3_TX, 371 .slave_id = SHDMA_SLAVE_SCIF3_TX,
396 .addr = 0xe6c70020, 372 .addr = 0xe6c70020,
397 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 373 .chcr = CHCR_TX(XMIT_SZ_8BIT),
398 .mid_rid = 0x2d, 374 .mid_rid = 0x2d,
399 }, { 375 }, {
400 .slave_id = SHDMA_SLAVE_SCIF3_RX, 376 .slave_id = SHDMA_SLAVE_SCIF3_RX,
401 .addr = 0xe6c70024, 377 .addr = 0xe6c70024,
402 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 378 .chcr = CHCR_RX(XMIT_SZ_8BIT),
403 .mid_rid = 0x2e, 379 .mid_rid = 0x2e,
404 }, { 380 }, {
405 .slave_id = SHDMA_SLAVE_SCIF4_TX, 381 .slave_id = SHDMA_SLAVE_SCIF4_TX,
406 .addr = 0xe6c80020, 382 .addr = 0xe6c80020,
407 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 383 .chcr = CHCR_TX(XMIT_SZ_8BIT),
408 .mid_rid = 0x39, 384 .mid_rid = 0x39,
409 }, { 385 }, {
410 .slave_id = SHDMA_SLAVE_SCIF4_RX, 386 .slave_id = SHDMA_SLAVE_SCIF4_RX,
411 .addr = 0xe6c80024, 387 .addr = 0xe6c80024,
412 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 388 .chcr = CHCR_RX(XMIT_SZ_8BIT),
413 .mid_rid = 0x3a, 389 .mid_rid = 0x3a,
414 }, { 390 }, {
415 .slave_id = SHDMA_SLAVE_SCIF5_TX, 391 .slave_id = SHDMA_SLAVE_SCIF5_TX,
416 .addr = 0xe6cb0020, 392 .addr = 0xe6cb0020,
417 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 393 .chcr = CHCR_TX(XMIT_SZ_8BIT),
418 .mid_rid = 0x35, 394 .mid_rid = 0x35,
419 }, { 395 }, {
420 .slave_id = SHDMA_SLAVE_SCIF5_RX, 396 .slave_id = SHDMA_SLAVE_SCIF5_RX,
421 .addr = 0xe6cb0024, 397 .addr = 0xe6cb0024,
422 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 398 .chcr = CHCR_RX(XMIT_SZ_8BIT),
423 .mid_rid = 0x36, 399 .mid_rid = 0x36,
424 }, { 400 }, {
425 .slave_id = SHDMA_SLAVE_SCIF6_TX, 401 .slave_id = SHDMA_SLAVE_SCIF6_TX,
426 .addr = 0xe6c30040, 402 .addr = 0xe6c30040,
427 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 403 .chcr = CHCR_TX(XMIT_SZ_8BIT),
428 .mid_rid = 0x3d, 404 .mid_rid = 0x3d,
429 }, { 405 }, {
430 .slave_id = SHDMA_SLAVE_SCIF6_RX, 406 .slave_id = SHDMA_SLAVE_SCIF6_RX,
431 .addr = 0xe6c30060, 407 .addr = 0xe6c30060,
432 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT), 408 .chcr = CHCR_RX(XMIT_SZ_8BIT),
433 .mid_rid = 0x3e, 409 .mid_rid = 0x3e,
434 }, { 410 }, {
435 .slave_id = SHDMA_SLAVE_SDHI0_TX, 411 .slave_id = SHDMA_SLAVE_SDHI0_TX,
436 .addr = 0xe6850030, 412 .addr = 0xe6850030,
437 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 413 .chcr = CHCR_TX(XMIT_SZ_16BIT),
438 .mid_rid = 0xc1, 414 .mid_rid = 0xc1,
439 }, { 415 }, {
440 .slave_id = SHDMA_SLAVE_SDHI0_RX, 416 .slave_id = SHDMA_SLAVE_SDHI0_RX,
441 .addr = 0xe6850030, 417 .addr = 0xe6850030,
442 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 418 .chcr = CHCR_RX(XMIT_SZ_16BIT),
443 .mid_rid = 0xc2, 419 .mid_rid = 0xc2,
444 }, { 420 }, {
445 .slave_id = SHDMA_SLAVE_SDHI1_TX, 421 .slave_id = SHDMA_SLAVE_SDHI1_TX,
446 .addr = 0xe6860030, 422 .addr = 0xe6860030,
447 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 423 .chcr = CHCR_TX(XMIT_SZ_16BIT),
448 .mid_rid = 0xc9, 424 .mid_rid = 0xc9,
449 }, { 425 }, {
450 .slave_id = SHDMA_SLAVE_SDHI1_RX, 426 .slave_id = SHDMA_SLAVE_SDHI1_RX,
451 .addr = 0xe6860030, 427 .addr = 0xe6860030,
452 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 428 .chcr = CHCR_RX(XMIT_SZ_16BIT),
453 .mid_rid = 0xca, 429 .mid_rid = 0xca,
454 }, { 430 }, {
455 .slave_id = SHDMA_SLAVE_SDHI2_TX, 431 .slave_id = SHDMA_SLAVE_SDHI2_TX,
456 .addr = 0xe6870030, 432 .addr = 0xe6870030,
457 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 433 .chcr = CHCR_TX(XMIT_SZ_16BIT),
458 .mid_rid = 0xcd, 434 .mid_rid = 0xcd,
459 }, { 435 }, {
460 .slave_id = SHDMA_SLAVE_SDHI2_RX, 436 .slave_id = SHDMA_SLAVE_SDHI2_RX,
461 .addr = 0xe6870030, 437 .addr = 0xe6870030,
462 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT), 438 .chcr = CHCR_RX(XMIT_SZ_16BIT),
463 .mid_rid = 0xce, 439 .mid_rid = 0xce,
464 }, { 440 }, {
465 .slave_id = SHDMA_SLAVE_FSIA_TX, 441 .slave_id = SHDMA_SLAVE_FSIA_TX,
466 .addr = 0xfe1f0024, 442 .addr = 0xfe1f0024,
467 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 443 .chcr = CHCR_TX(XMIT_SZ_32BIT),
468 .mid_rid = 0xb1, 444 .mid_rid = 0xb1,
469 }, { 445 }, {
470 .slave_id = SHDMA_SLAVE_FSIA_RX, 446 .slave_id = SHDMA_SLAVE_FSIA_RX,
471 .addr = 0xfe1f0020, 447 .addr = 0xfe1f0020,
472 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 448 .chcr = CHCR_RX(XMIT_SZ_32BIT),
473 .mid_rid = 0xb2, 449 .mid_rid = 0xb2,
474 }, { 450 }, {
475 .slave_id = SHDMA_SLAVE_MMCIF_TX, 451 .slave_id = SHDMA_SLAVE_MMCIF_TX,
476 .addr = 0xe6bd0034, 452 .addr = 0xe6bd0034,
477 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 453 .chcr = CHCR_TX(XMIT_SZ_32BIT),
478 .mid_rid = 0xd1, 454 .mid_rid = 0xd1,
479 }, { 455 }, {
480 .slave_id = SHDMA_SLAVE_MMCIF_RX, 456 .slave_id = SHDMA_SLAVE_MMCIF_RX,
481 .addr = 0xe6bd0034, 457 .addr = 0xe6bd0034,
482 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT), 458 .chcr = CHCR_RX(XMIT_SZ_32BIT),
483 .mid_rid = 0xd2, 459 .mid_rid = 0xd2,
484 }, 460 },
485}; 461};
@@ -520,19 +496,17 @@ static const struct sh_dmae_channel sh7372_dmae_channels[] = {
520 } 496 }
521}; 497};
522 498
523static const unsigned int ts_shift[] = TS_SHIFT;
524
525static struct sh_dmae_pdata dma_platform_data = { 499static struct sh_dmae_pdata dma_platform_data = {
526 .slave = sh7372_dmae_slaves, 500 .slave = sh7372_dmae_slaves,
527 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves), 501 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
528 .channel = sh7372_dmae_channels, 502 .channel = sh7372_dmae_channels,
529 .channel_num = ARRAY_SIZE(sh7372_dmae_channels), 503 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
530 .ts_low_shift = 3, 504 .ts_low_shift = TS_LOW_SHIFT,
531 .ts_low_mask = 0x18, 505 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
532 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */ 506 .ts_high_shift = TS_HI_SHIFT,
533 .ts_high_mask = 0x00300000, 507 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
534 .ts_shift = ts_shift, 508 .ts_shift = dma_ts_shift,
535 .ts_shift_num = ARRAY_SIZE(ts_shift), 509 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
536 .dmaor_init = DMAOR_DME, 510 .dmaor_init = DMAOR_DME,
537 .chclr_present = 1, 511 .chclr_present = 1,
538}; 512};
@@ -654,17 +628,6 @@ static struct platform_device dma2_device = {
654/* 628/*
655 * USB-DMAC 629 * USB-DMAC
656 */ 630 */
657
658unsigned int usbts_shift[] = {3, 4, 5};
659
660enum {
661 XMIT_SZ_8BYTE = 0,
662 XMIT_SZ_16BYTE = 1,
663 XMIT_SZ_32BYTE = 2,
664};
665
666#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
667
668static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = { 631static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
669 { 632 {
670 .offset = 0, 633 .offset = 0,
@@ -677,10 +640,10 @@ static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
677static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = { 640static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
678 { 641 {
679 .slave_id = SHDMA_SLAVE_USB0_TX, 642 .slave_id = SHDMA_SLAVE_USB0_TX,
680 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), 643 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
681 }, { 644 }, {
682 .slave_id = SHDMA_SLAVE_USB0_RX, 645 .slave_id = SHDMA_SLAVE_USB0_RX,
683 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), 646 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
684 }, 647 },
685}; 648};
686 649
@@ -689,12 +652,12 @@ static struct sh_dmae_pdata usb_dma0_platform_data = {
689 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves), 652 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
690 .channel = sh7372_usb_dmae_channels, 653 .channel = sh7372_usb_dmae_channels,
691 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), 654 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
692 .ts_low_shift = 6, 655 .ts_low_shift = USBTS_LOW_SHIFT,
693 .ts_low_mask = 0xc0, 656 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
694 .ts_high_shift = 0, 657 .ts_high_shift = USBTS_HI_SHIFT,
695 .ts_high_mask = 0, 658 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
696 .ts_shift = usbts_shift, 659 .ts_shift = dma_usbts_shift,
697 .ts_shift_num = ARRAY_SIZE(usbts_shift), 660 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
698 .dmaor_init = DMAOR_DME, 661 .dmaor_init = DMAOR_DME,
699 .chcr_offset = 0x14, 662 .chcr_offset = 0x14,
700 .chcr_ie_bit = 1 << 5, 663 .chcr_ie_bit = 1 << 5,
@@ -739,10 +702,10 @@ static struct platform_device usb_dma0_device = {
739static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = { 702static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
740 { 703 {
741 .slave_id = SHDMA_SLAVE_USB1_TX, 704 .slave_id = SHDMA_SLAVE_USB1_TX,
742 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), 705 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
743 }, { 706 }, {
744 .slave_id = SHDMA_SLAVE_USB1_RX, 707 .slave_id = SHDMA_SLAVE_USB1_RX,
745 .chcr = USBTS_INDEX2VAL(XMIT_SZ_8BYTE), 708 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
746 }, 709 },
747}; 710};
748 711
@@ -751,12 +714,12 @@ static struct sh_dmae_pdata usb_dma1_platform_data = {
751 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves), 714 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
752 .channel = sh7372_usb_dmae_channels, 715 .channel = sh7372_usb_dmae_channels,
753 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels), 716 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
754 .ts_low_shift = 6, 717 .ts_low_shift = USBTS_LOW_SHIFT,
755 .ts_low_mask = 0xc0, 718 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
756 .ts_high_shift = 0, 719 .ts_high_shift = USBTS_HI_SHIFT,
757 .ts_high_mask = 0, 720 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
758 .ts_shift = usbts_shift, 721 .ts_shift = dma_usbts_shift,
759 .ts_shift_num = ARRAY_SIZE(usbts_shift), 722 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
760 .dmaor_init = DMAOR_DME, 723 .dmaor_init = DMAOR_DME,
761 .chcr_offset = 0x14, 724 .chcr_offset = 0x14,
762 .chcr_ie_bit = 1 << 5, 725 .chcr_ie_bit = 1 << 5,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 23:59:01 -0500