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authorKim Phillips <kim.phillips@freescale.com>2011-03-23 09:23:36 -0400
committerHerbert Xu <herbert@gondor.apana.org.au>2011-03-26 22:45:18 -0400
commit7dfc2179ec7339a180e822a5af7eb1294da245cf (patch)
treec78bb9f778f17b8c95822705578118fec035e68b
parent6d00376ad15a931d4b148e52d80abc54173e9bf5 (diff)
crypto: caam - de-CHIP-ify device tree compatibles
- all the integration parameters have been captured by the binding. - the block name really uniquely identifies this hardware. Some advocate putting SoC names everywhere in case software needs to work around some chip-specific bug, but more precise SoC information already exists in SVR, and board information already exists in the top-level device tree node. Note that sometimes the SoC name is a worse identifier than the block version, as the block version can change between revisions of the same SoC. As a matter of historical reference, neither SEC versions 2.x nor 3.x (driven by talitos) ever needed CHIP references. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Cc: Kumar Gala <kumar.gala@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Acked-off-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/crypto/fsl-sec4.txt64
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts32
2 files changed, 37 insertions, 59 deletions
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
index 568aa3cb5276..bf57ecd5d73a 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
@@ -38,7 +38,7 @@ in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
38up to 4 JRs can be configured; and all 4 JRs process requests in parallel. 38up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
39 39
40===================================================================== 40=====================================================================
41P4080 SEC 4 Node 41SEC 4 Node
42 42
43Description 43Description
44 44
@@ -53,7 +53,7 @@ PROPERTIES
53 - compatible 53 - compatible
54 Usage: required 54 Usage: required
55 Value type: <string> 55 Value type: <string>
56 Definition: Must include "fsl,p4080-sec-v4.0","fsl,sec-v4.0" 56 Definition: Must include "fsl,sec-v4.0"
57 57
58 - #address-cells 58 - #address-cells
59 Usage: required 59 Usage: required
@@ -105,7 +105,7 @@ PROPERTIES
105 105
106EXAMPLE 106EXAMPLE
107 crypto@300000 { 107 crypto@300000 {
108 compatible = "fsl,p4080-sec-v4.0", "fsl,sec-v4.0"; 108 compatible = "fsl,sec-v4.0";
109 #address-cells = <1>; 109 #address-cells = <1>;
110 #size-cells = <1>; 110 #size-cells = <1>;
111 reg = <0x300000 0x10000>; 111 reg = <0x300000 0x10000>;
@@ -115,7 +115,7 @@ EXAMPLE
115 }; 115 };
116 116
117===================================================================== 117=====================================================================
118P4080 Job Ring (JR) Node 118Job Ring (JR) Node
119 119
120 Child of the crypto node defines data processing interface to SEC 4 120 Child of the crypto node defines data processing interface to SEC 4
121 across the peripheral bus for purposes of processing 121 across the peripheral bus for purposes of processing
@@ -127,7 +127,7 @@ P4080 Job Ring (JR) Node
127 - compatible 127 - compatible
128 Usage: required 128 Usage: required
129 Value type: <string> 129 Value type: <string>
130 Definition: Must include "fsl,p4080-sec-v4.0-job-ring","fsl,sec-v4.0-job-ring" 130 Definition: Must include "fsl,sec-v4.0-job-ring"
131 131
132 - reg 132 - reg
133 Usage: required 133 Usage: required
@@ -163,8 +163,7 @@ P4080 Job Ring (JR) Node
163 163
164EXAMPLE 164EXAMPLE
165 jr@1000 { 165 jr@1000 {
166 compatible = "fsl,p4080-sec-v4.0-job-ring", 166 compatible = "fsl,sec-v4.0-job-ring";
167 "fsl,sec-v4.0-job-ring";
168 reg = <0x1000 0x1000>; 167 reg = <0x1000 0x1000>;
169 fsl,liodn = <0x081>; 168 fsl,liodn = <0x081>;
170 interrupt-parent = <&mpic>; 169 interrupt-parent = <&mpic>;
@@ -173,7 +172,7 @@ EXAMPLE
173 172
174 173
175===================================================================== 174=====================================================================
176P4080 Run Time Integrity Check (RTIC) Node 175Run Time Integrity Check (RTIC) Node
177 176
178 Child node of the crypto node. Defines a register space that 177 Child node of the crypto node. Defines a register space that
179 contains up to 5 sets of addresses and their lengths (sizes) that 178 contains up to 5 sets of addresses and their lengths (sizes) that
@@ -186,7 +185,7 @@ P4080 Run Time Integrity Check (RTIC) Node
186 - compatible 185 - compatible
187 Usage: required 186 Usage: required
188 Value type: <string> 187 Value type: <string>
189 Definition: Must include "fsl,p4080-sec-v4.0-rtic","fsl,sec-v4.0-rtic". 188 Definition: Must include "fsl,sec-v4.0-rtic".
190 189
191 - #address-cells 190 - #address-cells
192 Usage: required 191 Usage: required
@@ -219,8 +218,7 @@ P4080 Run Time Integrity Check (RTIC) Node
219 218
220EXAMPLE 219EXAMPLE
221 rtic@6000 { 220 rtic@6000 {
222 compatible = "fsl,p4080-sec-v4.0-rtic", 221 compatible = "fsl,sec-v4.0-rtic";
223 "fsl,sec-v4.0-rtic";
224 #address-cells = <1>; 222 #address-cells = <1>;
225 #size-cells = <1>; 223 #size-cells = <1>;
226 reg = <0x6000 0x100>; 224 reg = <0x6000 0x100>;
@@ -228,7 +226,7 @@ EXAMPLE
228 }; 226 };
229 227
230===================================================================== 228=====================================================================
231P4080 Run Time Integrity Check (RTIC) Memory Node 229Run Time Integrity Check (RTIC) Memory Node
232 A child node that defines individual RTIC memory regions that are used to 230 A child node that defines individual RTIC memory regions that are used to
233 perform run-time integrity check of memory areas that should not modified. 231 perform run-time integrity check of memory areas that should not modified.
234 The node defines a register that contains the memory address & 232 The node defines a register that contains the memory address &
@@ -238,7 +236,7 @@ P4080 Run Time Integrity Check (RTIC) Memory Node
238 - compatible 236 - compatible
239 Usage: required 237 Usage: required
240 Value type: <string> 238 Value type: <string>
241 Definition: Must include "fsl,p4080-sec-v4.0-rtic-memory","fsl,sec-v4.0-rtic-memory". 239 Definition: Must include "fsl,sec-v4.0-rtic-memory".
242 240
243 - reg 241 - reg
244 Usage: required 242 Usage: required
@@ -270,15 +268,14 @@ P4080 Run Time Integrity Check (RTIC) Memory Node
270 268
271EXAMPLE 269EXAMPLE
272 rtic-a@0 { 270 rtic-a@0 {
273 compatible = "fsl,p4080-sec-v4.0-rtic-memory", 271 compatible = "fsl,sec-v4.0-rtic-memory";
274 "fsl,sec-v4.0-rtic-memory";
275 reg = <0x00 0x20 0x100 0x80>; 272 reg = <0x00 0x20 0x100 0x80>;
276 fsl,liodn = <0x03c>; 273 fsl,liodn = <0x03c>;
277 fsl,rtic-region = <0x12345678 0x12345678 0x12345678>; 274 fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
278 }; 275 };
279 276
280===================================================================== 277=====================================================================
281P4080 Secure Non-Volatile Storage (SNVS) Node 278Secure Non-Volatile Storage (SNVS) Node
282 279
283 Node defines address range and the associated 280 Node defines address range and the associated
284 interrupt for the SNVS function. This function 281 interrupt for the SNVS function. This function
@@ -288,7 +285,7 @@ P4080 Secure Non-Volatile Storage (SNVS) Node
288 - compatible 285 - compatible
289 Usage: required 286 Usage: required
290 Value type: <string> 287 Value type: <string>
291 Definition: Must include "fsl,p4080-sec-v4.0-mon", "fsl,sec-v4.0-mon". 288 Definition: Must include "fsl,sec-v4.0-mon".
292 289
293 - reg 290 - reg
294 Usage: required 291 Usage: required
@@ -315,7 +312,7 @@ P4080 Secure Non-Volatile Storage (SNVS) Node
315 312
316EXAMPLE 313EXAMPLE
317 sec_mon@314000 { 314 sec_mon@314000 {
318 compatible = "fsl,p4080-sec-v4.0-mon", "fsl,sec-v4.0-mon"; 315 compatible = "fsl,sec-v4.0-mon";
319 reg = <0x314000 0x1000>; 316 reg = <0x314000 0x1000>;
320 interrupt-parent = <&mpic>; 317 interrupt-parent = <&mpic>;
321 interrupts = <93 2>; 318 interrupts = <93 2>;
@@ -325,7 +322,7 @@ EXAMPLE
325FULL EXAMPLE 322FULL EXAMPLE
326 323
327 crypto: crypto@300000 { 324 crypto: crypto@300000 {
328 compatible = "fsl,p4080-sec-v4.0", "fsl,sec-v4.0"; 325 compatible = "fsl,sec-v4.0";
329 #address-cells = <1>; 326 #address-cells = <1>;
330 #size-cells = <1>; 327 #size-cells = <1>;
331 reg = <0x300000 0x10000>; 328 reg = <0x300000 0x10000>;
@@ -334,73 +331,64 @@ FULL EXAMPLE
334 interrupts = <92 2>; 331 interrupts = <92 2>;
335 332
336 sec_jr0: jr@1000 { 333 sec_jr0: jr@1000 {
337 compatible = "fsl,p4080-sec-v4.0-job-ring", 334 compatible = "fsl,sec-v4.0-job-ring";
338 "fsl,sec-v4.0-job-ring";
339 reg = <0x1000 0x1000>; 335 reg = <0x1000 0x1000>;
340 interrupt-parent = <&mpic>; 336 interrupt-parent = <&mpic>;
341 interrupts = <88 2>; 337 interrupts = <88 2>;
342 }; 338 };
343 339
344 sec_jr1: jr@2000 { 340 sec_jr1: jr@2000 {
345 compatible = "fsl,p4080-sec-v4.0-job-ring", 341 compatible = "fsl,sec-v4.0-job-ring";
346 "fsl,sec-v4.0-job-ring";
347 reg = <0x2000 0x1000>; 342 reg = <0x2000 0x1000>;
348 interrupt-parent = <&mpic>; 343 interrupt-parent = <&mpic>;
349 interrupts = <89 2>; 344 interrupts = <89 2>;
350 }; 345 };
351 346
352 sec_jr2: jr@3000 { 347 sec_jr2: jr@3000 {
353 compatible = "fsl,p4080-sec-v4.0-job-ring", 348 compatible = "fsl,sec-v4.0-job-ring";
354 "fsl,sec-v4.0-job-ring";
355 reg = <0x3000 0x1000>; 349 reg = <0x3000 0x1000>;
356 interrupt-parent = <&mpic>; 350 interrupt-parent = <&mpic>;
357 interrupts = <90 2>; 351 interrupts = <90 2>;
358 }; 352 };
359 353
360 sec_jr3: jr@4000 { 354 sec_jr3: jr@4000 {
361 compatible = "fsl,p4080-sec-v4.0-job-ring", 355 compatible = "fsl,sec-v4.0-job-ring";
362 "fsl,sec-v4.0-job-ring";
363 reg = <0x4000 0x1000>; 356 reg = <0x4000 0x1000>;
364 interrupt-parent = <&mpic>; 357 interrupt-parent = <&mpic>;
365 interrupts = <91 2>; 358 interrupts = <91 2>;
366 }; 359 };
367 360
368 rtic@6000 { 361 rtic@6000 {
369 compatible = "fsl,p4080-sec-v4.0-rtic", 362 compatible = "fsl,sec-v4.0-rtic";
370 "fsl,sec-v4.0-rtic";
371 #address-cells = <1>; 363 #address-cells = <1>;
372 #size-cells = <1>; 364 #size-cells = <1>;
373 reg = <0x6000 0x100>; 365 reg = <0x6000 0x100>;
374 ranges = <0x0 0x6100 0xe00>; 366 ranges = <0x0 0x6100 0xe00>;
375 367
376 rtic_a: rtic-a@0 { 368 rtic_a: rtic-a@0 {
377 compatible = "fsl,p4080-sec-v4.0-rtic-memory", 369 compatible = "fsl,sec-v4.0-rtic-memory";
378 "fsl,sec-v4.0-rtic-memory";
379 reg = <0x00 0x20 0x100 0x80>; 370 reg = <0x00 0x20 0x100 0x80>;
380 }; 371 };
381 372
382 rtic_b: rtic-b@20 { 373 rtic_b: rtic-b@20 {
383 compatible = "fsl,p4080-sec-v4.0-rtic-memory", 374 compatible = "fsl,sec-v4.0-rtic-memory";
384 "fsl,sec-v4.0-rtic-memory";
385 reg = <0x20 0x20 0x200 0x80>; 375 reg = <0x20 0x20 0x200 0x80>;
386 }; 376 };
387 377
388 rtic_c: rtic-c@40 { 378 rtic_c: rtic-c@40 {
389 compatible = "fsl,p4080-sec-v4.0-rtic-memory", 379 compatible = "fsl,sec-v4.0-rtic-memory";
390 "fsl,sec-v4.0-rtic-memory";
391 reg = <0x40 0x20 0x300 0x80>; 380 reg = <0x40 0x20 0x300 0x80>;
392 }; 381 };
393 382
394 rtic_d: rtic-d@60 { 383 rtic_d: rtic-d@60 {
395 compatible = "fsl,p4080-sec-v4.0-rtic-memory", 384 compatible = "fsl,sec-v4.0-rtic-memory";
396 "fsl,sec-v4.0-rtic-memory";
397 reg = <0x60 0x20 0x500 0x80>; 385 reg = <0x60 0x20 0x500 0x80>;
398 }; 386 };
399 }; 387 };
400 }; 388 };
401 389
402 sec_mon: sec_mon@314000 { 390 sec_mon: sec_mon@314000 {
403 compatible = "fsl,p4080-sec-v4.0-mon", "fsl,sec-v4.0-mon"; 391 compatible = "fsl,sec-v4.0-mon";
404 reg = <0x314000 0x1000>; 392 reg = <0x314000 0x1000>;
405 interrupt-parent = <&mpic>; 393 interrupt-parent = <&mpic>;
406 interrupts = <93 2>; 394 interrupts = <93 2>;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 0430d241fde8..927f94d16e9b 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -423,7 +423,7 @@
423 }; 423 };
424 424
425 crypto: crypto@300000 { 425 crypto: crypto@300000 {
426 compatible = "fsl,p4080-sec-v4.0", "fsl,sec-v4.0"; 426 compatible = "fsl,sec-v4.0";
427 #address-cells = <1>; 427 #address-cells = <1>;
428 #size-cells = <1>; 428 #size-cells = <1>;
429 reg = <0x300000 0x10000>; 429 reg = <0x300000 0x10000>;
@@ -432,74 +432,64 @@
432 interrupts = <92 2>; 432 interrupts = <92 2>;
433 433
434 sec_jr0: jr@1000 { 434 sec_jr0: jr@1000 {
435 compatible = "fsl,p4080-sec-v4.0-job-ring", 435 compatible = "fsl,sec-v4.0-job-ring";
436 "fsl,sec-v4.0-job-ring";
437 reg = <0x1000 0x1000>; 436 reg = <0x1000 0x1000>;
438 interrupt-parent = <&mpic>; 437 interrupt-parent = <&mpic>;
439 interrupts = <88 2>; 438 interrupts = <88 2>;
440 }; 439 };
441 440
442 sec_jr1: jr@2000 { 441 sec_jr1: jr@2000 {
443 compatible = "fsl,p4080-sec-v4.0-job-ring", 442 compatible = "fsl,sec-v4.0-job-ring";
444 "fsl,sec-v4.0-job-ring";
445 reg = <0x2000 0x1000>; 443 reg = <0x2000 0x1000>;
446 interrupt-parent = <&mpic>; 444 interrupt-parent = <&mpic>;
447 interrupts = <89 2>; 445 interrupts = <89 2>;
448 }; 446 };
449 447
450 sec_jr2: jr@3000 { 448 sec_jr2: jr@3000 {
451 compatible = "fsl,p4080-sec-v4.0-job-ring", 449 compatible = "fsl,sec-v4.0-job-ring";
452 "fsl,sec-v4.0-job-ring";
453 reg = <0x3000 0x1000>; 450 reg = <0x3000 0x1000>;
454 interrupt-parent = <&mpic>; 451 interrupt-parent = <&mpic>;
455 interrupts = <90 2>; 452 interrupts = <90 2>;
456 }; 453 };
457 454
458 sec_jr3: jr@4000 { 455 sec_jr3: jr@4000 {
459 compatible = "fsl,p4080-sec-v4.0-job-ring", 456 compatible = "fsl,sec-v4.0-job-ring";
460 "fsl,sec-v4.0-job-ring";
461 reg = <0x4000 0x1000>; 457 reg = <0x4000 0x1000>;
462 interrupt-parent = <&mpic>; 458 interrupt-parent = <&mpic>;
463 interrupts = <91 2>; 459 interrupts = <91 2>;
464 }; 460 };
465 461
466 rtic@6000 { 462 rtic@6000 {
467 compatible = "fsl,p4080-sec-v4.0-rtic", 463 compatible = "fsl,sec-v4.0-rtic";
468 "fsl,sec-v4.0-rtic";
469 #address-cells = <1>; 464 #address-cells = <1>;
470 #size-cells = <1>; 465 #size-cells = <1>;
471 reg = <0x6000 0x100>; 466 reg = <0x6000 0x100>;
472 ranges = <0x0 0x6100 0xe00>; 467 ranges = <0x0 0x6100 0xe00>;
473 468
474 rtic_a: rtic-a@0 { 469 rtic_a: rtic-a@0 {
475 compatible = "fsl,p4080-sec-v4.0-rtic-memory", 470 compatible = "fsl,sec-v4.0-rtic-memory";
476 "fsl,sec-v4.0-rtic-memory";
477 reg = <0x00 0x20 0x100 0x80>; 471 reg = <0x00 0x20 0x100 0x80>;
478 }; 472 };
479 473
480 rtic_b: rtic-b@20 { 474 rtic_b: rtic-b@20 {
481 compatible = "fsl,p4080-sec-v4.0-rtic-memory", 475 compatible = "fsl,sec-v4.0-rtic-memory";
482 "fsl,sec-v4.0-rtic-memory";
483 reg = <0x20 0x20 0x200 0x80>; 476 reg = <0x20 0x20 0x200 0x80>;
484 }; 477 };
485 478
486 rtic_c: rtic-c@40 { 479 rtic_c: rtic-c@40 {
487 compatible = "fsl,p4080-sec-v4.0-rtic-memory", 480 compatible = "fsl,sec-v4.0-rtic-memory";
488 "fsl,sec-v4.0-rtic-memory";
489 reg = <0x40 0x20 0x300 0x80>; 481 reg = <0x40 0x20 0x300 0x80>;
490 }; 482 };
491 483
492 rtic_d: rtic-d@60 { 484 rtic_d: rtic-d@60 {
493 compatible = "fsl,p4080-sec-v4.0-rtic-memory", 485 compatible = "fsl,sec-v4.0-rtic-memory";
494 "fsl,sec-v4.0-rtic-memory";
495 reg = <0x60 0x20 0x500 0x80>; 486 reg = <0x60 0x20 0x500 0x80>;
496 }; 487 };
497 }; 488 };
498 }; 489 };
499 490
500 sec_mon: sec_mon@314000 { 491 sec_mon: sec_mon@314000 {
501 compatible = "fsl,p4080-sec-v4.0-mon", 492 compatible = "fsl,sec-v4.0-mon";
502 "fsl,sec-v4.0-mon";
503 reg = <0x314000 0x1000>; 493 reg = <0x314000 0x1000>;
504 interrupt-parent = <&mpic>; 494 interrupt-parent = <&mpic>;
505 interrupts = <93 2>; 495 interrupts = <93 2>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 12:54:46 -0500