diff options
author | Benoit Cousson <b-cousson@ti.com> | 2011-07-09 21:15:06 -0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2011-07-09 21:15:06 -0400 |
commit | 3c95b707caf3504b37b11d2662bde77e1618d481 (patch) | |
tree | 0997b309bcce522718cdd97daa6ccdd38f9a1884 | |
parent | a3b90ad8d1fb0ddaa6964d83886283ae3e338cea (diff) |
OMAP4: clockdomain data: Fix data order and wrong name
MPUSS was renamed MPU and L3_D2D D2D.
The rename will slightly change the order of the structure
and thus generate some structures moves.
Add a comment and remove a comma.
Update Copyright for TI and Nokia and add back Paul
in the author list.
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r-- | arch/arm/mach-omap2/clockdomains44xx_data.c | 124 |
1 files changed, 63 insertions, 61 deletions
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index a607ec196e8b..66090f2676ce 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c | |||
@@ -1,11 +1,12 @@ | |||
1 | /* | 1 | /* |
2 | * OMAP4 Clock domains framework | 2 | * OMAP4 Clock domains framework |
3 | * | 3 | * |
4 | * Copyright (C) 2009 Texas Instruments, Inc. | 4 | * Copyright (C) 2009-2011 Texas Instruments, Inc. |
5 | * Copyright (C) 2009 Nokia Corporation | 5 | * Copyright (C) 2009-2011 Nokia Corporation |
6 | * | 6 | * |
7 | * Abhijit Pagare (abhijitpagare@ti.com) | 7 | * Abhijit Pagare (abhijitpagare@ti.com) |
8 | * Benoit Cousson (b-cousson@ti.com) | 8 | * Benoit Cousson (b-cousson@ti.com) |
9 | * Paul Walmsley (paul@pwsan.com) | ||
9 | * | 10 | * |
10 | * This file is automatically generated from the OMAP hardware databases. | 11 | * This file is automatically generated from the OMAP hardware databases. |
11 | * We respectfully ask that any modifications to this file be coordinated | 12 | * We respectfully ask that any modifications to this file be coordinated |
@@ -32,7 +33,7 @@ | |||
32 | 33 | ||
33 | /* Static Dependencies for OMAP4 Clock Domains */ | 34 | /* Static Dependencies for OMAP4 Clock Domains */ |
34 | 35 | ||
35 | static struct clkdm_dep ducati_wkup_sleep_deps[] = { | 36 | static struct clkdm_dep d2d_wkup_sleep_deps[] = { |
36 | { | 37 | { |
37 | .clkdm_name = "abe_clkdm", | 38 | .clkdm_name = "abe_clkdm", |
38 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 39 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
@@ -50,103 +51,103 @@ static struct clkdm_dep ducati_wkup_sleep_deps[] = { | |||
50 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 51 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
51 | }, | 52 | }, |
52 | { | 53 | { |
53 | .clkdm_name = "l3_dss_clkdm", | 54 | .clkdm_name = "l3_emif_clkdm", |
54 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 55 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
55 | }, | 56 | }, |
56 | { | 57 | { |
57 | .clkdm_name = "l3_emif_clkdm", | 58 | .clkdm_name = "l3_init_clkdm", |
58 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 59 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
59 | }, | 60 | }, |
60 | { | 61 | { |
61 | .clkdm_name = "l3_gfx_clkdm", | 62 | .clkdm_name = "l4_cfg_clkdm", |
62 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 63 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
63 | }, | 64 | }, |
64 | { | 65 | { |
65 | .clkdm_name = "l3_init_clkdm", | 66 | .clkdm_name = "l4_per_clkdm", |
66 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 67 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
67 | }, | 68 | }, |
69 | { NULL }, | ||
70 | }; | ||
71 | |||
72 | static struct clkdm_dep ducati_wkup_sleep_deps[] = { | ||
68 | { | 73 | { |
69 | .clkdm_name = "l4_cfg_clkdm", | 74 | .clkdm_name = "abe_clkdm", |
70 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 75 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
71 | }, | 76 | }, |
72 | { | 77 | { |
73 | .clkdm_name = "l4_per_clkdm", | 78 | .clkdm_name = "ivahd_clkdm", |
74 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
75 | }, | 80 | }, |
76 | { | 81 | { |
77 | .clkdm_name = "l4_secure_clkdm", | 82 | .clkdm_name = "l3_1_clkdm", |
78 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 83 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
79 | }, | 84 | }, |
80 | { | 85 | { |
81 | .clkdm_name = "l4_wkup_clkdm", | 86 | .clkdm_name = "l3_2_clkdm", |
82 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
83 | }, | 88 | }, |
84 | { | 89 | { |
85 | .clkdm_name = "tesla_clkdm", | 90 | .clkdm_name = "l3_dss_clkdm", |
86 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 91 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
87 | }, | 92 | }, |
88 | { NULL }, | ||
89 | }; | ||
90 | |||
91 | static struct clkdm_dep iss_wkup_sleep_deps[] = { | ||
92 | { | 93 | { |
93 | .clkdm_name = "ivahd_clkdm", | 94 | .clkdm_name = "l3_emif_clkdm", |
94 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 95 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
95 | }, | 96 | }, |
96 | { | 97 | { |
97 | .clkdm_name = "l3_1_clkdm", | 98 | .clkdm_name = "l3_gfx_clkdm", |
98 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 99 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
99 | }, | 100 | }, |
100 | { | 101 | { |
101 | .clkdm_name = "l3_emif_clkdm", | 102 | .clkdm_name = "l3_init_clkdm", |
102 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
103 | }, | 104 | }, |
104 | { NULL }, | ||
105 | }; | ||
106 | |||
107 | static struct clkdm_dep ivahd_wkup_sleep_deps[] = { | ||
108 | { | 105 | { |
109 | .clkdm_name = "l3_1_clkdm", | 106 | .clkdm_name = "l4_cfg_clkdm", |
110 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 107 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
111 | }, | 108 | }, |
112 | { | 109 | { |
113 | .clkdm_name = "l3_emif_clkdm", | 110 | .clkdm_name = "l4_per_clkdm", |
114 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 111 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
115 | }, | 112 | }, |
116 | { NULL }, | ||
117 | }; | ||
118 | |||
119 | static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = { | ||
120 | { | 113 | { |
121 | .clkdm_name = "abe_clkdm", | 114 | .clkdm_name = "l4_secure_clkdm", |
122 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 115 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
123 | }, | 116 | }, |
124 | { | 117 | { |
125 | .clkdm_name = "ivahd_clkdm", | 118 | .clkdm_name = "l4_wkup_clkdm", |
126 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 119 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
127 | }, | 120 | }, |
128 | { | 121 | { |
129 | .clkdm_name = "l3_1_clkdm", | 122 | .clkdm_name = "tesla_clkdm", |
130 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 123 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
131 | }, | 124 | }, |
125 | { NULL }, | ||
126 | }; | ||
127 | |||
128 | static struct clkdm_dep iss_wkup_sleep_deps[] = { | ||
132 | { | 129 | { |
133 | .clkdm_name = "l3_2_clkdm", | 130 | .clkdm_name = "ivahd_clkdm", |
134 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 131 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
135 | }, | 132 | }, |
136 | { | 133 | { |
137 | .clkdm_name = "l3_emif_clkdm", | 134 | .clkdm_name = "l3_1_clkdm", |
138 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 135 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
139 | }, | 136 | }, |
140 | { | 137 | { |
141 | .clkdm_name = "l3_init_clkdm", | 138 | .clkdm_name = "l3_emif_clkdm", |
142 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 139 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
143 | }, | 140 | }, |
141 | { NULL }, | ||
142 | }; | ||
143 | |||
144 | static struct clkdm_dep ivahd_wkup_sleep_deps[] = { | ||
144 | { | 145 | { |
145 | .clkdm_name = "l4_cfg_clkdm", | 146 | .clkdm_name = "l3_1_clkdm", |
146 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 147 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
147 | }, | 148 | }, |
148 | { | 149 | { |
149 | .clkdm_name = "l4_per_clkdm", | 150 | .clkdm_name = "l3_emif_clkdm", |
150 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 151 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
151 | }, | 152 | }, |
152 | { NULL }, | 153 | { NULL }, |
@@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = { | |||
280 | { NULL }, | 281 | { NULL }, |
281 | }; | 282 | }; |
282 | 283 | ||
283 | static struct clkdm_dep mpuss_wkup_sleep_deps[] = { | 284 | static struct clkdm_dep mpu_wkup_sleep_deps[] = { |
284 | { | 285 | { |
285 | .clkdm_name = "abe_clkdm", | 286 | .clkdm_name = "abe_clkdm", |
286 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) | 287 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) |
@@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = { | |||
497 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 498 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
498 | }; | 499 | }; |
499 | 500 | ||
500 | static struct clockdomain mpuss_44xx_clkdm = { | 501 | static struct clockdomain d2d_44xx_clkdm = { |
501 | .name = "mpuss_clkdm", | 502 | .name = "d2d_clkdm", |
502 | .pwrdm = { .name = "mpu_pwrdm" }, | 503 | .pwrdm = { .name = "core_pwrdm" }, |
503 | .prcm_partition = OMAP4430_CM1_PARTITION, | 504 | .prcm_partition = OMAP4430_CM2_PARTITION, |
504 | .cm_inst = OMAP4430_CM1_MPU_INST, | 505 | .cm_inst = OMAP4430_CM2_CORE_INST, |
505 | .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, | 506 | .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, |
506 | .wkdep_srcs = mpuss_wkup_sleep_deps, | 507 | .wkdep_srcs = d2d_wkup_sleep_deps, |
507 | .sleepdep_srcs = mpuss_wkup_sleep_deps, | 508 | .sleepdep_srcs = d2d_wkup_sleep_deps, |
508 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | 509 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, |
509 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 510 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
510 | }; | 511 | }; |
@@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = { | |||
563 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 564 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
564 | }; | 565 | }; |
565 | 566 | ||
567 | static struct clockdomain mpu_44xx_clkdm = { | ||
568 | .name = "mpu_clkdm", | ||
569 | .pwrdm = { .name = "mpu_pwrdm" }, | ||
570 | .prcm_partition = OMAP4430_CM1_PARTITION, | ||
571 | .cm_inst = OMAP4430_CM1_MPU_INST, | ||
572 | .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, | ||
573 | .wkdep_srcs = mpu_wkup_sleep_deps, | ||
574 | .sleepdep_srcs = mpu_wkup_sleep_deps, | ||
575 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
576 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
577 | }; | ||
578 | |||
566 | static struct clockdomain l3_2_44xx_clkdm = { | 579 | static struct clockdomain l3_2_44xx_clkdm = { |
567 | .name = "l3_2_clkdm", | 580 | .name = "l3_2_clkdm", |
568 | .pwrdm = { .name = "core_pwrdm" }, | 581 | .pwrdm = { .name = "core_pwrdm" }, |
@@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = { | |||
585 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 598 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
586 | }; | 599 | }; |
587 | 600 | ||
588 | static struct clockdomain l3_d2d_44xx_clkdm = { | ||
589 | .name = "l3_d2d_clkdm", | ||
590 | .pwrdm = { .name = "core_pwrdm" }, | ||
591 | .prcm_partition = OMAP4430_CM2_PARTITION, | ||
592 | .cm_inst = OMAP4430_CM2_CORE_INST, | ||
593 | .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, | ||
594 | .wkdep_srcs = l3_d2d_wkup_sleep_deps, | ||
595 | .sleepdep_srcs = l3_d2d_wkup_sleep_deps, | ||
596 | .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, | ||
597 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | ||
598 | }; | ||
599 | |||
600 | static struct clockdomain iss_44xx_clkdm = { | 601 | static struct clockdomain iss_44xx_clkdm = { |
601 | .name = "iss_clkdm", | 602 | .name = "iss_clkdm", |
602 | .pwrdm = { .name = "cam_pwrdm" }, | 603 | .pwrdm = { .name = "cam_pwrdm" }, |
@@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = { | |||
655 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), | 656 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), |
656 | }; | 657 | }; |
657 | 658 | ||
659 | /* As clockdomains are added or removed above, this list must also be changed */ | ||
658 | static struct clockdomain *clockdomains_omap44xx[] __initdata = { | 660 | static struct clockdomain *clockdomains_omap44xx[] __initdata = { |
659 | &l4_cefuse_44xx_clkdm, | 661 | &l4_cefuse_44xx_clkdm, |
660 | &l4_cfg_44xx_clkdm, | 662 | &l4_cfg_44xx_clkdm, |
@@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = { | |||
666 | &abe_44xx_clkdm, | 668 | &abe_44xx_clkdm, |
667 | &l3_instr_44xx_clkdm, | 669 | &l3_instr_44xx_clkdm, |
668 | &l3_init_44xx_clkdm, | 670 | &l3_init_44xx_clkdm, |
669 | &mpuss_44xx_clkdm, | 671 | &d2d_44xx_clkdm, |
670 | &mpu0_44xx_clkdm, | 672 | &mpu0_44xx_clkdm, |
671 | &mpu1_44xx_clkdm, | 673 | &mpu1_44xx_clkdm, |
672 | &l3_emif_44xx_clkdm, | 674 | &l3_emif_44xx_clkdm, |
673 | &l4_ao_44xx_clkdm, | 675 | &l4_ao_44xx_clkdm, |
674 | &ducati_44xx_clkdm, | 676 | &ducati_44xx_clkdm, |
677 | &mpu_44xx_clkdm, | ||
675 | &l3_2_44xx_clkdm, | 678 | &l3_2_44xx_clkdm, |
676 | &l3_1_44xx_clkdm, | 679 | &l3_1_44xx_clkdm, |
677 | &l3_d2d_44xx_clkdm, | ||
678 | &iss_44xx_clkdm, | 680 | &iss_44xx_clkdm, |
679 | &l3_dss_44xx_clkdm, | 681 | &l3_dss_44xx_clkdm, |
680 | &l4_wkup_44xx_clkdm, | 682 | &l4_wkup_44xx_clkdm, |
681 | &emu_sys_44xx_clkdm, | 683 | &emu_sys_44xx_clkdm, |
682 | &l3_dma_44xx_clkdm, | 684 | &l3_dma_44xx_clkdm, |
683 | NULL, | 685 | NULL |
684 | }; | 686 | }; |
685 | 687 | ||
686 | void __init omap44xx_clockdomains_init(void) | 688 | void __init omap44xx_clockdomains_init(void) |