diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2008-05-31 19:22:37 -0400 |
---|---|---|
committer | Lennert Buytenhek <buytenh@wantstofly.org> | 2008-06-12 02:40:25 -0400 |
commit | 2beff77b6e02f52376843fbea3df9d620ee24903 (patch) | |
tree | 25c60818f6a1011dddcccca9d5b401c2815e5e91 | |
parent | 2679a550d39d7815f9fdbde5cef2f54e5fbdeae2 (diff) |
mv643xx_eth: delete unused port serial control register bit defines
Over half of the port serial control register bit defines are never
used, and the PORT_SERIAL_CONTROL_DEFAULT_VALUE define is never used
either. Keep only those defines that are actually used.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Dale Farnsworth <dale@farnsworth.org>
-rw-r--r-- | drivers/net/mv643xx_eth.c | 78 |
1 files changed, 15 insertions, 63 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index ea7a578836c3..e61cfd4c052e 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c | |||
@@ -141,71 +141,23 @@ static char mv643xx_driver_version[] = "1.0"; | |||
141 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined | 141 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined |
142 | #endif | 142 | #endif |
143 | 143 | ||
144 | /* These macros describe Ethernet Port serial control reg (PSCR) bits */ | 144 | |
145 | #define SERIAL_PORT_DISABLE (0 << 0) | 145 | /* |
146 | #define SERIAL_PORT_ENABLE (1 << 0) | 146 | * Port serial control register. |
147 | #define DO_NOT_FORCE_LINK_PASS (0 << 1) | 147 | */ |
148 | #define FORCE_LINK_PASS (1 << 1) | 148 | #define SET_MII_SPEED_TO_100 (1 << 24) |
149 | #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2) | 149 | #define SET_GMII_SPEED_TO_1000 (1 << 23) |
150 | #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2) | 150 | #define SET_FULL_DUPLEX_MODE (1 << 21) |
151 | #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3) | ||
152 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) | ||
153 | #define ADV_NO_FLOW_CTRL (0 << 4) | ||
154 | #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4) | ||
155 | #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5) | ||
156 | #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) | ||
157 | #define FORCE_BP_MODE_NO_JAM (0 << 7) | ||
158 | #define FORCE_BP_MODE_JAM_TX (1 << 7) | ||
159 | #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7) | ||
160 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) | ||
161 | #define FORCE_LINK_FAIL (0 << 10) | ||
162 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) | ||
163 | #define RETRANSMIT_16_ATTEMPTS (0 << 11) | ||
164 | #define RETRANSMIT_FOREVER (1 << 11) | ||
165 | #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13) | ||
166 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) | ||
167 | #define DTE_ADV_0 (0 << 14) | ||
168 | #define DTE_ADV_1 (1 << 14) | ||
169 | #define DISABLE_AUTO_NEG_BYPASS (0 << 15) | ||
170 | #define ENABLE_AUTO_NEG_BYPASS (1 << 15) | ||
171 | #define AUTO_NEG_NO_CHANGE (0 << 16) | ||
172 | #define RESTART_AUTO_NEG (1 << 16) | ||
173 | #define MAX_RX_PACKET_1518BYTE (0 << 17) | ||
174 | #define MAX_RX_PACKET_1522BYTE (1 << 17) | 151 | #define MAX_RX_PACKET_1522BYTE (1 << 17) |
175 | #define MAX_RX_PACKET_1552BYTE (2 << 17) | ||
176 | #define MAX_RX_PACKET_9022BYTE (3 << 17) | ||
177 | #define MAX_RX_PACKET_9192BYTE (4 << 17) | ||
178 | #define MAX_RX_PACKET_9700BYTE (5 << 17) | 152 | #define MAX_RX_PACKET_9700BYTE (5 << 17) |
179 | #define MAX_RX_PACKET_MASK (7 << 17) | 153 | #define MAX_RX_PACKET_MASK (7 << 17) |
180 | #define CLR_EXT_LOOPBACK (0 << 20) | 154 | #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) |
181 | #define SET_EXT_LOOPBACK (1 << 20) | 155 | #define DO_NOT_FORCE_LINK_FAIL (1 << 10) |
182 | #define SET_HALF_DUPLEX_MODE (0 << 21) | 156 | #define SERIAL_PORT_CONTROL_RESERVED (1 << 9) |
183 | #define SET_FULL_DUPLEX_MODE (1 << 21) | 157 | #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) |
184 | #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22) | 158 | #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2) |
185 | #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) | 159 | #define FORCE_LINK_PASS (1 << 1) |
186 | #define SET_GMII_SPEED_TO_10_100 (0 << 23) | 160 | #define SERIAL_PORT_ENABLE (1 << 0) |
187 | #define SET_GMII_SPEED_TO_1000 (1 << 23) | ||
188 | #define SET_MII_SPEED_TO_10 (0 << 24) | ||
189 | #define SET_MII_SPEED_TO_100 (1 << 24) | ||
190 | |||
191 | #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \ | ||
192 | DO_NOT_FORCE_LINK_PASS | \ | ||
193 | ENABLE_AUTO_NEG_FOR_DUPLX | \ | ||
194 | DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ | ||
195 | ADV_SYMMETRIC_FLOW_CTRL | \ | ||
196 | FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ | ||
197 | FORCE_BP_MODE_NO_JAM | \ | ||
198 | (1 << 9) /* reserved */ | \ | ||
199 | DO_NOT_FORCE_LINK_FAIL | \ | ||
200 | RETRANSMIT_16_ATTEMPTS | \ | ||
201 | ENABLE_AUTO_NEG_SPEED_GMII | \ | ||
202 | DTE_ADV_0 | \ | ||
203 | DISABLE_AUTO_NEG_BYPASS | \ | ||
204 | AUTO_NEG_NO_CHANGE | \ | ||
205 | MAX_RX_PACKET_9700BYTE | \ | ||
206 | CLR_EXT_LOOPBACK | \ | ||
207 | SET_FULL_DUPLEX_MODE | \ | ||
208 | ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX | ||
209 | 161 | ||
210 | /* These macros describe Ethernet Serial Status reg (PSR) bits */ | 162 | /* These macros describe Ethernet Serial Status reg (PSR) bits */ |
211 | #define PORT_STATUS_MODE_10_BIT (1 << 0) | 163 | #define PORT_STATUS_MODE_10_BIT (1 << 0) |
@@ -2196,7 +2148,7 @@ static void eth_port_start(struct net_device *dev) | |||
2196 | 2148 | ||
2197 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | | 2149 | pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL | |
2198 | DISABLE_AUTO_NEG_SPEED_GMII | | 2150 | DISABLE_AUTO_NEG_SPEED_GMII | |
2199 | DISABLE_AUTO_NEG_FOR_DUPLX | | 2151 | DISABLE_AUTO_NEG_FOR_DUPLEX | |
2200 | DO_NOT_FORCE_LINK_FAIL | | 2152 | DO_NOT_FORCE_LINK_FAIL | |
2201 | SERIAL_PORT_CONTROL_RESERVED; | 2153 | SERIAL_PORT_CONTROL_RESERVED; |
2202 | 2154 | ||