[media] ds3000: clean up in tune procedure

Variable 'retune' does not make sense. Loop is not needed for only one try. Remove unnecessary dprintk's. Remove a lot of debug messages and delays. Signed-off-by: Igor M. Liplianin <liplianin@me.by> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
author: Igor M. Liplianin <liplianin@me.by> 2011-02-25 16:41:23 -0500
committer: Mauro Carvalho Chehab <mchehab@redhat.com> 2011-03-21 19:32:27 -0400
commit: 18a73f36a2109563beee00f8be3f19f6c1fe2ff6 (patch)
tree: bb4ca3b35a99ce9f4b587b3edd19a0231fb527bb
parent: 2f30fb49c347e8696a8784c57810b41d185707ec (diff)
1 files changed, 213 insertions, 259 deletions
diff --git a/drivers/media/dvb/frontends/ds3000.c b/drivers/media/dvb/frontends/ds3000.c
index 3373890c092e..882be672f5d2 100644
--- a/drivers/media/dvb/frontends/ds3000.c
+++ b/drivers/media/dvb/frontends/ds3000.c
@@ -536,25 +536,6 @@ static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
        return 0;
 }
-static void ds3000_dump_registers(struct dvb_frontend *fe)
-{
-        struct ds3000_state *state = fe->demodulator_priv;
-        int x, y, reg = 0, val;
-        for (y = 0; y < 16; y++) {
-                dprintk("%s: %02x: ", __func__, y);
-                for (x = 0; x < 16; x++) {
-                        reg = (y << 4) + x;
-                        val = ds3000_readreg(state, reg);
-                        if (x != 15)
-                                dprintk("%02x ",  val);
-                        else
-                                dprintk("%02x\n", val);
-                }
-        }
-        dprintk("%s: -- DS3000 DUMP DONE --\n", __func__);
-}
 static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
 {
        struct ds3000_state *state = fe->demodulator_priv;
@@ -589,16 +570,6 @@ static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
        return 0;
 }
-#define FE_IS_TUNED (FE_HAS_SIGNAL + FE_HAS_LOCK)
-static int ds3000_is_tuned(struct dvb_frontend *fe)
-{
-        fe_status_t tunerstat;
-        ds3000_read_status(fe, &tunerstat);
-        return ((tunerstat & FE_IS_TUNED) == FE_IS_TUNED);
-}
 /* read DS3000 BER value */
 static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
 {
@@ -1049,7 +1020,7 @@ static int ds3000_tune(struct dvb_frontend *fe,
        struct ds3000_state *state = fe->demodulator_priv;
        struct dtv_frontend_properties *c = &fe->dtv_property_cache;
-        int ret = 0, retune, i;
+        int i;
        u8 status, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf;
        u16 value, ndiv;
        u32 f3db;
@@ -1072,252 +1043,235 @@ static int ds3000_tune(struct dvb_frontend *fe,
        /* discard the 'current' tuning parameters and prepare to tune */
        ds3000_clone_params(fe);
-        retune = 1;     /* try 1 times */
+        /* Reset status register */
-        dprintk("%s:   retune = %d\n", __func__, retune);
+        status = 0;
-        dprintk("%s:   frequency   = %d\n", __func__, state->dcur.frequency);
+        /* Tune */
-        dprintk("%s:   symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
+        /* unknown */
-        dprintk("%s:   FEC       = %d \n", __func__,
+        ds3000_tuner_writereg(state, 0x07, 0x02);
-                state->dcur.fec);
+        ds3000_tuner_writereg(state, 0x10, 0x00);
-        dprintk("%s:   Inversion   = %d\n", __func__, state->dcur.inversion);
+        ds3000_tuner_writereg(state, 0x60, 0x79);
+        ds3000_tuner_writereg(state, 0x08, 0x01);
-        do {
+        ds3000_tuner_writereg(state, 0x00, 0x01);
-                /* Reset status register */
+        /* calculate and set freq divider */
-                status = 0;
+        if (state->dcur.frequency < 1146000) {
-                /* Tune */
+                ds3000_tuner_writereg(state, 0x10, 0x11);
-                /* unknown */
+                ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
-                ds3000_tuner_writereg(state, 0x07, 0x02);
+                                (DS3000_XTAL_FREQ / 2)) /
-                ds3000_tuner_writereg(state, 0x10, 0x00);
+                                DS3000_XTAL_FREQ - 1024;
-                ds3000_tuner_writereg(state, 0x60, 0x79);
+        } else {
-                ds3000_tuner_writereg(state, 0x08, 0x01);
+                ds3000_tuner_writereg(state, 0x10, 0x01);
-                ds3000_tuner_writereg(state, 0x00, 0x01);
+                ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
-                /* calculate and set freq divider */
+                                (DS3000_XTAL_FREQ / 2)) /
-                if (state->dcur.frequency < 1146000) {
+                                DS3000_XTAL_FREQ - 1024;
-                        ds3000_tuner_writereg(state, 0x10, 0x11);
+        }
-                        ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
-                                        (DS3000_XTAL_FREQ / 2)) /
-                                        DS3000_XTAL_FREQ - 1024;
-                } else {
-                        ds3000_tuner_writereg(state, 0x10, 0x01);
-                        ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
-                                        (DS3000_XTAL_FREQ / 2)) /
-                                        DS3000_XTAL_FREQ - 1024;
-                }
-                ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
+        ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
-                ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
+        ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
-                /* set pll */
+        /* set pll */
-                ds3000_tuner_writereg(state, 0x03, 0x06);
+        ds3000_tuner_writereg(state, 0x03, 0x06);
-                ds3000_tuner_writereg(state, 0x51, 0x0f);
+        ds3000_tuner_writereg(state, 0x51, 0x0f);
-                ds3000_tuner_writereg(state, 0x51, 0x1f);
+        ds3000_tuner_writereg(state, 0x51, 0x1f);
-                ds3000_tuner_writereg(state, 0x50, 0x10);
+        ds3000_tuner_writereg(state, 0x50, 0x10);
-                ds3000_tuner_writereg(state, 0x50, 0x00);
+        ds3000_tuner_writereg(state, 0x50, 0x00);
-                msleep(5);
+        msleep(5);
-                /* unknown */
+        /* unknown */
-                ds3000_tuner_writereg(state, 0x51, 0x17);
+        ds3000_tuner_writereg(state, 0x51, 0x17);
-                ds3000_tuner_writereg(state, 0x51, 0x1f);
+        ds3000_tuner_writereg(state, 0x51, 0x1f);
-                ds3000_tuner_writereg(state, 0x50, 0x08);
+        ds3000_tuner_writereg(state, 0x50, 0x08);
-                ds3000_tuner_writereg(state, 0x50, 0x00);
+        ds3000_tuner_writereg(state, 0x50, 0x00);
-                msleep(5);
+        msleep(5);
-                value = ds3000_tuner_readreg(state, 0x3d);
+        value = ds3000_tuner_readreg(state, 0x3d);
-                value &= 0x0f;
+        value &= 0x0f;
-                if ((value > 4) && (value < 15)) {
+        if ((value > 4) && (value < 15)) {
-                        value -= 3;
+                value -= 3;
-                        if (value < 4)
+                if (value < 4)
-                                value = 4;
+                        value = 4;
-                        value = ((value << 3) | 0x01) & 0x79;
+                value = ((value << 3) | 0x01) & 0x79;
-                }
+        }
-                ds3000_tuner_writereg(state, 0x60, value);
+        ds3000_tuner_writereg(state, 0x60, value);
-                ds3000_tuner_writereg(state, 0x51, 0x17);
+        ds3000_tuner_writereg(state, 0x51, 0x17);
-                ds3000_tuner_writereg(state, 0x51, 0x1f);
+        ds3000_tuner_writereg(state, 0x51, 0x1f);
-                ds3000_tuner_writereg(state, 0x50, 0x08);
+        ds3000_tuner_writereg(state, 0x50, 0x08);
-                ds3000_tuner_writereg(state, 0x50, 0x00);
+        ds3000_tuner_writereg(state, 0x50, 0x00);
-                /* set low-pass filter period */
+        /* set low-pass filter period */
-                ds3000_tuner_writereg(state, 0x04, 0x2e);
+        ds3000_tuner_writereg(state, 0x04, 0x2e);
-                ds3000_tuner_writereg(state, 0x51, 0x1b);
+        ds3000_tuner_writereg(state, 0x51, 0x1b);
-                ds3000_tuner_writereg(state, 0x51, 0x1f);
+        ds3000_tuner_writereg(state, 0x51, 0x1f);
-                ds3000_tuner_writereg(state, 0x50, 0x04);
+        ds3000_tuner_writereg(state, 0x50, 0x04);
-                ds3000_tuner_writereg(state, 0x50, 0x00);
+        ds3000_tuner_writereg(state, 0x50, 0x00);
-                msleep(5);
+        msleep(5);
-                f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
+        f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
-                if ((state->dcur.symbol_rate / 1000) < 5000)
+        if ((state->dcur.symbol_rate / 1000) < 5000)
-                        f3db += 3000;
+                f3db += 3000;
-                if (f3db < 7000)
+        if (f3db < 7000)
-                        f3db = 7000;
+                f3db = 7000;
-                if (f3db > 40000)
+        if (f3db > 40000)
-                        f3db = 40000;
+                f3db = 40000;
-                /* set low-pass filter baseband */
+        /* set low-pass filter baseband */
-                value = ds3000_tuner_readreg(state, 0x26);
+        value = ds3000_tuner_readreg(state, 0x26);
-                mlpf = 0x2e * 207 / ((value << 1) + 151);
+        mlpf = 0x2e * 207 / ((value << 1) + 151);
-                mlpf_max = mlpf * 135 / 100;
+        mlpf_max = mlpf * 135 / 100;
-                mlpf_min = mlpf * 78 / 100;
+        mlpf_min = mlpf * 78 / 100;
-                if (mlpf_max > 63)
+        if (mlpf_max > 63)
-                        mlpf_max = 63;
+                mlpf_max = 63;
-                /* rounded to the closest integer */
+        /* rounded to the closest integer */
-                nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
+        nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
-                                / (2766 * DS3000_XTAL_FREQ);
+                        / (2766 * DS3000_XTAL_FREQ);
-                if (nlpf > 23)
+        if (nlpf > 23)
-                        nlpf = 23;
+                nlpf = 23;
-                if (nlpf < 1)
+        if (nlpf < 1)
-                        nlpf = 1;
+                nlpf = 1;
-                /* rounded to the closest integer */
+        /* rounded to the closest integer */
+        mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
+                        (1000 * f3db / 2)) / (1000 * f3db);
+        if (mlpf_new < mlpf_min) {
+                nlpf++;
                mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
                                (1000 * f3db / 2)) / (1000 * f3db);
+        }
-                if (mlpf_new < mlpf_min) {
+        if (mlpf_new > mlpf_max)
-                        nlpf++;
+                mlpf_new = mlpf_max;
-                        mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
-                                        (1000 * f3db / 2)) / (1000 * f3db);
+        ds3000_tuner_writereg(state, 0x04, mlpf_new);
-                }
+        ds3000_tuner_writereg(state, 0x06, nlpf);
+        ds3000_tuner_writereg(state, 0x51, 0x1b);
+        ds3000_tuner_writereg(state, 0x51, 0x1f);
+        ds3000_tuner_writereg(state, 0x50, 0x04);
+        ds3000_tuner_writereg(state, 0x50, 0x00);
+        msleep(5);
+        /* unknown */
+        ds3000_tuner_writereg(state, 0x51, 0x1e);
+        ds3000_tuner_writereg(state, 0x51, 0x1f);
+        ds3000_tuner_writereg(state, 0x50, 0x01);
+        ds3000_tuner_writereg(state, 0x50, 0x00);
+        msleep(60);
+        /* ds3000 global reset */
+        ds3000_writereg(state, 0x07, 0x80);
+        ds3000_writereg(state, 0x07, 0x00);
+        /* ds3000 build-in uC reset */
+        ds3000_writereg(state, 0xb2, 0x01);
+        /* ds3000 software reset */
+        ds3000_writereg(state, 0x00, 0x01);
-                if (mlpf_new > mlpf_max)
+        switch (c->delivery_system) {
-                        mlpf_new = mlpf_max;
+        case SYS_DVBS:
+                /* initialise the demod in DVB-S mode */
-                ds3000_tuner_writereg(state, 0x04, mlpf_new);
+                for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
-                ds3000_tuner_writereg(state, 0x06, nlpf);
+                        ds3000_writereg(state,
-                ds3000_tuner_writereg(state, 0x51, 0x1b);
+                                ds3000_dvbs_init_tab[i],
-                ds3000_tuner_writereg(state, 0x51, 0x1f);
+                                ds3000_dvbs_init_tab[i + 1]);
-                ds3000_tuner_writereg(state, 0x50, 0x04);
+                value = ds3000_readreg(state, 0xfe);
-                ds3000_tuner_writereg(state, 0x50, 0x00);
+                value &= 0xc0;
-                msleep(5);
+                value |= 0x1b;
+                ds3000_writereg(state, 0xfe, value);
-                /* unknown */
+                break;
-                ds3000_tuner_writereg(state, 0x51, 0x1e);
+        case SYS_DVBS2:
-                ds3000_tuner_writereg(state, 0x51, 0x1f);
+                /* initialise the demod in DVB-S2 mode */
-                ds3000_tuner_writereg(state, 0x50, 0x01);
+                for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
-                ds3000_tuner_writereg(state, 0x50, 0x00);
+                        ds3000_writereg(state,
-                msleep(60);
+                                ds3000_dvbs2_init_tab[i],
+                                ds3000_dvbs2_init_tab[i + 1]);
-                /* ds3000 global reset */
+                ds3000_writereg(state, 0xfe, 0x98);
-                ds3000_writereg(state, 0x07, 0x80);
+                break;
-                ds3000_writereg(state, 0x07, 0x00);
+        default:
-                /* ds3000 build-in uC reset */
+                return 1;
-                ds3000_writereg(state, 0xb2, 0x01);
+        }
-                /* ds3000 software reset */
-                ds3000_writereg(state, 0x00, 0x01);
+        /* enable 27MHz clock output */
+        ds3000_writereg(state, 0x29, 0x80);
+        /* enable ac coupling */
+        ds3000_writereg(state, 0x25, 0x8a);
+        /* enhance symbol rate performance */
+        if ((state->dcur.symbol_rate / 1000) <= 5000) {
+                value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
+                if (value % 2 != 0)
+                        value++;
+                ds3000_writereg(state, 0xc3, 0x0d);
+                ds3000_writereg(state, 0xc8, value);
+                ds3000_writereg(state, 0xc4, 0x10);
+                ds3000_writereg(state, 0xc7, 0x0e);
+        } else if ((state->dcur.symbol_rate / 1000) <= 10000) {
+                value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
+                if (value % 2 != 0)
+                        value++;
+                ds3000_writereg(state, 0xc3, 0x07);
+                ds3000_writereg(state, 0xc8, value);
+                ds3000_writereg(state, 0xc4, 0x09);
+                ds3000_writereg(state, 0xc7, 0x12);
+        } else if ((state->dcur.symbol_rate / 1000) <= 20000) {
+                value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
+                ds3000_writereg(state, 0xc3, value);
+                ds3000_writereg(state, 0xc8, 0x0e);
+                ds3000_writereg(state, 0xc4, 0x07);
+                ds3000_writereg(state, 0xc7, 0x18);
+        } else {
+                value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
+                ds3000_writereg(state, 0xc3, value);
+                ds3000_writereg(state, 0xc8, 0x0a);
+                ds3000_writereg(state, 0xc4, 0x05);
+                ds3000_writereg(state, 0xc7, 0x24);
+        }
+        /* normalized symbol rate rounded to the closest integer */
+        value = (((state->dcur.symbol_rate / 1000) << 16) +
+                        (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
+        ds3000_writereg(state, 0x61, value & 0x00ff);
+        ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
+        /* co-channel interference cancellation disabled */
+        ds3000_writereg(state, 0x56, 0x00);
+        /* equalizer disabled */
+        ds3000_writereg(state, 0x76, 0x00);
+        /*ds3000_writereg(state, 0x08, 0x03);
+        ds3000_writereg(state, 0xfd, 0x22);
+        ds3000_writereg(state, 0x08, 0x07);
+        ds3000_writereg(state, 0xfd, 0x42);
+        ds3000_writereg(state, 0x08, 0x07);*/
+        if (state->config->ci_mode) {
                switch (c->delivery_system) {
                case SYS_DVBS:
-                        /* initialise the demod in DVB-S mode */
+                default:
-                        for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
+                        ds3000_writereg(state, 0xfd, 0x80);
-                                ds3000_writereg(state,
+                break;
-                                        ds3000_dvbs_init_tab[i],
-                                        ds3000_dvbs_init_tab[i + 1]);
-                        value = ds3000_readreg(state, 0xfe);
-                        value &= 0xc0;
-                        value |= 0x1b;
-                        ds3000_writereg(state, 0xfe, value);
-                        break;
                case SYS_DVBS2:
-                        /* initialise the demod in DVB-S2 mode */
+                        ds3000_writereg(state, 0xfd, 0x01);
-                        for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
-                                ds3000_writereg(state,
-                                        ds3000_dvbs2_init_tab[i],
-                                        ds3000_dvbs2_init_tab[i + 1]);
-                        ds3000_writereg(state, 0xfe, 0x98);
                        break;
-                default:
-                        return 1;
-                }
-                /* enable 27MHz clock output */
-                ds3000_writereg(state, 0x29, 0x80);
-                /* enable ac coupling */
-                ds3000_writereg(state, 0x25, 0x8a);
-                /* enhance symbol rate performance */
-                if ((state->dcur.symbol_rate / 1000) <= 5000) {
-                        value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
-                        if (value % 2 != 0)
-                                value++;
-                        ds3000_writereg(state, 0xc3, 0x0d);
-                        ds3000_writereg(state, 0xc8, value);
-                        ds3000_writereg(state, 0xc4, 0x10);
-                        ds3000_writereg(state, 0xc7, 0x0e);
-                } else if ((state->dcur.symbol_rate / 1000) <= 10000) {
-                        value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
-                        if (value % 2 != 0)
-                                value++;
-                        ds3000_writereg(state, 0xc3, 0x07);
-                        ds3000_writereg(state, 0xc8, value);
-                        ds3000_writereg(state, 0xc4, 0x09);
-                        ds3000_writereg(state, 0xc7, 0x12);
-                } else if ((state->dcur.symbol_rate / 1000) <= 20000) {
-                        value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
-                        ds3000_writereg(state, 0xc3, value);
-                        ds3000_writereg(state, 0xc8, 0x0e);
-                        ds3000_writereg(state, 0xc4, 0x07);
-                        ds3000_writereg(state, 0xc7, 0x18);
-                } else {
-                        value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
-                        ds3000_writereg(state, 0xc3, value);
-                        ds3000_writereg(state, 0xc8, 0x0a);
-                        ds3000_writereg(state, 0xc4, 0x05);
-                        ds3000_writereg(state, 0xc7, 0x24);
                }
+        }
-                /* normalized symbol rate rounded to the closest integer */
+        /* ds3000 out of software reset */
-                value = (((state->dcur.symbol_rate / 1000) << 16) +
+        ds3000_writereg(state, 0x00, 0x00);
-                                (DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
+        /* start ds3000 build-in uC */
-                ds3000_writereg(state, 0x61, value & 0x00ff);
+        ds3000_writereg(state, 0xb2, 0x00);
-                ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
-                /* co-channel interference cancellation disabled */
-                ds3000_writereg(state, 0x56, 0x00);
-                /* equalizer disabled */
-                ds3000_writereg(state, 0x76, 0x00);
-                /*ds3000_writereg(state, 0x08, 0x03);
-                ds3000_writereg(state, 0xfd, 0x22);
-                ds3000_writereg(state, 0x08, 0x07);
-                ds3000_writereg(state, 0xfd, 0x42);
-                ds3000_writereg(state, 0x08, 0x07);*/
-                if (state->config->ci_mode) {
-                        switch (c->delivery_system) {
-                        case SYS_DVBS:
-                        default:
-                                ds3000_writereg(state, 0xfd, 0x80);
-                        break;
-                        case SYS_DVBS2:
-                                ds3000_writereg(state, 0xfd, 0x01);
-                                break;
-                        }
-                }
-                /* ds3000 out of software reset */
+        /* TODO: calculate and set carrier offset */
-                ds3000_writereg(state, 0x00, 0x00);
-                /* start ds3000 build-in uC */
-                ds3000_writereg(state, 0xb2, 0x00);
-                /* TODO: calculate and set carrier offset */
-                /* wait before retrying */
-                for (i = 0; i < 30 ; i++) {
-                        if (ds3000_is_tuned(fe)) {
-                                dprintk("%s: Tuned\n", __func__);
-                                ds3000_dump_registers(fe);
-                                goto tuned;
-                        }
-                        msleep(1);
-                }
-                dprintk("%s: Not tuned\n", __func__);
+        for (i = 0; i < 30 ; i++) {
-                ds3000_dump_registers(fe);
+                ds3000_read_status(fe, &status);
+                if (status && FE_HAS_LOCK)
+                        break;
-        } while (--retune);
+                msleep(10);
+        }
-tuned:
+        return 0;
-        return ret;
 }
 static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
author	Igor M. Liplianin <liplianin@me.by>	2011-02-25 16:41:23 -0500
committer	Mauro Carvalho Chehab <mchehab@redhat.com>	2011-03-21 19:32:27 -0400
commit	18a73f36a2109563beee00f8be3f19f6c1fe2ff6 (patch)
tree	bb4ca3b35a99ce9f4b587b3edd19a0231fb527bb
parent	2f30fb49c347e8696a8784c57810b41d185707ec (diff)

diff --git a/drivers/media/dvb/frontends/ds3000.c b/drivers/media/dvb/frontends/ds3000.c index 3373890c092e..882be672f5d2 100644 --- a/drivers/media/dvb/frontends/ds3000.c +++ b/drivers/media/dvb/frontends/ds3000.c
@@ -536,25 +536,6 @@ static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
536	return 0;	536	return 0;
537	}	537	}
538		538
539	static void ds3000_dump_registers(struct dvb_frontend *fe)
540	{
541	struct ds3000_state *state = fe->demodulator_priv;
542	int x, y, reg = 0, val;
543
544	for (y = 0; y < 16; y++) {
545	dprintk("%s: %02x: ", __func__, y);
546	for (x = 0; x < 16; x++) {
547	reg = (y << 4) + x;
548	val = ds3000_readreg(state, reg);
549	if (x != 15)
550	dprintk("%02x ", val);
551	else
552	dprintk("%02x\n", val);
553	}
554	}
555	dprintk("%s: -- DS3000 DUMP DONE --\n", __func__);
556	}
557
558	static int ds3000_read_status(struct dvb_frontend fe, fe_status_t status)	539	static int ds3000_read_status(struct dvb_frontend fe, fe_status_t status)
559	{	540	{
560	struct ds3000_state *state = fe->demodulator_priv;	541	struct ds3000_state *state = fe->demodulator_priv;
@@ -589,16 +570,6 @@ static int ds3000_read_status(struct dvb_frontend fe, fe_status_t status)
589	return 0;	570	return 0;
590	}	571	}
591		572
592	#define FE_IS_TUNED (FE_HAS_SIGNAL + FE_HAS_LOCK)
593	static int ds3000_is_tuned(struct dvb_frontend *fe)
594	{
595	fe_status_t tunerstat;
596
597	ds3000_read_status(fe, &tunerstat);
598
599	return ((tunerstat & FE_IS_TUNED) == FE_IS_TUNED);
600	}
601
602	/* read DS3000 BER value */	573	/* read DS3000 BER value */
603	static int ds3000_read_ber(struct dvb_frontend fe, u32 ber)	574	static int ds3000_read_ber(struct dvb_frontend fe, u32 ber)
604	{	575	{
@@ -1049,7 +1020,7 @@ static int ds3000_tune(struct dvb_frontend *fe,
1049	struct ds3000_state *state = fe->demodulator_priv;	1020	struct ds3000_state *state = fe->demodulator_priv;
1050	struct dtv_frontend_properties *c = &fe->dtv_property_cache;	1021	struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1051		1022
1052	int ret = 0, retune, i;	1023	int i;
1053	u8 status, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf;	1024	u8 status, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf;
1054	u16 value, ndiv;	1025	u16 value, ndiv;
1055	u32 f3db;	1026	u32 f3db;
@@ -1072,252 +1043,235 @@ static int ds3000_tune(struct dvb_frontend *fe,
1072	/* discard the 'current' tuning parameters and prepare to tune */	1043	/* discard the 'current' tuning parameters and prepare to tune */
1073	ds3000_clone_params(fe);	1044	ds3000_clone_params(fe);
1074		1045
1075	retune = 1; /* try 1 times */	1046	/* Reset status register */
1076	dprintk("%s: retune = %d\n", __func__, retune);	1047	status = 0;
1077	dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency);	1048	/* Tune */
1078	dprintk("%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate);	1049	/* unknown */
1079	dprintk("%s: FEC = %d \n", __func__,	1050	ds3000_tuner_writereg(state, 0x07, 0x02);
1080	state->dcur.fec);	1051	ds3000_tuner_writereg(state, 0x10, 0x00);
1081	dprintk("%s: Inversion = %d\n", __func__, state->dcur.inversion);	1052	ds3000_tuner_writereg(state, 0x60, 0x79);
1082		1053	ds3000_tuner_writereg(state, 0x08, 0x01);
1083	do {	1054	ds3000_tuner_writereg(state, 0x00, 0x01);
1084	/* Reset status register */	1055	/* calculate and set freq divider */
1085	status = 0;	1056	if (state->dcur.frequency < 1146000) {
1086	/* Tune */	1057	ds3000_tuner_writereg(state, 0x10, 0x11);
1087	/* unknown */	1058	ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
1088	ds3000_tuner_writereg(state, 0x07, 0x02);	1059	(DS3000_XTAL_FREQ / 2)) /
1089	ds3000_tuner_writereg(state, 0x10, 0x00);	1060	DS3000_XTAL_FREQ - 1024;
1090	ds3000_tuner_writereg(state, 0x60, 0x79);	1061	} else {
1091	ds3000_tuner_writereg(state, 0x08, 0x01);	1062	ds3000_tuner_writereg(state, 0x10, 0x01);
1092	ds3000_tuner_writereg(state, 0x00, 0x01);	1063	ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
1093	/* calculate and set freq divider */	1064	(DS3000_XTAL_FREQ / 2)) /
1094	if (state->dcur.frequency < 1146000) {	1065	DS3000_XTAL_FREQ - 1024;
1095	ds3000_tuner_writereg(state, 0x10, 0x11);	1066	}
1096	ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
1097	(DS3000_XTAL_FREQ / 2)) /
1098	DS3000_XTAL_FREQ - 1024;
1099	} else {
1100	ds3000_tuner_writereg(state, 0x10, 0x01);
1101	ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
1102	(DS3000_XTAL_FREQ / 2)) /
1103	DS3000_XTAL_FREQ - 1024;
1104	}
1105		1067
1106	ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);	1068	ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
1107	ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);	1069	ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
1108		1070
1109	/* set pll */	1071	/* set pll */
1110	ds3000_tuner_writereg(state, 0x03, 0x06);	1072	ds3000_tuner_writereg(state, 0x03, 0x06);
1111	ds3000_tuner_writereg(state, 0x51, 0x0f);	1073	ds3000_tuner_writereg(state, 0x51, 0x0f);
1112	ds3000_tuner_writereg(state, 0x51, 0x1f);	1074	ds3000_tuner_writereg(state, 0x51, 0x1f);
1113	ds3000_tuner_writereg(state, 0x50, 0x10);	1075	ds3000_tuner_writereg(state, 0x50, 0x10);
1114	ds3000_tuner_writereg(state, 0x50, 0x00);	1076	ds3000_tuner_writereg(state, 0x50, 0x00);
1115	msleep(5);	1077	msleep(5);
1116		1078
1117	/* unknown */	1079	/* unknown */
1118	ds3000_tuner_writereg(state, 0x51, 0x17);	1080	ds3000_tuner_writereg(state, 0x51, 0x17);
1119	ds3000_tuner_writereg(state, 0x51, 0x1f);	1081	ds3000_tuner_writereg(state, 0x51, 0x1f);
1120	ds3000_tuner_writereg(state, 0x50, 0x08);	1082	ds3000_tuner_writereg(state, 0x50, 0x08);
1121	ds3000_tuner_writereg(state, 0x50, 0x00);	1083	ds3000_tuner_writereg(state, 0x50, 0x00);
1122	msleep(5);	1084	msleep(5);
1123		1085
1124	value = ds3000_tuner_readreg(state, 0x3d);	1086	value = ds3000_tuner_readreg(state, 0x3d);
1125	value &= 0x0f;	1087	value &= 0x0f;
1126	if ((value > 4) && (value < 15)) {	1088	if ((value > 4) && (value < 15)) {
1127	value -= 3;	1089	value -= 3;
1128	if (value < 4)	1090	if (value < 4)
1129	value = 4;	1091	value = 4;
1130	value = ((value << 3) \| 0x01) & 0x79;	1092	value = ((value << 3) \| 0x01) & 0x79;
1131	}	1093	}
1132		1094
1133	ds3000_tuner_writereg(state, 0x60, value);	1095	ds3000_tuner_writereg(state, 0x60, value);
1134	ds3000_tuner_writereg(state, 0x51, 0x17);	1096	ds3000_tuner_writereg(state, 0x51, 0x17);
1135	ds3000_tuner_writereg(state, 0x51, 0x1f);	1097	ds3000_tuner_writereg(state, 0x51, 0x1f);
1136	ds3000_tuner_writereg(state, 0x50, 0x08);	1098	ds3000_tuner_writereg(state, 0x50, 0x08);
1137	ds3000_tuner_writereg(state, 0x50, 0x00);	1099	ds3000_tuner_writereg(state, 0x50, 0x00);
1138		1100
1139	/* set low-pass filter period */	1101	/* set low-pass filter period */
1140	ds3000_tuner_writereg(state, 0x04, 0x2e);	1102	ds3000_tuner_writereg(state, 0x04, 0x2e);
1141	ds3000_tuner_writereg(state, 0x51, 0x1b);	1103	ds3000_tuner_writereg(state, 0x51, 0x1b);
1142	ds3000_tuner_writereg(state, 0x51, 0x1f);	1104	ds3000_tuner_writereg(state, 0x51, 0x1f);
1143	ds3000_tuner_writereg(state, 0x50, 0x04);	1105	ds3000_tuner_writereg(state, 0x50, 0x04);
1144	ds3000_tuner_writereg(state, 0x50, 0x00);	1106	ds3000_tuner_writereg(state, 0x50, 0x00);
1145	msleep(5);	1107	msleep(5);
1146		1108
1147	f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;	1109	f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
1148	if ((state->dcur.symbol_rate / 1000) < 5000)	1110	if ((state->dcur.symbol_rate / 1000) < 5000)
1149	f3db += 3000;	1111	f3db += 3000;
1150	if (f3db < 7000)	1112	if (f3db < 7000)
1151	f3db = 7000;	1113	f3db = 7000;
1152	if (f3db > 40000)	1114	if (f3db > 40000)
1153	f3db = 40000;	1115	f3db = 40000;
1154		1116
1155	/* set low-pass filter baseband */	1117	/* set low-pass filter baseband */
1156	value = ds3000_tuner_readreg(state, 0x26);	1118	value = ds3000_tuner_readreg(state, 0x26);
1157	mlpf = 0x2e * 207 / ((value << 1) + 151);	1119	mlpf = 0x2e * 207 / ((value << 1) + 151);
1158	mlpf_max = mlpf * 135 / 100;	1120	mlpf_max = mlpf * 135 / 100;
1159	mlpf_min = mlpf * 78 / 100;	1121	mlpf_min = mlpf * 78 / 100;
1160	if (mlpf_max > 63)	1122	if (mlpf_max > 63)
1161	mlpf_max = 63;	1123	mlpf_max = 63;
1162		1124
1163	/* rounded to the closest integer */	1125	/* rounded to the closest integer */
1164	nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))	1126	nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
1165	/ (2766 * DS3000_XTAL_FREQ);	1127	/ (2766 * DS3000_XTAL_FREQ);
1166	if (nlpf > 23)	1128	if (nlpf > 23)
1167	nlpf = 23;	1129	nlpf = 23;
1168	if (nlpf < 1)	1130	if (nlpf < 1)
1169	nlpf = 1;	1131	nlpf = 1;
1170		1132
1171	/* rounded to the closest integer */	1133	/* rounded to the closest integer */
		1134	mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
		1135	(1000 * f3db / 2)) / (1000 * f3db);
		1136
		1137	if (mlpf_new < mlpf_min) {
		1138	nlpf++;
1172	mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +	1139	mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
1173	(1000 * f3db / 2)) / (1000 * f3db);	1140	(1000 * f3db / 2)) / (1000 * f3db);
		1141	}
1174		1142
1175	if (mlpf_new < mlpf_min) {	1143	if (mlpf_new > mlpf_max)
1176	nlpf++;	1144	mlpf_new = mlpf_max;
1177	mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +	1145
1178	(1000 * f3db / 2)) / (1000 * f3db);	1146	ds3000_tuner_writereg(state, 0x04, mlpf_new);
1179	}	1147	ds3000_tuner_writereg(state, 0x06, nlpf);
		1148	ds3000_tuner_writereg(state, 0x51, 0x1b);
		1149	ds3000_tuner_writereg(state, 0x51, 0x1f);
		1150	ds3000_tuner_writereg(state, 0x50, 0x04);
		1151	ds3000_tuner_writereg(state, 0x50, 0x00);
		1152	msleep(5);
		1153
		1154	/* unknown */
		1155	ds3000_tuner_writereg(state, 0x51, 0x1e);
		1156	ds3000_tuner_writereg(state, 0x51, 0x1f);
		1157	ds3000_tuner_writereg(state, 0x50, 0x01);
		1158	ds3000_tuner_writereg(state, 0x50, 0x00);
		1159	msleep(60);
		1160
		1161	/* ds3000 global reset */
		1162	ds3000_writereg(state, 0x07, 0x80);
		1163	ds3000_writereg(state, 0x07, 0x00);
		1164	/* ds3000 build-in uC reset */
		1165	ds3000_writereg(state, 0xb2, 0x01);
		1166	/* ds3000 software reset */
		1167	ds3000_writereg(state, 0x00, 0x01);
1180		1168
1181	if (mlpf_new > mlpf_max)	1169	switch (c->delivery_system) {
1182	mlpf_new = mlpf_max;	1170	case SYS_DVBS:
1183		1171	/* initialise the demod in DVB-S mode */
1184	ds3000_tuner_writereg(state, 0x04, mlpf_new);	1172	for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
1185	ds3000_tuner_writereg(state, 0x06, nlpf);	1173	ds3000_writereg(state,
1186	ds3000_tuner_writereg(state, 0x51, 0x1b);	1174	ds3000_dvbs_init_tab[i],
1187	ds3000_tuner_writereg(state, 0x51, 0x1f);	1175	ds3000_dvbs_init_tab[i + 1]);
1188	ds3000_tuner_writereg(state, 0x50, 0x04);	1176	value = ds3000_readreg(state, 0xfe);
1189	ds3000_tuner_writereg(state, 0x50, 0x00);	1177	value &= 0xc0;
1190	msleep(5);	1178	value \|= 0x1b;
1191		1179	ds3000_writereg(state, 0xfe, value);
1192	/* unknown */	1180	break;
1193	ds3000_tuner_writereg(state, 0x51, 0x1e);	1181	case SYS_DVBS2:
1194	ds3000_tuner_writereg(state, 0x51, 0x1f);	1182	/* initialise the demod in DVB-S2 mode */
1195	ds3000_tuner_writereg(state, 0x50, 0x01);	1183	for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
1196	ds3000_tuner_writereg(state, 0x50, 0x00);	1184	ds3000_writereg(state,
1197	msleep(60);	1185	ds3000_dvbs2_init_tab[i],
1198		1186	ds3000_dvbs2_init_tab[i + 1]);
1199	/* ds3000 global reset */	1187	ds3000_writereg(state, 0xfe, 0x98);
1200	ds3000_writereg(state, 0x07, 0x80);	1188	break;
1201	ds3000_writereg(state, 0x07, 0x00);	1189	default:
1202	/* ds3000 build-in uC reset */	1190	return 1;
1203	ds3000_writereg(state, 0xb2, 0x01);	1191	}
1204	/* ds3000 software reset */	1192
1205	ds3000_writereg(state, 0x00, 0x01);	1193	/* enable 27MHz clock output */
		1194	ds3000_writereg(state, 0x29, 0x80);
		1195	/* enable ac coupling */
		1196	ds3000_writereg(state, 0x25, 0x8a);
		1197
		1198	/* enhance symbol rate performance */
		1199	if ((state->dcur.symbol_rate / 1000) <= 5000) {
		1200	value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
		1201	if (value % 2 != 0)
		1202	value++;
		1203	ds3000_writereg(state, 0xc3, 0x0d);
		1204	ds3000_writereg(state, 0xc8, value);
		1205	ds3000_writereg(state, 0xc4, 0x10);
		1206	ds3000_writereg(state, 0xc7, 0x0e);
		1207	} else if ((state->dcur.symbol_rate / 1000) <= 10000) {
		1208	value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
		1209	if (value % 2 != 0)
		1210	value++;
		1211	ds3000_writereg(state, 0xc3, 0x07);
		1212	ds3000_writereg(state, 0xc8, value);
		1213	ds3000_writereg(state, 0xc4, 0x09);
		1214	ds3000_writereg(state, 0xc7, 0x12);
		1215	} else if ((state->dcur.symbol_rate / 1000) <= 20000) {
		1216	value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
		1217	ds3000_writereg(state, 0xc3, value);
		1218	ds3000_writereg(state, 0xc8, 0x0e);
		1219	ds3000_writereg(state, 0xc4, 0x07);
		1220	ds3000_writereg(state, 0xc7, 0x18);
		1221	} else {
		1222	value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
		1223	ds3000_writereg(state, 0xc3, value);
		1224	ds3000_writereg(state, 0xc8, 0x0a);
		1225	ds3000_writereg(state, 0xc4, 0x05);
		1226	ds3000_writereg(state, 0xc7, 0x24);
		1227	}
		1228
		1229	/* normalized symbol rate rounded to the closest integer */
		1230	value = (((state->dcur.symbol_rate / 1000) << 16) +
		1231	(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
		1232	ds3000_writereg(state, 0x61, value & 0x00ff);
		1233	ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
		1234
		1235	/* co-channel interference cancellation disabled */
		1236	ds3000_writereg(state, 0x56, 0x00);
		1237
		1238	/* equalizer disabled */
		1239	ds3000_writereg(state, 0x76, 0x00);
1206		1240
		1241	/*ds3000_writereg(state, 0x08, 0x03);
		1242	ds3000_writereg(state, 0xfd, 0x22);
		1243	ds3000_writereg(state, 0x08, 0x07);
		1244	ds3000_writereg(state, 0xfd, 0x42);
		1245	ds3000_writereg(state, 0x08, 0x07);*/
		1246
		1247	if (state->config->ci_mode) {
1207	switch (c->delivery_system) {	1248	switch (c->delivery_system) {
1208	case SYS_DVBS:	1249	case SYS_DVBS:
1209	/* initialise the demod in DVB-S mode */	1250	default:
1210	for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)	1251	ds3000_writereg(state, 0xfd, 0x80);
1211	ds3000_writereg(state,	1252	break;
1212	ds3000_dvbs_init_tab[i],
1213	ds3000_dvbs_init_tab[i + 1]);
1214	value = ds3000_readreg(state, 0xfe);
1215	value &= 0xc0;
1216	value \|= 0x1b;
1217	ds3000_writereg(state, 0xfe, value);
1218	break;
1219	case SYS_DVBS2:	1253	case SYS_DVBS2:
1220	/* initialise the demod in DVB-S2 mode */	1254	ds3000_writereg(state, 0xfd, 0x01);
1221	for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
1222	ds3000_writereg(state,
1223	ds3000_dvbs2_init_tab[i],
1224	ds3000_dvbs2_init_tab[i + 1]);
1225	ds3000_writereg(state, 0xfe, 0x98);
1226	break;	1255	break;
1227	default:
1228	return 1;
1229	}
1230
1231	/* enable 27MHz clock output */
1232	ds3000_writereg(state, 0x29, 0x80);
1233	/* enable ac coupling */
1234	ds3000_writereg(state, 0x25, 0x8a);
1235
1236	/* enhance symbol rate performance */
1237	if ((state->dcur.symbol_rate / 1000) <= 5000) {
1238	value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
1239	if (value % 2 != 0)
1240	value++;
1241	ds3000_writereg(state, 0xc3, 0x0d);
1242	ds3000_writereg(state, 0xc8, value);
1243	ds3000_writereg(state, 0xc4, 0x10);
1244	ds3000_writereg(state, 0xc7, 0x0e);
1245	} else if ((state->dcur.symbol_rate / 1000) <= 10000) {
1246	value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
1247	if (value % 2 != 0)
1248	value++;
1249	ds3000_writereg(state, 0xc3, 0x07);
1250	ds3000_writereg(state, 0xc8, value);
1251	ds3000_writereg(state, 0xc4, 0x09);
1252	ds3000_writereg(state, 0xc7, 0x12);
1253	} else if ((state->dcur.symbol_rate / 1000) <= 20000) {
1254	value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
1255	ds3000_writereg(state, 0xc3, value);
1256	ds3000_writereg(state, 0xc8, 0x0e);
1257	ds3000_writereg(state, 0xc4, 0x07);
1258	ds3000_writereg(state, 0xc7, 0x18);
1259	} else {
1260	value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
1261	ds3000_writereg(state, 0xc3, value);
1262	ds3000_writereg(state, 0xc8, 0x0a);
1263	ds3000_writereg(state, 0xc4, 0x05);
1264	ds3000_writereg(state, 0xc7, 0x24);
1265	}	1256	}
		1257	}
1266		1258
1267	/* normalized symbol rate rounded to the closest integer */	1259	/* ds3000 out of software reset */
1268	value = (((state->dcur.symbol_rate / 1000) << 16) +	1260	ds3000_writereg(state, 0x00, 0x00);
1269	(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;	1261	/* start ds3000 build-in uC */
1270	ds3000_writereg(state, 0x61, value & 0x00ff);	1262	ds3000_writereg(state, 0xb2, 0x00);
1271	ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
1272
1273	/* co-channel interference cancellation disabled */
1274	ds3000_writereg(state, 0x56, 0x00);
1275
1276	/* equalizer disabled */
1277	ds3000_writereg(state, 0x76, 0x00);
1278
1279	/*ds3000_writereg(state, 0x08, 0x03);
1280	ds3000_writereg(state, 0xfd, 0x22);
1281	ds3000_writereg(state, 0x08, 0x07);
1282	ds3000_writereg(state, 0xfd, 0x42);
1283	ds3000_writereg(state, 0x08, 0x07);*/
1284
1285	if (state->config->ci_mode) {
1286	switch (c->delivery_system) {
1287	case SYS_DVBS:
1288	default:
1289	ds3000_writereg(state, 0xfd, 0x80);
1290	break;
1291	case SYS_DVBS2:
1292	ds3000_writereg(state, 0xfd, 0x01);
1293	break;
1294	}
1295	}
1296		1263
1297	/* ds3000 out of software reset */	1264	/* TODO: calculate and set carrier offset */
1298	ds3000_writereg(state, 0x00, 0x00);
1299	/* start ds3000 build-in uC */
1300	ds3000_writereg(state, 0xb2, 0x00);
1301
1302	/* TODO: calculate and set carrier offset */
1303
1304	/* wait before retrying */
1305	for (i = 0; i < 30 ; i++) {
1306	if (ds3000_is_tuned(fe)) {
1307	dprintk("%s: Tuned\n", __func__);
1308	ds3000_dump_registers(fe);
1309	goto tuned;
1310	}
1311	msleep(1);
1312	}
1313		1265
1314	dprintk("%s: Not tuned\n", __func__);	1266	for (i = 0; i < 30 ; i++) {
1315	ds3000_dump_registers(fe);	1267	ds3000_read_status(fe, &status);
		1268	if (status && FE_HAS_LOCK)
		1269	break;
1316		1270
1317	} while (--retune);	1271	msleep(10);
		1272	}
1318		1273
1319	tuned:	1274	return 0;
1320	return ret;
1321	}	1275	}
1322		1276
1323	static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)	1277	static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)