diff options
author | Will Deacon <will.deacon@arm.com> | 2011-09-29 13:23:39 -0400 |
---|---|---|
committer | Will Deacon <will.deacon@arm.com> | 2011-12-02 10:16:16 -0500 |
commit | 0445e7a58e794d82c3a76975b1eefd920addbf39 (patch) | |
tree | 0db845f2e96962dbcf0379ff7ab41878c29bdd84 | |
parent | 4d301512ab368f83f774f414213a5e6cf3641632 (diff) |
ARM: perf: add support for stalled cycle ABI events
Commit 8f622422 ("perf events: Add generic front-end and back-end
stalled cycle event definitions") added two new ABI events for counting
stalled cycles.
This patch adds support for these new events to the ARM perf
implementation.
Cc: Jamie Iles <jamie@jamieiles.com>
Cc: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r-- | arch/arm/kernel/perf_event_v6.c | 32 | ||||
-rw-r--r-- | arch/arm/kernel/perf_event_v7.c | 67 | ||||
-rw-r--r-- | arch/arm/kernel/perf_event_xscale.c | 16 |
3 files changed, 66 insertions, 49 deletions
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c index e63d8115c01b..533be9930ec2 100644 --- a/arch/arm/kernel/perf_event_v6.c +++ b/arch/arm/kernel/perf_event_v6.c | |||
@@ -65,13 +65,15 @@ enum armv6_counters { | |||
65 | * accesses/misses in hardware. | 65 | * accesses/misses in hardware. |
66 | */ | 66 | */ |
67 | static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = { | 67 | static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = { |
68 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES, | 68 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES, |
69 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC, | 69 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC, |
70 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | 70 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, |
71 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | 71 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, |
72 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC, | 72 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC, |
73 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT, | 73 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT, |
74 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | 74 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, |
75 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL, | ||
76 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL, | ||
75 | }; | 77 | }; |
76 | 78 | ||
77 | static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | 79 | static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
@@ -218,13 +220,15 @@ enum armv6mpcore_perf_types { | |||
218 | * accesses/misses in hardware. | 220 | * accesses/misses in hardware. |
219 | */ | 221 | */ |
220 | static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = { | 222 | static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = { |
221 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES, | 223 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES, |
222 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC, | 224 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC, |
223 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | 225 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, |
224 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | 226 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, |
225 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC, | 227 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC, |
226 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT, | 228 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT, |
227 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | 229 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, |
230 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL, | ||
231 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL, | ||
228 | }; | 232 | }; |
229 | 233 | ||
230 | static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | 234 | static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c index d2361e7dd884..460bbbb6b885 100644 --- a/arch/arm/kernel/perf_event_v7.c +++ b/arch/arm/kernel/perf_event_v7.c | |||
@@ -77,11 +77,14 @@ enum armv7_a8_perf_types { | |||
77 | ARMV7_A8_PERFCTR_L2_CACHE_ACCESS = 0x43, | 77 | ARMV7_A8_PERFCTR_L2_CACHE_ACCESS = 0x43, |
78 | ARMV7_A8_PERFCTR_L2_CACHE_REFILL = 0x44, | 78 | ARMV7_A8_PERFCTR_L2_CACHE_REFILL = 0x44, |
79 | ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS = 0x50, | 79 | ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS = 0x50, |
80 | ARMV7_A8_PERFCTR_STALL_ISIDE = 0x56, | ||
80 | }; | 81 | }; |
81 | 82 | ||
82 | /* ARMv7 Cortex-A9 specific event types */ | 83 | /* ARMv7 Cortex-A9 specific event types */ |
83 | enum armv7_a9_perf_types { | 84 | enum armv7_a9_perf_types { |
84 | ARMV7_A9_PERFCTR_INSTR_CORE_RENAME = 0x68, | 85 | ARMV7_A9_PERFCTR_INSTR_CORE_RENAME = 0x68, |
86 | ARMV7_A9_PERFCTR_STALL_ICACHE = 0x60, | ||
87 | ARMV7_A9_PERFCTR_STALL_DISPATCH = 0x66, | ||
85 | }; | 88 | }; |
86 | 89 | ||
87 | /* ARMv7 Cortex-A5 specific event types */ | 90 | /* ARMv7 Cortex-A5 specific event types */ |
@@ -116,13 +119,15 @@ enum armv7_a15_perf_types { | |||
116 | * accesses/misses in hardware. | 119 | * accesses/misses in hardware. |
117 | */ | 120 | */ |
118 | static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { | 121 | static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { |
119 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | 122 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
120 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, | 123 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
121 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, | 124 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
122 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, | 125 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
123 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | 126 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
124 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | 127 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
125 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | 128 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, |
129 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE, | ||
130 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED, | ||
126 | }; | 131 | }; |
127 | 132 | ||
128 | static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | 133 | static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
@@ -238,13 +243,15 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | |||
238 | * Cortex-A9 HW events mapping | 243 | * Cortex-A9 HW events mapping |
239 | */ | 244 | */ |
240 | static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { | 245 | static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { |
241 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | 246 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
242 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME, | 247 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME, |
243 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, | 248 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
244 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, | 249 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
245 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | 250 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
246 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | 251 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
247 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | 252 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, |
253 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE, | ||
254 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH, | ||
248 | }; | 255 | }; |
249 | 256 | ||
250 | static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | 257 | static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
@@ -360,13 +367,15 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | |||
360 | * Cortex-A5 HW events mapping | 367 | * Cortex-A5 HW events mapping |
361 | */ | 368 | */ |
362 | static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { | 369 | static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { |
363 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | 370 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
364 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, | 371 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
365 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, | 372 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
366 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, | 373 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
367 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, | 374 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
368 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | 375 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
369 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | 376 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, |
377 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED, | ||
378 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED, | ||
370 | }; | 379 | }; |
371 | 380 | ||
372 | static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | 381 | static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
@@ -466,13 +475,15 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | |||
466 | * Cortex-A15 HW events mapping | 475 | * Cortex-A15 HW events mapping |
467 | */ | 476 | */ |
468 | static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { | 477 | static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { |
469 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, | 478 | [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
470 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, | 479 | [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, |
471 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, | 480 | [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, |
472 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, | 481 | [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, |
473 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC, | 482 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC, |
474 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, | 483 | [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
475 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, | 484 | [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, |
485 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED, | ||
486 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED, | ||
476 | }; | 487 | }; |
477 | 488 | ||
478 | static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | 489 | static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c index e0cca10a8411..3b99d8269829 100644 --- a/arch/arm/kernel/perf_event_xscale.c +++ b/arch/arm/kernel/perf_event_xscale.c | |||
@@ -48,13 +48,15 @@ enum xscale_counters { | |||
48 | }; | 48 | }; |
49 | 49 | ||
50 | static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = { | 50 | static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = { |
51 | [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT, | 51 | [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT, |
52 | [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION, | 52 | [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION, |
53 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, | 53 | [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, |
54 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, | 54 | [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, |
55 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH, | 55 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH, |
56 | [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS, | 56 | [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS, |
57 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, | 57 | [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, |
58 | [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER, | ||
59 | [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED, | ||
58 | }; | 60 | }; |
59 | 61 | ||
60 | static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] | 62 | static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] |