diff options
| author | Ingo Molnar <mingo@elte.hu> | 2009-03-18 01:58:45 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-03-18 01:58:45 -0400 |
| commit | 03418c7efaa429dc7647ac93e3862e3fe1816873 (patch) | |
| tree | d5a101034139f846b700dfdf53eb6737ea6c4365 | |
| parent | 4176935b58eeb636917e65a2c388e4607e36cce6 (diff) | |
| parent | ee568b25ee9e160b32d1aef73d8b2ee9c05d34db (diff) | |
Merge branches 'tracing/ftrace' and 'linus' into tracing/core
51 files changed, 14388 insertions, 3622 deletions
diff --git a/Documentation/logo.gif b/Documentation/logo.gif deleted file mode 100644 index 2eae75fecfb9..000000000000 --- a/Documentation/logo.gif +++ /dev/null | |||
| Binary files differ | |||
diff --git a/Documentation/logo.svg b/Documentation/logo.svg new file mode 100644 index 000000000000..cb9e4851d8c3 --- /dev/null +++ b/Documentation/logo.svg | |||
| @@ -0,0 +1,2911 @@ | |||
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diff --git a/Documentation/logo.txt b/Documentation/logo.txt index 296f0f7f67eb..a2e62445e28e 100644 --- a/Documentation/logo.txt +++ b/Documentation/logo.txt | |||
| @@ -1,13 +1,4 @@ | |||
| 1 | This is the full-colour version of the currently unofficial Linux logo | 1 | Tux is taking a three month sabbatical to work as a barber, so Tuz is |
| 2 | ("currently unofficial" just means that there has been no paperwork and | 2 | standing in. He's taken pains to ensure you'll hardly notice. |
| 3 | that I have not really announced it yet). It was created by Larry Ewing, | ||
| 4 | and is freely usable as long as you acknowledge Larry as the original | ||
| 5 | artist. | ||
| 6 | |||
| 7 | Note that there are black-and-white versions of this available that | ||
| 8 | scale down to smaller sizes and are better for letterheads or whatever | ||
| 9 | you want to use it for: for the full range of logos take a look at | ||
| 10 | Larry's web-page: | ||
| 11 | |||
| 12 | http://www.isc.tamu.edu/~lewing/linux/ | ||
| 13 | 3 | ||
| 4 | Image by Andrew McGown and Josh Bush. Image is licensed CC BY-SA. | ||
diff --git a/MAINTAINERS b/MAINTAINERS index a17f0b161e03..dd3c11c4c3d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -3882,6 +3882,15 @@ L: linux-ide@vger.kernel.org | |||
| 3882 | T: git kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev.git | 3882 | T: git kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev.git |
| 3883 | S: Supported | 3883 | S: Supported |
| 3884 | 3884 | ||
| 3885 | SERVER ENGINES 10Gbps NIC - BladeEngine 2 DRIVER | ||
| 3886 | P: Sathya Perla | ||
| 3887 | M: sathyap@serverengines.com | ||
| 3888 | P: Subbu Seetharaman | ||
| 3889 | M: subbus@serverengines.com | ||
| 3890 | L: netdev@vger.kernel.org | ||
| 3891 | W: http://www.serverengines.com | ||
| 3892 | S: Supported | ||
| 3893 | |||
| 3885 | SFC NETWORK DRIVER | 3894 | SFC NETWORK DRIVER |
| 3886 | P: Steve Hodgson | 3895 | P: Steve Hodgson |
| 3887 | P: Ben Hutchings | 3896 | P: Ben Hutchings |
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c index e948b28a5a9a..4558dd3918cf 100644 --- a/arch/x86/kernel/kprobes.c +++ b/arch/x86/kernel/kprobes.c | |||
| @@ -193,6 +193,9 @@ static int __kprobes can_boost(kprobe_opcode_t *opcodes) | |||
| 193 | kprobe_opcode_t opcode; | 193 | kprobe_opcode_t opcode; |
| 194 | kprobe_opcode_t *orig_opcodes = opcodes; | 194 | kprobe_opcode_t *orig_opcodes = opcodes; |
| 195 | 195 | ||
| 196 | if (search_exception_tables(opcodes)) | ||
| 197 | return 0; /* Page fault may occur on this address. */ | ||
| 198 | |||
| 196 | retry: | 199 | retry: |
| 197 | if (opcodes - orig_opcodes > MAX_INSN_SIZE - 1) | 200 | if (opcodes - orig_opcodes > MAX_INSN_SIZE - 1) |
| 198 | return 0; | 201 | return 0; |
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 83d53ce5d4c4..462b9ba67e92 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c | |||
| @@ -273,30 +273,43 @@ static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) | |||
| 273 | * use the TSC value at the transitions to calculate a pretty | 273 | * use the TSC value at the transitions to calculate a pretty |
| 274 | * good value for the TSC frequencty. | 274 | * good value for the TSC frequencty. |
| 275 | */ | 275 | */ |
| 276 | static inline int pit_expect_msb(unsigned char val) | 276 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
| 277 | { | 277 | { |
| 278 | int count = 0; | 278 | int count; |
| 279 | u64 tsc = 0; | ||
| 279 | 280 | ||
| 280 | for (count = 0; count < 50000; count++) { | 281 | for (count = 0; count < 50000; count++) { |
| 281 | /* Ignore LSB */ | 282 | /* Ignore LSB */ |
| 282 | inb(0x42); | 283 | inb(0x42); |
| 283 | if (inb(0x42) != val) | 284 | if (inb(0x42) != val) |
| 284 | break; | 285 | break; |
| 286 | tsc = get_cycles(); | ||
| 285 | } | 287 | } |
| 286 | return count > 50; | 288 | *deltap = get_cycles() - tsc; |
| 289 | *tscp = tsc; | ||
| 290 | |||
| 291 | /* | ||
| 292 | * We require _some_ success, but the quality control | ||
| 293 | * will be based on the error terms on the TSC values. | ||
| 294 | */ | ||
| 295 | return count > 5; | ||
| 287 | } | 296 | } |
| 288 | 297 | ||
| 289 | /* | 298 | /* |
| 290 | * How many MSB values do we want to see? We aim for a | 299 | * How many MSB values do we want to see? We aim for |
| 291 | * 15ms calibration, which assuming a 2us counter read | 300 | * a maximum error rate of 500ppm (in practice the |
| 292 | * error should give us roughly 150 ppm precision for | 301 | * real error is much smaller), but refuse to spend |
| 293 | * the calibration. | 302 | * more than 25ms on it. |
| 294 | */ | 303 | */ |
| 295 | #define QUICK_PIT_MS 15 | 304 | #define MAX_QUICK_PIT_MS 25 |
| 296 | #define QUICK_PIT_ITERATIONS (QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) | 305 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
| 297 | 306 | ||
| 298 | static unsigned long quick_pit_calibrate(void) | 307 | static unsigned long quick_pit_calibrate(void) |
| 299 | { | 308 | { |
| 309 | int i; | ||
| 310 | u64 tsc, delta; | ||
| 311 | unsigned long d1, d2; | ||
| 312 | |||
| 300 | /* Set the Gate high, disable speaker */ | 313 | /* Set the Gate high, disable speaker */ |
| 301 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | 314 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
| 302 | 315 | ||
| @@ -315,45 +328,52 @@ static unsigned long quick_pit_calibrate(void) | |||
| 315 | outb(0xff, 0x42); | 328 | outb(0xff, 0x42); |
| 316 | outb(0xff, 0x42); | 329 | outb(0xff, 0x42); |
| 317 | 330 | ||
| 318 | if (pit_expect_msb(0xff)) { | 331 | /* |
| 319 | int i; | 332 | * The PIT starts counting at the next edge, so we |
| 320 | u64 t1, t2, delta; | 333 | * need to delay for a microsecond. The easiest way |
| 321 | unsigned char expect = 0xfe; | 334 | * to do that is to just read back the 16-bit counter |
| 322 | 335 | * once from the PIT. | |
| 323 | t1 = get_cycles(); | 336 | */ |
| 324 | for (i = 0; i < QUICK_PIT_ITERATIONS; i++, expect--) { | 337 | inb(0x42); |
| 325 | if (!pit_expect_msb(expect)) | 338 | inb(0x42); |
| 326 | goto failed; | 339 | |
| 340 | if (pit_expect_msb(0xff, &tsc, &d1)) { | ||
| 341 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | ||
| 342 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | ||
| 343 | break; | ||
| 344 | |||
| 345 | /* | ||
| 346 | * Iterate until the error is less than 500 ppm | ||
| 347 | */ | ||
| 348 | delta -= tsc; | ||
| 349 | if (d1+d2 < delta >> 11) | ||
| 350 | goto success; | ||
| 327 | } | 351 | } |
| 328 | t2 = get_cycles(); | ||
| 329 | |||
| 330 | /* | ||
| 331 | * Make sure we can rely on the second TSC timestamp: | ||
| 332 | */ | ||
| 333 | if (!pit_expect_msb(expect)) | ||
| 334 | goto failed; | ||
| 335 | |||
| 336 | /* | ||
| 337 | * Ok, if we get here, then we've seen the | ||
| 338 | * MSB of the PIT decrement QUICK_PIT_ITERATIONS | ||
| 339 | * times, and each MSB had many hits, so we never | ||
| 340 | * had any sudden jumps. | ||
| 341 | * | ||
| 342 | * As a result, we can depend on there not being | ||
| 343 | * any odd delays anywhere, and the TSC reads are | ||
| 344 | * reliable. | ||
| 345 | * | ||
| 346 | * kHz = ticks / time-in-seconds / 1000; | ||
| 347 | * kHz = (t2 - t1) / (QPI * 256 / PIT_TICK_RATE) / 1000 | ||
| 348 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (QPI * 256 * 1000) | ||
| 349 | */ | ||
| 350 | delta = (t2 - t1)*PIT_TICK_RATE; | ||
| 351 | do_div(delta, QUICK_PIT_ITERATIONS*256*1000); | ||
| 352 | printk("Fast TSC calibration using PIT\n"); | ||
| 353 | return delta; | ||
| 354 | } | 352 | } |
| 355 | failed: | 353 | printk("Fast TSC calibration failed\n"); |
| 356 | return 0; | 354 | return 0; |
| 355 | |||
| 356 | success: | ||
| 357 | /* | ||
| 358 | * Ok, if we get here, then we've seen the | ||
| 359 | * MSB of the PIT decrement 'i' times, and the | ||
| 360 | * error has shrunk to less than 500 ppm. | ||
| 361 | * | ||
| 362 | * As a result, we can depend on there not being | ||
| 363 | * any odd delays anywhere, and the TSC reads are | ||
| 364 | * reliable (within the error). We also adjust the | ||
| 365 | * delta to the middle of the error bars, just | ||
| 366 | * because it looks nicer. | ||
| 367 | * | ||
| 368 | * kHz = ticks / time-in-seconds / 1000; | ||
| 369 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | ||
| 370 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | ||
| 371 | */ | ||
| 372 | delta += (long)(d2 - d1)/2; | ||
| 373 | delta *= PIT_TICK_RATE; | ||
| 374 | do_div(delta, i*256*1000); | ||
| 375 | printk("Fast TSC calibration using PIT\n"); | ||
| 376 | return delta; | ||
| 357 | } | 377 | } |
| 358 | 378 | ||
| 359 | /** | 379 | /** |
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 765fd1c56cd6..bee64b73c919 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c | |||
| @@ -758,8 +758,7 @@ static int __init acpi_bus_init(void) | |||
| 758 | acpi_status status = AE_OK; | 758 | acpi_status status = AE_OK; |
| 759 | extern acpi_status acpi_os_initialize1(void); | 759 | extern acpi_status acpi_os_initialize1(void); |
| 760 | 760 | ||
| 761 | 761 | acpi_os_initialize1(); | |
| 762 | status = acpi_os_initialize1(); | ||
| 763 | 762 | ||
| 764 | status = | 763 | status = |
| 765 | acpi_enable_subsystem(ACPI_NO_HARDWARE_INIT | ACPI_NO_ACPI_ENABLE); | 764 | acpi_enable_subsystem(ACPI_NO_HARDWARE_INIT | ACPI_NO_ACPI_ENABLE); |
| @@ -769,12 +768,6 @@ static int __init acpi_bus_init(void) | |||
| 769 | goto error1; | 768 | goto error1; |
| 770 | } | 769 | } |
| 771 | 770 | ||
| 772 | if (ACPI_FAILURE(status)) { | ||
| 773 | printk(KERN_ERR PREFIX | ||
| 774 | "Unable to initialize ACPI OS objects\n"); | ||
| 775 | goto error1; | ||
| 776 | } | ||
| 777 | |||
| 778 | /* | 771 | /* |
| 779 | * ACPI 2.0 requires the EC driver to be loaded and work before | 772 | * ACPI 2.0 requires the EC driver to be loaded and work before |
| 780 | * the EC device is found in the namespace (i.e. before acpi_initialize_objects() | 773 | * the EC device is found in the namespace (i.e. before acpi_initialize_objects() |
diff --git a/drivers/acpi/numa.c b/drivers/acpi/numa.c index c5e292aab0e3..3a0d8ef25c75 100644 --- a/drivers/acpi/numa.c +++ b/drivers/acpi/numa.c | |||
| @@ -277,7 +277,7 @@ int acpi_get_node(acpi_handle *handle) | |||
| 277 | int pxm, node = -1; | 277 | int pxm, node = -1; |
| 278 | 278 | ||
| 279 | pxm = acpi_get_pxm(handle); | 279 | pxm = acpi_get_pxm(handle); |
| 280 | if (pxm >= 0) | 280 | if (pxm >= 0 && pxm < MAX_PXM_DOMAINS) |
| 281 | node = acpi_map_pxm_to_node(pxm); | 281 | node = acpi_map_pxm_to_node(pxm); |
| 282 | 282 | ||
| 283 | return node; | 283 | return node; |
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 2b6c59028254..eb8980d67368 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c | |||
| @@ -1324,54 +1324,6 @@ acpi_os_validate_interface (char *interface) | |||
| 1324 | return AE_SUPPORT; | 1324 | return AE_SUPPORT; |
| 1325 | } | 1325 | } |
| 1326 | 1326 | ||
| 1327 | #ifdef CONFIG_X86 | ||
| 1328 | |||
| 1329 | struct aml_port_desc { | ||
| 1330 | uint start; | ||
| 1331 | uint end; | ||
| 1332 | char* name; | ||
| 1333 | char warned; | ||
| 1334 | }; | ||
| 1335 | |||
| 1336 | static struct aml_port_desc aml_invalid_port_list[] = { | ||
| 1337 | {0x20, 0x21, "PIC0", 0}, | ||
| 1338 | {0xA0, 0xA1, "PIC1", 0}, | ||
| 1339 | {0x4D0, 0x4D1, "ELCR", 0} | ||
| 1340 | }; | ||
| 1341 | |||
| 1342 | /* | ||
| 1343 | * valid_aml_io_address() | ||
| 1344 | * | ||
| 1345 | * if valid, return true | ||
| 1346 | * else invalid, warn once, return false | ||
| 1347 | */ | ||
| 1348 | static bool valid_aml_io_address(uint address, uint length) | ||
| 1349 | { | ||
| 1350 | int i; | ||
| 1351 | int entries = sizeof(aml_invalid_port_list) / sizeof(struct aml_port_desc); | ||
| 1352 | |||
| 1353 | for (i = 0; i < entries; ++i) { | ||
| 1354 | if ((address >= aml_invalid_port_list[i].start && | ||
| 1355 | address <= aml_invalid_port_list[i].end) || | ||
| 1356 | (address + length >= aml_invalid_port_list[i].start && | ||
| 1357 | address + length <= aml_invalid_port_list[i].end)) | ||
| 1358 | { | ||
| 1359 | if (!aml_invalid_port_list[i].warned) | ||
| 1360 | { | ||
| 1361 | printk(KERN_ERR "ACPI: Denied BIOS AML access" | ||
| 1362 | " to invalid port 0x%x+0x%x (%s)\n", | ||
| 1363 | address, length, | ||
| 1364 | aml_invalid_port_list[i].name); | ||
| 1365 | aml_invalid_port_list[i].warned = 1; | ||
| 1366 | } | ||
| 1367 | return false; /* invalid */ | ||
| 1368 | } | ||
| 1369 | } | ||
| 1370 | return true; /* valid */ | ||
| 1371 | } | ||
| 1372 | #else | ||
| 1373 | static inline bool valid_aml_io_address(uint address, uint length) { return true; } | ||
| 1374 | #endif | ||
| 1375 | /****************************************************************************** | 1327 | /****************************************************************************** |
| 1376 | * | 1328 | * |
| 1377 | * FUNCTION: acpi_os_validate_address | 1329 | * FUNCTION: acpi_os_validate_address |
| @@ -1401,8 +1353,6 @@ acpi_os_validate_address ( | |||
| 1401 | 1353 | ||
| 1402 | switch (space_id) { | 1354 | switch (space_id) { |
| 1403 | case ACPI_ADR_SPACE_SYSTEM_IO: | 1355 | case ACPI_ADR_SPACE_SYSTEM_IO: |
| 1404 | if (!valid_aml_io_address(address, length)) | ||
| 1405 | return AE_AML_ILLEGAL_ADDRESS; | ||
| 1406 | case ACPI_ADR_SPACE_SYSTEM_MEMORY: | 1356 | case ACPI_ADR_SPACE_SYSTEM_MEMORY: |
| 1407 | /* Only interference checks against SystemIO and SytemMemory | 1357 | /* Only interference checks against SystemIO and SytemMemory |
| 1408 | are needed */ | 1358 | are needed */ |
diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c index 519266654f06..00456fccfa38 100644 --- a/drivers/acpi/sleep.c +++ b/drivers/acpi/sleep.c | |||
| @@ -378,6 +378,22 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = { | |||
| 378 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), | 378 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
| 379 | }, | 379 | }, |
| 380 | }, | 380 | }, |
| 381 | { | ||
| 382 | .callback = init_old_suspend_ordering, | ||
| 383 | .ident = "Asus Pundit P1-AH2 (M2N8L motherboard)", | ||
| 384 | .matches = { | ||
| 385 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."), | ||
| 386 | DMI_MATCH(DMI_BOARD_NAME, "M2N8L"), | ||
| 387 | }, | ||
| 388 | }, | ||
| 389 | { | ||
| 390 | .callback = init_set_sci_en_on_resume, | ||
| 391 | .ident = "Toshiba Satellite L300", | ||
| 392 | .matches = { | ||
| 393 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
| 394 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite L300"), | ||
| 395 | }, | ||
| 396 | }, | ||
| 381 | {}, | 397 | {}, |
| 382 | }; | 398 | }; |
| 383 | #endif /* CONFIG_SUSPEND */ | 399 | #endif /* CONFIG_SUSPEND */ |
diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c index 35bda49796fb..bfefd079a955 100644 --- a/drivers/md/dm-crypt.c +++ b/drivers/md/dm-crypt.c | |||
| @@ -60,6 +60,7 @@ struct dm_crypt_io { | |||
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | struct dm_crypt_request { | 62 | struct dm_crypt_request { |
| 63 | struct convert_context *ctx; | ||
| 63 | struct scatterlist sg_in; | 64 | struct scatterlist sg_in; |
| 64 | struct scatterlist sg_out; | 65 | struct scatterlist sg_out; |
| 65 | }; | 66 | }; |
| @@ -335,6 +336,18 @@ static void crypt_convert_init(struct crypt_config *cc, | |||
| 335 | init_completion(&ctx->restart); | 336 | init_completion(&ctx->restart); |
| 336 | } | 337 | } |
| 337 | 338 | ||
| 339 | static struct dm_crypt_request *dmreq_of_req(struct crypt_config *cc, | ||
| 340 | struct ablkcipher_request *req) | ||
| 341 | { | ||
| 342 | return (struct dm_crypt_request *)((char *)req + cc->dmreq_start); | ||
| 343 | } | ||
| 344 | |||
| 345 | static struct ablkcipher_request *req_of_dmreq(struct crypt_config *cc, | ||
| 346 | struct dm_crypt_request *dmreq) | ||
| 347 | { | ||
| 348 | return (struct ablkcipher_request *)((char *)dmreq - cc->dmreq_start); | ||
| 349 | } | ||
| 350 | |||
| 338 | static int crypt_convert_block(struct crypt_config *cc, | 351 | static int crypt_convert_block(struct crypt_config *cc, |
| 339 | struct convert_context *ctx, | 352 | struct convert_context *ctx, |
| 340 | struct ablkcipher_request *req) | 353 | struct ablkcipher_request *req) |
| @@ -345,10 +358,11 @@ static int crypt_convert_block(struct crypt_config *cc, | |||
| 345 | u8 *iv; | 358 | u8 *iv; |
| 346 | int r = 0; | 359 | int r = 0; |
| 347 | 360 | ||
| 348 | dmreq = (struct dm_crypt_request *)((char *)req + cc->dmreq_start); | 361 | dmreq = dmreq_of_req(cc, req); |
| 349 | iv = (u8 *)ALIGN((unsigned long)(dmreq + 1), | 362 | iv = (u8 *)ALIGN((unsigned long)(dmreq + 1), |
| 350 | crypto_ablkcipher_alignmask(cc->tfm) + 1); | 363 | crypto_ablkcipher_alignmask(cc->tfm) + 1); |
| 351 | 364 | ||
| 365 | dmreq->ctx = ctx; | ||
| 352 | sg_init_table(&dmreq->sg_in, 1); | 366 | sg_init_table(&dmreq->sg_in, 1); |
| 353 | sg_set_page(&dmreq->sg_in, bv_in->bv_page, 1 << SECTOR_SHIFT, | 367 | sg_set_page(&dmreq->sg_in, bv_in->bv_page, 1 << SECTOR_SHIFT, |
| 354 | bv_in->bv_offset + ctx->offset_in); | 368 | bv_in->bv_offset + ctx->offset_in); |
| @@ -395,8 +409,9 @@ static void crypt_alloc_req(struct crypt_config *cc, | |||
| 395 | cc->req = mempool_alloc(cc->req_pool, GFP_NOIO); | 409 | cc->req = mempool_alloc(cc->req_pool, GFP_NOIO); |
| 396 | ablkcipher_request_set_tfm(cc->req, cc->tfm); | 410 | ablkcipher_request_set_tfm(cc->req, cc->tfm); |
| 397 | ablkcipher_request_set_callback(cc->req, CRYPTO_TFM_REQ_MAY_BACKLOG | | 411 | ablkcipher_request_set_callback(cc->req, CRYPTO_TFM_REQ_MAY_BACKLOG | |
| 398 | CRYPTO_TFM_REQ_MAY_SLEEP, | 412 | CRYPTO_TFM_REQ_MAY_SLEEP, |
| 399 | kcryptd_async_done, ctx); | 413 | kcryptd_async_done, |
| 414 | dmreq_of_req(cc, cc->req)); | ||
| 400 | } | 415 | } |
| 401 | 416 | ||
| 402 | /* | 417 | /* |
| @@ -553,19 +568,22 @@ static void crypt_inc_pending(struct dm_crypt_io *io) | |||
| 553 | static void crypt_dec_pending(struct dm_crypt_io *io) | 568 | static void crypt_dec_pending(struct dm_crypt_io *io) |
| 554 | { | 569 | { |
| 555 | struct crypt_config *cc = io->target->private; | 570 | struct crypt_config *cc = io->target->private; |
| 571 | struct bio *base_bio = io->base_bio; | ||
| 572 | struct dm_crypt_io *base_io = io->base_io; | ||
| 573 | int error = io->error; | ||
| 556 | 574 | ||
| 557 | if (!atomic_dec_and_test(&io->pending)) | 575 | if (!atomic_dec_and_test(&io->pending)) |
| 558 | return; | 576 | return; |
| 559 | 577 | ||
| 560 | if (likely(!io->base_io)) | 578 | mempool_free(io, cc->io_pool); |
| 561 | bio_endio(io->base_bio, io->error); | 579 | |
| 580 | if (likely(!base_io)) | ||
| 581 | bio_endio(base_bio, error); | ||
| 562 | else { | 582 | else { |
| 563 | if (io->error && !io->base_io->error) | 583 | if (error && !base_io->error) |
| 564 | io->base_io->error = io->error; | 584 | base_io->error = error; |
| 565 | crypt_dec_pending(io->base_io); | 585 | crypt_dec_pending(base_io); |
| 566 | } | 586 | } |
| 567 | |||
| 568 | mempool_free(io, cc->io_pool); | ||
| 569 | } | 587 | } |
| 570 | 588 | ||
| 571 | /* | 589 | /* |
| @@ -821,7 +839,8 @@ static void kcryptd_crypt_read_convert(struct dm_crypt_io *io) | |||
| 821 | static void kcryptd_async_done(struct crypto_async_request *async_req, | 839 | static void kcryptd_async_done(struct crypto_async_request *async_req, |
| 822 | int error) | 840 | int error) |
| 823 | { | 841 | { |
| 824 | struct convert_context *ctx = async_req->data; | 842 | struct dm_crypt_request *dmreq = async_req->data; |
| 843 | struct convert_context *ctx = dmreq->ctx; | ||
| 825 | struct dm_crypt_io *io = container_of(ctx, struct dm_crypt_io, ctx); | 844 | struct dm_crypt_io *io = container_of(ctx, struct dm_crypt_io, ctx); |
| 826 | struct crypt_config *cc = io->target->private; | 845 | struct crypt_config *cc = io->target->private; |
| 827 | 846 | ||
| @@ -830,7 +849,7 @@ static void kcryptd_async_done(struct crypto_async_request *async_req, | |||
| 830 | return; | 849 | return; |
| 831 | } | 850 | } |
| 832 | 851 | ||
| 833 | mempool_free(ablkcipher_request_cast(async_req), cc->req_pool); | 852 | mempool_free(req_of_dmreq(cc, dmreq), cc->req_pool); |
| 834 | 853 | ||
| 835 | if (!atomic_dec_and_test(&ctx->pending)) | 854 | if (!atomic_dec_and_test(&ctx->pending)) |
| 836 | return; | 855 | return; |
diff --git a/drivers/md/dm-io.c b/drivers/md/dm-io.c index f14813be4eff..36e2b5e46a6b 100644 --- a/drivers/md/dm-io.c +++ b/drivers/md/dm-io.c | |||
| @@ -292,6 +292,8 @@ static void do_region(int rw, unsigned region, struct dm_io_region *where, | |||
| 292 | (PAGE_SIZE >> SECTOR_SHIFT)); | 292 | (PAGE_SIZE >> SECTOR_SHIFT)); |
| 293 | num_bvecs = 1 + min_t(int, bio_get_nr_vecs(where->bdev), | 293 | num_bvecs = 1 + min_t(int, bio_get_nr_vecs(where->bdev), |
| 294 | num_bvecs); | 294 | num_bvecs); |
| 295 | if (unlikely(num_bvecs > BIO_MAX_PAGES)) | ||
| 296 | num_bvecs = BIO_MAX_PAGES; | ||
| 295 | bio = bio_alloc_bioset(GFP_NOIO, num_bvecs, io->client->bios); | 297 | bio = bio_alloc_bioset(GFP_NOIO, num_bvecs, io->client->bios); |
| 296 | bio->bi_sector = where->sector + (where->count - remaining); | 298 | bio->bi_sector = where->sector + (where->count - remaining); |
| 297 | bio->bi_bdev = where->bdev; | 299 | bio->bi_bdev = where->bdev; |
diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c index 54d0588fc1f6..f01096549a93 100644 --- a/drivers/md/dm-ioctl.c +++ b/drivers/md/dm-ioctl.c | |||
| @@ -704,7 +704,8 @@ static int dev_rename(struct dm_ioctl *param, size_t param_size) | |||
| 704 | char *new_name = (char *) param + param->data_start; | 704 | char *new_name = (char *) param + param->data_start; |
| 705 | 705 | ||
| 706 | if (new_name < param->data || | 706 | if (new_name < param->data || |
| 707 | invalid_str(new_name, (void *) param + param_size)) { | 707 | invalid_str(new_name, (void *) param + param_size) || |
| 708 | strlen(new_name) > DM_NAME_LEN - 1) { | ||
| 708 | DMWARN("Invalid new logical volume name supplied."); | 709 | DMWARN("Invalid new logical volume name supplied."); |
| 709 | return -EINVAL; | 710 | return -EINVAL; |
| 710 | } | 711 | } |
| @@ -1063,7 +1064,7 @@ static int table_load(struct dm_ioctl *param, size_t param_size) | |||
| 1063 | 1064 | ||
| 1064 | r = populate_table(t, param, param_size); | 1065 | r = populate_table(t, param, param_size); |
| 1065 | if (r) { | 1066 | if (r) { |
| 1066 | dm_table_put(t); | 1067 | dm_table_destroy(t); |
| 1067 | goto out; | 1068 | goto out; |
| 1068 | } | 1069 | } |
| 1069 | 1070 | ||
| @@ -1071,7 +1072,7 @@ static int table_load(struct dm_ioctl *param, size_t param_size) | |||
| 1071 | hc = dm_get_mdptr(md); | 1072 | hc = dm_get_mdptr(md); |
| 1072 | if (!hc || hc->md != md) { | 1073 | if (!hc || hc->md != md) { |
| 1073 | DMWARN("device has been removed from the dev hash table."); | 1074 | DMWARN("device has been removed from the dev hash table."); |
| 1074 | dm_table_put(t); | 1075 | dm_table_destroy(t); |
| 1075 | up_write(&_hash_lock); | 1076 | up_write(&_hash_lock); |
| 1076 | r = -ENXIO; | 1077 | r = -ENXIO; |
| 1077 | goto out; | 1078 | goto out; |
diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 51ba1db4b3e7..8d40f27cce89 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c | |||
| @@ -525,9 +525,12 @@ static int __noflush_suspending(struct mapped_device *md) | |||
| 525 | static void dec_pending(struct dm_io *io, int error) | 525 | static void dec_pending(struct dm_io *io, int error) |
| 526 | { | 526 | { |
| 527 | unsigned long flags; | 527 | unsigned long flags; |
| 528 | int io_error; | ||
| 529 | struct bio *bio; | ||
| 530 | struct mapped_device *md = io->md; | ||
| 528 | 531 | ||
| 529 | /* Push-back supersedes any I/O errors */ | 532 | /* Push-back supersedes any I/O errors */ |
| 530 | if (error && !(io->error > 0 && __noflush_suspending(io->md))) | 533 | if (error && !(io->error > 0 && __noflush_suspending(md))) |
| 531 | io->error = error; | 534 | io->error = error; |
| 532 | 535 | ||
| 533 | if (atomic_dec_and_test(&io->io_count)) { | 536 | if (atomic_dec_and_test(&io->io_count)) { |
| @@ -537,24 +540,27 @@ static void dec_pending(struct dm_io *io, int error) | |||
| 537 | * This must be handled before the sleeper on | 540 | * This must be handled before the sleeper on |
| 538 | * suspend queue merges the pushback list. | 541 | * suspend queue merges the pushback list. |
| 539 | */ | 542 | */ |
| 540 | spin_lock_irqsave(&io->md->pushback_lock, flags); | 543 | spin_lock_irqsave(&md->pushback_lock, flags); |
| 541 | if (__noflush_suspending(io->md)) | 544 | if (__noflush_suspending(md)) |
| 542 | bio_list_add(&io->md->pushback, io->bio); | 545 | bio_list_add(&md->pushback, io->bio); |
| 543 | else | 546 | else |
| 544 | /* noflush suspend was interrupted. */ | 547 | /* noflush suspend was interrupted. */ |
| 545 | io->error = -EIO; | 548 | io->error = -EIO; |
| 546 | spin_unlock_irqrestore(&io->md->pushback_lock, flags); | 549 | spin_unlock_irqrestore(&md->pushback_lock, flags); |
| 547 | } | 550 | } |
| 548 | 551 | ||
| 549 | end_io_acct(io); | 552 | end_io_acct(io); |
| 550 | 553 | ||
| 551 | if (io->error != DM_ENDIO_REQUEUE) { | 554 | io_error = io->error; |
| 552 | trace_block_bio_complete(io->md->queue, io->bio); | 555 | bio = io->bio; |
| 553 | 556 | ||
| 554 | bio_endio(io->bio, io->error); | 557 | free_io(md, io); |
| 555 | } | 558 | |
| 559 | if (io_error != DM_ENDIO_REQUEUE) { | ||
| 560 | trace_block_bio_complete(md->queue, bio); | ||
| 556 | 561 | ||
| 557 | free_io(io->md, io); | 562 | bio_endio(bio, io_error); |
| 563 | } | ||
| 558 | } | 564 | } |
| 559 | } | 565 | } |
| 560 | 566 | ||
| @@ -562,6 +568,7 @@ static void clone_endio(struct bio *bio, int error) | |||
| 562 | { | 568 | { |
| 563 | int r = 0; | 569 | int r = 0; |
| 564 | struct dm_target_io *tio = bio->bi_private; | 570 | struct dm_target_io *tio = bio->bi_private; |
| 571 | struct dm_io *io = tio->io; | ||
| 565 | struct mapped_device *md = tio->io->md; | 572 | struct mapped_device *md = tio->io->md; |
| 566 | dm_endio_fn endio = tio->ti->type->end_io; | 573 | dm_endio_fn endio = tio->ti->type->end_io; |
| 567 | 574 | ||
| @@ -585,15 +592,14 @@ static void clone_endio(struct bio *bio, int error) | |||
| 585 | } | 592 | } |
| 586 | } | 593 | } |
| 587 | 594 | ||
| 588 | dec_pending(tio->io, error); | ||
| 589 | |||
| 590 | /* | 595 | /* |
| 591 | * Store md for cleanup instead of tio which is about to get freed. | 596 | * Store md for cleanup instead of tio which is about to get freed. |
| 592 | */ | 597 | */ |
| 593 | bio->bi_private = md->bs; | 598 | bio->bi_private = md->bs; |
| 594 | 599 | ||
| 595 | bio_put(bio); | ||
| 596 | free_tio(md, tio); | 600 | free_tio(md, tio); |
| 601 | bio_put(bio); | ||
| 602 | dec_pending(io, error); | ||
| 597 | } | 603 | } |
| 598 | 604 | ||
| 599 | static sector_t max_io_len(struct mapped_device *md, | 605 | static sector_t max_io_len(struct mapped_device *md, |
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index a2f185fd7072..435e2e3a82c8 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
| @@ -1040,6 +1040,17 @@ config NI65 | |||
| 1040 | To compile this driver as a module, choose M here. The module | 1040 | To compile this driver as a module, choose M here. The module |
| 1041 | will be called ni65. | 1041 | will be called ni65. |
| 1042 | 1042 | ||
| 1043 | config DNET | ||
| 1044 | tristate "Dave ethernet support (DNET)" | ||
| 1045 | depends on NET_ETHERNET | ||
| 1046 | select PHYLIB | ||
| 1047 | help | ||
| 1048 | The Dave ethernet interface (DNET) is found on Qong Board FPGA. | ||
| 1049 | Say Y to include support for the DNET chip. | ||
| 1050 | |||
| 1051 | To compile this driver as a module, choose M here: the module | ||
| 1052 | will be called dnet. | ||
| 1053 | |||
| 1043 | source "drivers/net/tulip/Kconfig" | 1054 | source "drivers/net/tulip/Kconfig" |
| 1044 | 1055 | ||
| 1045 | config AT1700 | 1056 | config AT1700 |
| @@ -2619,6 +2630,8 @@ config QLGE | |||
| 2619 | 2630 | ||
| 2620 | source "drivers/net/sfc/Kconfig" | 2631 | source "drivers/net/sfc/Kconfig" |
| 2621 | 2632 | ||
| 2633 | source "drivers/net/benet/Kconfig" | ||
| 2634 | |||
| 2622 | endif # NETDEV_10000 | 2635 | endif # NETDEV_10000 |
| 2623 | 2636 | ||
| 2624 | source "drivers/net/tokenring/Kconfig" | 2637 | source "drivers/net/tokenring/Kconfig" |
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index aca8492db654..471baaff229f 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile | |||
| @@ -22,6 +22,7 @@ obj-$(CONFIG_GIANFAR) += gianfar_driver.o | |||
| 22 | obj-$(CONFIG_TEHUTI) += tehuti.o | 22 | obj-$(CONFIG_TEHUTI) += tehuti.o |
| 23 | obj-$(CONFIG_ENIC) += enic/ | 23 | obj-$(CONFIG_ENIC) += enic/ |
| 24 | obj-$(CONFIG_JME) += jme.o | 24 | obj-$(CONFIG_JME) += jme.o |
| 25 | obj-$(CONFIG_BE2NET) += benet/ | ||
| 25 | 26 | ||
| 26 | gianfar_driver-objs := gianfar.o \ | 27 | gianfar_driver-objs := gianfar.o \ |
| 27 | gianfar_ethtool.o \ | 28 | gianfar_ethtool.o \ |
| @@ -231,6 +232,7 @@ obj-$(CONFIG_ENC28J60) += enc28j60.o | |||
| 231 | 232 | ||
| 232 | obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o | 233 | obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o |
| 233 | 234 | ||
| 235 | obj-$(CONFIG_DNET) += dnet.o | ||
| 234 | obj-$(CONFIG_MACB) += macb.o | 236 | obj-$(CONFIG_MACB) += macb.o |
| 235 | 237 | ||
| 236 | obj-$(CONFIG_ARM) += arm/ | 238 | obj-$(CONFIG_ARM) += arm/ |
diff --git a/drivers/net/benet/Kconfig b/drivers/net/benet/Kconfig new file mode 100644 index 000000000000..c6934f179c09 --- /dev/null +++ b/drivers/net/benet/Kconfig | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | config BE2NET | ||
| 2 | tristate "ServerEngines' 10Gbps NIC - BladeEngine 2" | ||
| 3 | depends on PCI && INET | ||
| 4 | select INET_LRO | ||
| 5 | help | ||
| 6 | This driver implements the NIC functionality for ServerEngines' | ||
| 7 | 10Gbps network adapter - BladeEngine 2. | ||
diff --git a/drivers/net/benet/Makefile b/drivers/net/benet/Makefile new file mode 100644 index 000000000000..a60cd8051135 --- /dev/null +++ b/drivers/net/benet/Makefile | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | # | ||
| 2 | # Makefile to build the network driver for ServerEngine's BladeEngine. | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-$(CONFIG_BE2NET) += be2net.o | ||
| 6 | |||
| 7 | be2net-y := be_main.o be_cmds.o be_ethtool.o | ||
diff --git a/drivers/net/benet/be.h b/drivers/net/benet/be.h new file mode 100644 index 000000000000..63d593d53153 --- /dev/null +++ b/drivers/net/benet/be.h | |||
| @@ -0,0 +1,327 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef BE_H | ||
| 19 | #define BE_H | ||
| 20 | |||
| 21 | #include <linux/pci.h> | ||
| 22 | #include <linux/etherdevice.h> | ||
| 23 | #include <linux/version.h> | ||
| 24 | #include <linux/delay.h> | ||
| 25 | #include <net/tcp.h> | ||
| 26 | #include <net/ip.h> | ||
| 27 | #include <net/ipv6.h> | ||
| 28 | #include <linux/if_vlan.h> | ||
| 29 | #include <linux/workqueue.h> | ||
| 30 | #include <linux/interrupt.h> | ||
| 31 | #include <linux/inet_lro.h> | ||
| 32 | |||
| 33 | #include "be_hw.h" | ||
| 34 | |||
| 35 | #define DRV_VER "2.0.348" | ||
| 36 | #define DRV_NAME "be2net" | ||
| 37 | #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" | ||
| 38 | #define DRV_DESC BE_NAME "Driver" | ||
| 39 | |||
| 40 | /* Number of bytes of an RX frame that are copied to skb->data */ | ||
| 41 | #define BE_HDR_LEN 64 | ||
| 42 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 | ||
| 43 | #define BE_MIN_MTU 256 | ||
| 44 | |||
| 45 | #define BE_NUM_VLANS_SUPPORTED 64 | ||
| 46 | #define BE_MAX_EQD 96 | ||
| 47 | #define BE_MAX_TX_FRAG_COUNT 30 | ||
| 48 | |||
| 49 | #define EVNT_Q_LEN 1024 | ||
| 50 | #define TX_Q_LEN 2048 | ||
| 51 | #define TX_CQ_LEN 1024 | ||
| 52 | #define RX_Q_LEN 1024 /* Does not support any other value */ | ||
| 53 | #define RX_CQ_LEN 1024 | ||
| 54 | #define MCC_Q_LEN 64 /* total size not to exceed 8 pages */ | ||
| 55 | #define MCC_CQ_LEN 256 | ||
| 56 | |||
| 57 | #define BE_NAPI_WEIGHT 64 | ||
| 58 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ | ||
| 59 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) | ||
| 60 | |||
| 61 | #define BE_MAX_LRO_DESCRIPTORS 16 | ||
| 62 | #define BE_MAX_FRAGS_PER_FRAME 16 | ||
| 63 | |||
| 64 | struct be_dma_mem { | ||
| 65 | void *va; | ||
| 66 | dma_addr_t dma; | ||
| 67 | u32 size; | ||
| 68 | }; | ||
| 69 | |||
| 70 | struct be_queue_info { | ||
| 71 | struct be_dma_mem dma_mem; | ||
| 72 | u16 len; | ||
| 73 | u16 entry_size; /* Size of an element in the queue */ | ||
| 74 | u16 id; | ||
| 75 | u16 tail, head; | ||
| 76 | bool created; | ||
| 77 | atomic_t used; /* Number of valid elements in the queue */ | ||
| 78 | }; | ||
| 79 | |||
| 80 | struct be_ctrl_info { | ||
| 81 | u8 __iomem *csr; | ||
| 82 | u8 __iomem *db; /* Door Bell */ | ||
| 83 | u8 __iomem *pcicfg; /* PCI config space */ | ||
| 84 | int pci_func; | ||
| 85 | |||
| 86 | /* Mbox used for cmd request/response */ | ||
| 87 | spinlock_t cmd_lock; /* For serializing cmds to BE card */ | ||
| 88 | struct be_dma_mem mbox_mem; | ||
| 89 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | ||
| 90 | * is stored for freeing purpose */ | ||
| 91 | struct be_dma_mem mbox_mem_alloced; | ||
| 92 | }; | ||
| 93 | |||
| 94 | #include "be_cmds.h" | ||
| 95 | |||
| 96 | struct be_drvr_stats { | ||
| 97 | u32 be_tx_reqs; /* number of TX requests initiated */ | ||
| 98 | u32 be_tx_stops; /* number of times TX Q was stopped */ | ||
| 99 | u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */ | ||
| 100 | u32 be_tx_wrbs; /* number of tx WRBs used */ | ||
| 101 | u32 be_tx_events; /* number of tx completion events */ | ||
| 102 | u32 be_tx_compl; /* number of tx completion entries processed */ | ||
| 103 | u64 be_tx_jiffies; | ||
| 104 | ulong be_tx_bytes; | ||
| 105 | ulong be_tx_bytes_prev; | ||
| 106 | u32 be_tx_rate; | ||
| 107 | |||
| 108 | u32 cache_barrier[16]; | ||
| 109 | |||
| 110 | u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */ | ||
| 111 | u32 be_polls; /* number of times NAPI called poll function */ | ||
| 112 | u32 be_rx_events; /* number of ucast rx completion events */ | ||
| 113 | u32 be_rx_compl; /* number of rx completion entries processed */ | ||
| 114 | u32 be_lro_hgram_data[8]; /* histogram of LRO data packets */ | ||
| 115 | u32 be_lro_hgram_ack[8]; /* histogram of LRO ACKs */ | ||
| 116 | u64 be_rx_jiffies; | ||
| 117 | ulong be_rx_bytes; | ||
| 118 | ulong be_rx_bytes_prev; | ||
| 119 | u32 be_rx_rate; | ||
| 120 | /* number of non ether type II frames dropped where | ||
| 121 | * frame len > length field of Mac Hdr */ | ||
| 122 | u32 be_802_3_dropped_frames; | ||
| 123 | /* number of non ether type II frames malformed where | ||
| 124 | * in frame len < length field of Mac Hdr */ | ||
| 125 | u32 be_802_3_malformed_frames; | ||
| 126 | u32 be_rxcp_err; /* Num rx completion entries w/ err set. */ | ||
| 127 | ulong rx_fps_jiffies; /* jiffies at last FPS calc */ | ||
| 128 | u32 be_rx_frags; | ||
| 129 | u32 be_prev_rx_frags; | ||
| 130 | u32 be_rx_fps; /* Rx frags per second */ | ||
| 131 | }; | ||
| 132 | |||
| 133 | struct be_stats_obj { | ||
| 134 | struct be_drvr_stats drvr_stats; | ||
| 135 | struct net_device_stats net_stats; | ||
| 136 | struct be_dma_mem cmd; | ||
| 137 | }; | ||
| 138 | |||
| 139 | struct be_eq_obj { | ||
| 140 | struct be_queue_info q; | ||
| 141 | char desc[32]; | ||
| 142 | |||
| 143 | /* Adaptive interrupt coalescing (AIC) info */ | ||
| 144 | bool enable_aic; | ||
| 145 | u16 min_eqd; /* in usecs */ | ||
| 146 | u16 max_eqd; /* in usecs */ | ||
| 147 | u16 cur_eqd; /* in usecs */ | ||
| 148 | |||
| 149 | struct napi_struct napi; | ||
| 150 | }; | ||
| 151 | |||
| 152 | struct be_tx_obj { | ||
| 153 | struct be_queue_info q; | ||
| 154 | struct be_queue_info cq; | ||
| 155 | /* Remember the skbs that were transmitted */ | ||
| 156 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | ||
| 157 | }; | ||
| 158 | |||
| 159 | /* Struct to remember the pages posted for rx frags */ | ||
| 160 | struct be_rx_page_info { | ||
| 161 | struct page *page; | ||
| 162 | dma_addr_t bus; | ||
| 163 | u16 page_offset; | ||
| 164 | bool last_page_user; | ||
| 165 | }; | ||
| 166 | |||
| 167 | struct be_rx_obj { | ||
| 168 | struct be_queue_info q; | ||
| 169 | struct be_queue_info cq; | ||
| 170 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; | ||
| 171 | struct net_lro_mgr lro_mgr; | ||
| 172 | struct net_lro_desc lro_desc[BE_MAX_LRO_DESCRIPTORS]; | ||
| 173 | }; | ||
| 174 | |||
| 175 | #define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */ | ||
| 176 | struct be_adapter { | ||
| 177 | struct pci_dev *pdev; | ||
| 178 | struct net_device *netdev; | ||
| 179 | |||
| 180 | /* Mbox, pci config, csr address information */ | ||
| 181 | struct be_ctrl_info ctrl; | ||
| 182 | |||
| 183 | struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS]; | ||
| 184 | bool msix_enabled; | ||
| 185 | bool isr_registered; | ||
| 186 | |||
| 187 | /* TX Rings */ | ||
| 188 | struct be_eq_obj tx_eq; | ||
| 189 | struct be_tx_obj tx_obj; | ||
| 190 | |||
| 191 | u32 cache_line_break[8]; | ||
| 192 | |||
| 193 | /* Rx rings */ | ||
| 194 | struct be_eq_obj rx_eq; | ||
| 195 | struct be_rx_obj rx_obj; | ||
| 196 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ | ||
| 197 | |||
| 198 | struct vlan_group *vlan_grp; | ||
| 199 | u16 num_vlans; | ||
| 200 | u8 vlan_tag[VLAN_GROUP_ARRAY_LEN]; | ||
| 201 | |||
| 202 | struct be_stats_obj stats; | ||
| 203 | /* Work queue used to perform periodic tasks like getting statistics */ | ||
| 204 | struct delayed_work work; | ||
| 205 | |||
| 206 | /* Ethtool knobs and info */ | ||
| 207 | bool rx_csum; /* BE card must perform rx-checksumming */ | ||
| 208 | u32 max_rx_coal; | ||
| 209 | char fw_ver[FW_VER_LEN]; | ||
| 210 | u32 if_handle; /* Used to configure filtering */ | ||
| 211 | u32 pmac_id; /* MAC addr handle used by BE card */ | ||
| 212 | |||
| 213 | struct be_link_info link; | ||
| 214 | u32 port_num; | ||
| 215 | }; | ||
| 216 | |||
| 217 | extern struct ethtool_ops be_ethtool_ops; | ||
| 218 | |||
| 219 | #define drvr_stats(adapter) (&adapter->stats.drvr_stats) | ||
| 220 | |||
| 221 | #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops) | ||
| 222 | |||
| 223 | static inline u32 MODULO(u16 val, u16 limit) | ||
| 224 | { | ||
| 225 | BUG_ON(limit & (limit - 1)); | ||
| 226 | return val & (limit - 1); | ||
| 227 | } | ||
| 228 | |||
| 229 | static inline void index_adv(u16 *index, u16 val, u16 limit) | ||
| 230 | { | ||
| 231 | *index = MODULO((*index + val), limit); | ||
| 232 | } | ||
| 233 | |||
| 234 | static inline void index_inc(u16 *index, u16 limit) | ||
| 235 | { | ||
| 236 | *index = MODULO((*index + 1), limit); | ||
| 237 | } | ||
| 238 | |||
| 239 | #define PAGE_SHIFT_4K 12 | ||
| 240 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | ||
| 241 | |||
| 242 | /* Returns number of pages spanned by the data starting at the given addr */ | ||
| 243 | #define PAGES_4K_SPANNED(_address, size) \ | ||
| 244 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | ||
| 245 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | ||
| 246 | |||
| 247 | /* Byte offset into the page corresponding to given address */ | ||
| 248 | #define OFFSET_IN_PAGE(addr) \ | ||
| 249 | ((size_t)(addr) & (PAGE_SIZE_4K-1)) | ||
| 250 | |||
| 251 | /* Returns bit offset within a DWORD of a bitfield */ | ||
| 252 | #define AMAP_BIT_OFFSET(_struct, field) \ | ||
| 253 | (((size_t)&(((_struct *)0)->field))%32) | ||
| 254 | |||
| 255 | /* Returns the bit mask of the field that is NOT shifted into location. */ | ||
| 256 | static inline u32 amap_mask(u32 bitsize) | ||
| 257 | { | ||
| 258 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | ||
| 259 | } | ||
| 260 | |||
| 261 | static inline void | ||
| 262 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | ||
| 263 | { | ||
| 264 | u32 *dw = (u32 *) ptr + dw_offset; | ||
| 265 | *dw &= ~(mask << offset); | ||
| 266 | *dw |= (mask & value) << offset; | ||
| 267 | } | ||
| 268 | |||
| 269 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | ||
| 270 | amap_set(ptr, \ | ||
| 271 | offsetof(_struct, field)/32, \ | ||
| 272 | amap_mask(sizeof(((_struct *)0)->field)), \ | ||
| 273 | AMAP_BIT_OFFSET(_struct, field), \ | ||
| 274 | val) | ||
| 275 | |||
| 276 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | ||
| 277 | { | ||
| 278 | u32 *dw = (u32 *) ptr; | ||
| 279 | return mask & (*(dw + dw_offset) >> offset); | ||
| 280 | } | ||
| 281 | |||
| 282 | #define AMAP_GET_BITS(_struct, field, ptr) \ | ||
| 283 | amap_get(ptr, \ | ||
| 284 | offsetof(_struct, field)/32, \ | ||
| 285 | amap_mask(sizeof(((_struct *)0)->field)), \ | ||
| 286 | AMAP_BIT_OFFSET(_struct, field)) | ||
| 287 | |||
| 288 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) | ||
| 289 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | ||
| 290 | static inline void swap_dws(void *wrb, int len) | ||
| 291 | { | ||
| 292 | #ifdef __BIG_ENDIAN | ||
| 293 | u32 *dw = wrb; | ||
| 294 | BUG_ON(len % 4); | ||
| 295 | do { | ||
| 296 | *dw = cpu_to_le32(*dw); | ||
| 297 | dw++; | ||
| 298 | len -= 4; | ||
| 299 | } while (len); | ||
| 300 | #endif /* __BIG_ENDIAN */ | ||
| 301 | } | ||
| 302 | |||
| 303 | static inline u8 is_tcp_pkt(struct sk_buff *skb) | ||
| 304 | { | ||
| 305 | u8 val = 0; | ||
| 306 | |||
| 307 | if (ip_hdr(skb)->version == 4) | ||
| 308 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | ||
| 309 | else if (ip_hdr(skb)->version == 6) | ||
| 310 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | ||
| 311 | |||
| 312 | return val; | ||
| 313 | } | ||
| 314 | |||
| 315 | static inline u8 is_udp_pkt(struct sk_buff *skb) | ||
| 316 | { | ||
| 317 | u8 val = 0; | ||
| 318 | |||
| 319 | if (ip_hdr(skb)->version == 4) | ||
| 320 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | ||
| 321 | else if (ip_hdr(skb)->version == 6) | ||
| 322 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | ||
| 323 | |||
| 324 | return val; | ||
| 325 | } | ||
| 326 | |||
| 327 | #endif /* BE_H */ | ||
diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c new file mode 100644 index 000000000000..d444aed962bc --- /dev/null +++ b/drivers/net/benet/be_cmds.c | |||
| @@ -0,0 +1,861 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include "be.h" | ||
| 19 | |||
| 20 | static int be_mbox_db_ready_wait(void __iomem *db) | ||
| 21 | { | ||
| 22 | int cnt = 0, wait = 5; | ||
| 23 | u32 ready; | ||
| 24 | |||
| 25 | do { | ||
| 26 | ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK; | ||
| 27 | if (ready) | ||
| 28 | break; | ||
| 29 | |||
| 30 | if (cnt > 200000) { | ||
| 31 | printk(KERN_WARNING DRV_NAME | ||
| 32 | ": mbox_db poll timed out\n"); | ||
| 33 | return -1; | ||
| 34 | } | ||
| 35 | |||
| 36 | if (cnt > 50) | ||
| 37 | wait = 200; | ||
| 38 | cnt += wait; | ||
| 39 | udelay(wait); | ||
| 40 | } while (true); | ||
| 41 | |||
| 42 | return 0; | ||
| 43 | } | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Insert the mailbox address into the doorbell in two steps | ||
| 47 | */ | ||
| 48 | static int be_mbox_db_ring(struct be_ctrl_info *ctrl) | ||
| 49 | { | ||
| 50 | int status; | ||
| 51 | u16 compl_status, extd_status; | ||
| 52 | u32 val = 0; | ||
| 53 | void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; | ||
| 54 | struct be_dma_mem *mbox_mem = &ctrl->mbox_mem; | ||
| 55 | struct be_mcc_mailbox *mbox = mbox_mem->va; | ||
| 56 | struct be_mcc_cq_entry *cqe = &mbox->cqe; | ||
| 57 | |||
| 58 | memset(cqe, 0, sizeof(*cqe)); | ||
| 59 | |||
| 60 | val &= ~MPU_MAILBOX_DB_RDY_MASK; | ||
| 61 | val |= MPU_MAILBOX_DB_HI_MASK; | ||
| 62 | /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ | ||
| 63 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | ||
| 64 | iowrite32(val, db); | ||
| 65 | |||
| 66 | /* wait for ready to be set */ | ||
| 67 | status = be_mbox_db_ready_wait(db); | ||
| 68 | if (status != 0) | ||
| 69 | return status; | ||
| 70 | |||
| 71 | val = 0; | ||
| 72 | val &= ~MPU_MAILBOX_DB_RDY_MASK; | ||
| 73 | val &= ~MPU_MAILBOX_DB_HI_MASK; | ||
| 74 | /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ | ||
| 75 | val |= (u32)(mbox_mem->dma >> 4) << 2; | ||
| 76 | iowrite32(val, db); | ||
| 77 | |||
| 78 | status = be_mbox_db_ready_wait(db); | ||
| 79 | if (status != 0) | ||
| 80 | return status; | ||
| 81 | |||
| 82 | /* compl entry has been made now */ | ||
| 83 | be_dws_le_to_cpu(cqe, sizeof(*cqe)); | ||
| 84 | if (!(cqe->flags & CQE_FLAGS_VALID_MASK)) { | ||
| 85 | printk(KERN_WARNING DRV_NAME ": ERROR invalid mbox compl\n"); | ||
| 86 | return -1; | ||
| 87 | } | ||
| 88 | |||
| 89 | compl_status = (cqe->status >> CQE_STATUS_COMPL_SHIFT) & | ||
| 90 | CQE_STATUS_COMPL_MASK; | ||
| 91 | if (compl_status != MCC_STATUS_SUCCESS) { | ||
| 92 | extd_status = (cqe->status >> CQE_STATUS_EXTD_SHIFT) & | ||
| 93 | CQE_STATUS_EXTD_MASK; | ||
| 94 | printk(KERN_WARNING DRV_NAME | ||
| 95 | ": ERROR in cmd compl. status(compl/extd)=%d/%d\n", | ||
| 96 | compl_status, extd_status); | ||
| 97 | } | ||
| 98 | |||
| 99 | return compl_status; | ||
| 100 | } | ||
| 101 | |||
| 102 | static int be_POST_stage_get(struct be_ctrl_info *ctrl, u16 *stage) | ||
| 103 | { | ||
| 104 | u32 sem = ioread32(ctrl->csr + MPU_EP_SEMAPHORE_OFFSET); | ||
| 105 | |||
| 106 | *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK; | ||
| 107 | if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK) | ||
| 108 | return -1; | ||
| 109 | else | ||
| 110 | return 0; | ||
| 111 | } | ||
| 112 | |||
| 113 | static int be_POST_stage_poll(struct be_ctrl_info *ctrl, u16 poll_stage) | ||
| 114 | { | ||
| 115 | u16 stage, cnt, error; | ||
| 116 | for (cnt = 0; cnt < 5000; cnt++) { | ||
| 117 | error = be_POST_stage_get(ctrl, &stage); | ||
| 118 | if (error) | ||
| 119 | return -1; | ||
| 120 | |||
| 121 | if (stage == poll_stage) | ||
| 122 | break; | ||
| 123 | udelay(1000); | ||
| 124 | } | ||
| 125 | if (stage != poll_stage) | ||
| 126 | return -1; | ||
| 127 | return 0; | ||
| 128 | } | ||
| 129 | |||
| 130 | |||
| 131 | int be_cmd_POST(struct be_ctrl_info *ctrl) | ||
| 132 | { | ||
| 133 | u16 stage, error; | ||
| 134 | |||
| 135 | error = be_POST_stage_get(ctrl, &stage); | ||
| 136 | if (error) | ||
| 137 | goto err; | ||
| 138 | |||
| 139 | if (stage == POST_STAGE_ARMFW_RDY) | ||
| 140 | return 0; | ||
| 141 | |||
| 142 | if (stage != POST_STAGE_AWAITING_HOST_RDY) | ||
| 143 | goto err; | ||
| 144 | |||
| 145 | /* On awaiting host rdy, reset and again poll on awaiting host rdy */ | ||
| 146 | iowrite32(POST_STAGE_BE_RESET, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET); | ||
| 147 | error = be_POST_stage_poll(ctrl, POST_STAGE_AWAITING_HOST_RDY); | ||
| 148 | if (error) | ||
| 149 | goto err; | ||
| 150 | |||
| 151 | /* Now kickoff POST and poll on armfw ready */ | ||
| 152 | iowrite32(POST_STAGE_HOST_RDY, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET); | ||
| 153 | error = be_POST_stage_poll(ctrl, POST_STAGE_ARMFW_RDY); | ||
| 154 | if (error) | ||
| 155 | goto err; | ||
| 156 | |||
| 157 | return 0; | ||
| 158 | err: | ||
| 159 | printk(KERN_WARNING DRV_NAME ": ERROR, stage=%d\n", stage); | ||
| 160 | return -1; | ||
| 161 | } | ||
| 162 | |||
| 163 | static inline void *embedded_payload(struct be_mcc_wrb *wrb) | ||
| 164 | { | ||
| 165 | return wrb->payload.embedded_payload; | ||
| 166 | } | ||
| 167 | |||
| 168 | static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) | ||
| 169 | { | ||
| 170 | return &wrb->payload.sgl[0]; | ||
| 171 | } | ||
| 172 | |||
| 173 | /* Don't touch the hdr after it's prepared */ | ||
| 174 | static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, | ||
| 175 | bool embedded, u8 sge_cnt) | ||
| 176 | { | ||
| 177 | if (embedded) | ||
| 178 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | ||
| 179 | else | ||
| 180 | wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << | ||
| 181 | MCC_WRB_SGE_CNT_SHIFT; | ||
| 182 | wrb->payload_length = payload_len; | ||
| 183 | be_dws_cpu_to_le(wrb, 20); | ||
| 184 | } | ||
| 185 | |||
| 186 | /* Don't touch the hdr after it's prepared */ | ||
| 187 | static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | ||
| 188 | u8 subsystem, u8 opcode, int cmd_len) | ||
| 189 | { | ||
| 190 | req_hdr->opcode = opcode; | ||
| 191 | req_hdr->subsystem = subsystem; | ||
| 192 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | ||
| 193 | } | ||
| 194 | |||
| 195 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | ||
| 196 | struct be_dma_mem *mem) | ||
| 197 | { | ||
| 198 | int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | ||
| 199 | u64 dma = (u64)mem->dma; | ||
| 200 | |||
| 201 | for (i = 0; i < buf_pages; i++) { | ||
| 202 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | ||
| 203 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | ||
| 204 | dma += PAGE_SIZE_4K; | ||
| 205 | } | ||
| 206 | } | ||
| 207 | |||
| 208 | /* Converts interrupt delay in microseconds to multiplier value */ | ||
| 209 | static u32 eq_delay_to_mult(u32 usec_delay) | ||
| 210 | { | ||
| 211 | #define MAX_INTR_RATE 651042 | ||
| 212 | const u32 round = 10; | ||
| 213 | u32 multiplier; | ||
| 214 | |||
| 215 | if (usec_delay == 0) | ||
| 216 | multiplier = 0; | ||
| 217 | else { | ||
| 218 | u32 interrupt_rate = 1000000 / usec_delay; | ||
| 219 | /* Max delay, corresponding to the lowest interrupt rate */ | ||
| 220 | if (interrupt_rate == 0) | ||
| 221 | multiplier = 1023; | ||
| 222 | else { | ||
| 223 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | ||
| 224 | multiplier /= interrupt_rate; | ||
| 225 | /* Round the multiplier to the closest value.*/ | ||
| 226 | multiplier = (multiplier + round/2) / round; | ||
| 227 | multiplier = min(multiplier, (u32)1023); | ||
| 228 | } | ||
| 229 | } | ||
| 230 | return multiplier; | ||
| 231 | } | ||
| 232 | |||
| 233 | static inline struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem) | ||
| 234 | { | ||
| 235 | return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | ||
| 236 | } | ||
| 237 | |||
| 238 | int be_cmd_eq_create(struct be_ctrl_info *ctrl, | ||
| 239 | struct be_queue_info *eq, int eq_delay) | ||
| 240 | { | ||
| 241 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 242 | struct be_cmd_req_eq_create *req = embedded_payload(wrb); | ||
| 243 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); | ||
| 244 | struct be_dma_mem *q_mem = &eq->dma_mem; | ||
| 245 | int status; | ||
| 246 | |||
| 247 | spin_lock(&ctrl->cmd_lock); | ||
| 248 | memset(wrb, 0, sizeof(*wrb)); | ||
| 249 | |||
| 250 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 251 | |||
| 252 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 253 | OPCODE_COMMON_EQ_CREATE, sizeof(*req)); | ||
| 254 | |||
| 255 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | ||
| 256 | |||
| 257 | AMAP_SET_BITS(struct amap_eq_context, func, req->context, | ||
| 258 | ctrl->pci_func); | ||
| 259 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); | ||
| 260 | /* 4byte eqe*/ | ||
| 261 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | ||
| 262 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | ||
| 263 | __ilog2_u32(eq->len/256)); | ||
| 264 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | ||
| 265 | eq_delay_to_mult(eq_delay)); | ||
| 266 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | ||
| 267 | |||
| 268 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | ||
| 269 | |||
| 270 | status = be_mbox_db_ring(ctrl); | ||
| 271 | if (!status) { | ||
| 272 | eq->id = le16_to_cpu(resp->eq_id); | ||
| 273 | eq->created = true; | ||
| 274 | } | ||
| 275 | spin_unlock(&ctrl->cmd_lock); | ||
| 276 | return status; | ||
| 277 | } | ||
| 278 | |||
| 279 | int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr, | ||
| 280 | u8 type, bool permanent, u32 if_handle) | ||
| 281 | { | ||
| 282 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 283 | struct be_cmd_req_mac_query *req = embedded_payload(wrb); | ||
| 284 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); | ||
| 285 | int status; | ||
| 286 | |||
| 287 | spin_lock(&ctrl->cmd_lock); | ||
| 288 | memset(wrb, 0, sizeof(*wrb)); | ||
| 289 | |||
| 290 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 291 | |||
| 292 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 293 | OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req)); | ||
| 294 | |||
| 295 | req->type = type; | ||
| 296 | if (permanent) { | ||
| 297 | req->permanent = 1; | ||
| 298 | } else { | ||
| 299 | req->if_id = cpu_to_le16((u16)if_handle); | ||
| 300 | req->permanent = 0; | ||
| 301 | } | ||
| 302 | |||
| 303 | status = be_mbox_db_ring(ctrl); | ||
| 304 | if (!status) | ||
| 305 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); | ||
| 306 | |||
| 307 | spin_unlock(&ctrl->cmd_lock); | ||
| 308 | return status; | ||
| 309 | } | ||
| 310 | |||
| 311 | int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr, | ||
| 312 | u32 if_id, u32 *pmac_id) | ||
| 313 | { | ||
| 314 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 315 | struct be_cmd_req_pmac_add *req = embedded_payload(wrb); | ||
| 316 | int status; | ||
| 317 | |||
| 318 | spin_lock(&ctrl->cmd_lock); | ||
| 319 | memset(wrb, 0, sizeof(*wrb)); | ||
| 320 | |||
| 321 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 322 | |||
| 323 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 324 | OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req)); | ||
| 325 | |||
| 326 | req->if_id = cpu_to_le32(if_id); | ||
| 327 | memcpy(req->mac_address, mac_addr, ETH_ALEN); | ||
| 328 | |||
| 329 | status = be_mbox_db_ring(ctrl); | ||
| 330 | if (!status) { | ||
| 331 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); | ||
| 332 | *pmac_id = le32_to_cpu(resp->pmac_id); | ||
| 333 | } | ||
| 334 | |||
| 335 | spin_unlock(&ctrl->cmd_lock); | ||
| 336 | return status; | ||
| 337 | } | ||
| 338 | |||
| 339 | int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id) | ||
| 340 | { | ||
| 341 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 342 | struct be_cmd_req_pmac_del *req = embedded_payload(wrb); | ||
| 343 | int status; | ||
| 344 | |||
| 345 | spin_lock(&ctrl->cmd_lock); | ||
| 346 | memset(wrb, 0, sizeof(*wrb)); | ||
| 347 | |||
| 348 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 349 | |||
| 350 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 351 | OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req)); | ||
| 352 | |||
| 353 | req->if_id = cpu_to_le32(if_id); | ||
| 354 | req->pmac_id = cpu_to_le32(pmac_id); | ||
| 355 | |||
| 356 | status = be_mbox_db_ring(ctrl); | ||
| 357 | spin_unlock(&ctrl->cmd_lock); | ||
| 358 | |||
| 359 | return status; | ||
| 360 | } | ||
| 361 | |||
| 362 | int be_cmd_cq_create(struct be_ctrl_info *ctrl, | ||
| 363 | struct be_queue_info *cq, struct be_queue_info *eq, | ||
| 364 | bool sol_evts, bool no_delay, int coalesce_wm) | ||
| 365 | { | ||
| 366 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 367 | struct be_cmd_req_cq_create *req = embedded_payload(wrb); | ||
| 368 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); | ||
| 369 | struct be_dma_mem *q_mem = &cq->dma_mem; | ||
| 370 | void *ctxt = &req->context; | ||
| 371 | int status; | ||
| 372 | |||
| 373 | spin_lock(&ctrl->cmd_lock); | ||
| 374 | memset(wrb, 0, sizeof(*wrb)); | ||
| 375 | |||
| 376 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 377 | |||
| 378 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 379 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | ||
| 380 | |||
| 381 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | ||
| 382 | |||
| 383 | AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm); | ||
| 384 | AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); | ||
| 385 | AMAP_SET_BITS(struct amap_cq_context, count, ctxt, | ||
| 386 | __ilog2_u32(cq->len/256)); | ||
| 387 | AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); | ||
| 388 | AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); | ||
| 389 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); | ||
| 390 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); | ||
| 391 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 0); | ||
| 392 | AMAP_SET_BITS(struct amap_cq_context, func, ctxt, ctrl->pci_func); | ||
| 393 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | ||
| 394 | |||
| 395 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | ||
| 396 | |||
| 397 | status = be_mbox_db_ring(ctrl); | ||
| 398 | if (!status) { | ||
| 399 | cq->id = le16_to_cpu(resp->cq_id); | ||
| 400 | cq->created = true; | ||
| 401 | } | ||
| 402 | spin_unlock(&ctrl->cmd_lock); | ||
| 403 | |||
| 404 | return status; | ||
| 405 | } | ||
| 406 | |||
| 407 | int be_cmd_txq_create(struct be_ctrl_info *ctrl, | ||
| 408 | struct be_queue_info *txq, | ||
| 409 | struct be_queue_info *cq) | ||
| 410 | { | ||
| 411 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 412 | struct be_cmd_req_eth_tx_create *req = embedded_payload(wrb); | ||
| 413 | struct be_dma_mem *q_mem = &txq->dma_mem; | ||
| 414 | void *ctxt = &req->context; | ||
| 415 | int status; | ||
| 416 | u32 len_encoded; | ||
| 417 | |||
| 418 | spin_lock(&ctrl->cmd_lock); | ||
| 419 | memset(wrb, 0, sizeof(*wrb)); | ||
| 420 | |||
| 421 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 422 | |||
| 423 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE, | ||
| 424 | sizeof(*req)); | ||
| 425 | |||
| 426 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | ||
| 427 | req->ulp_num = BE_ULP1_NUM; | ||
| 428 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; | ||
| 429 | |||
| 430 | len_encoded = fls(txq->len); /* log2(len) + 1 */ | ||
| 431 | if (len_encoded == 16) | ||
| 432 | len_encoded = 0; | ||
| 433 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, len_encoded); | ||
| 434 | AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt, | ||
| 435 | ctrl->pci_func); | ||
| 436 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); | ||
| 437 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); | ||
| 438 | |||
| 439 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | ||
| 440 | |||
| 441 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | ||
| 442 | |||
| 443 | status = be_mbox_db_ring(ctrl); | ||
| 444 | if (!status) { | ||
| 445 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | ||
| 446 | txq->id = le16_to_cpu(resp->cid); | ||
| 447 | txq->created = true; | ||
| 448 | } | ||
| 449 | spin_unlock(&ctrl->cmd_lock); | ||
| 450 | |||
| 451 | return status; | ||
| 452 | } | ||
| 453 | |||
| 454 | int be_cmd_rxq_create(struct be_ctrl_info *ctrl, | ||
| 455 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, | ||
| 456 | u16 max_frame_size, u32 if_id, u32 rss) | ||
| 457 | { | ||
| 458 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 459 | struct be_cmd_req_eth_rx_create *req = embedded_payload(wrb); | ||
| 460 | struct be_dma_mem *q_mem = &rxq->dma_mem; | ||
| 461 | int status; | ||
| 462 | |||
| 463 | spin_lock(&ctrl->cmd_lock); | ||
| 464 | memset(wrb, 0, sizeof(*wrb)); | ||
| 465 | |||
| 466 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 467 | |||
| 468 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE, | ||
| 469 | sizeof(*req)); | ||
| 470 | |||
| 471 | req->cq_id = cpu_to_le16(cq_id); | ||
| 472 | req->frag_size = fls(frag_size) - 1; | ||
| 473 | req->num_pages = 2; | ||
| 474 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | ||
| 475 | req->interface_id = cpu_to_le32(if_id); | ||
| 476 | req->max_frame_size = cpu_to_le16(max_frame_size); | ||
| 477 | req->rss_queue = cpu_to_le32(rss); | ||
| 478 | |||
| 479 | status = be_mbox_db_ring(ctrl); | ||
| 480 | if (!status) { | ||
| 481 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); | ||
| 482 | rxq->id = le16_to_cpu(resp->id); | ||
| 483 | rxq->created = true; | ||
| 484 | } | ||
| 485 | spin_unlock(&ctrl->cmd_lock); | ||
| 486 | |||
| 487 | return status; | ||
| 488 | } | ||
| 489 | |||
| 490 | /* Generic destroyer function for all types of queues */ | ||
| 491 | int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | ||
| 492 | int queue_type) | ||
| 493 | { | ||
| 494 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 495 | struct be_cmd_req_q_destroy *req = embedded_payload(wrb); | ||
| 496 | u8 subsys = 0, opcode = 0; | ||
| 497 | int status; | ||
| 498 | |||
| 499 | spin_lock(&ctrl->cmd_lock); | ||
| 500 | |||
| 501 | memset(wrb, 0, sizeof(*wrb)); | ||
| 502 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 503 | |||
| 504 | switch (queue_type) { | ||
| 505 | case QTYPE_EQ: | ||
| 506 | subsys = CMD_SUBSYSTEM_COMMON; | ||
| 507 | opcode = OPCODE_COMMON_EQ_DESTROY; | ||
| 508 | break; | ||
| 509 | case QTYPE_CQ: | ||
| 510 | subsys = CMD_SUBSYSTEM_COMMON; | ||
| 511 | opcode = OPCODE_COMMON_CQ_DESTROY; | ||
| 512 | break; | ||
| 513 | case QTYPE_TXQ: | ||
| 514 | subsys = CMD_SUBSYSTEM_ETH; | ||
| 515 | opcode = OPCODE_ETH_TX_DESTROY; | ||
| 516 | break; | ||
| 517 | case QTYPE_RXQ: | ||
| 518 | subsys = CMD_SUBSYSTEM_ETH; | ||
| 519 | opcode = OPCODE_ETH_RX_DESTROY; | ||
| 520 | break; | ||
| 521 | default: | ||
| 522 | printk(KERN_WARNING DRV_NAME ":bad Q type in Q destroy cmd\n"); | ||
| 523 | status = -1; | ||
| 524 | goto err; | ||
| 525 | } | ||
| 526 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); | ||
| 527 | req->id = cpu_to_le16(q->id); | ||
| 528 | |||
| 529 | status = be_mbox_db_ring(ctrl); | ||
| 530 | err: | ||
| 531 | spin_unlock(&ctrl->cmd_lock); | ||
| 532 | |||
| 533 | return status; | ||
| 534 | } | ||
| 535 | |||
| 536 | /* Create an rx filtering policy configuration on an i/f */ | ||
| 537 | int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 flags, u8 *mac, | ||
| 538 | bool pmac_invalid, u32 *if_handle, u32 *pmac_id) | ||
| 539 | { | ||
| 540 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 541 | struct be_cmd_req_if_create *req = embedded_payload(wrb); | ||
| 542 | int status; | ||
| 543 | |||
| 544 | spin_lock(&ctrl->cmd_lock); | ||
| 545 | memset(wrb, 0, sizeof(*wrb)); | ||
| 546 | |||
| 547 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 548 | |||
| 549 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 550 | OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req)); | ||
| 551 | |||
| 552 | req->capability_flags = cpu_to_le32(flags); | ||
| 553 | req->enable_flags = cpu_to_le32(flags); | ||
| 554 | if (!pmac_invalid) | ||
| 555 | memcpy(req->mac_addr, mac, ETH_ALEN); | ||
| 556 | |||
| 557 | status = be_mbox_db_ring(ctrl); | ||
| 558 | if (!status) { | ||
| 559 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); | ||
| 560 | *if_handle = le32_to_cpu(resp->interface_id); | ||
| 561 | if (!pmac_invalid) | ||
| 562 | *pmac_id = le32_to_cpu(resp->pmac_id); | ||
| 563 | } | ||
| 564 | |||
| 565 | spin_unlock(&ctrl->cmd_lock); | ||
| 566 | return status; | ||
| 567 | } | ||
| 568 | |||
| 569 | int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 interface_id) | ||
| 570 | { | ||
| 571 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 572 | struct be_cmd_req_if_destroy *req = embedded_payload(wrb); | ||
| 573 | int status; | ||
| 574 | |||
| 575 | spin_lock(&ctrl->cmd_lock); | ||
| 576 | memset(wrb, 0, sizeof(*wrb)); | ||
| 577 | |||
| 578 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 579 | |||
| 580 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 581 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); | ||
| 582 | |||
| 583 | req->interface_id = cpu_to_le32(interface_id); | ||
| 584 | status = be_mbox_db_ring(ctrl); | ||
| 585 | |||
| 586 | spin_unlock(&ctrl->cmd_lock); | ||
| 587 | |||
| 588 | return status; | ||
| 589 | } | ||
| 590 | |||
| 591 | /* Get stats is a non embedded command: the request is not embedded inside | ||
| 592 | * WRB but is a separate dma memory block | ||
| 593 | */ | ||
| 594 | int be_cmd_get_stats(struct be_ctrl_info *ctrl, struct be_dma_mem *nonemb_cmd) | ||
| 595 | { | ||
| 596 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 597 | struct be_cmd_req_get_stats *req = nonemb_cmd->va; | ||
| 598 | struct be_sge *sge = nonembedded_sgl(wrb); | ||
| 599 | int status; | ||
| 600 | |||
| 601 | spin_lock(&ctrl->cmd_lock); | ||
| 602 | memset(wrb, 0, sizeof(*wrb)); | ||
| 603 | |||
| 604 | memset(req, 0, sizeof(*req)); | ||
| 605 | |||
| 606 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1); | ||
| 607 | |||
| 608 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | ||
| 609 | OPCODE_ETH_GET_STATISTICS, sizeof(*req)); | ||
| 610 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | ||
| 611 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | ||
| 612 | sge->len = cpu_to_le32(nonemb_cmd->size); | ||
| 613 | |||
| 614 | status = be_mbox_db_ring(ctrl); | ||
| 615 | if (!status) { | ||
| 616 | struct be_cmd_resp_get_stats *resp = nonemb_cmd->va; | ||
| 617 | be_dws_le_to_cpu(&resp->hw_stats, sizeof(resp->hw_stats)); | ||
| 618 | } | ||
| 619 | |||
| 620 | spin_unlock(&ctrl->cmd_lock); | ||
| 621 | return status; | ||
| 622 | } | ||
| 623 | |||
| 624 | int be_cmd_link_status_query(struct be_ctrl_info *ctrl, | ||
| 625 | struct be_link_info *link) | ||
| 626 | { | ||
| 627 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 628 | struct be_cmd_req_link_status *req = embedded_payload(wrb); | ||
| 629 | int status; | ||
| 630 | |||
| 631 | spin_lock(&ctrl->cmd_lock); | ||
| 632 | memset(wrb, 0, sizeof(*wrb)); | ||
| 633 | |||
| 634 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 635 | |||
| 636 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 637 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); | ||
| 638 | |||
| 639 | status = be_mbox_db_ring(ctrl); | ||
| 640 | if (!status) { | ||
| 641 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); | ||
| 642 | link->speed = resp->mac_speed; | ||
| 643 | link->duplex = resp->mac_duplex; | ||
| 644 | link->fault = resp->mac_fault; | ||
| 645 | } else { | ||
| 646 | link->speed = PHY_LINK_SPEED_ZERO; | ||
| 647 | } | ||
| 648 | |||
| 649 | spin_unlock(&ctrl->cmd_lock); | ||
| 650 | return status; | ||
| 651 | } | ||
| 652 | |||
| 653 | int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver) | ||
| 654 | { | ||
| 655 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 656 | struct be_cmd_req_get_fw_version *req = embedded_payload(wrb); | ||
| 657 | int status; | ||
| 658 | |||
| 659 | spin_lock(&ctrl->cmd_lock); | ||
| 660 | memset(wrb, 0, sizeof(*wrb)); | ||
| 661 | |||
| 662 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 663 | |||
| 664 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 665 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); | ||
| 666 | |||
| 667 | status = be_mbox_db_ring(ctrl); | ||
| 668 | if (!status) { | ||
| 669 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); | ||
| 670 | strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN); | ||
| 671 | } | ||
| 672 | |||
| 673 | spin_unlock(&ctrl->cmd_lock); | ||
| 674 | return status; | ||
| 675 | } | ||
| 676 | |||
| 677 | /* set the EQ delay interval of an EQ to specified value */ | ||
| 678 | int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd) | ||
| 679 | { | ||
| 680 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 681 | struct be_cmd_req_modify_eq_delay *req = embedded_payload(wrb); | ||
| 682 | int status; | ||
| 683 | |||
| 684 | spin_lock(&ctrl->cmd_lock); | ||
| 685 | memset(wrb, 0, sizeof(*wrb)); | ||
| 686 | |||
| 687 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 688 | |||
| 689 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 690 | OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req)); | ||
| 691 | |||
| 692 | req->num_eq = cpu_to_le32(1); | ||
| 693 | req->delay[0].eq_id = cpu_to_le32(eq_id); | ||
| 694 | req->delay[0].phase = 0; | ||
| 695 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); | ||
| 696 | |||
| 697 | status = be_mbox_db_ring(ctrl); | ||
| 698 | |||
| 699 | spin_unlock(&ctrl->cmd_lock); | ||
| 700 | return status; | ||
| 701 | } | ||
| 702 | |||
| 703 | int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id, u16 *vtag_array, | ||
| 704 | u32 num, bool untagged, bool promiscuous) | ||
| 705 | { | ||
| 706 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 707 | struct be_cmd_req_vlan_config *req = embedded_payload(wrb); | ||
| 708 | int status; | ||
| 709 | |||
| 710 | spin_lock(&ctrl->cmd_lock); | ||
| 711 | memset(wrb, 0, sizeof(*wrb)); | ||
| 712 | |||
| 713 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 714 | |||
| 715 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 716 | OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req)); | ||
| 717 | |||
| 718 | req->interface_id = if_id; | ||
| 719 | req->promiscuous = promiscuous; | ||
| 720 | req->untagged = untagged; | ||
| 721 | req->num_vlan = num; | ||
| 722 | if (!promiscuous) { | ||
| 723 | memcpy(req->normal_vlan, vtag_array, | ||
| 724 | req->num_vlan * sizeof(vtag_array[0])); | ||
| 725 | } | ||
| 726 | |||
| 727 | status = be_mbox_db_ring(ctrl); | ||
| 728 | |||
| 729 | spin_unlock(&ctrl->cmd_lock); | ||
| 730 | return status; | ||
| 731 | } | ||
| 732 | |||
| 733 | int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, u8 port_num, bool en) | ||
| 734 | { | ||
| 735 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 736 | struct be_cmd_req_promiscuous_config *req = embedded_payload(wrb); | ||
| 737 | int status; | ||
| 738 | |||
| 739 | spin_lock(&ctrl->cmd_lock); | ||
| 740 | memset(wrb, 0, sizeof(*wrb)); | ||
| 741 | |||
| 742 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 743 | |||
| 744 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | ||
| 745 | OPCODE_ETH_PROMISCUOUS, sizeof(*req)); | ||
| 746 | |||
| 747 | if (port_num) | ||
| 748 | req->port1_promiscuous = en; | ||
| 749 | else | ||
| 750 | req->port0_promiscuous = en; | ||
| 751 | |||
| 752 | status = be_mbox_db_ring(ctrl); | ||
| 753 | |||
| 754 | spin_unlock(&ctrl->cmd_lock); | ||
| 755 | return status; | ||
| 756 | } | ||
| 757 | |||
| 758 | int be_cmd_mcast_mac_set(struct be_ctrl_info *ctrl, u32 if_id, u8 *mac_table, | ||
| 759 | u32 num, bool promiscuous) | ||
| 760 | { | ||
| 761 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 762 | struct be_cmd_req_mcast_mac_config *req = embedded_payload(wrb); | ||
| 763 | int status; | ||
| 764 | |||
| 765 | spin_lock(&ctrl->cmd_lock); | ||
| 766 | memset(wrb, 0, sizeof(*wrb)); | ||
| 767 | |||
| 768 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 769 | |||
| 770 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 771 | OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req)); | ||
| 772 | |||
| 773 | req->interface_id = if_id; | ||
| 774 | req->promiscuous = promiscuous; | ||
| 775 | if (!promiscuous) { | ||
| 776 | req->num_mac = cpu_to_le16(num); | ||
| 777 | if (num) | ||
| 778 | memcpy(req->mac, mac_table, ETH_ALEN * num); | ||
| 779 | } | ||
| 780 | |||
| 781 | status = be_mbox_db_ring(ctrl); | ||
| 782 | |||
| 783 | spin_unlock(&ctrl->cmd_lock); | ||
| 784 | return status; | ||
| 785 | } | ||
| 786 | |||
| 787 | int be_cmd_set_flow_control(struct be_ctrl_info *ctrl, u32 tx_fc, u32 rx_fc) | ||
| 788 | { | ||
| 789 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 790 | struct be_cmd_req_set_flow_control *req = embedded_payload(wrb); | ||
| 791 | int status; | ||
| 792 | |||
| 793 | spin_lock(&ctrl->cmd_lock); | ||
| 794 | |||
| 795 | memset(wrb, 0, sizeof(*wrb)); | ||
| 796 | |||
| 797 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 798 | |||
| 799 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 800 | OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req)); | ||
| 801 | |||
| 802 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); | ||
| 803 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); | ||
| 804 | |||
| 805 | status = be_mbox_db_ring(ctrl); | ||
| 806 | |||
| 807 | spin_unlock(&ctrl->cmd_lock); | ||
| 808 | return status; | ||
| 809 | } | ||
| 810 | |||
| 811 | int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, u32 *tx_fc, u32 *rx_fc) | ||
| 812 | { | ||
| 813 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 814 | struct be_cmd_req_get_flow_control *req = embedded_payload(wrb); | ||
| 815 | int status; | ||
| 816 | |||
| 817 | spin_lock(&ctrl->cmd_lock); | ||
| 818 | |||
| 819 | memset(wrb, 0, sizeof(*wrb)); | ||
| 820 | |||
| 821 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 822 | |||
| 823 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 824 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); | ||
| 825 | |||
| 826 | status = be_mbox_db_ring(ctrl); | ||
| 827 | if (!status) { | ||
| 828 | struct be_cmd_resp_get_flow_control *resp = | ||
| 829 | embedded_payload(wrb); | ||
| 830 | *tx_fc = le16_to_cpu(resp->tx_flow_control); | ||
| 831 | *rx_fc = le16_to_cpu(resp->rx_flow_control); | ||
| 832 | } | ||
| 833 | |||
| 834 | spin_unlock(&ctrl->cmd_lock); | ||
| 835 | return status; | ||
| 836 | } | ||
| 837 | |||
| 838 | int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num) | ||
| 839 | { | ||
| 840 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 841 | struct be_cmd_req_query_fw_cfg *req = embedded_payload(wrb); | ||
| 842 | int status; | ||
| 843 | |||
| 844 | spin_lock(&ctrl->cmd_lock); | ||
| 845 | |||
| 846 | memset(wrb, 0, sizeof(*wrb)); | ||
| 847 | |||
| 848 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 849 | |||
| 850 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 851 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); | ||
| 852 | |||
| 853 | status = be_mbox_db_ring(ctrl); | ||
| 854 | if (!status) { | ||
| 855 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | ||
| 856 | *port_num = le32_to_cpu(resp->phys_port); | ||
| 857 | } | ||
| 858 | |||
| 859 | spin_unlock(&ctrl->cmd_lock); | ||
| 860 | return status; | ||
| 861 | } | ||
diff --git a/drivers/net/benet/be_cmds.h b/drivers/net/benet/be_cmds.h new file mode 100644 index 000000000000..e499e2d5b8c3 --- /dev/null +++ b/drivers/net/benet/be_cmds.h | |||
| @@ -0,0 +1,688 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The driver sends configuration and managements command requests to the | ||
| 20 | * firmware in the BE. These requests are communicated to the processor | ||
| 21 | * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one | ||
| 22 | * WRB inside a MAILBOX. | ||
| 23 | * The commands are serviced by the ARM processor in the BladeEngine's MPU. | ||
| 24 | */ | ||
| 25 | |||
| 26 | struct be_sge { | ||
| 27 | u32 pa_lo; | ||
| 28 | u32 pa_hi; | ||
| 29 | u32 len; | ||
| 30 | }; | ||
| 31 | |||
| 32 | #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ | ||
| 33 | #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ | ||
| 34 | #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ | ||
| 35 | struct be_mcc_wrb { | ||
| 36 | u32 embedded; /* dword 0 */ | ||
| 37 | u32 payload_length; /* dword 1 */ | ||
| 38 | u32 tag0; /* dword 2 */ | ||
| 39 | u32 tag1; /* dword 3 */ | ||
| 40 | u32 rsvd; /* dword 4 */ | ||
| 41 | union { | ||
| 42 | u8 embedded_payload[236]; /* used by embedded cmds */ | ||
| 43 | struct be_sge sgl[19]; /* used by non-embedded cmds */ | ||
| 44 | } payload; | ||
| 45 | }; | ||
| 46 | |||
| 47 | #define CQE_FLAGS_VALID_MASK (1 << 31) | ||
| 48 | #define CQE_FLAGS_ASYNC_MASK (1 << 30) | ||
| 49 | #define CQE_FLAGS_COMPLETED_MASK (1 << 28) | ||
| 50 | #define CQE_FLAGS_CONSUMED_MASK (1 << 27) | ||
| 51 | |||
| 52 | /* Completion Status */ | ||
| 53 | enum { | ||
| 54 | MCC_STATUS_SUCCESS = 0x0, | ||
| 55 | /* The client does not have sufficient privileges to execute the command */ | ||
| 56 | MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1, | ||
| 57 | /* A parameter in the command was invalid. */ | ||
| 58 | MCC_STATUS_INVALID_PARAMETER = 0x2, | ||
| 59 | /* There are insufficient chip resources to execute the command */ | ||
| 60 | MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3, | ||
| 61 | /* The command is completing because the queue was getting flushed */ | ||
| 62 | MCC_STATUS_QUEUE_FLUSHING = 0x4, | ||
| 63 | /* The command is completing with a DMA error */ | ||
| 64 | MCC_STATUS_DMA_FAILED = 0x5 | ||
| 65 | }; | ||
| 66 | |||
| 67 | #define CQE_STATUS_COMPL_MASK 0xFFFF | ||
| 68 | #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */ | ||
| 69 | #define CQE_STATUS_EXTD_MASK 0xFFFF | ||
| 70 | #define CQE_STATUS_EXTD_SHIFT 0 /* bits 0 - 15 */ | ||
| 71 | |||
| 72 | struct be_mcc_cq_entry { | ||
| 73 | u32 status; /* dword 0 */ | ||
| 74 | u32 tag0; /* dword 1 */ | ||
| 75 | u32 tag1; /* dword 2 */ | ||
| 76 | u32 flags; /* dword 3 */ | ||
| 77 | }; | ||
| 78 | |||
| 79 | struct be_mcc_mailbox { | ||
| 80 | struct be_mcc_wrb wrb; | ||
| 81 | struct be_mcc_cq_entry cqe; | ||
| 82 | }; | ||
| 83 | |||
| 84 | #define CMD_SUBSYSTEM_COMMON 0x1 | ||
| 85 | #define CMD_SUBSYSTEM_ETH 0x3 | ||
| 86 | |||
| 87 | #define OPCODE_COMMON_NTWK_MAC_QUERY 1 | ||
| 88 | #define OPCODE_COMMON_NTWK_MAC_SET 2 | ||
| 89 | #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 | ||
| 90 | #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 | ||
| 91 | #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 | ||
| 92 | #define OPCODE_COMMON_CQ_CREATE 12 | ||
| 93 | #define OPCODE_COMMON_EQ_CREATE 13 | ||
| 94 | #define OPCODE_COMMON_MCC_CREATE 21 | ||
| 95 | #define OPCODE_COMMON_NTWK_RX_FILTER 34 | ||
| 96 | #define OPCODE_COMMON_GET_FW_VERSION 35 | ||
| 97 | #define OPCODE_COMMON_SET_FLOW_CONTROL 36 | ||
| 98 | #define OPCODE_COMMON_GET_FLOW_CONTROL 37 | ||
| 99 | #define OPCODE_COMMON_SET_FRAME_SIZE 39 | ||
| 100 | #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 | ||
| 101 | #define OPCODE_COMMON_FIRMWARE_CONFIG 42 | ||
| 102 | #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 | ||
| 103 | #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 | ||
| 104 | #define OPCODE_COMMON_CQ_DESTROY 54 | ||
| 105 | #define OPCODE_COMMON_EQ_DESTROY 55 | ||
| 106 | #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 | ||
| 107 | #define OPCODE_COMMON_NTWK_PMAC_ADD 59 | ||
| 108 | #define OPCODE_COMMON_NTWK_PMAC_DEL 60 | ||
| 109 | |||
| 110 | #define OPCODE_ETH_ACPI_CONFIG 2 | ||
| 111 | #define OPCODE_ETH_PROMISCUOUS 3 | ||
| 112 | #define OPCODE_ETH_GET_STATISTICS 4 | ||
| 113 | #define OPCODE_ETH_TX_CREATE 7 | ||
| 114 | #define OPCODE_ETH_RX_CREATE 8 | ||
| 115 | #define OPCODE_ETH_TX_DESTROY 9 | ||
| 116 | #define OPCODE_ETH_RX_DESTROY 10 | ||
| 117 | |||
| 118 | struct be_cmd_req_hdr { | ||
| 119 | u8 opcode; /* dword 0 */ | ||
| 120 | u8 subsystem; /* dword 0 */ | ||
| 121 | u8 port_number; /* dword 0 */ | ||
| 122 | u8 domain; /* dword 0 */ | ||
| 123 | u32 timeout; /* dword 1 */ | ||
| 124 | u32 request_length; /* dword 2 */ | ||
| 125 | u32 rsvd; /* dword 3 */ | ||
| 126 | }; | ||
| 127 | |||
| 128 | #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ | ||
| 129 | #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ | ||
| 130 | struct be_cmd_resp_hdr { | ||
| 131 | u32 info; /* dword 0 */ | ||
| 132 | u32 status; /* dword 1 */ | ||
| 133 | u32 response_length; /* dword 2 */ | ||
| 134 | u32 actual_resp_len; /* dword 3 */ | ||
| 135 | }; | ||
| 136 | |||
| 137 | struct phys_addr { | ||
| 138 | u32 lo; | ||
| 139 | u32 hi; | ||
| 140 | }; | ||
| 141 | |||
| 142 | /************************** | ||
| 143 | * BE Command definitions * | ||
| 144 | **************************/ | ||
| 145 | |||
| 146 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
| 147 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
| 148 | struct amap_eq_context { | ||
| 149 | u8 cidx[13]; /* dword 0*/ | ||
| 150 | u8 rsvd0[3]; /* dword 0*/ | ||
| 151 | u8 epidx[13]; /* dword 0*/ | ||
| 152 | u8 valid; /* dword 0*/ | ||
| 153 | u8 rsvd1; /* dword 0*/ | ||
| 154 | u8 size; /* dword 0*/ | ||
| 155 | u8 pidx[13]; /* dword 1*/ | ||
| 156 | u8 rsvd2[3]; /* dword 1*/ | ||
| 157 | u8 pd[10]; /* dword 1*/ | ||
| 158 | u8 count[3]; /* dword 1*/ | ||
| 159 | u8 solevent; /* dword 1*/ | ||
| 160 | u8 stalled; /* dword 1*/ | ||
| 161 | u8 armed; /* dword 1*/ | ||
| 162 | u8 rsvd3[4]; /* dword 2*/ | ||
| 163 | u8 func[8]; /* dword 2*/ | ||
| 164 | u8 rsvd4; /* dword 2*/ | ||
| 165 | u8 delaymult[10]; /* dword 2*/ | ||
| 166 | u8 rsvd5[2]; /* dword 2*/ | ||
| 167 | u8 phase[2]; /* dword 2*/ | ||
| 168 | u8 nodelay; /* dword 2*/ | ||
| 169 | u8 rsvd6[4]; /* dword 2*/ | ||
| 170 | u8 rsvd7[32]; /* dword 3*/ | ||
| 171 | } __packed; | ||
| 172 | |||
| 173 | struct be_cmd_req_eq_create { | ||
| 174 | struct be_cmd_req_hdr hdr; | ||
| 175 | u16 num_pages; /* sword */ | ||
| 176 | u16 rsvd0; /* sword */ | ||
| 177 | u8 context[sizeof(struct amap_eq_context) / 8]; | ||
| 178 | struct phys_addr pages[8]; | ||
| 179 | } __packed; | ||
| 180 | |||
| 181 | struct be_cmd_resp_eq_create { | ||
| 182 | struct be_cmd_resp_hdr resp_hdr; | ||
| 183 | u16 eq_id; /* sword */ | ||
| 184 | u16 rsvd0; /* sword */ | ||
| 185 | } __packed; | ||
| 186 | |||
| 187 | /******************** Mac query ***************************/ | ||
| 188 | enum { | ||
| 189 | MAC_ADDRESS_TYPE_STORAGE = 0x0, | ||
| 190 | MAC_ADDRESS_TYPE_NETWORK = 0x1, | ||
| 191 | MAC_ADDRESS_TYPE_PD = 0x2, | ||
| 192 | MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 | ||
| 193 | }; | ||
| 194 | |||
| 195 | struct mac_addr { | ||
| 196 | u16 size_of_struct; | ||
| 197 | u8 addr[ETH_ALEN]; | ||
| 198 | } __packed; | ||
| 199 | |||
| 200 | struct be_cmd_req_mac_query { | ||
| 201 | struct be_cmd_req_hdr hdr; | ||
| 202 | u8 type; | ||
| 203 | u8 permanent; | ||
| 204 | u16 if_id; | ||
| 205 | } __packed; | ||
| 206 | |||
| 207 | struct be_cmd_resp_mac_query { | ||
| 208 | struct be_cmd_resp_hdr hdr; | ||
| 209 | struct mac_addr mac; | ||
| 210 | }; | ||
| 211 | |||
| 212 | /******************** PMac Add ***************************/ | ||
| 213 | struct be_cmd_req_pmac_add { | ||
| 214 | struct be_cmd_req_hdr hdr; | ||
| 215 | u32 if_id; | ||
| 216 | u8 mac_address[ETH_ALEN]; | ||
| 217 | u8 rsvd0[2]; | ||
| 218 | } __packed; | ||
| 219 | |||
| 220 | struct be_cmd_resp_pmac_add { | ||
| 221 | struct be_cmd_resp_hdr hdr; | ||
| 222 | u32 pmac_id; | ||
| 223 | }; | ||
| 224 | |||
| 225 | /******************** PMac Del ***************************/ | ||
| 226 | struct be_cmd_req_pmac_del { | ||
| 227 | struct be_cmd_req_hdr hdr; | ||
| 228 | u32 if_id; | ||
| 229 | u32 pmac_id; | ||
| 230 | }; | ||
| 231 | |||
| 232 | /******************** Create CQ ***************************/ | ||
| 233 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
| 234 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
| 235 | struct amap_cq_context { | ||
| 236 | u8 cidx[11]; /* dword 0*/ | ||
| 237 | u8 rsvd0; /* dword 0*/ | ||
| 238 | u8 coalescwm[2]; /* dword 0*/ | ||
| 239 | u8 nodelay; /* dword 0*/ | ||
| 240 | u8 epidx[11]; /* dword 0*/ | ||
| 241 | u8 rsvd1; /* dword 0*/ | ||
| 242 | u8 count[2]; /* dword 0*/ | ||
| 243 | u8 valid; /* dword 0*/ | ||
| 244 | u8 solevent; /* dword 0*/ | ||
| 245 | u8 eventable; /* dword 0*/ | ||
| 246 | u8 pidx[11]; /* dword 1*/ | ||
| 247 | u8 rsvd2; /* dword 1*/ | ||
| 248 | u8 pd[10]; /* dword 1*/ | ||
| 249 | u8 eqid[8]; /* dword 1*/ | ||
| 250 | u8 stalled; /* dword 1*/ | ||
| 251 | u8 armed; /* dword 1*/ | ||
| 252 | u8 rsvd3[4]; /* dword 2*/ | ||
| 253 | u8 func[8]; /* dword 2*/ | ||
| 254 | u8 rsvd4[20]; /* dword 2*/ | ||
| 255 | u8 rsvd5[32]; /* dword 3*/ | ||
| 256 | } __packed; | ||
| 257 | |||
| 258 | struct be_cmd_req_cq_create { | ||
| 259 | struct be_cmd_req_hdr hdr; | ||
| 260 | u16 num_pages; | ||
| 261 | u16 rsvd0; | ||
| 262 | u8 context[sizeof(struct amap_cq_context) / 8]; | ||
| 263 | struct phys_addr pages[8]; | ||
| 264 | } __packed; | ||
| 265 | |||
| 266 | struct be_cmd_resp_cq_create { | ||
| 267 | struct be_cmd_resp_hdr hdr; | ||
| 268 | u16 cq_id; | ||
| 269 | u16 rsvd0; | ||
| 270 | } __packed; | ||
| 271 | |||
| 272 | /******************** Create TxQ ***************************/ | ||
| 273 | #define BE_ETH_TX_RING_TYPE_STANDARD 2 | ||
| 274 | #define BE_ULP1_NUM 1 | ||
| 275 | |||
| 276 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
| 277 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
| 278 | struct amap_tx_context { | ||
| 279 | u8 rsvd0[16]; /* dword 0 */ | ||
| 280 | u8 tx_ring_size[4]; /* dword 0 */ | ||
| 281 | u8 rsvd1[26]; /* dword 0 */ | ||
| 282 | u8 pci_func_id[8]; /* dword 1 */ | ||
| 283 | u8 rsvd2[9]; /* dword 1 */ | ||
| 284 | u8 ctx_valid; /* dword 1 */ | ||
| 285 | u8 cq_id_send[16]; /* dword 2 */ | ||
| 286 | u8 rsvd3[16]; /* dword 2 */ | ||
| 287 | u8 rsvd4[32]; /* dword 3 */ | ||
| 288 | u8 rsvd5[32]; /* dword 4 */ | ||
| 289 | u8 rsvd6[32]; /* dword 5 */ | ||
| 290 | u8 rsvd7[32]; /* dword 6 */ | ||
| 291 | u8 rsvd8[32]; /* dword 7 */ | ||
| 292 | u8 rsvd9[32]; /* dword 8 */ | ||
| 293 | u8 rsvd10[32]; /* dword 9 */ | ||
| 294 | u8 rsvd11[32]; /* dword 10 */ | ||
| 295 | u8 rsvd12[32]; /* dword 11 */ | ||
| 296 | u8 rsvd13[32]; /* dword 12 */ | ||
| 297 | u8 rsvd14[32]; /* dword 13 */ | ||
| 298 | u8 rsvd15[32]; /* dword 14 */ | ||
| 299 | u8 rsvd16[32]; /* dword 15 */ | ||
| 300 | } __packed; | ||
| 301 | |||
| 302 | struct be_cmd_req_eth_tx_create { | ||
| 303 | struct be_cmd_req_hdr hdr; | ||
| 304 | u8 num_pages; | ||
| 305 | u8 ulp_num; | ||
| 306 | u8 type; | ||
| 307 | u8 bound_port; | ||
| 308 | u8 context[sizeof(struct amap_tx_context) / 8]; | ||
| 309 | struct phys_addr pages[8]; | ||
| 310 | } __packed; | ||
| 311 | |||
| 312 | struct be_cmd_resp_eth_tx_create { | ||
| 313 | struct be_cmd_resp_hdr hdr; | ||
| 314 | u16 cid; | ||
| 315 | u16 rsvd0; | ||
| 316 | } __packed; | ||
| 317 | |||
| 318 | /******************** Create RxQ ***************************/ | ||
| 319 | struct be_cmd_req_eth_rx_create { | ||
| 320 | struct be_cmd_req_hdr hdr; | ||
| 321 | u16 cq_id; | ||
| 322 | u8 frag_size; | ||
| 323 | u8 num_pages; | ||
| 324 | struct phys_addr pages[2]; | ||
| 325 | u32 interface_id; | ||
| 326 | u16 max_frame_size; | ||
| 327 | u16 rsvd0; | ||
| 328 | u32 rss_queue; | ||
| 329 | } __packed; | ||
| 330 | |||
| 331 | struct be_cmd_resp_eth_rx_create { | ||
| 332 | struct be_cmd_resp_hdr hdr; | ||
| 333 | u16 id; | ||
| 334 | u8 cpu_id; | ||
| 335 | u8 rsvd0; | ||
| 336 | } __packed; | ||
| 337 | |||
| 338 | /******************** Q Destroy ***************************/ | ||
| 339 | /* Type of Queue to be destroyed */ | ||
| 340 | enum { | ||
| 341 | QTYPE_EQ = 1, | ||
| 342 | QTYPE_CQ, | ||
| 343 | QTYPE_TXQ, | ||
| 344 | QTYPE_RXQ | ||
| 345 | }; | ||
| 346 | |||
| 347 | struct be_cmd_req_q_destroy { | ||
| 348 | struct be_cmd_req_hdr hdr; | ||
| 349 | u16 id; | ||
| 350 | u16 bypass_flush; /* valid only for rx q destroy */ | ||
| 351 | } __packed; | ||
| 352 | |||
| 353 | /************ I/f Create (it's actually I/f Config Create)**********/ | ||
| 354 | |||
| 355 | /* Capability flags for the i/f */ | ||
| 356 | enum be_if_flags { | ||
| 357 | BE_IF_FLAGS_RSS = 0x4, | ||
| 358 | BE_IF_FLAGS_PROMISCUOUS = 0x8, | ||
| 359 | BE_IF_FLAGS_BROADCAST = 0x10, | ||
| 360 | BE_IF_FLAGS_UNTAGGED = 0x20, | ||
| 361 | BE_IF_FLAGS_ULP = 0x40, | ||
| 362 | BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, | ||
| 363 | BE_IF_FLAGS_VLAN = 0x100, | ||
| 364 | BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, | ||
| 365 | BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, | ||
| 366 | BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800 | ||
| 367 | }; | ||
| 368 | |||
| 369 | /* An RX interface is an object with one or more MAC addresses and | ||
| 370 | * filtering capabilities. */ | ||
| 371 | struct be_cmd_req_if_create { | ||
| 372 | struct be_cmd_req_hdr hdr; | ||
| 373 | u32 version; /* ignore currntly */ | ||
| 374 | u32 capability_flags; | ||
| 375 | u32 enable_flags; | ||
| 376 | u8 mac_addr[ETH_ALEN]; | ||
| 377 | u8 rsvd0; | ||
| 378 | u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ | ||
| 379 | u32 vlan_tag; /* not used currently */ | ||
| 380 | } __packed; | ||
| 381 | |||
| 382 | struct be_cmd_resp_if_create { | ||
| 383 | struct be_cmd_resp_hdr hdr; | ||
| 384 | u32 interface_id; | ||
| 385 | u32 pmac_id; | ||
| 386 | }; | ||
| 387 | |||
| 388 | /****** I/f Destroy(it's actually I/f Config Destroy )**********/ | ||
| 389 | struct be_cmd_req_if_destroy { | ||
| 390 | struct be_cmd_req_hdr hdr; | ||
| 391 | u32 interface_id; | ||
| 392 | }; | ||
| 393 | |||
| 394 | /*************** HW Stats Get **********************************/ | ||
| 395 | struct be_port_rxf_stats { | ||
| 396 | u32 rx_bytes_lsd; /* dword 0*/ | ||
| 397 | u32 rx_bytes_msd; /* dword 1*/ | ||
| 398 | u32 rx_total_frames; /* dword 2*/ | ||
| 399 | u32 rx_unicast_frames; /* dword 3*/ | ||
| 400 | u32 rx_multicast_frames; /* dword 4*/ | ||
| 401 | u32 rx_broadcast_frames; /* dword 5*/ | ||
| 402 | u32 rx_crc_errors; /* dword 6*/ | ||
| 403 | u32 rx_alignment_symbol_errors; /* dword 7*/ | ||
| 404 | u32 rx_pause_frames; /* dword 8*/ | ||
| 405 | u32 rx_control_frames; /* dword 9*/ | ||
| 406 | u32 rx_in_range_errors; /* dword 10*/ | ||
| 407 | u32 rx_out_range_errors; /* dword 11*/ | ||
| 408 | u32 rx_frame_too_long; /* dword 12*/ | ||
| 409 | u32 rx_address_match_errors; /* dword 13*/ | ||
| 410 | u32 rx_vlan_mismatch; /* dword 14*/ | ||
| 411 | u32 rx_dropped_too_small; /* dword 15*/ | ||
| 412 | u32 rx_dropped_too_short; /* dword 16*/ | ||
| 413 | u32 rx_dropped_header_too_small; /* dword 17*/ | ||
| 414 | u32 rx_dropped_tcp_length; /* dword 18*/ | ||
| 415 | u32 rx_dropped_runt; /* dword 19*/ | ||
| 416 | u32 rx_64_byte_packets; /* dword 20*/ | ||
| 417 | u32 rx_65_127_byte_packets; /* dword 21*/ | ||
| 418 | u32 rx_128_256_byte_packets; /* dword 22*/ | ||
| 419 | u32 rx_256_511_byte_packets; /* dword 23*/ | ||
| 420 | u32 rx_512_1023_byte_packets; /* dword 24*/ | ||
| 421 | u32 rx_1024_1518_byte_packets; /* dword 25*/ | ||
| 422 | u32 rx_1519_2047_byte_packets; /* dword 26*/ | ||
| 423 | u32 rx_2048_4095_byte_packets; /* dword 27*/ | ||
| 424 | u32 rx_4096_8191_byte_packets; /* dword 28*/ | ||
| 425 | u32 rx_8192_9216_byte_packets; /* dword 29*/ | ||
| 426 | u32 rx_ip_checksum_errs; /* dword 30*/ | ||
| 427 | u32 rx_tcp_checksum_errs; /* dword 31*/ | ||
| 428 | u32 rx_udp_checksum_errs; /* dword 32*/ | ||
| 429 | u32 rx_non_rss_packets; /* dword 33*/ | ||
| 430 | u32 rx_ipv4_packets; /* dword 34*/ | ||
| 431 | u32 rx_ipv6_packets; /* dword 35*/ | ||
| 432 | u32 rx_ipv4_bytes_lsd; /* dword 36*/ | ||
| 433 | u32 rx_ipv4_bytes_msd; /* dword 37*/ | ||
| 434 | u32 rx_ipv6_bytes_lsd; /* dword 38*/ | ||
| 435 | u32 rx_ipv6_bytes_msd; /* dword 39*/ | ||
| 436 | u32 rx_chute1_packets; /* dword 40*/ | ||
| 437 | u32 rx_chute2_packets; /* dword 41*/ | ||
| 438 | u32 rx_chute3_packets; /* dword 42*/ | ||
| 439 | u32 rx_management_packets; /* dword 43*/ | ||
| 440 | u32 rx_switched_unicast_packets; /* dword 44*/ | ||
| 441 | u32 rx_switched_multicast_packets; /* dword 45*/ | ||
| 442 | u32 rx_switched_broadcast_packets; /* dword 46*/ | ||
| 443 | u32 tx_bytes_lsd; /* dword 47*/ | ||
| 444 | u32 tx_bytes_msd; /* dword 48*/ | ||
| 445 | u32 tx_unicastframes; /* dword 49*/ | ||
| 446 | u32 tx_multicastframes; /* dword 50*/ | ||
| 447 | u32 tx_broadcastframes; /* dword 51*/ | ||
| 448 | u32 tx_pauseframes; /* dword 52*/ | ||
| 449 | u32 tx_controlframes; /* dword 53*/ | ||
| 450 | u32 tx_64_byte_packets; /* dword 54*/ | ||
| 451 | u32 tx_65_127_byte_packets; /* dword 55*/ | ||
| 452 | u32 tx_128_256_byte_packets; /* dword 56*/ | ||
| 453 | u32 tx_256_511_byte_packets; /* dword 57*/ | ||
| 454 | u32 tx_512_1023_byte_packets; /* dword 58*/ | ||
| 455 | u32 tx_1024_1518_byte_packets; /* dword 59*/ | ||
| 456 | u32 tx_1519_2047_byte_packets; /* dword 60*/ | ||
| 457 | u32 tx_2048_4095_byte_packets; /* dword 61*/ | ||
| 458 | u32 tx_4096_8191_byte_packets; /* dword 62*/ | ||
| 459 | u32 tx_8192_9216_byte_packets; /* dword 63*/ | ||
| 460 | u32 rx_fifo_overflow; /* dword 64*/ | ||
| 461 | u32 rx_input_fifo_overflow; /* dword 65*/ | ||
| 462 | }; | ||
| 463 | |||
| 464 | struct be_rxf_stats { | ||
| 465 | struct be_port_rxf_stats port[2]; | ||
| 466 | u32 rx_drops_no_pbuf; /* dword 132*/ | ||
| 467 | u32 rx_drops_no_txpb; /* dword 133*/ | ||
| 468 | u32 rx_drops_no_erx_descr; /* dword 134*/ | ||
| 469 | u32 rx_drops_no_tpre_descr; /* dword 135*/ | ||
| 470 | u32 management_rx_port_packets; /* dword 136*/ | ||
| 471 | u32 management_rx_port_bytes; /* dword 137*/ | ||
| 472 | u32 management_rx_port_pause_frames; /* dword 138*/ | ||
| 473 | u32 management_rx_port_errors; /* dword 139*/ | ||
| 474 | u32 management_tx_port_packets; /* dword 140*/ | ||
| 475 | u32 management_tx_port_bytes; /* dword 141*/ | ||
| 476 | u32 management_tx_port_pause; /* dword 142*/ | ||
| 477 | u32 management_rx_port_rxfifo_overflow; /* dword 143*/ | ||
| 478 | u32 rx_drops_too_many_frags; /* dword 144*/ | ||
| 479 | u32 rx_drops_invalid_ring; /* dword 145*/ | ||
| 480 | u32 forwarded_packets; /* dword 146*/ | ||
| 481 | u32 rx_drops_mtu; /* dword 147*/ | ||
| 482 | u32 rsvd0[15]; | ||
| 483 | }; | ||
| 484 | |||
| 485 | struct be_erx_stats { | ||
| 486 | u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ | ||
| 487 | u32 debug_wdma_sent_hold; /* dword 44*/ | ||
| 488 | u32 debug_wdma_pbfree_sent_hold; /* dword 45*/ | ||
| 489 | u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/ | ||
| 490 | u32 debug_pmem_pbuf_dealloc; /* dword 47*/ | ||
| 491 | }; | ||
| 492 | |||
| 493 | struct be_hw_stats { | ||
| 494 | struct be_rxf_stats rxf; | ||
| 495 | u32 rsvd[48]; | ||
| 496 | struct be_erx_stats erx; | ||
| 497 | }; | ||
| 498 | |||
| 499 | struct be_cmd_req_get_stats { | ||
| 500 | struct be_cmd_req_hdr hdr; | ||
| 501 | u8 rsvd[sizeof(struct be_hw_stats)]; | ||
| 502 | }; | ||
| 503 | |||
| 504 | struct be_cmd_resp_get_stats { | ||
| 505 | struct be_cmd_resp_hdr hdr; | ||
| 506 | struct be_hw_stats hw_stats; | ||
| 507 | }; | ||
| 508 | |||
| 509 | struct be_cmd_req_vlan_config { | ||
| 510 | struct be_cmd_req_hdr hdr; | ||
| 511 | u8 interface_id; | ||
| 512 | u8 promiscuous; | ||
| 513 | u8 untagged; | ||
| 514 | u8 num_vlan; | ||
| 515 | u16 normal_vlan[64]; | ||
| 516 | } __packed; | ||
| 517 | |||
| 518 | struct be_cmd_req_promiscuous_config { | ||
| 519 | struct be_cmd_req_hdr hdr; | ||
| 520 | u8 port0_promiscuous; | ||
| 521 | u8 port1_promiscuous; | ||
| 522 | u16 rsvd0; | ||
| 523 | } __packed; | ||
| 524 | |||
| 525 | struct macaddr { | ||
| 526 | u8 byte[ETH_ALEN]; | ||
| 527 | }; | ||
| 528 | |||
| 529 | struct be_cmd_req_mcast_mac_config { | ||
| 530 | struct be_cmd_req_hdr hdr; | ||
| 531 | u16 num_mac; | ||
| 532 | u8 promiscuous; | ||
| 533 | u8 interface_id; | ||
| 534 | struct macaddr mac[32]; | ||
| 535 | } __packed; | ||
| 536 | |||
| 537 | static inline struct be_hw_stats * | ||
| 538 | hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd) | ||
| 539 | { | ||
| 540 | return &cmd->hw_stats; | ||
| 541 | } | ||
| 542 | |||
| 543 | /******************** Link Status Query *******************/ | ||
| 544 | struct be_cmd_req_link_status { | ||
| 545 | struct be_cmd_req_hdr hdr; | ||
| 546 | u32 rsvd; | ||
| 547 | }; | ||
| 548 | |||
| 549 | struct be_link_info { | ||
| 550 | u8 duplex; | ||
| 551 | u8 speed; | ||
| 552 | u8 fault; | ||
| 553 | }; | ||
| 554 | |||
| 555 | enum { | ||
| 556 | PHY_LINK_DUPLEX_NONE = 0x0, | ||
| 557 | PHY_LINK_DUPLEX_HALF = 0x1, | ||
| 558 | PHY_LINK_DUPLEX_FULL = 0x2 | ||
| 559 | }; | ||
| 560 | |||
| 561 | enum { | ||
| 562 | PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ | ||
| 563 | PHY_LINK_SPEED_10MBPS = 0x1, | ||
| 564 | PHY_LINK_SPEED_100MBPS = 0x2, | ||
| 565 | PHY_LINK_SPEED_1GBPS = 0x3, | ||
| 566 | PHY_LINK_SPEED_10GBPS = 0x4 | ||
| 567 | }; | ||
| 568 | |||
| 569 | struct be_cmd_resp_link_status { | ||
| 570 | struct be_cmd_resp_hdr hdr; | ||
| 571 | u8 physical_port; | ||
| 572 | u8 mac_duplex; | ||
| 573 | u8 mac_speed; | ||
| 574 | u8 mac_fault; | ||
| 575 | u8 mgmt_mac_duplex; | ||
| 576 | u8 mgmt_mac_speed; | ||
| 577 | u16 rsvd0; | ||
| 578 | } __packed; | ||
| 579 | |||
| 580 | /******************** Get FW Version *******************/ | ||
| 581 | #define FW_VER_LEN 32 | ||
| 582 | struct be_cmd_req_get_fw_version { | ||
| 583 | struct be_cmd_req_hdr hdr; | ||
| 584 | u8 rsvd0[FW_VER_LEN]; | ||
| 585 | u8 rsvd1[FW_VER_LEN]; | ||
| 586 | } __packed; | ||
| 587 | |||
| 588 | struct be_cmd_resp_get_fw_version { | ||
| 589 | struct be_cmd_resp_hdr hdr; | ||
| 590 | u8 firmware_version_string[FW_VER_LEN]; | ||
| 591 | u8 fw_on_flash_version_string[FW_VER_LEN]; | ||
| 592 | } __packed; | ||
| 593 | |||
| 594 | /******************** Set Flow Contrl *******************/ | ||
| 595 | struct be_cmd_req_set_flow_control { | ||
| 596 | struct be_cmd_req_hdr hdr; | ||
| 597 | u16 tx_flow_control; | ||
| 598 | u16 rx_flow_control; | ||
| 599 | } __packed; | ||
| 600 | |||
| 601 | /******************** Get Flow Contrl *******************/ | ||
| 602 | struct be_cmd_req_get_flow_control { | ||
| 603 | struct be_cmd_req_hdr hdr; | ||
| 604 | u32 rsvd; | ||
| 605 | }; | ||
| 606 | |||
| 607 | struct be_cmd_resp_get_flow_control { | ||
| 608 | struct be_cmd_resp_hdr hdr; | ||
| 609 | u16 tx_flow_control; | ||
| 610 | u16 rx_flow_control; | ||
| 611 | } __packed; | ||
| 612 | |||
| 613 | /******************** Modify EQ Delay *******************/ | ||
| 614 | struct be_cmd_req_modify_eq_delay { | ||
| 615 | struct be_cmd_req_hdr hdr; | ||
| 616 | u32 num_eq; | ||
| 617 | struct { | ||
| 618 | u32 eq_id; | ||
| 619 | u32 phase; | ||
| 620 | u32 delay_multiplier; | ||
| 621 | } delay[8]; | ||
| 622 | } __packed; | ||
| 623 | |||
| 624 | struct be_cmd_resp_modify_eq_delay { | ||
| 625 | struct be_cmd_resp_hdr hdr; | ||
| 626 | u32 rsvd0; | ||
| 627 | } __packed; | ||
| 628 | |||
| 629 | /******************** Get FW Config *******************/ | ||
| 630 | struct be_cmd_req_query_fw_cfg { | ||
| 631 | struct be_cmd_req_hdr hdr; | ||
| 632 | u32 rsvd[30]; | ||
| 633 | }; | ||
| 634 | |||
| 635 | struct be_cmd_resp_query_fw_cfg { | ||
| 636 | struct be_cmd_resp_hdr hdr; | ||
| 637 | u32 be_config_number; | ||
| 638 | u32 asic_revision; | ||
| 639 | u32 phys_port; | ||
| 640 | u32 function_mode; | ||
| 641 | u32 rsvd[26]; | ||
| 642 | }; | ||
| 643 | |||
| 644 | extern int be_pci_fnum_get(struct be_ctrl_info *ctrl); | ||
| 645 | extern int be_cmd_POST(struct be_ctrl_info *ctrl); | ||
| 646 | extern int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr, | ||
| 647 | u8 type, bool permanent, u32 if_handle); | ||
| 648 | extern int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr, | ||
| 649 | u32 if_id, u32 *pmac_id); | ||
| 650 | extern int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id); | ||
| 651 | extern int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 if_flags, u8 *mac, | ||
| 652 | bool pmac_invalid, u32 *if_handle, u32 *pmac_id); | ||
| 653 | extern int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 if_handle); | ||
| 654 | extern int be_cmd_eq_create(struct be_ctrl_info *ctrl, | ||
| 655 | struct be_queue_info *eq, int eq_delay); | ||
| 656 | extern int be_cmd_cq_create(struct be_ctrl_info *ctrl, | ||
| 657 | struct be_queue_info *cq, struct be_queue_info *eq, | ||
| 658 | bool sol_evts, bool no_delay, | ||
| 659 | int num_cqe_dma_coalesce); | ||
| 660 | extern int be_cmd_txq_create(struct be_ctrl_info *ctrl, | ||
| 661 | struct be_queue_info *txq, | ||
| 662 | struct be_queue_info *cq); | ||
| 663 | extern int be_cmd_rxq_create(struct be_ctrl_info *ctrl, | ||
| 664 | struct be_queue_info *rxq, u16 cq_id, | ||
| 665 | u16 frag_size, u16 max_frame_size, u32 if_id, | ||
| 666 | u32 rss); | ||
| 667 | extern int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | ||
| 668 | int type); | ||
| 669 | extern int be_cmd_link_status_query(struct be_ctrl_info *ctrl, | ||
| 670 | struct be_link_info *link); | ||
| 671 | extern int be_cmd_reset(struct be_ctrl_info *ctrl); | ||
| 672 | extern int be_cmd_get_stats(struct be_ctrl_info *ctrl, | ||
| 673 | struct be_dma_mem *nonemb_cmd); | ||
| 674 | extern int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver); | ||
| 675 | |||
| 676 | extern int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd); | ||
| 677 | extern int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id, | ||
| 678 | u16 *vtag_array, u32 num, bool untagged, | ||
| 679 | bool promiscuous); | ||
| 680 | extern int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, | ||
| 681 | u8 port_num, bool en); | ||
| 682 | extern int be_cmd_mcast_mac_set(struct be_ctrl_info *ctrl, u32 if_id, | ||
| 683 | u8 *mac_table, u32 num, bool promiscuous); | ||
| 684 | extern int be_cmd_set_flow_control(struct be_ctrl_info *ctrl, | ||
| 685 | u32 tx_fc, u32 rx_fc); | ||
| 686 | extern int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, | ||
| 687 | u32 *tx_fc, u32 *rx_fc); | ||
| 688 | extern int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num); | ||
diff --git a/drivers/net/benet/be_ethtool.c b/drivers/net/benet/be_ethtool.c new file mode 100644 index 000000000000..04f4b73fa8d8 --- /dev/null +++ b/drivers/net/benet/be_ethtool.c | |||
| @@ -0,0 +1,362 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include "be.h" | ||
| 19 | #include <linux/ethtool.h> | ||
| 20 | |||
| 21 | struct be_ethtool_stat { | ||
| 22 | char desc[ETH_GSTRING_LEN]; | ||
| 23 | int type; | ||
| 24 | int size; | ||
| 25 | int offset; | ||
| 26 | }; | ||
| 27 | |||
| 28 | enum {NETSTAT, PORTSTAT, MISCSTAT, DRVSTAT, ERXSTAT}; | ||
| 29 | #define FIELDINFO(_struct, field) FIELD_SIZEOF(_struct, field), \ | ||
| 30 | offsetof(_struct, field) | ||
| 31 | #define NETSTAT_INFO(field) #field, NETSTAT,\ | ||
| 32 | FIELDINFO(struct net_device_stats,\ | ||
| 33 | field) | ||
| 34 | #define DRVSTAT_INFO(field) #field, DRVSTAT,\ | ||
| 35 | FIELDINFO(struct be_drvr_stats, field) | ||
| 36 | #define MISCSTAT_INFO(field) #field, MISCSTAT,\ | ||
| 37 | FIELDINFO(struct be_rxf_stats, field) | ||
| 38 | #define PORTSTAT_INFO(field) #field, PORTSTAT,\ | ||
| 39 | FIELDINFO(struct be_port_rxf_stats, \ | ||
| 40 | field) | ||
| 41 | #define ERXSTAT_INFO(field) #field, ERXSTAT,\ | ||
| 42 | FIELDINFO(struct be_erx_stats, field) | ||
| 43 | |||
| 44 | static const struct be_ethtool_stat et_stats[] = { | ||
| 45 | {NETSTAT_INFO(rx_packets)}, | ||
| 46 | {NETSTAT_INFO(tx_packets)}, | ||
| 47 | {NETSTAT_INFO(rx_bytes)}, | ||
| 48 | {NETSTAT_INFO(tx_bytes)}, | ||
| 49 | {NETSTAT_INFO(rx_errors)}, | ||
| 50 | {NETSTAT_INFO(tx_errors)}, | ||
| 51 | {NETSTAT_INFO(rx_dropped)}, | ||
| 52 | {NETSTAT_INFO(tx_dropped)}, | ||
| 53 | {DRVSTAT_INFO(be_tx_reqs)}, | ||
| 54 | {DRVSTAT_INFO(be_tx_stops)}, | ||
| 55 | {DRVSTAT_INFO(be_fwd_reqs)}, | ||
| 56 | {DRVSTAT_INFO(be_tx_wrbs)}, | ||
| 57 | {DRVSTAT_INFO(be_polls)}, | ||
| 58 | {DRVSTAT_INFO(be_tx_events)}, | ||
| 59 | {DRVSTAT_INFO(be_rx_events)}, | ||
| 60 | {DRVSTAT_INFO(be_tx_compl)}, | ||
| 61 | {DRVSTAT_INFO(be_rx_compl)}, | ||
| 62 | {DRVSTAT_INFO(be_ethrx_post_fail)}, | ||
| 63 | {DRVSTAT_INFO(be_802_3_dropped_frames)}, | ||
| 64 | {DRVSTAT_INFO(be_802_3_malformed_frames)}, | ||
| 65 | {DRVSTAT_INFO(be_tx_rate)}, | ||
| 66 | {DRVSTAT_INFO(be_rx_rate)}, | ||
| 67 | {PORTSTAT_INFO(rx_unicast_frames)}, | ||
| 68 | {PORTSTAT_INFO(rx_multicast_frames)}, | ||
| 69 | {PORTSTAT_INFO(rx_broadcast_frames)}, | ||
| 70 | {PORTSTAT_INFO(rx_crc_errors)}, | ||
| 71 | {PORTSTAT_INFO(rx_alignment_symbol_errors)}, | ||
| 72 | {PORTSTAT_INFO(rx_pause_frames)}, | ||
| 73 | {PORTSTAT_INFO(rx_control_frames)}, | ||
| 74 | {PORTSTAT_INFO(rx_in_range_errors)}, | ||
| 75 | {PORTSTAT_INFO(rx_out_range_errors)}, | ||
| 76 | {PORTSTAT_INFO(rx_frame_too_long)}, | ||
| 77 | {PORTSTAT_INFO(rx_address_match_errors)}, | ||
| 78 | {PORTSTAT_INFO(rx_vlan_mismatch)}, | ||
| 79 | {PORTSTAT_INFO(rx_dropped_too_small)}, | ||
| 80 | {PORTSTAT_INFO(rx_dropped_too_short)}, | ||
| 81 | {PORTSTAT_INFO(rx_dropped_header_too_small)}, | ||
| 82 | {PORTSTAT_INFO(rx_dropped_tcp_length)}, | ||
| 83 | {PORTSTAT_INFO(rx_dropped_runt)}, | ||
| 84 | {PORTSTAT_INFO(rx_fifo_overflow)}, | ||
| 85 | {PORTSTAT_INFO(rx_input_fifo_overflow)}, | ||
| 86 | {PORTSTAT_INFO(rx_ip_checksum_errs)}, | ||
| 87 | {PORTSTAT_INFO(rx_tcp_checksum_errs)}, | ||
| 88 | {PORTSTAT_INFO(rx_udp_checksum_errs)}, | ||
| 89 | {PORTSTAT_INFO(rx_non_rss_packets)}, | ||
| 90 | {PORTSTAT_INFO(rx_ipv4_packets)}, | ||
| 91 | {PORTSTAT_INFO(rx_ipv6_packets)}, | ||
| 92 | {PORTSTAT_INFO(tx_unicastframes)}, | ||
| 93 | {PORTSTAT_INFO(tx_multicastframes)}, | ||
| 94 | {PORTSTAT_INFO(tx_broadcastframes)}, | ||
| 95 | {PORTSTAT_INFO(tx_pauseframes)}, | ||
| 96 | {PORTSTAT_INFO(tx_controlframes)}, | ||
| 97 | {MISCSTAT_INFO(rx_drops_no_pbuf)}, | ||
| 98 | {MISCSTAT_INFO(rx_drops_no_txpb)}, | ||
| 99 | {MISCSTAT_INFO(rx_drops_no_erx_descr)}, | ||
| 100 | {MISCSTAT_INFO(rx_drops_no_tpre_descr)}, | ||
| 101 | {MISCSTAT_INFO(rx_drops_too_many_frags)}, | ||
| 102 | {MISCSTAT_INFO(rx_drops_invalid_ring)}, | ||
| 103 | {MISCSTAT_INFO(forwarded_packets)}, | ||
| 104 | {MISCSTAT_INFO(rx_drops_mtu)}, | ||
| 105 | {ERXSTAT_INFO(rx_drops_no_fragments)}, | ||
| 106 | }; | ||
| 107 | #define ETHTOOL_STATS_NUM ARRAY_SIZE(et_stats) | ||
| 108 | |||
| 109 | static void | ||
| 110 | be_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) | ||
| 111 | { | ||
| 112 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 113 | |||
| 114 | strcpy(drvinfo->driver, DRV_NAME); | ||
| 115 | strcpy(drvinfo->version, DRV_VER); | ||
| 116 | strncpy(drvinfo->fw_version, adapter->fw_ver, FW_VER_LEN); | ||
| 117 | strcpy(drvinfo->bus_info, pci_name(adapter->pdev)); | ||
| 118 | drvinfo->testinfo_len = 0; | ||
| 119 | drvinfo->regdump_len = 0; | ||
| 120 | drvinfo->eedump_len = 0; | ||
| 121 | } | ||
| 122 | |||
| 123 | static int | ||
| 124 | be_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce) | ||
| 125 | { | ||
| 126 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 127 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 128 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 129 | |||
| 130 | coalesce->rx_max_coalesced_frames = adapter->max_rx_coal; | ||
| 131 | |||
| 132 | coalesce->rx_coalesce_usecs = rx_eq->cur_eqd; | ||
| 133 | coalesce->rx_coalesce_usecs_high = rx_eq->max_eqd; | ||
| 134 | coalesce->rx_coalesce_usecs_low = rx_eq->min_eqd; | ||
| 135 | |||
| 136 | coalesce->tx_coalesce_usecs = tx_eq->cur_eqd; | ||
| 137 | coalesce->tx_coalesce_usecs_high = tx_eq->max_eqd; | ||
| 138 | coalesce->tx_coalesce_usecs_low = tx_eq->min_eqd; | ||
| 139 | |||
| 140 | coalesce->use_adaptive_rx_coalesce = rx_eq->enable_aic; | ||
| 141 | coalesce->use_adaptive_tx_coalesce = tx_eq->enable_aic; | ||
| 142 | |||
| 143 | return 0; | ||
| 144 | } | ||
| 145 | |||
| 146 | /* | ||
| 147 | * This routine is used to set interrup coalescing delay *as well as* | ||
| 148 | * the number of pkts to coalesce for LRO. | ||
| 149 | */ | ||
| 150 | static int | ||
| 151 | be_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce) | ||
| 152 | { | ||
| 153 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 154 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 155 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 156 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 157 | u32 tx_max, tx_min, tx_cur; | ||
| 158 | u32 rx_max, rx_min, rx_cur; | ||
| 159 | int status = 0; | ||
| 160 | |||
| 161 | if (coalesce->use_adaptive_tx_coalesce == 1) | ||
| 162 | return -EINVAL; | ||
| 163 | |||
| 164 | adapter->max_rx_coal = coalesce->rx_max_coalesced_frames; | ||
| 165 | if (adapter->max_rx_coal > MAX_SKB_FRAGS) | ||
| 166 | adapter->max_rx_coal = MAX_SKB_FRAGS - 1; | ||
| 167 | |||
| 168 | /* if AIC is being turned on now, start with an EQD of 0 */ | ||
| 169 | if (rx_eq->enable_aic == 0 && | ||
| 170 | coalesce->use_adaptive_rx_coalesce == 1) { | ||
| 171 | rx_eq->cur_eqd = 0; | ||
| 172 | } | ||
| 173 | rx_eq->enable_aic = coalesce->use_adaptive_rx_coalesce; | ||
| 174 | |||
| 175 | rx_max = coalesce->rx_coalesce_usecs_high; | ||
| 176 | rx_min = coalesce->rx_coalesce_usecs_low; | ||
| 177 | rx_cur = coalesce->rx_coalesce_usecs; | ||
| 178 | |||
| 179 | tx_max = coalesce->tx_coalesce_usecs_high; | ||
| 180 | tx_min = coalesce->tx_coalesce_usecs_low; | ||
| 181 | tx_cur = coalesce->tx_coalesce_usecs; | ||
| 182 | |||
| 183 | if (tx_cur > BE_MAX_EQD) | ||
| 184 | tx_cur = BE_MAX_EQD; | ||
| 185 | if (tx_eq->cur_eqd != tx_cur) { | ||
| 186 | status = be_cmd_modify_eqd(ctrl, tx_eq->q.id, tx_cur); | ||
| 187 | if (!status) | ||
| 188 | tx_eq->cur_eqd = tx_cur; | ||
| 189 | } | ||
| 190 | |||
| 191 | if (rx_eq->enable_aic) { | ||
| 192 | if (rx_max > BE_MAX_EQD) | ||
| 193 | rx_max = BE_MAX_EQD; | ||
| 194 | if (rx_min > rx_max) | ||
| 195 | rx_min = rx_max; | ||
| 196 | rx_eq->max_eqd = rx_max; | ||
| 197 | rx_eq->min_eqd = rx_min; | ||
| 198 | if (rx_eq->cur_eqd > rx_max) | ||
| 199 | rx_eq->cur_eqd = rx_max; | ||
| 200 | if (rx_eq->cur_eqd < rx_min) | ||
| 201 | rx_eq->cur_eqd = rx_min; | ||
| 202 | } else { | ||
| 203 | if (rx_cur > BE_MAX_EQD) | ||
| 204 | rx_cur = BE_MAX_EQD; | ||
| 205 | if (rx_eq->cur_eqd != rx_cur) { | ||
| 206 | status = be_cmd_modify_eqd(ctrl, rx_eq->q.id, rx_cur); | ||
| 207 | if (!status) | ||
| 208 | rx_eq->cur_eqd = rx_cur; | ||
| 209 | } | ||
| 210 | } | ||
| 211 | return 0; | ||
| 212 | } | ||
| 213 | |||
| 214 | static u32 be_get_rx_csum(struct net_device *netdev) | ||
| 215 | { | ||
| 216 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 217 | |||
| 218 | return adapter->rx_csum; | ||
| 219 | } | ||
| 220 | |||
| 221 | static int be_set_rx_csum(struct net_device *netdev, uint32_t data) | ||
| 222 | { | ||
| 223 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 224 | |||
| 225 | if (data) | ||
| 226 | adapter->rx_csum = true; | ||
| 227 | else | ||
| 228 | adapter->rx_csum = false; | ||
| 229 | |||
| 230 | return 0; | ||
| 231 | } | ||
| 232 | |||
| 233 | static void | ||
| 234 | be_get_ethtool_stats(struct net_device *netdev, | ||
| 235 | struct ethtool_stats *stats, uint64_t *data) | ||
| 236 | { | ||
| 237 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 238 | struct be_drvr_stats *drvr_stats = &adapter->stats.drvr_stats; | ||
| 239 | struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va); | ||
| 240 | struct be_rxf_stats *rxf_stats = &hw_stats->rxf; | ||
| 241 | struct be_port_rxf_stats *port_stats = | ||
| 242 | &rxf_stats->port[adapter->port_num]; | ||
| 243 | struct net_device_stats *net_stats = &adapter->stats.net_stats; | ||
| 244 | struct be_erx_stats *erx_stats = &hw_stats->erx; | ||
| 245 | void *p = NULL; | ||
| 246 | int i; | ||
| 247 | |||
| 248 | for (i = 0; i < ETHTOOL_STATS_NUM; i++) { | ||
| 249 | switch (et_stats[i].type) { | ||
| 250 | case NETSTAT: | ||
| 251 | p = net_stats; | ||
| 252 | break; | ||
| 253 | case DRVSTAT: | ||
| 254 | p = drvr_stats; | ||
| 255 | break; | ||
| 256 | case PORTSTAT: | ||
| 257 | p = port_stats; | ||
| 258 | break; | ||
| 259 | case MISCSTAT: | ||
| 260 | p = rxf_stats; | ||
| 261 | break; | ||
| 262 | case ERXSTAT: /* Currently only one ERX stat is provided */ | ||
| 263 | p = (u32 *)erx_stats + adapter->rx_obj.q.id; | ||
| 264 | break; | ||
| 265 | } | ||
| 266 | |||
| 267 | p = (u8 *)p + et_stats[i].offset; | ||
| 268 | data[i] = (et_stats[i].size == sizeof(u64)) ? | ||
| 269 | *(u64 *)p: *(u32 *)p; | ||
| 270 | } | ||
| 271 | |||
| 272 | return; | ||
| 273 | } | ||
| 274 | |||
| 275 | static void | ||
| 276 | be_get_stat_strings(struct net_device *netdev, uint32_t stringset, | ||
| 277 | uint8_t *data) | ||
| 278 | { | ||
| 279 | int i; | ||
| 280 | switch (stringset) { | ||
| 281 | case ETH_SS_STATS: | ||
| 282 | for (i = 0; i < ETHTOOL_STATS_NUM; i++) { | ||
| 283 | memcpy(data, et_stats[i].desc, ETH_GSTRING_LEN); | ||
| 284 | data += ETH_GSTRING_LEN; | ||
| 285 | } | ||
| 286 | break; | ||
| 287 | } | ||
| 288 | } | ||
| 289 | |||
| 290 | static int be_get_stats_count(struct net_device *netdev) | ||
| 291 | { | ||
| 292 | return ETHTOOL_STATS_NUM; | ||
| 293 | } | ||
| 294 | |||
| 295 | static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | ||
| 296 | { | ||
| 297 | ecmd->speed = SPEED_10000; | ||
| 298 | ecmd->duplex = DUPLEX_FULL; | ||
| 299 | ecmd->autoneg = AUTONEG_DISABLE; | ||
| 300 | return 0; | ||
| 301 | } | ||
| 302 | |||
| 303 | static void | ||
| 304 | be_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) | ||
| 305 | { | ||
| 306 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 307 | |||
| 308 | ring->rx_max_pending = adapter->rx_obj.q.len; | ||
| 309 | ring->tx_max_pending = adapter->tx_obj.q.len; | ||
| 310 | |||
| 311 | ring->rx_pending = atomic_read(&adapter->rx_obj.q.used); | ||
| 312 | ring->tx_pending = atomic_read(&adapter->tx_obj.q.used); | ||
| 313 | } | ||
| 314 | |||
| 315 | static void | ||
| 316 | be_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd) | ||
| 317 | { | ||
| 318 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 319 | |||
| 320 | be_cmd_get_flow_control(&adapter->ctrl, &ecmd->tx_pause, | ||
| 321 | &ecmd->rx_pause); | ||
| 322 | ecmd->autoneg = AUTONEG_ENABLE; | ||
| 323 | } | ||
| 324 | |||
| 325 | static int | ||
| 326 | be_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd) | ||
| 327 | { | ||
| 328 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 329 | int status; | ||
| 330 | |||
| 331 | if (ecmd->autoneg != AUTONEG_ENABLE) | ||
| 332 | return -EINVAL; | ||
| 333 | |||
| 334 | status = be_cmd_set_flow_control(&adapter->ctrl, ecmd->tx_pause, | ||
| 335 | ecmd->rx_pause); | ||
| 336 | if (!status) | ||
| 337 | dev_warn(&adapter->pdev->dev, "Pause param set failed.\n"); | ||
| 338 | |||
| 339 | return status; | ||
| 340 | } | ||
| 341 | |||
| 342 | struct ethtool_ops be_ethtool_ops = { | ||
| 343 | .get_settings = be_get_settings, | ||
| 344 | .get_drvinfo = be_get_drvinfo, | ||
| 345 | .get_link = ethtool_op_get_link, | ||
| 346 | .get_coalesce = be_get_coalesce, | ||
| 347 | .set_coalesce = be_set_coalesce, | ||
| 348 | .get_ringparam = be_get_ringparam, | ||
| 349 | .get_pauseparam = be_get_pauseparam, | ||
| 350 | .set_pauseparam = be_set_pauseparam, | ||
| 351 | .get_rx_csum = be_get_rx_csum, | ||
| 352 | .set_rx_csum = be_set_rx_csum, | ||
| 353 | .get_tx_csum = ethtool_op_get_tx_csum, | ||
| 354 | .set_tx_csum = ethtool_op_set_tx_csum, | ||
| 355 | .get_sg = ethtool_op_get_sg, | ||
| 356 | .set_sg = ethtool_op_set_sg, | ||
| 357 | .get_tso = ethtool_op_get_tso, | ||
| 358 | .set_tso = ethtool_op_set_tso, | ||
| 359 | .get_strings = be_get_stat_strings, | ||
| 360 | .get_stats_count = be_get_stats_count, | ||
| 361 | .get_ethtool_stats = be_get_ethtool_stats, | ||
| 362 | }; | ||
diff --git a/drivers/net/benet/be_hw.h b/drivers/net/benet/be_hw.h new file mode 100644 index 000000000000..b132aa4893ca --- /dev/null +++ b/drivers/net/benet/be_hw.h | |||
| @@ -0,0 +1,211 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | /********* Mailbox door bell *************/ | ||
| 19 | /* Used for driver communication with the FW. | ||
| 20 | * The software must write this register twice to post any command. First, | ||
| 21 | * it writes the register with hi=1 and the upper bits of the physical address | ||
| 22 | * for the MAILBOX structure. Software must poll the ready bit until this | ||
| 23 | * is acknowledged. Then, sotware writes the register with hi=0 with the lower | ||
| 24 | * bits in the address. It must poll the ready bit until the command is | ||
| 25 | * complete. Upon completion, the MAILBOX will contain a valid completion | ||
| 26 | * queue entry. | ||
| 27 | */ | ||
| 28 | #define MPU_MAILBOX_DB_OFFSET 0x160 | ||
| 29 | #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */ | ||
| 30 | #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */ | ||
| 31 | |||
| 32 | #define MPU_EP_CONTROL 0 | ||
| 33 | |||
| 34 | /********** MPU semphore ******************/ | ||
| 35 | #define MPU_EP_SEMAPHORE_OFFSET 0xac | ||
| 36 | #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF | ||
| 37 | #define EP_SEMAPHORE_POST_ERR_MASK 0x1 | ||
| 38 | #define EP_SEMAPHORE_POST_ERR_SHIFT 31 | ||
| 39 | /* MPU semphore POST stage values */ | ||
| 40 | #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */ | ||
| 41 | #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */ | ||
| 42 | #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */ | ||
| 43 | #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ | ||
| 44 | |||
| 45 | /********* Memory BAR register ************/ | ||
| 46 | #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc | ||
| 47 | /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt | ||
| 48 | * Disable" may still globally block interrupts in addition to individual | ||
| 49 | * interrupt masks; a mechanism for the device driver to block all interrupts | ||
| 50 | * atomically without having to arbitrate for the PCI Interrupt Disable bit | ||
| 51 | * with the OS. | ||
| 52 | */ | ||
| 53 | #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ | ||
| 54 | /* PCI physical function number */ | ||
| 55 | #define MEMBAR_CTRL_INT_CTRL_PFUNC_MASK 0x7 /* bits 26 - 28 */ | ||
| 56 | #define MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT 26 | ||
| 57 | |||
| 58 | /********* Event Q door bell *************/ | ||
| 59 | #define DB_EQ_OFFSET DB_CQ_OFFSET | ||
| 60 | #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ | ||
| 61 | /* Clear the interrupt for this eq */ | ||
| 62 | #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ | ||
| 63 | /* Must be 1 */ | ||
| 64 | #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ | ||
| 65 | /* Number of event entries processed */ | ||
| 66 | #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ | ||
| 67 | /* Rearm bit */ | ||
| 68 | #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ | ||
| 69 | |||
| 70 | /********* Compl Q door bell *************/ | ||
| 71 | #define DB_CQ_OFFSET 0x120 | ||
| 72 | #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ | ||
| 73 | /* Number of event entries processed */ | ||
| 74 | #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ | ||
| 75 | /* Rearm bit */ | ||
| 76 | #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ | ||
| 77 | |||
| 78 | /********** TX ULP door bell *************/ | ||
| 79 | #define DB_TXULP1_OFFSET 0x60 | ||
| 80 | #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */ | ||
| 81 | /* Number of tx entries posted */ | ||
| 82 | #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ | ||
| 83 | #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */ | ||
| 84 | |||
| 85 | /********** RQ(erx) door bell ************/ | ||
| 86 | #define DB_RQ_OFFSET 0x100 | ||
| 87 | #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ | ||
| 88 | /* Number of rx frags posted */ | ||
| 89 | #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */ | ||
| 90 | |||
| 91 | /* | ||
| 92 | * BE descriptors: host memory data structures whose formats | ||
| 93 | * are hardwired in BE silicon. | ||
| 94 | */ | ||
| 95 | /* Event Queue Descriptor */ | ||
| 96 | #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */ | ||
| 97 | #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */ | ||
| 98 | #define EQ_ENTRY_RES_ID_SHIFT 16 | ||
| 99 | struct be_eq_entry { | ||
| 100 | u32 evt; | ||
| 101 | }; | ||
| 102 | |||
| 103 | /* TX Queue Descriptor */ | ||
| 104 | #define ETH_WRB_FRAG_LEN_MASK 0xFFFF | ||
| 105 | struct be_eth_wrb { | ||
| 106 | u32 frag_pa_hi; /* dword 0 */ | ||
| 107 | u32 frag_pa_lo; /* dword 1 */ | ||
| 108 | u32 rsvd0; /* dword 2 */ | ||
| 109 | u32 frag_len; /* dword 3: bits 0 - 15 */ | ||
| 110 | } __packed; | ||
| 111 | |||
| 112 | /* Pseudo amap definition for eth_hdr_wrb in which each bit of the | ||
| 113 | * actual structure is defined as a byte : used to calculate | ||
| 114 | * offset/shift/mask of each field */ | ||
| 115 | struct amap_eth_hdr_wrb { | ||
| 116 | u8 rsvd0[32]; /* dword 0 */ | ||
| 117 | u8 rsvd1[32]; /* dword 1 */ | ||
| 118 | u8 complete; /* dword 2 */ | ||
| 119 | u8 event; | ||
| 120 | u8 crc; | ||
| 121 | u8 forward; | ||
| 122 | u8 ipsec; | ||
| 123 | u8 mgmt; | ||
| 124 | u8 ipcs; | ||
| 125 | u8 udpcs; | ||
| 126 | u8 tcpcs; | ||
| 127 | u8 lso; | ||
| 128 | u8 vlan; | ||
| 129 | u8 gso[2]; | ||
| 130 | u8 num_wrb[5]; | ||
| 131 | u8 lso_mss[14]; | ||
| 132 | u8 len[16]; /* dword 3 */ | ||
| 133 | u8 vlan_tag[16]; | ||
| 134 | } __packed; | ||
| 135 | |||
| 136 | struct be_eth_hdr_wrb { | ||
| 137 | u32 dw[4]; | ||
| 138 | }; | ||
| 139 | |||
| 140 | /* TX Compl Queue Descriptor */ | ||
| 141 | |||
| 142 | /* Pseudo amap definition for eth_tx_compl in which each bit of the | ||
| 143 | * actual structure is defined as a byte: used to calculate | ||
| 144 | * offset/shift/mask of each field */ | ||
| 145 | struct amap_eth_tx_compl { | ||
| 146 | u8 wrb_index[16]; /* dword 0 */ | ||
| 147 | u8 ct[2]; /* dword 0 */ | ||
| 148 | u8 port[2]; /* dword 0 */ | ||
| 149 | u8 rsvd0[8]; /* dword 0 */ | ||
| 150 | u8 status[4]; /* dword 0 */ | ||
| 151 | u8 user_bytes[16]; /* dword 1 */ | ||
| 152 | u8 nwh_bytes[8]; /* dword 1 */ | ||
| 153 | u8 lso; /* dword 1 */ | ||
| 154 | u8 cast_enc[2]; /* dword 1 */ | ||
| 155 | u8 rsvd1[5]; /* dword 1 */ | ||
| 156 | u8 rsvd2[32]; /* dword 2 */ | ||
| 157 | u8 pkts[16]; /* dword 3 */ | ||
| 158 | u8 ringid[11]; /* dword 3 */ | ||
| 159 | u8 hash_val[4]; /* dword 3 */ | ||
| 160 | u8 valid; /* dword 3 */ | ||
| 161 | } __packed; | ||
| 162 | |||
| 163 | struct be_eth_tx_compl { | ||
| 164 | u32 dw[4]; | ||
| 165 | }; | ||
| 166 | |||
| 167 | /* RX Queue Descriptor */ | ||
| 168 | struct be_eth_rx_d { | ||
| 169 | u32 fragpa_hi; | ||
| 170 | u32 fragpa_lo; | ||
| 171 | }; | ||
| 172 | |||
| 173 | /* RX Compl Queue Descriptor */ | ||
| 174 | |||
| 175 | /* Pseudo amap definition for eth_rx_compl in which each bit of the | ||
| 176 | * actual structure is defined as a byte: used to calculate | ||
| 177 | * offset/shift/mask of each field */ | ||
| 178 | struct amap_eth_rx_compl { | ||
| 179 | u8 vlan_tag[16]; /* dword 0 */ | ||
| 180 | u8 pktsize[14]; /* dword 0 */ | ||
| 181 | u8 port; /* dword 0 */ | ||
| 182 | u8 ip_opt; /* dword 0 */ | ||
| 183 | u8 err; /* dword 1 */ | ||
| 184 | u8 rsshp; /* dword 1 */ | ||
| 185 | u8 ipf; /* dword 1 */ | ||
| 186 | u8 tcpf; /* dword 1 */ | ||
| 187 | u8 udpf; /* dword 1 */ | ||
| 188 | u8 ipcksm; /* dword 1 */ | ||
| 189 | u8 l4_cksm; /* dword 1 */ | ||
| 190 | u8 ip_version; /* dword 1 */ | ||
| 191 | u8 macdst[6]; /* dword 1 */ | ||
| 192 | u8 vtp; /* dword 1 */ | ||
| 193 | u8 rsvd0; /* dword 1 */ | ||
| 194 | u8 fragndx[10]; /* dword 1 */ | ||
| 195 | u8 ct[2]; /* dword 1 */ | ||
| 196 | u8 sw; /* dword 1 */ | ||
| 197 | u8 numfrags[3]; /* dword 1 */ | ||
| 198 | u8 rss_flush; /* dword 2 */ | ||
| 199 | u8 cast_enc[2]; /* dword 2 */ | ||
| 200 | u8 qnq; /* dword 2 */ | ||
| 201 | u8 rss_bank; /* dword 2 */ | ||
| 202 | u8 rsvd1[23]; /* dword 2 */ | ||
| 203 | u8 lro_pkt; /* dword 2 */ | ||
| 204 | u8 rsvd2[2]; /* dword 2 */ | ||
| 205 | u8 valid; /* dword 2 */ | ||
| 206 | u8 rsshash[32]; /* dword 3 */ | ||
| 207 | } __packed; | ||
| 208 | |||
| 209 | struct be_eth_rx_compl { | ||
| 210 | u32 dw[4]; | ||
| 211 | }; | ||
diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c new file mode 100644 index 000000000000..897a63de5bdb --- /dev/null +++ b/drivers/net/benet/be_main.c | |||
| @@ -0,0 +1,1903 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include "be.h" | ||
| 19 | |||
| 20 | MODULE_VERSION(DRV_VER); | ||
| 21 | MODULE_DEVICE_TABLE(pci, be_dev_ids); | ||
| 22 | MODULE_DESCRIPTION(DRV_DESC " " DRV_VER); | ||
| 23 | MODULE_AUTHOR("ServerEngines Corporation"); | ||
| 24 | MODULE_LICENSE("GPL"); | ||
| 25 | |||
| 26 | static unsigned int rx_frag_size = 2048; | ||
| 27 | module_param(rx_frag_size, uint, S_IRUGO); | ||
| 28 | MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data."); | ||
| 29 | |||
| 30 | #define BE_VENDOR_ID 0x19a2 | ||
| 31 | #define BE2_DEVICE_ID_1 0x0211 | ||
| 32 | static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = { | ||
| 33 | { PCI_DEVICE(BE_VENDOR_ID, BE2_DEVICE_ID_1) }, | ||
| 34 | { 0 } | ||
| 35 | }; | ||
| 36 | MODULE_DEVICE_TABLE(pci, be_dev_ids); | ||
| 37 | |||
| 38 | static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q) | ||
| 39 | { | ||
| 40 | struct be_dma_mem *mem = &q->dma_mem; | ||
| 41 | if (mem->va) | ||
| 42 | pci_free_consistent(adapter->pdev, mem->size, | ||
| 43 | mem->va, mem->dma); | ||
| 44 | } | ||
| 45 | |||
| 46 | static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q, | ||
| 47 | u16 len, u16 entry_size) | ||
| 48 | { | ||
| 49 | struct be_dma_mem *mem = &q->dma_mem; | ||
| 50 | |||
| 51 | memset(q, 0, sizeof(*q)); | ||
| 52 | q->len = len; | ||
| 53 | q->entry_size = entry_size; | ||
| 54 | mem->size = len * entry_size; | ||
| 55 | mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma); | ||
| 56 | if (!mem->va) | ||
| 57 | return -1; | ||
| 58 | memset(mem->va, 0, mem->size); | ||
| 59 | return 0; | ||
| 60 | } | ||
| 61 | |||
| 62 | static inline void *queue_head_node(struct be_queue_info *q) | ||
| 63 | { | ||
| 64 | return q->dma_mem.va + q->head * q->entry_size; | ||
| 65 | } | ||
| 66 | |||
| 67 | static inline void *queue_tail_node(struct be_queue_info *q) | ||
| 68 | { | ||
| 69 | return q->dma_mem.va + q->tail * q->entry_size; | ||
| 70 | } | ||
| 71 | |||
| 72 | static inline void queue_head_inc(struct be_queue_info *q) | ||
| 73 | { | ||
| 74 | index_inc(&q->head, q->len); | ||
| 75 | } | ||
| 76 | |||
| 77 | static inline void queue_tail_inc(struct be_queue_info *q) | ||
| 78 | { | ||
| 79 | index_inc(&q->tail, q->len); | ||
| 80 | } | ||
| 81 | |||
| 82 | static void be_intr_set(struct be_ctrl_info *ctrl, bool enable) | ||
| 83 | { | ||
| 84 | u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET; | ||
| 85 | u32 reg = ioread32(addr); | ||
| 86 | u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | ||
| 87 | if (!enabled && enable) { | ||
| 88 | reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | ||
| 89 | } else if (enabled && !enable) { | ||
| 90 | reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | ||
| 91 | } else { | ||
| 92 | printk(KERN_WARNING DRV_NAME | ||
| 93 | ": bad value in membar_int_ctrl reg=0x%x\n", reg); | ||
| 94 | return; | ||
| 95 | } | ||
| 96 | iowrite32(reg, addr); | ||
| 97 | } | ||
| 98 | |||
| 99 | static void be_rxq_notify(struct be_ctrl_info *ctrl, u16 qid, u16 posted) | ||
| 100 | { | ||
| 101 | u32 val = 0; | ||
| 102 | val |= qid & DB_RQ_RING_ID_MASK; | ||
| 103 | val |= posted << DB_RQ_NUM_POSTED_SHIFT; | ||
| 104 | iowrite32(val, ctrl->db + DB_RQ_OFFSET); | ||
| 105 | } | ||
| 106 | |||
| 107 | static void be_txq_notify(struct be_ctrl_info *ctrl, u16 qid, u16 posted) | ||
| 108 | { | ||
| 109 | u32 val = 0; | ||
| 110 | val |= qid & DB_TXULP_RING_ID_MASK; | ||
| 111 | val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT; | ||
| 112 | iowrite32(val, ctrl->db + DB_TXULP1_OFFSET); | ||
| 113 | } | ||
| 114 | |||
| 115 | static void be_eq_notify(struct be_ctrl_info *ctrl, u16 qid, | ||
| 116 | bool arm, bool clear_int, u16 num_popped) | ||
| 117 | { | ||
| 118 | u32 val = 0; | ||
| 119 | val |= qid & DB_EQ_RING_ID_MASK; | ||
| 120 | if (arm) | ||
| 121 | val |= 1 << DB_EQ_REARM_SHIFT; | ||
| 122 | if (clear_int) | ||
| 123 | val |= 1 << DB_EQ_CLR_SHIFT; | ||
| 124 | val |= 1 << DB_EQ_EVNT_SHIFT; | ||
| 125 | val |= num_popped << DB_EQ_NUM_POPPED_SHIFT; | ||
| 126 | iowrite32(val, ctrl->db + DB_EQ_OFFSET); | ||
| 127 | } | ||
| 128 | |||
| 129 | static void be_cq_notify(struct be_ctrl_info *ctrl, u16 qid, | ||
| 130 | bool arm, u16 num_popped) | ||
| 131 | { | ||
| 132 | u32 val = 0; | ||
| 133 | val |= qid & DB_CQ_RING_ID_MASK; | ||
| 134 | if (arm) | ||
| 135 | val |= 1 << DB_CQ_REARM_SHIFT; | ||
| 136 | val |= num_popped << DB_CQ_NUM_POPPED_SHIFT; | ||
| 137 | iowrite32(val, ctrl->db + DB_CQ_OFFSET); | ||
| 138 | } | ||
| 139 | |||
| 140 | |||
| 141 | static int be_mac_addr_set(struct net_device *netdev, void *p) | ||
| 142 | { | ||
| 143 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 144 | struct sockaddr *addr = p; | ||
| 145 | int status = 0; | ||
| 146 | |||
| 147 | if (netif_running(netdev)) { | ||
| 148 | status = be_cmd_pmac_del(&adapter->ctrl, adapter->if_handle, | ||
| 149 | adapter->pmac_id); | ||
| 150 | if (status) | ||
| 151 | return status; | ||
| 152 | |||
| 153 | status = be_cmd_pmac_add(&adapter->ctrl, (u8 *)addr->sa_data, | ||
| 154 | adapter->if_handle, &adapter->pmac_id); | ||
| 155 | } | ||
| 156 | |||
| 157 | if (!status) | ||
| 158 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | ||
| 159 | |||
| 160 | return status; | ||
| 161 | } | ||
| 162 | |||
| 163 | static void netdev_stats_update(struct be_adapter *adapter) | ||
| 164 | { | ||
| 165 | struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va); | ||
| 166 | struct be_rxf_stats *rxf_stats = &hw_stats->rxf; | ||
| 167 | struct be_port_rxf_stats *port_stats = | ||
| 168 | &rxf_stats->port[adapter->port_num]; | ||
| 169 | struct net_device_stats *dev_stats = &adapter->stats.net_stats; | ||
| 170 | |||
| 171 | dev_stats->rx_packets = port_stats->rx_total_frames; | ||
| 172 | dev_stats->tx_packets = port_stats->tx_unicastframes + | ||
| 173 | port_stats->tx_multicastframes + port_stats->tx_broadcastframes; | ||
| 174 | dev_stats->rx_bytes = (u64) port_stats->rx_bytes_msd << 32 | | ||
| 175 | (u64) port_stats->rx_bytes_lsd; | ||
| 176 | dev_stats->tx_bytes = (u64) port_stats->tx_bytes_msd << 32 | | ||
| 177 | (u64) port_stats->tx_bytes_lsd; | ||
| 178 | |||
| 179 | /* bad pkts received */ | ||
| 180 | dev_stats->rx_errors = port_stats->rx_crc_errors + | ||
| 181 | port_stats->rx_alignment_symbol_errors + | ||
| 182 | port_stats->rx_in_range_errors + | ||
| 183 | port_stats->rx_out_range_errors + port_stats->rx_frame_too_long; | ||
| 184 | |||
| 185 | /* packet transmit problems */ | ||
| 186 | dev_stats->tx_errors = 0; | ||
| 187 | |||
| 188 | /* no space in linux buffers */ | ||
| 189 | dev_stats->rx_dropped = 0; | ||
| 190 | |||
| 191 | /* no space available in linux */ | ||
| 192 | dev_stats->tx_dropped = 0; | ||
| 193 | |||
| 194 | dev_stats->multicast = port_stats->tx_multicastframes; | ||
| 195 | dev_stats->collisions = 0; | ||
| 196 | |||
| 197 | /* detailed rx errors */ | ||
| 198 | dev_stats->rx_length_errors = port_stats->rx_in_range_errors + | ||
| 199 | port_stats->rx_out_range_errors + port_stats->rx_frame_too_long; | ||
| 200 | /* receive ring buffer overflow */ | ||
| 201 | dev_stats->rx_over_errors = 0; | ||
| 202 | dev_stats->rx_crc_errors = port_stats->rx_crc_errors; | ||
| 203 | |||
| 204 | /* frame alignment errors */ | ||
| 205 | dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors; | ||
| 206 | /* receiver fifo overrun */ | ||
| 207 | /* drops_no_pbuf is no per i/f, it's per BE card */ | ||
| 208 | dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow + | ||
| 209 | port_stats->rx_input_fifo_overflow + | ||
| 210 | rxf_stats->rx_drops_no_pbuf; | ||
| 211 | /* receiver missed packetd */ | ||
| 212 | dev_stats->rx_missed_errors = 0; | ||
| 213 | /* detailed tx_errors */ | ||
| 214 | dev_stats->tx_aborted_errors = 0; | ||
| 215 | dev_stats->tx_carrier_errors = 0; | ||
| 216 | dev_stats->tx_fifo_errors = 0; | ||
| 217 | dev_stats->tx_heartbeat_errors = 0; | ||
| 218 | dev_stats->tx_window_errors = 0; | ||
| 219 | } | ||
| 220 | |||
| 221 | static void be_link_status_update(struct be_adapter *adapter) | ||
| 222 | { | ||
| 223 | struct be_link_info *prev = &adapter->link; | ||
| 224 | struct be_link_info now = { 0 }; | ||
| 225 | struct net_device *netdev = adapter->netdev; | ||
| 226 | |||
| 227 | be_cmd_link_status_query(&adapter->ctrl, &now); | ||
| 228 | |||
| 229 | /* If link came up or went down */ | ||
| 230 | if (now.speed != prev->speed && (now.speed == PHY_LINK_SPEED_ZERO || | ||
| 231 | prev->speed == PHY_LINK_SPEED_ZERO)) { | ||
| 232 | if (now.speed == PHY_LINK_SPEED_ZERO) { | ||
| 233 | netif_stop_queue(netdev); | ||
| 234 | netif_carrier_off(netdev); | ||
| 235 | printk(KERN_INFO "%s: Link down\n", netdev->name); | ||
| 236 | } else { | ||
| 237 | netif_start_queue(netdev); | ||
| 238 | netif_carrier_on(netdev); | ||
| 239 | printk(KERN_INFO "%s: Link up\n", netdev->name); | ||
| 240 | } | ||
| 241 | } | ||
| 242 | *prev = now; | ||
| 243 | } | ||
| 244 | |||
| 245 | /* Update the EQ delay n BE based on the RX frags consumed / sec */ | ||
| 246 | static void be_rx_eqd_update(struct be_adapter *adapter) | ||
| 247 | { | ||
| 248 | u32 eqd; | ||
| 249 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 250 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 251 | struct be_drvr_stats *stats = &adapter->stats.drvr_stats; | ||
| 252 | |||
| 253 | /* Update once a second */ | ||
| 254 | if (((jiffies - stats->rx_fps_jiffies) < HZ) || rx_eq->enable_aic == 0) | ||
| 255 | return; | ||
| 256 | |||
| 257 | stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) / | ||
| 258 | ((jiffies - stats->rx_fps_jiffies) / HZ); | ||
| 259 | |||
| 260 | stats->rx_fps_jiffies = jiffies; | ||
| 261 | stats->be_prev_rx_frags = stats->be_rx_frags; | ||
| 262 | eqd = stats->be_rx_fps / 110000; | ||
| 263 | eqd = eqd << 3; | ||
| 264 | if (eqd > rx_eq->max_eqd) | ||
| 265 | eqd = rx_eq->max_eqd; | ||
| 266 | if (eqd < rx_eq->min_eqd) | ||
| 267 | eqd = rx_eq->min_eqd; | ||
| 268 | if (eqd < 10) | ||
| 269 | eqd = 0; | ||
| 270 | if (eqd != rx_eq->cur_eqd) | ||
| 271 | be_cmd_modify_eqd(ctrl, rx_eq->q.id, eqd); | ||
| 272 | |||
| 273 | rx_eq->cur_eqd = eqd; | ||
| 274 | } | ||
| 275 | |||
| 276 | static void be_worker(struct work_struct *work) | ||
| 277 | { | ||
| 278 | struct be_adapter *adapter = | ||
| 279 | container_of(work, struct be_adapter, work.work); | ||
| 280 | int status; | ||
| 281 | |||
| 282 | /* Check link */ | ||
| 283 | be_link_status_update(adapter); | ||
| 284 | |||
| 285 | /* Get Stats */ | ||
| 286 | status = be_cmd_get_stats(&adapter->ctrl, &adapter->stats.cmd); | ||
| 287 | if (!status) | ||
| 288 | netdev_stats_update(adapter); | ||
| 289 | |||
| 290 | /* Set EQ delay */ | ||
| 291 | be_rx_eqd_update(adapter); | ||
| 292 | |||
| 293 | schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000)); | ||
| 294 | } | ||
| 295 | |||
| 296 | static struct net_device_stats *be_get_stats(struct net_device *dev) | ||
| 297 | { | ||
| 298 | struct be_adapter *adapter = netdev_priv(dev); | ||
| 299 | |||
| 300 | return &adapter->stats.net_stats; | ||
| 301 | } | ||
| 302 | |||
| 303 | static void be_tx_stats_update(struct be_adapter *adapter, | ||
| 304 | u32 wrb_cnt, u32 copied, bool stopped) | ||
| 305 | { | ||
| 306 | struct be_drvr_stats *stats = &adapter->stats.drvr_stats; | ||
| 307 | stats->be_tx_reqs++; | ||
| 308 | stats->be_tx_wrbs += wrb_cnt; | ||
| 309 | stats->be_tx_bytes += copied; | ||
| 310 | if (stopped) | ||
| 311 | stats->be_tx_stops++; | ||
| 312 | |||
| 313 | /* Update tx rate once in two seconds */ | ||
| 314 | if ((jiffies - stats->be_tx_jiffies) > 2 * HZ) { | ||
| 315 | u32 r; | ||
| 316 | r = (stats->be_tx_bytes - stats->be_tx_bytes_prev) / | ||
| 317 | ((u32) (jiffies - stats->be_tx_jiffies) / HZ); | ||
| 318 | r = (r / 1000000); /* M bytes/s */ | ||
| 319 | stats->be_tx_rate = (r * 8); /* M bits/s */ | ||
| 320 | stats->be_tx_jiffies = jiffies; | ||
| 321 | stats->be_tx_bytes_prev = stats->be_tx_bytes; | ||
| 322 | } | ||
| 323 | } | ||
| 324 | |||
| 325 | /* Determine number of WRB entries needed to xmit data in an skb */ | ||
| 326 | static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy) | ||
| 327 | { | ||
| 328 | int cnt = 0; | ||
| 329 | while (skb) { | ||
| 330 | if (skb->len > skb->data_len) | ||
| 331 | cnt++; | ||
| 332 | cnt += skb_shinfo(skb)->nr_frags; | ||
| 333 | skb = skb_shinfo(skb)->frag_list; | ||
| 334 | } | ||
| 335 | /* to account for hdr wrb */ | ||
| 336 | cnt++; | ||
| 337 | if (cnt & 1) { | ||
| 338 | /* add a dummy to make it an even num */ | ||
| 339 | cnt++; | ||
| 340 | *dummy = true; | ||
| 341 | } else | ||
| 342 | *dummy = false; | ||
| 343 | BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT); | ||
| 344 | return cnt; | ||
| 345 | } | ||
| 346 | |||
| 347 | static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len) | ||
| 348 | { | ||
| 349 | wrb->frag_pa_hi = upper_32_bits(addr); | ||
| 350 | wrb->frag_pa_lo = addr & 0xFFFFFFFF; | ||
| 351 | wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK; | ||
| 352 | } | ||
| 353 | |||
| 354 | static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb, | ||
| 355 | bool vlan, u32 wrb_cnt, u32 len) | ||
| 356 | { | ||
| 357 | memset(hdr, 0, sizeof(*hdr)); | ||
| 358 | |||
| 359 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1); | ||
| 360 | |||
| 361 | if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) { | ||
| 362 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1); | ||
| 363 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss, | ||
| 364 | hdr, skb_shinfo(skb)->gso_size); | ||
| 365 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | ||
| 366 | if (is_tcp_pkt(skb)) | ||
| 367 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1); | ||
| 368 | else if (is_udp_pkt(skb)) | ||
| 369 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1); | ||
| 370 | } | ||
| 371 | |||
| 372 | if (vlan && vlan_tx_tag_present(skb)) { | ||
| 373 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1); | ||
| 374 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, | ||
| 375 | hdr, vlan_tx_tag_get(skb)); | ||
| 376 | } | ||
| 377 | |||
| 378 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1); | ||
| 379 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1); | ||
| 380 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt); | ||
| 381 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len); | ||
| 382 | } | ||
| 383 | |||
| 384 | |||
| 385 | static int make_tx_wrbs(struct be_adapter *adapter, | ||
| 386 | struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb) | ||
| 387 | { | ||
| 388 | u64 busaddr; | ||
| 389 | u32 i, copied = 0; | ||
| 390 | struct pci_dev *pdev = adapter->pdev; | ||
| 391 | struct sk_buff *first_skb = skb; | ||
| 392 | struct be_queue_info *txq = &adapter->tx_obj.q; | ||
| 393 | struct be_eth_wrb *wrb; | ||
| 394 | struct be_eth_hdr_wrb *hdr; | ||
| 395 | |||
| 396 | atomic_add(wrb_cnt, &txq->used); | ||
| 397 | hdr = queue_head_node(txq); | ||
| 398 | queue_head_inc(txq); | ||
| 399 | |||
| 400 | while (skb) { | ||
| 401 | if (skb->len > skb->data_len) { | ||
| 402 | int len = skb->len - skb->data_len; | ||
| 403 | busaddr = pci_map_single(pdev, skb->data, len, | ||
| 404 | PCI_DMA_TODEVICE); | ||
| 405 | wrb = queue_head_node(txq); | ||
| 406 | wrb_fill(wrb, busaddr, len); | ||
| 407 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | ||
| 408 | queue_head_inc(txq); | ||
| 409 | copied += len; | ||
| 410 | } | ||
| 411 | |||
| 412 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | ||
| 413 | struct skb_frag_struct *frag = | ||
| 414 | &skb_shinfo(skb)->frags[i]; | ||
| 415 | busaddr = pci_map_page(pdev, frag->page, | ||
| 416 | frag->page_offset, | ||
| 417 | frag->size, PCI_DMA_TODEVICE); | ||
| 418 | wrb = queue_head_node(txq); | ||
| 419 | wrb_fill(wrb, busaddr, frag->size); | ||
| 420 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | ||
| 421 | queue_head_inc(txq); | ||
| 422 | copied += frag->size; | ||
| 423 | } | ||
| 424 | skb = skb_shinfo(skb)->frag_list; | ||
| 425 | } | ||
| 426 | |||
| 427 | if (dummy_wrb) { | ||
| 428 | wrb = queue_head_node(txq); | ||
| 429 | wrb_fill(wrb, 0, 0); | ||
| 430 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | ||
| 431 | queue_head_inc(txq); | ||
| 432 | } | ||
| 433 | |||
| 434 | wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false, | ||
| 435 | wrb_cnt, copied); | ||
| 436 | be_dws_cpu_to_le(hdr, sizeof(*hdr)); | ||
| 437 | |||
| 438 | return copied; | ||
| 439 | } | ||
| 440 | |||
| 441 | static int be_xmit(struct sk_buff *skb, struct net_device *netdev) | ||
| 442 | { | ||
| 443 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 444 | struct be_tx_obj *tx_obj = &adapter->tx_obj; | ||
| 445 | struct be_queue_info *txq = &tx_obj->q; | ||
| 446 | u32 wrb_cnt = 0, copied = 0; | ||
| 447 | u32 start = txq->head; | ||
| 448 | bool dummy_wrb, stopped = false; | ||
| 449 | |||
| 450 | wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb); | ||
| 451 | |||
| 452 | copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb); | ||
| 453 | |||
| 454 | /* record the sent skb in the sent_skb table */ | ||
| 455 | BUG_ON(tx_obj->sent_skb_list[start]); | ||
| 456 | tx_obj->sent_skb_list[start] = skb; | ||
| 457 | |||
| 458 | /* Ensure that txq has space for the next skb; Else stop the queue | ||
| 459 | * *BEFORE* ringing the tx doorbell, so that we serialze the | ||
| 460 | * tx compls of the current transmit which'll wake up the queue | ||
| 461 | */ | ||
| 462 | if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >= txq->len) { | ||
| 463 | netif_stop_queue(netdev); | ||
| 464 | stopped = true; | ||
| 465 | } | ||
| 466 | |||
| 467 | be_txq_notify(&adapter->ctrl, txq->id, wrb_cnt); | ||
| 468 | |||
| 469 | netdev->trans_start = jiffies; | ||
| 470 | |||
| 471 | be_tx_stats_update(adapter, wrb_cnt, copied, stopped); | ||
| 472 | return NETDEV_TX_OK; | ||
| 473 | } | ||
| 474 | |||
| 475 | static int be_change_mtu(struct net_device *netdev, int new_mtu) | ||
| 476 | { | ||
| 477 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 478 | if (new_mtu < BE_MIN_MTU || | ||
| 479 | new_mtu > BE_MAX_JUMBO_FRAME_SIZE) { | ||
| 480 | dev_info(&adapter->pdev->dev, | ||
| 481 | "MTU must be between %d and %d bytes\n", | ||
| 482 | BE_MIN_MTU, BE_MAX_JUMBO_FRAME_SIZE); | ||
| 483 | return -EINVAL; | ||
| 484 | } | ||
| 485 | dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n", | ||
| 486 | netdev->mtu, new_mtu); | ||
| 487 | netdev->mtu = new_mtu; | ||
| 488 | return 0; | ||
| 489 | } | ||
| 490 | |||
| 491 | /* | ||
| 492 | * if there are BE_NUM_VLANS_SUPPORTED or lesser number of VLANS configured, | ||
| 493 | * program them in BE. If more than BE_NUM_VLANS_SUPPORTED are configured, | ||
| 494 | * set the BE in promiscuous VLAN mode. | ||
| 495 | */ | ||
| 496 | static void be_vids_config(struct net_device *netdev) | ||
| 497 | { | ||
| 498 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 499 | u16 vtag[BE_NUM_VLANS_SUPPORTED]; | ||
| 500 | u16 ntags = 0, i; | ||
| 501 | |||
| 502 | if (adapter->num_vlans <= BE_NUM_VLANS_SUPPORTED) { | ||
| 503 | /* Construct VLAN Table to give to HW */ | ||
| 504 | for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) { | ||
| 505 | if (adapter->vlan_tag[i]) { | ||
| 506 | vtag[ntags] = cpu_to_le16(i); | ||
| 507 | ntags++; | ||
| 508 | } | ||
| 509 | } | ||
| 510 | be_cmd_vlan_config(&adapter->ctrl, adapter->if_handle, | ||
| 511 | vtag, ntags, 1, 0); | ||
| 512 | } else { | ||
| 513 | be_cmd_vlan_config(&adapter->ctrl, adapter->if_handle, | ||
| 514 | NULL, 0, 1, 1); | ||
| 515 | } | ||
| 516 | } | ||
| 517 | |||
| 518 | static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp) | ||
| 519 | { | ||
| 520 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 521 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 522 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 523 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 524 | |||
| 525 | be_eq_notify(ctrl, rx_eq->q.id, false, false, 0); | ||
| 526 | be_eq_notify(ctrl, tx_eq->q.id, false, false, 0); | ||
| 527 | adapter->vlan_grp = grp; | ||
| 528 | be_eq_notify(ctrl, rx_eq->q.id, true, false, 0); | ||
| 529 | be_eq_notify(ctrl, tx_eq->q.id, true, false, 0); | ||
| 530 | } | ||
| 531 | |||
| 532 | static void be_vlan_add_vid(struct net_device *netdev, u16 vid) | ||
| 533 | { | ||
| 534 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 535 | |||
| 536 | adapter->num_vlans++; | ||
| 537 | adapter->vlan_tag[vid] = 1; | ||
| 538 | |||
| 539 | be_vids_config(netdev); | ||
| 540 | } | ||
| 541 | |||
| 542 | static void be_vlan_rem_vid(struct net_device *netdev, u16 vid) | ||
| 543 | { | ||
| 544 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 545 | |||
| 546 | adapter->num_vlans--; | ||
| 547 | adapter->vlan_tag[vid] = 0; | ||
| 548 | |||
| 549 | vlan_group_set_device(adapter->vlan_grp, vid, NULL); | ||
| 550 | be_vids_config(netdev); | ||
| 551 | } | ||
| 552 | |||
| 553 | static void be_set_multicast_filter(struct net_device *netdev) | ||
| 554 | { | ||
| 555 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 556 | struct dev_mc_list *mc_ptr; | ||
| 557 | u8 mac_addr[32][ETH_ALEN]; | ||
| 558 | int i = 0; | ||
| 559 | |||
| 560 | if (netdev->flags & IFF_ALLMULTI) { | ||
| 561 | /* set BE in Multicast promiscuous */ | ||
| 562 | be_cmd_mcast_mac_set(&adapter->ctrl, | ||
| 563 | adapter->if_handle, NULL, 0, true); | ||
| 564 | return; | ||
| 565 | } | ||
| 566 | |||
| 567 | for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | ||
| 568 | memcpy(&mac_addr[i][0], mc_ptr->dmi_addr, ETH_ALEN); | ||
| 569 | if (++i >= 32) { | ||
| 570 | be_cmd_mcast_mac_set(&adapter->ctrl, | ||
| 571 | adapter->if_handle, &mac_addr[0][0], i, false); | ||
| 572 | i = 0; | ||
| 573 | } | ||
| 574 | |||
| 575 | } | ||
| 576 | |||
| 577 | if (i) { | ||
| 578 | /* reset the promiscuous mode also. */ | ||
| 579 | be_cmd_mcast_mac_set(&adapter->ctrl, | ||
| 580 | adapter->if_handle, &mac_addr[0][0], i, false); | ||
| 581 | } | ||
| 582 | } | ||
| 583 | |||
| 584 | static void be_set_multicast_list(struct net_device *netdev) | ||
| 585 | { | ||
| 586 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 587 | |||
| 588 | if (netdev->flags & IFF_PROMISC) { | ||
| 589 | be_cmd_promiscuous_config(&adapter->ctrl, adapter->port_num, 1); | ||
| 590 | } else { | ||
| 591 | be_cmd_promiscuous_config(&adapter->ctrl, adapter->port_num, 0); | ||
| 592 | be_set_multicast_filter(netdev); | ||
| 593 | } | ||
| 594 | } | ||
| 595 | |||
| 596 | static void be_rx_rate_update(struct be_adapter *adapter, u32 pktsize, | ||
| 597 | u16 numfrags) | ||
| 598 | { | ||
| 599 | struct be_drvr_stats *stats = &adapter->stats.drvr_stats; | ||
| 600 | u32 rate; | ||
| 601 | |||
| 602 | stats->be_rx_compl++; | ||
| 603 | stats->be_rx_frags += numfrags; | ||
| 604 | stats->be_rx_bytes += pktsize; | ||
| 605 | |||
| 606 | /* Update the rate once in two seconds */ | ||
| 607 | if ((jiffies - stats->be_rx_jiffies) < 2 * HZ) | ||
| 608 | return; | ||
| 609 | |||
| 610 | rate = (stats->be_rx_bytes - stats->be_rx_bytes_prev) / | ||
| 611 | ((u32) (jiffies - stats->be_rx_jiffies) / HZ); | ||
| 612 | rate = (rate / 1000000); /* MB/Sec */ | ||
| 613 | stats->be_rx_rate = (rate * 8); /* Mega Bits/Sec */ | ||
| 614 | stats->be_rx_jiffies = jiffies; | ||
| 615 | stats->be_rx_bytes_prev = stats->be_rx_bytes; | ||
| 616 | } | ||
| 617 | |||
| 618 | static struct be_rx_page_info * | ||
| 619 | get_rx_page_info(struct be_adapter *adapter, u16 frag_idx) | ||
| 620 | { | ||
| 621 | struct be_rx_page_info *rx_page_info; | ||
| 622 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 623 | |||
| 624 | rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx]; | ||
| 625 | BUG_ON(!rx_page_info->page); | ||
| 626 | |||
| 627 | if (rx_page_info->last_page_user) | ||
| 628 | pci_unmap_page(adapter->pdev, pci_unmap_addr(rx_page_info, bus), | ||
| 629 | adapter->big_page_size, PCI_DMA_FROMDEVICE); | ||
| 630 | |||
| 631 | atomic_dec(&rxq->used); | ||
| 632 | return rx_page_info; | ||
| 633 | } | ||
| 634 | |||
| 635 | /* Throwaway the data in the Rx completion */ | ||
| 636 | static void be_rx_compl_discard(struct be_adapter *adapter, | ||
| 637 | struct be_eth_rx_compl *rxcp) | ||
| 638 | { | ||
| 639 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 640 | struct be_rx_page_info *page_info; | ||
| 641 | u16 rxq_idx, i, num_rcvd; | ||
| 642 | |||
| 643 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | ||
| 644 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); | ||
| 645 | |||
| 646 | for (i = 0; i < num_rcvd; i++) { | ||
| 647 | page_info = get_rx_page_info(adapter, rxq_idx); | ||
| 648 | put_page(page_info->page); | ||
| 649 | memset(page_info, 0, sizeof(*page_info)); | ||
| 650 | index_inc(&rxq_idx, rxq->len); | ||
| 651 | } | ||
| 652 | } | ||
| 653 | |||
| 654 | /* | ||
| 655 | * skb_fill_rx_data forms a complete skb for an ether frame | ||
| 656 | * indicated by rxcp. | ||
| 657 | */ | ||
| 658 | static void skb_fill_rx_data(struct be_adapter *adapter, | ||
| 659 | struct sk_buff *skb, struct be_eth_rx_compl *rxcp) | ||
| 660 | { | ||
| 661 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 662 | struct be_rx_page_info *page_info; | ||
| 663 | u16 rxq_idx, i, num_rcvd; | ||
| 664 | u32 pktsize, hdr_len, curr_frag_len; | ||
| 665 | u8 *start; | ||
| 666 | |||
| 667 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | ||
| 668 | pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp); | ||
| 669 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); | ||
| 670 | |||
| 671 | page_info = get_rx_page_info(adapter, rxq_idx); | ||
| 672 | |||
| 673 | start = page_address(page_info->page) + page_info->page_offset; | ||
| 674 | prefetch(start); | ||
| 675 | |||
| 676 | /* Copy data in the first descriptor of this completion */ | ||
| 677 | curr_frag_len = min(pktsize, rx_frag_size); | ||
| 678 | |||
| 679 | /* Copy the header portion into skb_data */ | ||
| 680 | hdr_len = min((u32)BE_HDR_LEN, curr_frag_len); | ||
| 681 | memcpy(skb->data, start, hdr_len); | ||
| 682 | skb->len = curr_frag_len; | ||
| 683 | if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */ | ||
| 684 | /* Complete packet has now been moved to data */ | ||
| 685 | put_page(page_info->page); | ||
| 686 | skb->data_len = 0; | ||
| 687 | skb->tail += curr_frag_len; | ||
| 688 | } else { | ||
| 689 | skb_shinfo(skb)->nr_frags = 1; | ||
| 690 | skb_shinfo(skb)->frags[0].page = page_info->page; | ||
| 691 | skb_shinfo(skb)->frags[0].page_offset = | ||
| 692 | page_info->page_offset + hdr_len; | ||
| 693 | skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len; | ||
| 694 | skb->data_len = curr_frag_len - hdr_len; | ||
| 695 | skb->tail += hdr_len; | ||
| 696 | } | ||
| 697 | memset(page_info, 0, sizeof(*page_info)); | ||
| 698 | |||
| 699 | if (pktsize <= rx_frag_size) { | ||
| 700 | BUG_ON(num_rcvd != 1); | ||
| 701 | return; | ||
| 702 | } | ||
| 703 | |||
| 704 | /* More frags present for this completion */ | ||
| 705 | pktsize -= curr_frag_len; /* account for above copied frag */ | ||
| 706 | for (i = 1; i < num_rcvd; i++) { | ||
| 707 | index_inc(&rxq_idx, rxq->len); | ||
| 708 | page_info = get_rx_page_info(adapter, rxq_idx); | ||
| 709 | |||
| 710 | curr_frag_len = min(pktsize, rx_frag_size); | ||
| 711 | |||
| 712 | skb_shinfo(skb)->frags[i].page = page_info->page; | ||
| 713 | skb_shinfo(skb)->frags[i].page_offset = page_info->page_offset; | ||
| 714 | skb_shinfo(skb)->frags[i].size = curr_frag_len; | ||
| 715 | skb->len += curr_frag_len; | ||
| 716 | skb->data_len += curr_frag_len; | ||
| 717 | skb_shinfo(skb)->nr_frags++; | ||
| 718 | pktsize -= curr_frag_len; | ||
| 719 | |||
| 720 | memset(page_info, 0, sizeof(*page_info)); | ||
| 721 | } | ||
| 722 | |||
| 723 | be_rx_rate_update(adapter, pktsize, num_rcvd); | ||
| 724 | return; | ||
| 725 | } | ||
| 726 | |||
| 727 | /* Process the RX completion indicated by rxcp when LRO is disabled */ | ||
| 728 | static void be_rx_compl_process(struct be_adapter *adapter, | ||
| 729 | struct be_eth_rx_compl *rxcp) | ||
| 730 | { | ||
| 731 | struct sk_buff *skb; | ||
| 732 | u32 vtp, vid; | ||
| 733 | int l4_cksm; | ||
| 734 | |||
| 735 | l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp); | ||
| 736 | vtp = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); | ||
| 737 | |||
| 738 | skb = netdev_alloc_skb(adapter->netdev, BE_HDR_LEN + NET_IP_ALIGN); | ||
| 739 | if (!skb) { | ||
| 740 | if (net_ratelimit()) | ||
| 741 | dev_warn(&adapter->pdev->dev, "skb alloc failed\n"); | ||
| 742 | be_rx_compl_discard(adapter, rxcp); | ||
| 743 | return; | ||
| 744 | } | ||
| 745 | |||
| 746 | skb_reserve(skb, NET_IP_ALIGN); | ||
| 747 | |||
| 748 | skb_fill_rx_data(adapter, skb, rxcp); | ||
| 749 | |||
| 750 | if (l4_cksm && adapter->rx_csum) | ||
| 751 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 752 | else | ||
| 753 | skb->ip_summed = CHECKSUM_NONE; | ||
| 754 | |||
| 755 | skb->truesize = skb->len + sizeof(struct sk_buff); | ||
| 756 | skb->protocol = eth_type_trans(skb, adapter->netdev); | ||
| 757 | skb->dev = adapter->netdev; | ||
| 758 | |||
| 759 | if (vtp) { | ||
| 760 | if (!adapter->vlan_grp || adapter->num_vlans == 0) { | ||
| 761 | kfree_skb(skb); | ||
| 762 | return; | ||
| 763 | } | ||
| 764 | vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp); | ||
| 765 | vid = be16_to_cpu(vid); | ||
| 766 | vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid); | ||
| 767 | } else { | ||
| 768 | netif_receive_skb(skb); | ||
| 769 | } | ||
| 770 | |||
| 771 | adapter->netdev->last_rx = jiffies; | ||
| 772 | |||
| 773 | return; | ||
| 774 | } | ||
| 775 | |||
| 776 | /* Process the RX completion indicated by rxcp when LRO is enabled */ | ||
| 777 | static void be_rx_compl_process_lro(struct be_adapter *adapter, | ||
| 778 | struct be_eth_rx_compl *rxcp) | ||
| 779 | { | ||
| 780 | struct be_rx_page_info *page_info; | ||
| 781 | struct skb_frag_struct rx_frags[BE_MAX_FRAGS_PER_FRAME]; | ||
| 782 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 783 | u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len; | ||
| 784 | u16 i, rxq_idx = 0, vid; | ||
| 785 | |||
| 786 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); | ||
| 787 | pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp); | ||
| 788 | vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); | ||
| 789 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | ||
| 790 | |||
| 791 | remaining = pkt_size; | ||
| 792 | for (i = 0; i < num_rcvd; i++) { | ||
| 793 | page_info = get_rx_page_info(adapter, rxq_idx); | ||
| 794 | |||
| 795 | curr_frag_len = min(remaining, rx_frag_size); | ||
| 796 | |||
| 797 | rx_frags[i].page = page_info->page; | ||
| 798 | rx_frags[i].page_offset = page_info->page_offset; | ||
| 799 | rx_frags[i].size = curr_frag_len; | ||
| 800 | remaining -= curr_frag_len; | ||
| 801 | |||
| 802 | index_inc(&rxq_idx, rxq->len); | ||
| 803 | |||
| 804 | memset(page_info, 0, sizeof(*page_info)); | ||
| 805 | } | ||
| 806 | |||
| 807 | if (likely(!vlanf)) { | ||
| 808 | lro_receive_frags(&adapter->rx_obj.lro_mgr, rx_frags, pkt_size, | ||
| 809 | pkt_size, NULL, 0); | ||
| 810 | } else { | ||
| 811 | vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp); | ||
| 812 | vid = be16_to_cpu(vid); | ||
| 813 | |||
| 814 | if (!adapter->vlan_grp || adapter->num_vlans == 0) | ||
| 815 | return; | ||
| 816 | |||
| 817 | lro_vlan_hwaccel_receive_frags(&adapter->rx_obj.lro_mgr, | ||
| 818 | rx_frags, pkt_size, pkt_size, adapter->vlan_grp, | ||
| 819 | vid, NULL, 0); | ||
| 820 | } | ||
| 821 | |||
| 822 | be_rx_rate_update(adapter, pkt_size, num_rcvd); | ||
| 823 | return; | ||
| 824 | } | ||
| 825 | |||
| 826 | static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter) | ||
| 827 | { | ||
| 828 | struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq); | ||
| 829 | |||
| 830 | if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0) | ||
| 831 | return NULL; | ||
| 832 | |||
| 833 | be_dws_le_to_cpu(rxcp, sizeof(*rxcp)); | ||
| 834 | |||
| 835 | rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0; | ||
| 836 | |||
| 837 | queue_tail_inc(&adapter->rx_obj.cq); | ||
| 838 | return rxcp; | ||
| 839 | } | ||
| 840 | |||
| 841 | static inline struct page *be_alloc_pages(u32 size) | ||
| 842 | { | ||
| 843 | gfp_t alloc_flags = GFP_ATOMIC; | ||
| 844 | u32 order = get_order(size); | ||
| 845 | if (order > 0) | ||
| 846 | alloc_flags |= __GFP_COMP; | ||
| 847 | return alloc_pages(alloc_flags, order); | ||
| 848 | } | ||
| 849 | |||
| 850 | /* | ||
| 851 | * Allocate a page, split it to fragments of size rx_frag_size and post as | ||
| 852 | * receive buffers to BE | ||
| 853 | */ | ||
| 854 | static void be_post_rx_frags(struct be_adapter *adapter) | ||
| 855 | { | ||
| 856 | struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl; | ||
| 857 | struct be_rx_page_info *page_info = NULL; | ||
| 858 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 859 | struct page *pagep = NULL; | ||
| 860 | struct be_eth_rx_d *rxd; | ||
| 861 | u64 page_dmaaddr = 0, frag_dmaaddr; | ||
| 862 | u32 posted, page_offset = 0; | ||
| 863 | |||
| 864 | |||
| 865 | page_info = &page_info_tbl[rxq->head]; | ||
| 866 | for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) { | ||
| 867 | if (!pagep) { | ||
| 868 | pagep = be_alloc_pages(adapter->big_page_size); | ||
| 869 | if (unlikely(!pagep)) { | ||
| 870 | drvr_stats(adapter)->be_ethrx_post_fail++; | ||
| 871 | break; | ||
| 872 | } | ||
| 873 | page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0, | ||
| 874 | adapter->big_page_size, | ||
| 875 | PCI_DMA_FROMDEVICE); | ||
| 876 | page_info->page_offset = 0; | ||
| 877 | } else { | ||
| 878 | get_page(pagep); | ||
| 879 | page_info->page_offset = page_offset + rx_frag_size; | ||
| 880 | } | ||
| 881 | page_offset = page_info->page_offset; | ||
| 882 | page_info->page = pagep; | ||
| 883 | pci_unmap_addr_set(page_info, bus, page_dmaaddr); | ||
| 884 | frag_dmaaddr = page_dmaaddr + page_info->page_offset; | ||
| 885 | |||
| 886 | rxd = queue_head_node(rxq); | ||
| 887 | rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF); | ||
| 888 | rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr)); | ||
| 889 | queue_head_inc(rxq); | ||
| 890 | |||
| 891 | /* Any space left in the current big page for another frag? */ | ||
| 892 | if ((page_offset + rx_frag_size + rx_frag_size) > | ||
| 893 | adapter->big_page_size) { | ||
| 894 | pagep = NULL; | ||
| 895 | page_info->last_page_user = true; | ||
| 896 | } | ||
| 897 | page_info = &page_info_tbl[rxq->head]; | ||
| 898 | } | ||
| 899 | if (pagep) | ||
| 900 | page_info->last_page_user = true; | ||
| 901 | |||
| 902 | if (posted) { | ||
| 903 | be_rxq_notify(&adapter->ctrl, rxq->id, posted); | ||
| 904 | atomic_add(posted, &rxq->used); | ||
| 905 | } | ||
| 906 | |||
| 907 | return; | ||
| 908 | } | ||
| 909 | |||
| 910 | static struct be_eth_tx_compl * | ||
| 911 | be_tx_compl_get(struct be_adapter *adapter) | ||
| 912 | { | ||
| 913 | struct be_queue_info *tx_cq = &adapter->tx_obj.cq; | ||
| 914 | struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq); | ||
| 915 | |||
| 916 | if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0) | ||
| 917 | return NULL; | ||
| 918 | |||
| 919 | be_dws_le_to_cpu(txcp, sizeof(*txcp)); | ||
| 920 | |||
| 921 | txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0; | ||
| 922 | |||
| 923 | queue_tail_inc(tx_cq); | ||
| 924 | return txcp; | ||
| 925 | } | ||
| 926 | |||
| 927 | static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index) | ||
| 928 | { | ||
| 929 | struct be_queue_info *txq = &adapter->tx_obj.q; | ||
| 930 | struct be_eth_wrb *wrb; | ||
| 931 | struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list; | ||
| 932 | struct sk_buff *sent_skb; | ||
| 933 | u64 busaddr; | ||
| 934 | u16 cur_index, num_wrbs = 0; | ||
| 935 | |||
| 936 | cur_index = txq->tail; | ||
| 937 | sent_skb = sent_skbs[cur_index]; | ||
| 938 | BUG_ON(!sent_skb); | ||
| 939 | sent_skbs[cur_index] = NULL; | ||
| 940 | |||
| 941 | do { | ||
| 942 | cur_index = txq->tail; | ||
| 943 | wrb = queue_tail_node(txq); | ||
| 944 | be_dws_le_to_cpu(wrb, sizeof(*wrb)); | ||
| 945 | busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo; | ||
| 946 | if (busaddr != 0) { | ||
| 947 | pci_unmap_single(adapter->pdev, busaddr, | ||
| 948 | wrb->frag_len, PCI_DMA_TODEVICE); | ||
| 949 | } | ||
| 950 | num_wrbs++; | ||
| 951 | queue_tail_inc(txq); | ||
| 952 | } while (cur_index != last_index); | ||
| 953 | |||
| 954 | atomic_sub(num_wrbs, &txq->used); | ||
| 955 | |||
| 956 | kfree_skb(sent_skb); | ||
| 957 | } | ||
| 958 | |||
| 959 | static void be_rx_q_clean(struct be_adapter *adapter) | ||
| 960 | { | ||
| 961 | struct be_rx_page_info *page_info; | ||
| 962 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 963 | struct be_queue_info *rx_cq = &adapter->rx_obj.cq; | ||
| 964 | struct be_eth_rx_compl *rxcp; | ||
| 965 | u16 tail; | ||
| 966 | |||
| 967 | /* First cleanup pending rx completions */ | ||
| 968 | while ((rxcp = be_rx_compl_get(adapter)) != NULL) { | ||
| 969 | be_rx_compl_discard(adapter, rxcp); | ||
| 970 | be_cq_notify(&adapter->ctrl, rx_cq->id, true, 1); | ||
| 971 | } | ||
| 972 | |||
| 973 | /* Then free posted rx buffer that were not used */ | ||
| 974 | tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len; | ||
| 975 | for (; tail != rxq->head; index_inc(&tail, rxq->len)) { | ||
| 976 | page_info = get_rx_page_info(adapter, tail); | ||
| 977 | put_page(page_info->page); | ||
| 978 | memset(page_info, 0, sizeof(*page_info)); | ||
| 979 | } | ||
| 980 | BUG_ON(atomic_read(&rxq->used)); | ||
| 981 | } | ||
| 982 | |||
| 983 | static void be_tx_q_clean(struct be_adapter *adapter) | ||
| 984 | { | ||
| 985 | struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list; | ||
| 986 | struct sk_buff *sent_skb; | ||
| 987 | struct be_queue_info *txq = &adapter->tx_obj.q; | ||
| 988 | u16 last_index; | ||
| 989 | bool dummy_wrb; | ||
| 990 | |||
| 991 | while (atomic_read(&txq->used)) { | ||
| 992 | sent_skb = sent_skbs[txq->tail]; | ||
| 993 | last_index = txq->tail; | ||
| 994 | index_adv(&last_index, | ||
| 995 | wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len); | ||
| 996 | be_tx_compl_process(adapter, last_index); | ||
| 997 | } | ||
| 998 | } | ||
| 999 | |||
| 1000 | static void be_tx_queues_destroy(struct be_adapter *adapter) | ||
| 1001 | { | ||
| 1002 | struct be_queue_info *q; | ||
| 1003 | |||
| 1004 | q = &adapter->tx_obj.q; | ||
| 1005 | if (q->created) | ||
| 1006 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_TXQ); | ||
| 1007 | be_queue_free(adapter, q); | ||
| 1008 | |||
| 1009 | q = &adapter->tx_obj.cq; | ||
| 1010 | if (q->created) | ||
| 1011 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_CQ); | ||
| 1012 | be_queue_free(adapter, q); | ||
| 1013 | |||
| 1014 | /* No more tx completions can be rcvd now; clean up if there are | ||
| 1015 | * any pending completions or pending tx requests */ | ||
| 1016 | be_tx_q_clean(adapter); | ||
| 1017 | |||
| 1018 | q = &adapter->tx_eq.q; | ||
| 1019 | if (q->created) | ||
| 1020 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_EQ); | ||
| 1021 | be_queue_free(adapter, q); | ||
| 1022 | } | ||
| 1023 | |||
| 1024 | static int be_tx_queues_create(struct be_adapter *adapter) | ||
| 1025 | { | ||
| 1026 | struct be_queue_info *eq, *q, *cq; | ||
| 1027 | |||
| 1028 | adapter->tx_eq.max_eqd = 0; | ||
| 1029 | adapter->tx_eq.min_eqd = 0; | ||
| 1030 | adapter->tx_eq.cur_eqd = 96; | ||
| 1031 | adapter->tx_eq.enable_aic = false; | ||
| 1032 | /* Alloc Tx Event queue */ | ||
| 1033 | eq = &adapter->tx_eq.q; | ||
| 1034 | if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry))) | ||
| 1035 | return -1; | ||
| 1036 | |||
| 1037 | /* Ask BE to create Tx Event queue */ | ||
| 1038 | if (be_cmd_eq_create(&adapter->ctrl, eq, adapter->tx_eq.cur_eqd)) | ||
| 1039 | goto tx_eq_free; | ||
| 1040 | /* Alloc TX eth compl queue */ | ||
| 1041 | cq = &adapter->tx_obj.cq; | ||
| 1042 | if (be_queue_alloc(adapter, cq, TX_CQ_LEN, | ||
| 1043 | sizeof(struct be_eth_tx_compl))) | ||
| 1044 | goto tx_eq_destroy; | ||
| 1045 | |||
| 1046 | /* Ask BE to create Tx eth compl queue */ | ||
| 1047 | if (be_cmd_cq_create(&adapter->ctrl, cq, eq, false, false, 3)) | ||
| 1048 | goto tx_cq_free; | ||
| 1049 | |||
| 1050 | /* Alloc TX eth queue */ | ||
| 1051 | q = &adapter->tx_obj.q; | ||
| 1052 | if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb))) | ||
| 1053 | goto tx_cq_destroy; | ||
| 1054 | |||
| 1055 | /* Ask BE to create Tx eth queue */ | ||
| 1056 | if (be_cmd_txq_create(&adapter->ctrl, q, cq)) | ||
| 1057 | goto tx_q_free; | ||
| 1058 | return 0; | ||
| 1059 | |||
| 1060 | tx_q_free: | ||
| 1061 | be_queue_free(adapter, q); | ||
| 1062 | tx_cq_destroy: | ||
| 1063 | be_cmd_q_destroy(&adapter->ctrl, cq, QTYPE_CQ); | ||
| 1064 | tx_cq_free: | ||
| 1065 | be_queue_free(adapter, cq); | ||
| 1066 | tx_eq_destroy: | ||
| 1067 | be_cmd_q_destroy(&adapter->ctrl, eq, QTYPE_EQ); | ||
| 1068 | tx_eq_free: | ||
| 1069 | be_queue_free(adapter, eq); | ||
| 1070 | return -1; | ||
| 1071 | } | ||
| 1072 | |||
| 1073 | static void be_rx_queues_destroy(struct be_adapter *adapter) | ||
| 1074 | { | ||
| 1075 | struct be_queue_info *q; | ||
| 1076 | |||
| 1077 | q = &adapter->rx_obj.q; | ||
| 1078 | if (q->created) { | ||
| 1079 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_RXQ); | ||
| 1080 | be_rx_q_clean(adapter); | ||
| 1081 | } | ||
| 1082 | be_queue_free(adapter, q); | ||
| 1083 | |||
| 1084 | q = &adapter->rx_obj.cq; | ||
| 1085 | if (q->created) | ||
| 1086 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_CQ); | ||
| 1087 | be_queue_free(adapter, q); | ||
| 1088 | |||
| 1089 | q = &adapter->rx_eq.q; | ||
| 1090 | if (q->created) | ||
| 1091 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_EQ); | ||
| 1092 | be_queue_free(adapter, q); | ||
| 1093 | } | ||
| 1094 | |||
| 1095 | static int be_rx_queues_create(struct be_adapter *adapter) | ||
| 1096 | { | ||
| 1097 | struct be_queue_info *eq, *q, *cq; | ||
| 1098 | int rc; | ||
| 1099 | |||
| 1100 | adapter->max_rx_coal = BE_MAX_FRAGS_PER_FRAME; | ||
| 1101 | adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE; | ||
| 1102 | adapter->rx_eq.max_eqd = BE_MAX_EQD; | ||
| 1103 | adapter->rx_eq.min_eqd = 0; | ||
| 1104 | adapter->rx_eq.cur_eqd = 0; | ||
| 1105 | adapter->rx_eq.enable_aic = true; | ||
| 1106 | |||
| 1107 | /* Alloc Rx Event queue */ | ||
| 1108 | eq = &adapter->rx_eq.q; | ||
| 1109 | rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN, | ||
| 1110 | sizeof(struct be_eq_entry)); | ||
| 1111 | if (rc) | ||
| 1112 | return rc; | ||
| 1113 | |||
| 1114 | /* Ask BE to create Rx Event queue */ | ||
| 1115 | rc = be_cmd_eq_create(&adapter->ctrl, eq, adapter->rx_eq.cur_eqd); | ||
| 1116 | if (rc) | ||
| 1117 | goto rx_eq_free; | ||
| 1118 | |||
| 1119 | /* Alloc RX eth compl queue */ | ||
| 1120 | cq = &adapter->rx_obj.cq; | ||
| 1121 | rc = be_queue_alloc(adapter, cq, RX_CQ_LEN, | ||
| 1122 | sizeof(struct be_eth_rx_compl)); | ||
| 1123 | if (rc) | ||
| 1124 | goto rx_eq_destroy; | ||
| 1125 | |||
| 1126 | /* Ask BE to create Rx eth compl queue */ | ||
| 1127 | rc = be_cmd_cq_create(&adapter->ctrl, cq, eq, false, false, 3); | ||
| 1128 | if (rc) | ||
| 1129 | goto rx_cq_free; | ||
| 1130 | |||
| 1131 | /* Alloc RX eth queue */ | ||
| 1132 | q = &adapter->rx_obj.q; | ||
| 1133 | rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d)); | ||
| 1134 | if (rc) | ||
| 1135 | goto rx_cq_destroy; | ||
| 1136 | |||
| 1137 | /* Ask BE to create Rx eth queue */ | ||
| 1138 | rc = be_cmd_rxq_create(&adapter->ctrl, q, cq->id, rx_frag_size, | ||
| 1139 | BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false); | ||
| 1140 | if (rc) | ||
| 1141 | goto rx_q_free; | ||
| 1142 | |||
| 1143 | return 0; | ||
| 1144 | rx_q_free: | ||
| 1145 | be_queue_free(adapter, q); | ||
| 1146 | rx_cq_destroy: | ||
| 1147 | be_cmd_q_destroy(&adapter->ctrl, cq, QTYPE_CQ); | ||
| 1148 | rx_cq_free: | ||
| 1149 | be_queue_free(adapter, cq); | ||
| 1150 | rx_eq_destroy: | ||
| 1151 | be_cmd_q_destroy(&adapter->ctrl, eq, QTYPE_EQ); | ||
| 1152 | rx_eq_free: | ||
| 1153 | be_queue_free(adapter, eq); | ||
| 1154 | return rc; | ||
| 1155 | } | ||
| 1156 | static bool event_get(struct be_eq_obj *eq_obj, u16 *rid) | ||
| 1157 | { | ||
| 1158 | struct be_eq_entry *entry = queue_tail_node(&eq_obj->q); | ||
| 1159 | u32 evt = entry->evt; | ||
| 1160 | |||
| 1161 | if (!evt) | ||
| 1162 | return false; | ||
| 1163 | |||
| 1164 | evt = le32_to_cpu(evt); | ||
| 1165 | *rid = (evt >> EQ_ENTRY_RES_ID_SHIFT) & EQ_ENTRY_RES_ID_MASK; | ||
| 1166 | entry->evt = 0; | ||
| 1167 | queue_tail_inc(&eq_obj->q); | ||
| 1168 | return true; | ||
| 1169 | } | ||
| 1170 | |||
| 1171 | static int event_handle(struct be_ctrl_info *ctrl, | ||
| 1172 | struct be_eq_obj *eq_obj) | ||
| 1173 | { | ||
| 1174 | u16 rid = 0, num = 0; | ||
| 1175 | |||
| 1176 | while (event_get(eq_obj, &rid)) | ||
| 1177 | num++; | ||
| 1178 | |||
| 1179 | /* We can see an interrupt and no event */ | ||
| 1180 | be_eq_notify(ctrl, eq_obj->q.id, true, true, num); | ||
| 1181 | if (num) | ||
| 1182 | napi_schedule(&eq_obj->napi); | ||
| 1183 | |||
| 1184 | return num; | ||
| 1185 | } | ||
| 1186 | |||
| 1187 | static irqreturn_t be_intx(int irq, void *dev) | ||
| 1188 | { | ||
| 1189 | struct be_adapter *adapter = dev; | ||
| 1190 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1191 | int rx, tx; | ||
| 1192 | |||
| 1193 | tx = event_handle(ctrl, &adapter->tx_eq); | ||
| 1194 | rx = event_handle(ctrl, &adapter->rx_eq); | ||
| 1195 | |||
| 1196 | if (rx || tx) | ||
| 1197 | return IRQ_HANDLED; | ||
| 1198 | else | ||
| 1199 | return IRQ_NONE; | ||
| 1200 | } | ||
| 1201 | |||
| 1202 | static irqreturn_t be_msix_rx(int irq, void *dev) | ||
| 1203 | { | ||
| 1204 | struct be_adapter *adapter = dev; | ||
| 1205 | |||
| 1206 | event_handle(&adapter->ctrl, &adapter->rx_eq); | ||
| 1207 | |||
| 1208 | return IRQ_HANDLED; | ||
| 1209 | } | ||
| 1210 | |||
| 1211 | static irqreturn_t be_msix_tx(int irq, void *dev) | ||
| 1212 | { | ||
| 1213 | struct be_adapter *adapter = dev; | ||
| 1214 | |||
| 1215 | event_handle(&adapter->ctrl, &adapter->tx_eq); | ||
| 1216 | |||
| 1217 | return IRQ_HANDLED; | ||
| 1218 | } | ||
| 1219 | |||
| 1220 | static inline bool do_lro(struct be_adapter *adapter, | ||
| 1221 | struct be_eth_rx_compl *rxcp) | ||
| 1222 | { | ||
| 1223 | int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp); | ||
| 1224 | int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp); | ||
| 1225 | |||
| 1226 | if (err) | ||
| 1227 | drvr_stats(adapter)->be_rxcp_err++; | ||
| 1228 | |||
| 1229 | return (!tcp_frame || err || (adapter->max_rx_coal <= 1)) ? | ||
| 1230 | false : true; | ||
| 1231 | } | ||
| 1232 | |||
| 1233 | int be_poll_rx(struct napi_struct *napi, int budget) | ||
| 1234 | { | ||
| 1235 | struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi); | ||
| 1236 | struct be_adapter *adapter = | ||
| 1237 | container_of(rx_eq, struct be_adapter, rx_eq); | ||
| 1238 | struct be_queue_info *rx_cq = &adapter->rx_obj.cq; | ||
| 1239 | struct be_eth_rx_compl *rxcp; | ||
| 1240 | u32 work_done; | ||
| 1241 | |||
| 1242 | for (work_done = 0; work_done < budget; work_done++) { | ||
| 1243 | rxcp = be_rx_compl_get(adapter); | ||
| 1244 | if (!rxcp) | ||
| 1245 | break; | ||
| 1246 | |||
| 1247 | if (do_lro(adapter, rxcp)) | ||
| 1248 | be_rx_compl_process_lro(adapter, rxcp); | ||
| 1249 | else | ||
| 1250 | be_rx_compl_process(adapter, rxcp); | ||
| 1251 | } | ||
| 1252 | |||
| 1253 | lro_flush_all(&adapter->rx_obj.lro_mgr); | ||
| 1254 | |||
| 1255 | /* Refill the queue */ | ||
| 1256 | if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM) | ||
| 1257 | be_post_rx_frags(adapter); | ||
| 1258 | |||
| 1259 | /* All consumed */ | ||
| 1260 | if (work_done < budget) { | ||
| 1261 | napi_complete(napi); | ||
| 1262 | be_cq_notify(&adapter->ctrl, rx_cq->id, true, work_done); | ||
| 1263 | } else { | ||
| 1264 | /* More to be consumed; continue with interrupts disabled */ | ||
| 1265 | be_cq_notify(&adapter->ctrl, rx_cq->id, false, work_done); | ||
| 1266 | } | ||
| 1267 | return work_done; | ||
| 1268 | } | ||
| 1269 | |||
| 1270 | /* For TX we don't honour budget; consume everything */ | ||
| 1271 | int be_poll_tx(struct napi_struct *napi, int budget) | ||
| 1272 | { | ||
| 1273 | struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi); | ||
| 1274 | struct be_adapter *adapter = | ||
| 1275 | container_of(tx_eq, struct be_adapter, tx_eq); | ||
| 1276 | struct be_tx_obj *tx_obj = &adapter->tx_obj; | ||
| 1277 | struct be_queue_info *tx_cq = &tx_obj->cq; | ||
| 1278 | struct be_queue_info *txq = &tx_obj->q; | ||
| 1279 | struct be_eth_tx_compl *txcp; | ||
| 1280 | u32 num_cmpl = 0; | ||
| 1281 | u16 end_idx; | ||
| 1282 | |||
| 1283 | while ((txcp = be_tx_compl_get(adapter))) { | ||
| 1284 | end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl, | ||
| 1285 | wrb_index, txcp); | ||
| 1286 | be_tx_compl_process(adapter, end_idx); | ||
| 1287 | num_cmpl++; | ||
| 1288 | } | ||
| 1289 | |||
| 1290 | /* As Tx wrbs have been freed up, wake up netdev queue if | ||
| 1291 | * it was stopped due to lack of tx wrbs. | ||
| 1292 | */ | ||
| 1293 | if (netif_queue_stopped(adapter->netdev) && | ||
| 1294 | atomic_read(&txq->used) < txq->len / 2) { | ||
| 1295 | netif_wake_queue(adapter->netdev); | ||
| 1296 | } | ||
| 1297 | |||
| 1298 | napi_complete(napi); | ||
| 1299 | |||
| 1300 | be_cq_notify(&adapter->ctrl, tx_cq->id, true, num_cmpl); | ||
| 1301 | |||
| 1302 | drvr_stats(adapter)->be_tx_events++; | ||
| 1303 | drvr_stats(adapter)->be_tx_compl += num_cmpl; | ||
| 1304 | |||
| 1305 | return 1; | ||
| 1306 | } | ||
| 1307 | |||
| 1308 | static void be_msix_enable(struct be_adapter *adapter) | ||
| 1309 | { | ||
| 1310 | int i, status; | ||
| 1311 | |||
| 1312 | for (i = 0; i < BE_NUM_MSIX_VECTORS; i++) | ||
| 1313 | adapter->msix_entries[i].entry = i; | ||
| 1314 | |||
| 1315 | status = pci_enable_msix(adapter->pdev, adapter->msix_entries, | ||
| 1316 | BE_NUM_MSIX_VECTORS); | ||
| 1317 | if (status == 0) | ||
| 1318 | adapter->msix_enabled = true; | ||
| 1319 | return; | ||
| 1320 | } | ||
| 1321 | |||
| 1322 | static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id) | ||
| 1323 | { | ||
| 1324 | return adapter->msix_entries[eq_id - | ||
| 1325 | 8 * adapter->ctrl.pci_func].vector; | ||
| 1326 | } | ||
| 1327 | |||
| 1328 | static int be_msix_register(struct be_adapter *adapter) | ||
| 1329 | { | ||
| 1330 | struct net_device *netdev = adapter->netdev; | ||
| 1331 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 1332 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 1333 | int status, vec; | ||
| 1334 | |||
| 1335 | sprintf(tx_eq->desc, "%s-tx", netdev->name); | ||
| 1336 | vec = be_msix_vec_get(adapter, tx_eq->q.id); | ||
| 1337 | status = request_irq(vec, be_msix_tx, 0, tx_eq->desc, adapter); | ||
| 1338 | if (status) | ||
| 1339 | goto err; | ||
| 1340 | |||
| 1341 | sprintf(rx_eq->desc, "%s-rx", netdev->name); | ||
| 1342 | vec = be_msix_vec_get(adapter, rx_eq->q.id); | ||
| 1343 | status = request_irq(vec, be_msix_rx, 0, rx_eq->desc, adapter); | ||
| 1344 | if (status) { /* Free TX IRQ */ | ||
| 1345 | vec = be_msix_vec_get(adapter, tx_eq->q.id); | ||
| 1346 | free_irq(vec, adapter); | ||
| 1347 | goto err; | ||
| 1348 | } | ||
| 1349 | return 0; | ||
| 1350 | err: | ||
| 1351 | dev_warn(&adapter->pdev->dev, | ||
| 1352 | "MSIX Request IRQ failed - err %d\n", status); | ||
| 1353 | pci_disable_msix(adapter->pdev); | ||
| 1354 | adapter->msix_enabled = false; | ||
| 1355 | return status; | ||
| 1356 | } | ||
| 1357 | |||
| 1358 | static int be_irq_register(struct be_adapter *adapter) | ||
| 1359 | { | ||
| 1360 | struct net_device *netdev = adapter->netdev; | ||
| 1361 | int status; | ||
| 1362 | |||
| 1363 | if (adapter->msix_enabled) { | ||
| 1364 | status = be_msix_register(adapter); | ||
| 1365 | if (status == 0) | ||
| 1366 | goto done; | ||
| 1367 | } | ||
| 1368 | |||
| 1369 | /* INTx */ | ||
| 1370 | netdev->irq = adapter->pdev->irq; | ||
| 1371 | status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name, | ||
| 1372 | adapter); | ||
| 1373 | if (status) { | ||
| 1374 | dev_err(&adapter->pdev->dev, | ||
| 1375 | "INTx request IRQ failed - err %d\n", status); | ||
| 1376 | return status; | ||
| 1377 | } | ||
| 1378 | done: | ||
| 1379 | adapter->isr_registered = true; | ||
| 1380 | return 0; | ||
| 1381 | } | ||
| 1382 | |||
| 1383 | static void be_irq_unregister(struct be_adapter *adapter) | ||
| 1384 | { | ||
| 1385 | struct net_device *netdev = adapter->netdev; | ||
| 1386 | int vec; | ||
| 1387 | |||
| 1388 | if (!adapter->isr_registered) | ||
| 1389 | return; | ||
| 1390 | |||
| 1391 | /* INTx */ | ||
| 1392 | if (!adapter->msix_enabled) { | ||
| 1393 | free_irq(netdev->irq, adapter); | ||
| 1394 | goto done; | ||
| 1395 | } | ||
| 1396 | |||
| 1397 | /* MSIx */ | ||
| 1398 | vec = be_msix_vec_get(adapter, adapter->tx_eq.q.id); | ||
| 1399 | free_irq(vec, adapter); | ||
| 1400 | vec = be_msix_vec_get(adapter, adapter->rx_eq.q.id); | ||
| 1401 | free_irq(vec, adapter); | ||
| 1402 | done: | ||
| 1403 | adapter->isr_registered = false; | ||
| 1404 | return; | ||
| 1405 | } | ||
| 1406 | |||
| 1407 | static int be_open(struct net_device *netdev) | ||
| 1408 | { | ||
| 1409 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 1410 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1411 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 1412 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 1413 | u32 if_flags; | ||
| 1414 | int status; | ||
| 1415 | |||
| 1416 | if_flags = BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_PROMISCUOUS | | ||
| 1417 | BE_IF_FLAGS_MCAST_PROMISCUOUS | BE_IF_FLAGS_UNTAGGED | | ||
| 1418 | BE_IF_FLAGS_PASS_L3L4_ERRORS; | ||
| 1419 | status = be_cmd_if_create(ctrl, if_flags, netdev->dev_addr, | ||
| 1420 | false/* pmac_invalid */, &adapter->if_handle, | ||
| 1421 | &adapter->pmac_id); | ||
| 1422 | if (status != 0) | ||
| 1423 | goto do_none; | ||
| 1424 | |||
| 1425 | status = be_cmd_set_flow_control(ctrl, true, true); | ||
| 1426 | if (status != 0) | ||
| 1427 | goto if_destroy; | ||
| 1428 | |||
| 1429 | status = be_tx_queues_create(adapter); | ||
| 1430 | if (status != 0) | ||
| 1431 | goto if_destroy; | ||
| 1432 | |||
| 1433 | status = be_rx_queues_create(adapter); | ||
| 1434 | if (status != 0) | ||
| 1435 | goto tx_qs_destroy; | ||
| 1436 | |||
| 1437 | /* First time posting */ | ||
| 1438 | be_post_rx_frags(adapter); | ||
| 1439 | |||
| 1440 | napi_enable(&rx_eq->napi); | ||
| 1441 | napi_enable(&tx_eq->napi); | ||
| 1442 | |||
| 1443 | be_irq_register(adapter); | ||
| 1444 | |||
| 1445 | be_intr_set(ctrl, true); | ||
| 1446 | |||
| 1447 | /* The evt queues are created in the unarmed state; arm them */ | ||
| 1448 | be_eq_notify(ctrl, rx_eq->q.id, true, false, 0); | ||
| 1449 | be_eq_notify(ctrl, tx_eq->q.id, true, false, 0); | ||
| 1450 | |||
| 1451 | /* The compl queues are created in the unarmed state; arm them */ | ||
| 1452 | be_cq_notify(ctrl, adapter->rx_obj.cq.id, true, 0); | ||
| 1453 | be_cq_notify(ctrl, adapter->tx_obj.cq.id, true, 0); | ||
| 1454 | |||
| 1455 | be_link_status_update(adapter); | ||
| 1456 | |||
| 1457 | schedule_delayed_work(&adapter->work, msecs_to_jiffies(100)); | ||
| 1458 | return 0; | ||
| 1459 | |||
| 1460 | tx_qs_destroy: | ||
| 1461 | be_tx_queues_destroy(adapter); | ||
| 1462 | if_destroy: | ||
| 1463 | be_cmd_if_destroy(ctrl, adapter->if_handle); | ||
| 1464 | do_none: | ||
| 1465 | return status; | ||
| 1466 | } | ||
| 1467 | |||
| 1468 | static int be_close(struct net_device *netdev) | ||
| 1469 | { | ||
| 1470 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 1471 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1472 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 1473 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 1474 | int vec; | ||
| 1475 | |||
| 1476 | cancel_delayed_work(&adapter->work); | ||
| 1477 | |||
| 1478 | netif_stop_queue(netdev); | ||
| 1479 | netif_carrier_off(netdev); | ||
| 1480 | adapter->link.speed = PHY_LINK_SPEED_ZERO; | ||
| 1481 | |||
| 1482 | be_intr_set(ctrl, false); | ||
| 1483 | |||
| 1484 | if (adapter->msix_enabled) { | ||
| 1485 | vec = be_msix_vec_get(adapter, tx_eq->q.id); | ||
| 1486 | synchronize_irq(vec); | ||
| 1487 | vec = be_msix_vec_get(adapter, rx_eq->q.id); | ||
| 1488 | synchronize_irq(vec); | ||
| 1489 | } else { | ||
| 1490 | synchronize_irq(netdev->irq); | ||
| 1491 | } | ||
| 1492 | be_irq_unregister(adapter); | ||
| 1493 | |||
| 1494 | napi_disable(&rx_eq->napi); | ||
| 1495 | napi_disable(&tx_eq->napi); | ||
| 1496 | |||
| 1497 | be_rx_queues_destroy(adapter); | ||
| 1498 | be_tx_queues_destroy(adapter); | ||
| 1499 | |||
| 1500 | be_cmd_if_destroy(ctrl, adapter->if_handle); | ||
| 1501 | return 0; | ||
| 1502 | } | ||
| 1503 | |||
| 1504 | static int be_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr, | ||
| 1505 | void **ip_hdr, void **tcpudp_hdr, | ||
| 1506 | u64 *hdr_flags, void *priv) | ||
| 1507 | { | ||
| 1508 | struct ethhdr *eh; | ||
| 1509 | struct vlan_ethhdr *veh; | ||
| 1510 | struct iphdr *iph; | ||
| 1511 | u8 *va = page_address(frag->page) + frag->page_offset; | ||
| 1512 | unsigned long ll_hlen; | ||
| 1513 | |||
| 1514 | prefetch(va); | ||
| 1515 | eh = (struct ethhdr *)va; | ||
| 1516 | *mac_hdr = eh; | ||
| 1517 | ll_hlen = ETH_HLEN; | ||
| 1518 | if (eh->h_proto != htons(ETH_P_IP)) { | ||
| 1519 | if (eh->h_proto == htons(ETH_P_8021Q)) { | ||
| 1520 | veh = (struct vlan_ethhdr *)va; | ||
| 1521 | if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP)) | ||
| 1522 | return -1; | ||
| 1523 | |||
| 1524 | ll_hlen += VLAN_HLEN; | ||
| 1525 | } else { | ||
| 1526 | return -1; | ||
| 1527 | } | ||
| 1528 | } | ||
| 1529 | *hdr_flags = LRO_IPV4; | ||
| 1530 | iph = (struct iphdr *)(va + ll_hlen); | ||
| 1531 | *ip_hdr = iph; | ||
| 1532 | if (iph->protocol != IPPROTO_TCP) | ||
| 1533 | return -1; | ||
| 1534 | *hdr_flags |= LRO_TCP; | ||
| 1535 | *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2); | ||
| 1536 | |||
| 1537 | return 0; | ||
| 1538 | } | ||
| 1539 | |||
| 1540 | static void be_lro_init(struct be_adapter *adapter, struct net_device *netdev) | ||
| 1541 | { | ||
| 1542 | struct net_lro_mgr *lro_mgr; | ||
| 1543 | |||
| 1544 | lro_mgr = &adapter->rx_obj.lro_mgr; | ||
| 1545 | lro_mgr->dev = netdev; | ||
| 1546 | lro_mgr->features = LRO_F_NAPI; | ||
| 1547 | lro_mgr->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 1548 | lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY; | ||
| 1549 | lro_mgr->max_desc = BE_MAX_LRO_DESCRIPTORS; | ||
| 1550 | lro_mgr->lro_arr = adapter->rx_obj.lro_desc; | ||
| 1551 | lro_mgr->get_frag_header = be_get_frag_header; | ||
| 1552 | lro_mgr->max_aggr = BE_MAX_FRAGS_PER_FRAME; | ||
| 1553 | } | ||
| 1554 | |||
| 1555 | static struct net_device_ops be_netdev_ops = { | ||
| 1556 | .ndo_open = be_open, | ||
| 1557 | .ndo_stop = be_close, | ||
| 1558 | .ndo_start_xmit = be_xmit, | ||
| 1559 | .ndo_get_stats = be_get_stats, | ||
| 1560 | .ndo_set_rx_mode = be_set_multicast_list, | ||
| 1561 | .ndo_set_mac_address = be_mac_addr_set, | ||
| 1562 | .ndo_change_mtu = be_change_mtu, | ||
| 1563 | .ndo_validate_addr = eth_validate_addr, | ||
| 1564 | .ndo_vlan_rx_register = be_vlan_register, | ||
| 1565 | .ndo_vlan_rx_add_vid = be_vlan_add_vid, | ||
| 1566 | .ndo_vlan_rx_kill_vid = be_vlan_rem_vid, | ||
| 1567 | }; | ||
| 1568 | |||
| 1569 | static void be_netdev_init(struct net_device *netdev) | ||
| 1570 | { | ||
| 1571 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 1572 | |||
| 1573 | netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO | | ||
| 1574 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_IP_CSUM | | ||
| 1575 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | ||
| 1576 | |||
| 1577 | netdev->flags |= IFF_MULTICAST; | ||
| 1578 | |||
| 1579 | BE_SET_NETDEV_OPS(netdev, &be_netdev_ops); | ||
| 1580 | |||
| 1581 | SET_ETHTOOL_OPS(netdev, &be_ethtool_ops); | ||
| 1582 | |||
| 1583 | be_lro_init(adapter, netdev); | ||
| 1584 | |||
| 1585 | netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx, | ||
| 1586 | BE_NAPI_WEIGHT); | ||
| 1587 | netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx, | ||
| 1588 | BE_NAPI_WEIGHT); | ||
| 1589 | |||
| 1590 | netif_carrier_off(netdev); | ||
| 1591 | netif_stop_queue(netdev); | ||
| 1592 | } | ||
| 1593 | |||
| 1594 | static void be_unmap_pci_bars(struct be_adapter *adapter) | ||
| 1595 | { | ||
| 1596 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1597 | if (ctrl->csr) | ||
| 1598 | iounmap(ctrl->csr); | ||
| 1599 | if (ctrl->db) | ||
| 1600 | iounmap(ctrl->db); | ||
| 1601 | if (ctrl->pcicfg) | ||
| 1602 | iounmap(ctrl->pcicfg); | ||
| 1603 | } | ||
| 1604 | |||
| 1605 | static int be_map_pci_bars(struct be_adapter *adapter) | ||
| 1606 | { | ||
| 1607 | u8 __iomem *addr; | ||
| 1608 | |||
| 1609 | addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2), | ||
| 1610 | pci_resource_len(adapter->pdev, 2)); | ||
| 1611 | if (addr == NULL) | ||
| 1612 | return -ENOMEM; | ||
| 1613 | adapter->ctrl.csr = addr; | ||
| 1614 | |||
| 1615 | addr = ioremap_nocache(pci_resource_start(adapter->pdev, 4), | ||
| 1616 | 128 * 1024); | ||
| 1617 | if (addr == NULL) | ||
| 1618 | goto pci_map_err; | ||
| 1619 | adapter->ctrl.db = addr; | ||
| 1620 | |||
| 1621 | addr = ioremap_nocache(pci_resource_start(adapter->pdev, 1), | ||
| 1622 | pci_resource_len(adapter->pdev, 1)); | ||
| 1623 | if (addr == NULL) | ||
| 1624 | goto pci_map_err; | ||
| 1625 | adapter->ctrl.pcicfg = addr; | ||
| 1626 | |||
| 1627 | return 0; | ||
| 1628 | pci_map_err: | ||
| 1629 | be_unmap_pci_bars(adapter); | ||
| 1630 | return -ENOMEM; | ||
| 1631 | } | ||
| 1632 | |||
| 1633 | |||
| 1634 | static void be_ctrl_cleanup(struct be_adapter *adapter) | ||
| 1635 | { | ||
| 1636 | struct be_dma_mem *mem = &adapter->ctrl.mbox_mem_alloced; | ||
| 1637 | |||
| 1638 | be_unmap_pci_bars(adapter); | ||
| 1639 | |||
| 1640 | if (mem->va) | ||
| 1641 | pci_free_consistent(adapter->pdev, mem->size, | ||
| 1642 | mem->va, mem->dma); | ||
| 1643 | } | ||
| 1644 | |||
| 1645 | /* Initialize the mbox required to send cmds to BE */ | ||
| 1646 | static int be_ctrl_init(struct be_adapter *adapter) | ||
| 1647 | { | ||
| 1648 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1649 | struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced; | ||
| 1650 | struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem; | ||
| 1651 | int status; | ||
| 1652 | u32 val; | ||
| 1653 | |||
| 1654 | status = be_map_pci_bars(adapter); | ||
| 1655 | if (status) | ||
| 1656 | return status; | ||
| 1657 | |||
| 1658 | mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16; | ||
| 1659 | mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev, | ||
| 1660 | mbox_mem_alloc->size, &mbox_mem_alloc->dma); | ||
| 1661 | if (!mbox_mem_alloc->va) { | ||
| 1662 | be_unmap_pci_bars(adapter); | ||
| 1663 | return -1; | ||
| 1664 | } | ||
| 1665 | mbox_mem_align->size = sizeof(struct be_mcc_mailbox); | ||
| 1666 | mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16); | ||
| 1667 | mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16); | ||
| 1668 | memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox)); | ||
| 1669 | spin_lock_init(&ctrl->cmd_lock); | ||
| 1670 | |||
| 1671 | val = ioread32(ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET); | ||
| 1672 | ctrl->pci_func = (val >> MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT) & | ||
| 1673 | MEMBAR_CTRL_INT_CTRL_PFUNC_MASK; | ||
| 1674 | return 0; | ||
| 1675 | } | ||
| 1676 | |||
| 1677 | static void be_stats_cleanup(struct be_adapter *adapter) | ||
| 1678 | { | ||
| 1679 | struct be_stats_obj *stats = &adapter->stats; | ||
| 1680 | struct be_dma_mem *cmd = &stats->cmd; | ||
| 1681 | |||
| 1682 | if (cmd->va) | ||
| 1683 | pci_free_consistent(adapter->pdev, cmd->size, | ||
| 1684 | cmd->va, cmd->dma); | ||
| 1685 | } | ||
| 1686 | |||
| 1687 | static int be_stats_init(struct be_adapter *adapter) | ||
| 1688 | { | ||
| 1689 | struct be_stats_obj *stats = &adapter->stats; | ||
| 1690 | struct be_dma_mem *cmd = &stats->cmd; | ||
| 1691 | |||
| 1692 | cmd->size = sizeof(struct be_cmd_req_get_stats); | ||
| 1693 | cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma); | ||
| 1694 | if (cmd->va == NULL) | ||
| 1695 | return -1; | ||
| 1696 | return 0; | ||
| 1697 | } | ||
| 1698 | |||
| 1699 | static void __devexit be_remove(struct pci_dev *pdev) | ||
| 1700 | { | ||
| 1701 | struct be_adapter *adapter = pci_get_drvdata(pdev); | ||
| 1702 | if (!adapter) | ||
| 1703 | return; | ||
| 1704 | |||
| 1705 | unregister_netdev(adapter->netdev); | ||
| 1706 | |||
| 1707 | be_stats_cleanup(adapter); | ||
| 1708 | |||
| 1709 | be_ctrl_cleanup(adapter); | ||
| 1710 | |||
| 1711 | if (adapter->msix_enabled) { | ||
| 1712 | pci_disable_msix(adapter->pdev); | ||
| 1713 | adapter->msix_enabled = false; | ||
| 1714 | } | ||
| 1715 | |||
| 1716 | pci_set_drvdata(pdev, NULL); | ||
| 1717 | pci_release_regions(pdev); | ||
| 1718 | pci_disable_device(pdev); | ||
| 1719 | |||
| 1720 | free_netdev(adapter->netdev); | ||
| 1721 | } | ||
| 1722 | |||
| 1723 | static int be_hw_up(struct be_adapter *adapter) | ||
| 1724 | { | ||
| 1725 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1726 | int status; | ||
| 1727 | |||
| 1728 | status = be_cmd_POST(ctrl); | ||
| 1729 | if (status) | ||
| 1730 | return status; | ||
| 1731 | |||
| 1732 | status = be_cmd_get_fw_ver(ctrl, adapter->fw_ver); | ||
| 1733 | if (status) | ||
| 1734 | return status; | ||
| 1735 | |||
| 1736 | status = be_cmd_query_fw_cfg(ctrl, &adapter->port_num); | ||
| 1737 | return status; | ||
| 1738 | } | ||
| 1739 | |||
| 1740 | static int __devinit be_probe(struct pci_dev *pdev, | ||
| 1741 | const struct pci_device_id *pdev_id) | ||
| 1742 | { | ||
| 1743 | int status = 0; | ||
| 1744 | struct be_adapter *adapter; | ||
| 1745 | struct net_device *netdev; | ||
| 1746 | struct be_ctrl_info *ctrl; | ||
| 1747 | u8 mac[ETH_ALEN]; | ||
| 1748 | |||
| 1749 | status = pci_enable_device(pdev); | ||
| 1750 | if (status) | ||
| 1751 | goto do_none; | ||
| 1752 | |||
| 1753 | status = pci_request_regions(pdev, DRV_NAME); | ||
| 1754 | if (status) | ||
| 1755 | goto disable_dev; | ||
| 1756 | pci_set_master(pdev); | ||
| 1757 | |||
| 1758 | netdev = alloc_etherdev(sizeof(struct be_adapter)); | ||
| 1759 | if (netdev == NULL) { | ||
| 1760 | status = -ENOMEM; | ||
| 1761 | goto rel_reg; | ||
| 1762 | } | ||
| 1763 | adapter = netdev_priv(netdev); | ||
| 1764 | adapter->pdev = pdev; | ||
| 1765 | pci_set_drvdata(pdev, adapter); | ||
| 1766 | adapter->netdev = netdev; | ||
| 1767 | |||
| 1768 | be_msix_enable(adapter); | ||
| 1769 | |||
| 1770 | status = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | ||
| 1771 | if (!status) { | ||
| 1772 | netdev->features |= NETIF_F_HIGHDMA; | ||
| 1773 | } else { | ||
| 1774 | status = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | ||
| 1775 | if (status) { | ||
| 1776 | dev_err(&pdev->dev, "Could not set PCI DMA Mask\n"); | ||
| 1777 | goto free_netdev; | ||
| 1778 | } | ||
| 1779 | } | ||
| 1780 | |||
| 1781 | ctrl = &adapter->ctrl; | ||
| 1782 | status = be_ctrl_init(adapter); | ||
| 1783 | if (status) | ||
| 1784 | goto free_netdev; | ||
| 1785 | |||
| 1786 | status = be_stats_init(adapter); | ||
| 1787 | if (status) | ||
| 1788 | goto ctrl_clean; | ||
| 1789 | |||
| 1790 | status = be_hw_up(adapter); | ||
| 1791 | if (status) | ||
| 1792 | goto stats_clean; | ||
| 1793 | |||
| 1794 | status = be_cmd_mac_addr_query(ctrl, mac, MAC_ADDRESS_TYPE_NETWORK, | ||
| 1795 | true /* permanent */, 0); | ||
| 1796 | if (status) | ||
| 1797 | goto stats_clean; | ||
| 1798 | memcpy(netdev->dev_addr, mac, ETH_ALEN); | ||
| 1799 | |||
| 1800 | INIT_DELAYED_WORK(&adapter->work, be_worker); | ||
| 1801 | be_netdev_init(netdev); | ||
| 1802 | SET_NETDEV_DEV(netdev, &adapter->pdev->dev); | ||
| 1803 | |||
| 1804 | status = register_netdev(netdev); | ||
| 1805 | if (status != 0) | ||
| 1806 | goto stats_clean; | ||
| 1807 | |||
| 1808 | dev_info(&pdev->dev, BE_NAME " port %d\n", adapter->port_num); | ||
| 1809 | return 0; | ||
| 1810 | |||
| 1811 | stats_clean: | ||
| 1812 | be_stats_cleanup(adapter); | ||
| 1813 | ctrl_clean: | ||
| 1814 | be_ctrl_cleanup(adapter); | ||
| 1815 | free_netdev: | ||
| 1816 | free_netdev(adapter->netdev); | ||
| 1817 | rel_reg: | ||
| 1818 | pci_release_regions(pdev); | ||
| 1819 | disable_dev: | ||
| 1820 | pci_disable_device(pdev); | ||
| 1821 | do_none: | ||
| 1822 | dev_warn(&pdev->dev, BE_NAME " initialization failed\n"); | ||
| 1823 | return status; | ||
| 1824 | } | ||
| 1825 | |||
| 1826 | static int be_suspend(struct pci_dev *pdev, pm_message_t state) | ||
| 1827 | { | ||
| 1828 | struct be_adapter *adapter = pci_get_drvdata(pdev); | ||
| 1829 | struct net_device *netdev = adapter->netdev; | ||
| 1830 | |||
| 1831 | netif_device_detach(netdev); | ||
| 1832 | if (netif_running(netdev)) { | ||
| 1833 | rtnl_lock(); | ||
| 1834 | be_close(netdev); | ||
| 1835 | rtnl_unlock(); | ||
| 1836 | } | ||
| 1837 | |||
| 1838 | pci_save_state(pdev); | ||
| 1839 | pci_disable_device(pdev); | ||
| 1840 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
| 1841 | return 0; | ||
| 1842 | } | ||
| 1843 | |||
| 1844 | static int be_resume(struct pci_dev *pdev) | ||
| 1845 | { | ||
| 1846 | int status = 0; | ||
| 1847 | struct be_adapter *adapter = pci_get_drvdata(pdev); | ||
| 1848 | struct net_device *netdev = adapter->netdev; | ||
| 1849 | |||
| 1850 | netif_device_detach(netdev); | ||
| 1851 | |||
| 1852 | status = pci_enable_device(pdev); | ||
| 1853 | if (status) | ||
| 1854 | return status; | ||
| 1855 | |||
| 1856 | pci_set_power_state(pdev, 0); | ||
| 1857 | pci_restore_state(pdev); | ||
| 1858 | |||
| 1859 | be_vids_config(netdev); | ||
| 1860 | |||
| 1861 | if (netif_running(netdev)) { | ||
| 1862 | rtnl_lock(); | ||
| 1863 | be_open(netdev); | ||
| 1864 | rtnl_unlock(); | ||
| 1865 | } | ||
| 1866 | netif_device_attach(netdev); | ||
| 1867 | return 0; | ||
| 1868 | } | ||
| 1869 | |||
| 1870 | static struct pci_driver be_driver = { | ||
| 1871 | .name = DRV_NAME, | ||
| 1872 | .id_table = be_dev_ids, | ||
| 1873 | .probe = be_probe, | ||
| 1874 | .remove = be_remove, | ||
| 1875 | .suspend = be_suspend, | ||
| 1876 | .resume = be_resume | ||
| 1877 | }; | ||
| 1878 | |||
| 1879 | static int __init be_init_module(void) | ||
| 1880 | { | ||
| 1881 | if (rx_frag_size != 8192 && rx_frag_size != 4096 | ||
| 1882 | && rx_frag_size != 2048) { | ||
| 1883 | printk(KERN_WARNING DRV_NAME | ||
| 1884 | " : Module param rx_frag_size must be 2048/4096/8192." | ||
| 1885 | " Using 2048\n"); | ||
| 1886 | rx_frag_size = 2048; | ||
| 1887 | } | ||
| 1888 | /* Ensure rx_frag_size is aligned to chache line */ | ||
| 1889 | if (SKB_DATA_ALIGN(rx_frag_size) != rx_frag_size) { | ||
| 1890 | printk(KERN_WARNING DRV_NAME | ||
| 1891 | " : Bad module param rx_frag_size. Using 2048\n"); | ||
| 1892 | rx_frag_size = 2048; | ||
| 1893 | } | ||
| 1894 | |||
| 1895 | return pci_register_driver(&be_driver); | ||
| 1896 | } | ||
| 1897 | module_init(be_init_module); | ||
| 1898 | |||
| 1899 | static void __exit be_exit_module(void) | ||
| 1900 | { | ||
| 1901 | pci_unregister_driver(&be_driver); | ||
| 1902 | } | ||
| 1903 | module_exit(be_exit_module); | ||
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h index 15a5cf0f676b..3cf2b92eef3b 100644 --- a/drivers/net/bnx2x.h +++ b/drivers/net/bnx2x.h | |||
| @@ -152,7 +152,7 @@ struct sw_rx_page { | |||
| 152 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | 152 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) |
| 153 | #define SGE_PAGE_SIZE PAGE_SIZE | 153 | #define SGE_PAGE_SIZE PAGE_SIZE |
| 154 | #define SGE_PAGE_SHIFT PAGE_SHIFT | 154 | #define SGE_PAGE_SHIFT PAGE_SHIFT |
| 155 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr) | 155 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))addr) |
| 156 | 156 | ||
| 157 | #define BCM_RX_ETH_PAYLOAD_ALIGN 64 | 157 | #define BCM_RX_ETH_PAYLOAD_ALIGN 64 |
| 158 | 158 | ||
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h index a6c0b3abba29..3b0c2499ef17 100644 --- a/drivers/net/bnx2x_init.h +++ b/drivers/net/bnx2x_init.h | |||
| @@ -150,7 +150,6 @@ static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data, | |||
| 150 | 150 | ||
| 151 | static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) | 151 | static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) |
| 152 | { | 152 | { |
| 153 | #ifdef USE_DMAE | ||
| 154 | int offset = 0; | 153 | int offset = 0; |
| 155 | 154 | ||
| 156 | if (bp->dmae_ready) { | 155 | if (bp->dmae_ready) { |
| @@ -164,9 +163,6 @@ static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) | |||
| 164 | addr + offset, len); | 163 | addr + offset, len); |
| 165 | } else | 164 | } else |
| 166 | bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); | 165 | bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); |
| 167 | #else | ||
| 168 | bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); | ||
| 169 | #endif | ||
| 170 | } | 166 | } |
| 171 | 167 | ||
| 172 | static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) | 168 | static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index d3e7775a9ccf..2e346a5e98cf 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c | |||
| @@ -57,7 +57,7 @@ | |||
| 57 | #include "bnx2x.h" | 57 | #include "bnx2x.h" |
| 58 | #include "bnx2x_init.h" | 58 | #include "bnx2x_init.h" |
| 59 | 59 | ||
| 60 | #define DRV_MODULE_VERSION "1.45.26" | 60 | #define DRV_MODULE_VERSION "1.45.27" |
| 61 | #define DRV_MODULE_RELDATE "2009/01/26" | 61 | #define DRV_MODULE_RELDATE "2009/01/26" |
| 62 | #define BNX2X_BC_VER 0x040200 | 62 | #define BNX2X_BC_VER 0x040200 |
| 63 | 63 | ||
| @@ -4035,10 +4035,10 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id) | |||
| 4035 | { | 4035 | { |
| 4036 | int port = BP_PORT(bp); | 4036 | int port = BP_PORT(bp); |
| 4037 | 4037 | ||
| 4038 | bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + | 4038 | bnx2x_init_fill(bp, USTORM_INTMEM_ADDR + |
| 4039 | USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, | 4039 | USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, |
| 4040 | sizeof(struct ustorm_status_block)/4); | 4040 | sizeof(struct ustorm_status_block)/4); |
| 4041 | bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + | 4041 | bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR + |
| 4042 | CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, | 4042 | CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, |
| 4043 | sizeof(struct cstorm_status_block)/4); | 4043 | sizeof(struct cstorm_status_block)/4); |
| 4044 | } | 4044 | } |
| @@ -4092,18 +4092,18 @@ static void bnx2x_zero_def_sb(struct bnx2x *bp) | |||
| 4092 | { | 4092 | { |
| 4093 | int func = BP_FUNC(bp); | 4093 | int func = BP_FUNC(bp); |
| 4094 | 4094 | ||
| 4095 | bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + | 4095 | bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR + |
| 4096 | TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | ||
| 4097 | sizeof(struct tstorm_def_status_block)/4); | ||
| 4098 | bnx2x_init_fill(bp, USTORM_INTMEM_ADDR + | ||
| 4096 | USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | 4099 | USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, |
| 4097 | sizeof(struct ustorm_def_status_block)/4); | 4100 | sizeof(struct ustorm_def_status_block)/4); |
| 4098 | bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + | 4101 | bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR + |
| 4099 | CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | 4102 | CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, |
| 4100 | sizeof(struct cstorm_def_status_block)/4); | 4103 | sizeof(struct cstorm_def_status_block)/4); |
| 4101 | bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM + | 4104 | bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR + |
| 4102 | XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | 4105 | XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, |
| 4103 | sizeof(struct xstorm_def_status_block)/4); | 4106 | sizeof(struct xstorm_def_status_block)/4); |
| 4104 | bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM + | ||
| 4105 | TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | ||
| 4106 | sizeof(struct tstorm_def_status_block)/4); | ||
| 4107 | } | 4107 | } |
| 4108 | 4108 | ||
| 4109 | static void bnx2x_init_def_sb(struct bnx2x *bp, | 4109 | static void bnx2x_init_def_sb(struct bnx2x *bp, |
| @@ -4518,7 +4518,8 @@ static void bnx2x_init_context(struct bnx2x *bp) | |||
| 4518 | (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA | | 4518 | (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA | |
| 4519 | USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING); | 4519 | USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING); |
| 4520 | context->ustorm_st_context.common.sge_buff_size = | 4520 | context->ustorm_st_context.common.sge_buff_size = |
| 4521 | (u16)(BCM_PAGE_SIZE*PAGES_PER_SGE); | 4521 | (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE, |
| 4522 | (u32)0xffff); | ||
| 4522 | context->ustorm_st_context.common.sge_page_base_hi = | 4523 | context->ustorm_st_context.common.sge_page_base_hi = |
| 4523 | U64_HI(fp->rx_sge_mapping); | 4524 | U64_HI(fp->rx_sge_mapping); |
| 4524 | context->ustorm_st_context.common.sge_page_base_lo = | 4525 | context->ustorm_st_context.common.sge_page_base_lo = |
diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c new file mode 100644 index 000000000000..5c347f70cb67 --- /dev/null +++ b/drivers/net/dnet.c | |||
| @@ -0,0 +1,994 @@ | |||
| 1 | /* | ||
| 2 | * Dave DNET Ethernet Controller driver | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> | ||
| 5 | * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/version.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/moduleparam.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <linux/slab.h> | ||
| 17 | #include <linux/delay.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/netdevice.h> | ||
| 20 | #include <linux/etherdevice.h> | ||
| 21 | #include <linux/dma-mapping.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/phy.h> | ||
| 24 | #include <linux/platform_device.h> | ||
| 25 | |||
| 26 | #include "dnet.h" | ||
| 27 | |||
| 28 | #undef DEBUG | ||
| 29 | |||
| 30 | /* function for reading internal MAC register */ | ||
| 31 | u16 dnet_readw_mac(struct dnet *bp, u16 reg) | ||
| 32 | { | ||
| 33 | u16 data_read; | ||
| 34 | |||
| 35 | /* issue a read */ | ||
| 36 | dnet_writel(bp, reg, MACREG_ADDR); | ||
| 37 | |||
| 38 | /* since a read/write op to the MAC is very slow, | ||
| 39 | * we must wait before reading the data */ | ||
| 40 | ndelay(500); | ||
| 41 | |||
| 42 | /* read data read from the MAC register */ | ||
| 43 | data_read = dnet_readl(bp, MACREG_DATA); | ||
| 44 | |||
| 45 | /* all done */ | ||
| 46 | return data_read; | ||
| 47 | } | ||
| 48 | |||
| 49 | /* function for writing internal MAC register */ | ||
| 50 | void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val) | ||
| 51 | { | ||
| 52 | /* load data to write */ | ||
| 53 | dnet_writel(bp, val, MACREG_DATA); | ||
| 54 | |||
| 55 | /* issue a write */ | ||
| 56 | dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR); | ||
| 57 | |||
| 58 | /* since a read/write op to the MAC is very slow, | ||
| 59 | * we must wait before exiting */ | ||
| 60 | ndelay(500); | ||
| 61 | } | ||
| 62 | |||
| 63 | static void __dnet_set_hwaddr(struct dnet *bp) | ||
| 64 | { | ||
| 65 | u16 tmp; | ||
| 66 | |||
| 67 | tmp = cpu_to_be16(*((u16 *) bp->dev->dev_addr)); | ||
| 68 | dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp); | ||
| 69 | tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 2))); | ||
| 70 | dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp); | ||
| 71 | tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 4))); | ||
| 72 | dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp); | ||
| 73 | } | ||
| 74 | |||
| 75 | static void __devinit dnet_get_hwaddr(struct dnet *bp) | ||
| 76 | { | ||
| 77 | u16 tmp; | ||
| 78 | u8 addr[6]; | ||
| 79 | |||
| 80 | /* | ||
| 81 | * from MAC docs: | ||
| 82 | * "Note that the MAC address is stored in the registers in Hexadecimal | ||
| 83 | * form. For example, to set the MAC Address to: AC-DE-48-00-00-80 | ||
| 84 | * would require writing 0xAC (octet 0) to address 0x0B (high byte of | ||
| 85 | * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of | ||
| 86 | * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of | ||
| 87 | * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of | ||
| 88 | * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of | ||
| 89 | * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of | ||
| 90 | * Mac_addr[15:0]). | ||
| 91 | */ | ||
| 92 | tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG); | ||
| 93 | *((u16 *) addr) = be16_to_cpu(tmp); | ||
| 94 | tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG); | ||
| 95 | *((u16 *) (addr + 2)) = be16_to_cpu(tmp); | ||
| 96 | tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG); | ||
| 97 | *((u16 *) (addr + 4)) = be16_to_cpu(tmp); | ||
| 98 | |||
| 99 | if (is_valid_ether_addr(addr)) | ||
| 100 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); | ||
| 101 | } | ||
| 102 | |||
| 103 | static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) | ||
| 104 | { | ||
| 105 | struct dnet *bp = bus->priv; | ||
| 106 | u16 value; | ||
| 107 | |||
| 108 | while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) | ||
| 109 | & DNET_INTERNAL_GMII_MNG_CMD_FIN)) | ||
| 110 | cpu_relax(); | ||
| 111 | |||
| 112 | /* only 5 bits allowed for phy-addr and reg_offset */ | ||
| 113 | mii_id &= 0x1f; | ||
| 114 | regnum &= 0x1f; | ||
| 115 | |||
| 116 | /* prepare reg_value for a read */ | ||
| 117 | value = (mii_id << 8); | ||
| 118 | value |= regnum; | ||
| 119 | |||
| 120 | /* write control word */ | ||
| 121 | dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value); | ||
| 122 | |||
| 123 | /* wait for end of transfer */ | ||
| 124 | while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) | ||
| 125 | & DNET_INTERNAL_GMII_MNG_CMD_FIN)) | ||
| 126 | cpu_relax(); | ||
| 127 | |||
| 128 | value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG); | ||
| 129 | |||
| 130 | pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value); | ||
| 131 | |||
| 132 | return value; | ||
| 133 | } | ||
| 134 | |||
| 135 | static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, | ||
| 136 | u16 value) | ||
| 137 | { | ||
| 138 | struct dnet *bp = bus->priv; | ||
| 139 | u16 tmp; | ||
| 140 | |||
| 141 | pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value); | ||
| 142 | |||
| 143 | while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) | ||
| 144 | & DNET_INTERNAL_GMII_MNG_CMD_FIN)) | ||
| 145 | cpu_relax(); | ||
| 146 | |||
| 147 | /* prepare for a write operation */ | ||
| 148 | tmp = (1 << 13); | ||
| 149 | |||
| 150 | /* only 5 bits allowed for phy-addr and reg_offset */ | ||
| 151 | mii_id &= 0x1f; | ||
| 152 | regnum &= 0x1f; | ||
| 153 | |||
| 154 | /* only 16 bits on data */ | ||
| 155 | value &= 0xffff; | ||
| 156 | |||
| 157 | /* prepare reg_value for a write */ | ||
| 158 | tmp |= (mii_id << 8); | ||
| 159 | tmp |= regnum; | ||
| 160 | |||
| 161 | /* write data to write first */ | ||
| 162 | dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value); | ||
| 163 | |||
| 164 | /* write control word */ | ||
| 165 | dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp); | ||
| 166 | |||
| 167 | while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) | ||
| 168 | & DNET_INTERNAL_GMII_MNG_CMD_FIN)) | ||
| 169 | cpu_relax(); | ||
| 170 | |||
| 171 | return 0; | ||
| 172 | } | ||
| 173 | |||
| 174 | static int dnet_mdio_reset(struct mii_bus *bus) | ||
| 175 | { | ||
| 176 | return 0; | ||
| 177 | } | ||
| 178 | |||
| 179 | static void dnet_handle_link_change(struct net_device *dev) | ||
| 180 | { | ||
| 181 | struct dnet *bp = netdev_priv(dev); | ||
| 182 | struct phy_device *phydev = bp->phy_dev; | ||
| 183 | unsigned long flags; | ||
| 184 | u32 mode_reg, ctl_reg; | ||
| 185 | |||
| 186 | int status_change = 0; | ||
| 187 | |||
| 188 | spin_lock_irqsave(&bp->lock, flags); | ||
| 189 | |||
| 190 | mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); | ||
| 191 | ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); | ||
| 192 | |||
| 193 | if (phydev->link) { | ||
| 194 | if (bp->duplex != phydev->duplex) { | ||
| 195 | if (phydev->duplex) | ||
| 196 | ctl_reg &= | ||
| 197 | ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP); | ||
| 198 | else | ||
| 199 | ctl_reg |= | ||
| 200 | DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP; | ||
| 201 | |||
| 202 | bp->duplex = phydev->duplex; | ||
| 203 | status_change = 1; | ||
| 204 | } | ||
| 205 | |||
| 206 | if (bp->speed != phydev->speed) { | ||
| 207 | status_change = 1; | ||
| 208 | switch (phydev->speed) { | ||
| 209 | case 1000: | ||
| 210 | mode_reg |= DNET_INTERNAL_MODE_GBITEN; | ||
| 211 | break; | ||
| 212 | case 100: | ||
| 213 | case 10: | ||
| 214 | mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; | ||
| 215 | break; | ||
| 216 | default: | ||
| 217 | printk(KERN_WARNING | ||
| 218 | "%s: Ack! Speed (%d) is not " | ||
| 219 | "10/100/1000!\n", dev->name, | ||
| 220 | phydev->speed); | ||
| 221 | break; | ||
| 222 | } | ||
| 223 | bp->speed = phydev->speed; | ||
| 224 | } | ||
| 225 | } | ||
| 226 | |||
| 227 | if (phydev->link != bp->link) { | ||
| 228 | if (phydev->link) { | ||
| 229 | mode_reg |= | ||
| 230 | (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN); | ||
| 231 | } else { | ||
| 232 | mode_reg &= | ||
| 233 | ~(DNET_INTERNAL_MODE_RXEN | | ||
| 234 | DNET_INTERNAL_MODE_TXEN); | ||
| 235 | bp->speed = 0; | ||
| 236 | bp->duplex = -1; | ||
| 237 | } | ||
| 238 | bp->link = phydev->link; | ||
| 239 | |||
| 240 | status_change = 1; | ||
| 241 | } | ||
| 242 | |||
| 243 | if (status_change) { | ||
| 244 | dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); | ||
| 245 | dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); | ||
| 246 | } | ||
| 247 | |||
| 248 | spin_unlock_irqrestore(&bp->lock, flags); | ||
| 249 | |||
| 250 | if (status_change) { | ||
| 251 | if (phydev->link) | ||
| 252 | printk(KERN_INFO "%s: link up (%d/%s)\n", | ||
| 253 | dev->name, phydev->speed, | ||
| 254 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); | ||
| 255 | else | ||
| 256 | printk(KERN_INFO "%s: link down\n", dev->name); | ||
| 257 | } | ||
| 258 | } | ||
| 259 | |||
| 260 | static int dnet_mii_probe(struct net_device *dev) | ||
| 261 | { | ||
| 262 | struct dnet *bp = netdev_priv(dev); | ||
| 263 | struct phy_device *phydev = NULL; | ||
| 264 | int phy_addr; | ||
| 265 | |||
| 266 | /* find the first phy */ | ||
| 267 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | ||
| 268 | if (bp->mii_bus->phy_map[phy_addr]) { | ||
| 269 | phydev = bp->mii_bus->phy_map[phy_addr]; | ||
| 270 | break; | ||
| 271 | } | ||
| 272 | } | ||
| 273 | |||
| 274 | if (!phydev) { | ||
| 275 | printk(KERN_ERR "%s: no PHY found\n", dev->name); | ||
| 276 | return -ENODEV; | ||
| 277 | } | ||
| 278 | |||
| 279 | /* TODO : add pin_irq */ | ||
| 280 | |||
| 281 | /* attach the mac to the phy */ | ||
| 282 | if (bp->capabilities & DNET_HAS_RMII) { | ||
| 283 | phydev = phy_connect(dev, phydev->dev.bus_id, | ||
| 284 | &dnet_handle_link_change, 0, | ||
| 285 | PHY_INTERFACE_MODE_RMII); | ||
| 286 | } else { | ||
| 287 | phydev = phy_connect(dev, phydev->dev.bus_id, | ||
| 288 | &dnet_handle_link_change, 0, | ||
| 289 | PHY_INTERFACE_MODE_MII); | ||
| 290 | } | ||
| 291 | |||
| 292 | if (IS_ERR(phydev)) { | ||
| 293 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | ||
| 294 | return PTR_ERR(phydev); | ||
| 295 | } | ||
| 296 | |||
| 297 | /* mask with MAC supported features */ | ||
| 298 | if (bp->capabilities & DNET_HAS_GIGABIT) | ||
| 299 | phydev->supported &= PHY_GBIT_FEATURES; | ||
| 300 | else | ||
| 301 | phydev->supported &= PHY_BASIC_FEATURES; | ||
| 302 | |||
| 303 | phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause; | ||
| 304 | |||
| 305 | phydev->advertising = phydev->supported; | ||
| 306 | |||
| 307 | bp->link = 0; | ||
| 308 | bp->speed = 0; | ||
| 309 | bp->duplex = -1; | ||
| 310 | bp->phy_dev = phydev; | ||
| 311 | |||
| 312 | return 0; | ||
| 313 | } | ||
| 314 | |||
| 315 | static int dnet_mii_init(struct dnet *bp) | ||
| 316 | { | ||
| 317 | int err, i; | ||
| 318 | |||
| 319 | bp->mii_bus = mdiobus_alloc(); | ||
| 320 | if (bp->mii_bus == NULL) | ||
| 321 | return -ENOMEM; | ||
| 322 | |||
| 323 | bp->mii_bus->name = "dnet_mii_bus"; | ||
| 324 | bp->mii_bus->read = &dnet_mdio_read; | ||
| 325 | bp->mii_bus->write = &dnet_mdio_write; | ||
| 326 | bp->mii_bus->reset = &dnet_mdio_reset; | ||
| 327 | |||
| 328 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); | ||
| 329 | |||
| 330 | bp->mii_bus->priv = bp; | ||
| 331 | |||
| 332 | bp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | ||
| 333 | if (!bp->mii_bus->irq) { | ||
| 334 | err = -ENOMEM; | ||
| 335 | goto err_out; | ||
| 336 | } | ||
| 337 | |||
| 338 | for (i = 0; i < PHY_MAX_ADDR; i++) | ||
| 339 | bp->mii_bus->irq[i] = PHY_POLL; | ||
| 340 | |||
| 341 | platform_set_drvdata(bp->dev, bp->mii_bus); | ||
| 342 | |||
| 343 | if (mdiobus_register(bp->mii_bus)) { | ||
| 344 | err = -ENXIO; | ||
| 345 | goto err_out_free_mdio_irq; | ||
| 346 | } | ||
| 347 | |||
| 348 | if (dnet_mii_probe(bp->dev) != 0) { | ||
| 349 | err = -ENXIO; | ||
| 350 | goto err_out_unregister_bus; | ||
| 351 | } | ||
| 352 | |||
| 353 | return 0; | ||
| 354 | |||
| 355 | err_out_unregister_bus: | ||
| 356 | mdiobus_unregister(bp->mii_bus); | ||
| 357 | err_out_free_mdio_irq: | ||
| 358 | kfree(bp->mii_bus->irq); | ||
| 359 | err_out: | ||
| 360 | mdiobus_free(bp->mii_bus); | ||
| 361 | return err; | ||
| 362 | } | ||
| 363 | |||
| 364 | /* For Neptune board: LINK1000 as Link LED and TX as activity LED */ | ||
| 365 | int dnet_phy_marvell_fixup(struct phy_device *phydev) | ||
| 366 | { | ||
| 367 | return phy_write(phydev, 0x18, 0x4148); | ||
| 368 | } | ||
| 369 | |||
| 370 | static void dnet_update_stats(struct dnet *bp) | ||
| 371 | { | ||
| 372 | u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT; | ||
| 373 | u32 *p = &bp->hw_stats.rx_pkt_ignr; | ||
| 374 | u32 *end = &bp->hw_stats.rx_byte + 1; | ||
| 375 | |||
| 376 | WARN_ON((unsigned long)(end - p - 1) != | ||
| 377 | (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4); | ||
| 378 | |||
| 379 | for (; p < end; p++, reg++) | ||
| 380 | *p += readl(reg); | ||
| 381 | |||
| 382 | reg = bp->regs + DNET_TX_UNICAST_CNT; | ||
| 383 | p = &bp->hw_stats.tx_unicast; | ||
| 384 | end = &bp->hw_stats.tx_byte + 1; | ||
| 385 | |||
| 386 | WARN_ON((unsigned long)(end - p - 1) != | ||
| 387 | (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4); | ||
| 388 | |||
| 389 | for (; p < end; p++, reg++) | ||
| 390 | *p += readl(reg); | ||
| 391 | } | ||
| 392 | |||
| 393 | static int dnet_poll(struct napi_struct *napi, int budget) | ||
| 394 | { | ||
| 395 | struct dnet *bp = container_of(napi, struct dnet, napi); | ||
| 396 | struct net_device *dev = bp->dev; | ||
| 397 | int npackets = 0; | ||
| 398 | unsigned int pkt_len; | ||
| 399 | struct sk_buff *skb; | ||
| 400 | unsigned int *data_ptr; | ||
| 401 | u32 int_enable; | ||
| 402 | u32 cmd_word; | ||
| 403 | int i; | ||
| 404 | |||
| 405 | while (npackets < budget) { | ||
| 406 | /* | ||
| 407 | * break out of while loop if there are no more | ||
| 408 | * packets waiting | ||
| 409 | */ | ||
| 410 | if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) { | ||
| 411 | napi_complete(napi); | ||
| 412 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 413 | int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; | ||
| 414 | dnet_writel(bp, int_enable, INTR_ENB); | ||
| 415 | return 0; | ||
| 416 | } | ||
| 417 | |||
| 418 | cmd_word = dnet_readl(bp, RX_LEN_FIFO); | ||
| 419 | pkt_len = cmd_word & 0xFFFF; | ||
| 420 | |||
| 421 | if (cmd_word & 0xDF180000) | ||
| 422 | printk(KERN_ERR "%s packet receive error %x\n", | ||
| 423 | __func__, cmd_word); | ||
| 424 | |||
| 425 | skb = dev_alloc_skb(pkt_len + 5); | ||
| 426 | if (skb != NULL) { | ||
| 427 | /* Align IP on 16 byte boundaries */ | ||
| 428 | skb_reserve(skb, 2); | ||
| 429 | /* | ||
| 430 | * 'skb_put()' points to the start of sk_buff | ||
| 431 | * data area. | ||
| 432 | */ | ||
| 433 | data_ptr = (unsigned int *)skb_put(skb, pkt_len); | ||
| 434 | for (i = 0; i < (pkt_len + 3) >> 2; i++) | ||
| 435 | *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO); | ||
| 436 | skb->protocol = eth_type_trans(skb, dev); | ||
| 437 | netif_receive_skb(skb); | ||
| 438 | npackets++; | ||
| 439 | } else | ||
| 440 | printk(KERN_NOTICE | ||
| 441 | "%s: No memory to allocate a sk_buff of " | ||
| 442 | "size %u.\n", dev->name, pkt_len); | ||
| 443 | } | ||
| 444 | |||
| 445 | budget -= npackets; | ||
| 446 | |||
| 447 | if (npackets < budget) { | ||
| 448 | /* We processed all packets available. Tell NAPI it can | ||
| 449 | * stop polling then re-enable rx interrupts */ | ||
| 450 | napi_complete(napi); | ||
| 451 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 452 | int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; | ||
| 453 | dnet_writel(bp, int_enable, INTR_ENB); | ||
| 454 | return 0; | ||
| 455 | } | ||
| 456 | |||
| 457 | /* There are still packets waiting */ | ||
| 458 | return 1; | ||
| 459 | } | ||
| 460 | |||
| 461 | static irqreturn_t dnet_interrupt(int irq, void *dev_id) | ||
| 462 | { | ||
| 463 | struct net_device *dev = dev_id; | ||
| 464 | struct dnet *bp = netdev_priv(dev); | ||
| 465 | u32 int_src, int_enable, int_current; | ||
| 466 | unsigned long flags; | ||
| 467 | unsigned int handled = 0; | ||
| 468 | |||
| 469 | spin_lock_irqsave(&bp->lock, flags); | ||
| 470 | |||
| 471 | /* read and clear the DNET irq (clear on read) */ | ||
| 472 | int_src = dnet_readl(bp, INTR_SRC); | ||
| 473 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 474 | int_current = int_src & int_enable; | ||
| 475 | |||
| 476 | /* restart the queue if we had stopped it for TX fifo almost full */ | ||
| 477 | if (int_current & DNET_INTR_SRC_TX_FIFOAE) { | ||
| 478 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 479 | int_enable &= ~DNET_INTR_ENB_TX_FIFOAE; | ||
| 480 | dnet_writel(bp, int_enable, INTR_ENB); | ||
| 481 | netif_wake_queue(dev); | ||
| 482 | handled = 1; | ||
| 483 | } | ||
| 484 | |||
| 485 | /* RX FIFO error checking */ | ||
| 486 | if (int_current & | ||
| 487 | (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) { | ||
| 488 | printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__, | ||
| 489 | dnet_readl(bp, RX_STATUS), int_current); | ||
| 490 | /* we can only flush the RX FIFOs */ | ||
| 491 | dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL); | ||
| 492 | ndelay(500); | ||
| 493 | dnet_writel(bp, 0, SYS_CTL); | ||
| 494 | handled = 1; | ||
| 495 | } | ||
| 496 | |||
| 497 | /* TX FIFO error checking */ | ||
| 498 | if (int_current & | ||
| 499 | (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) { | ||
| 500 | printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__, | ||
| 501 | dnet_readl(bp, TX_STATUS), int_current); | ||
| 502 | /* we can only flush the TX FIFOs */ | ||
| 503 | dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL); | ||
| 504 | ndelay(500); | ||
| 505 | dnet_writel(bp, 0, SYS_CTL); | ||
| 506 | handled = 1; | ||
| 507 | } | ||
| 508 | |||
| 509 | if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) { | ||
| 510 | if (napi_schedule_prep(&bp->napi)) { | ||
| 511 | /* | ||
| 512 | * There's no point taking any more interrupts | ||
| 513 | * until we have processed the buffers | ||
| 514 | */ | ||
| 515 | /* Disable Rx interrupts and schedule NAPI poll */ | ||
| 516 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 517 | int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF; | ||
| 518 | dnet_writel(bp, int_enable, INTR_ENB); | ||
| 519 | __napi_schedule(&bp->napi); | ||
| 520 | } | ||
| 521 | handled = 1; | ||
| 522 | } | ||
| 523 | |||
| 524 | if (!handled) | ||
| 525 | pr_debug("%s: irq %x remains\n", __func__, int_current); | ||
| 526 | |||
| 527 | spin_unlock_irqrestore(&bp->lock, flags); | ||
| 528 | |||
| 529 | return IRQ_RETVAL(handled); | ||
| 530 | } | ||
| 531 | |||
| 532 | #ifdef DEBUG | ||
| 533 | static inline void dnet_print_skb(struct sk_buff *skb) | ||
| 534 | { | ||
| 535 | int k; | ||
| 536 | printk(KERN_DEBUG PFX "data:"); | ||
| 537 | for (k = 0; k < skb->len; k++) | ||
| 538 | printk(" %02x", (unsigned int)skb->data[k]); | ||
| 539 | printk("\n"); | ||
| 540 | } | ||
| 541 | #else | ||
| 542 | #define dnet_print_skb(skb) do {} while (0) | ||
| 543 | #endif | ||
| 544 | |||
| 545 | static int dnet_start_xmit(struct sk_buff *skb, struct net_device *dev) | ||
| 546 | { | ||
| 547 | |||
| 548 | struct dnet *bp = netdev_priv(dev); | ||
| 549 | u32 tx_status, irq_enable; | ||
| 550 | unsigned int len, i, tx_cmd, wrsz; | ||
| 551 | unsigned long flags; | ||
| 552 | unsigned int *bufp; | ||
| 553 | |||
| 554 | tx_status = dnet_readl(bp, TX_STATUS); | ||
| 555 | |||
| 556 | pr_debug("start_xmit: len %u head %p data %p\n", | ||
| 557 | skb->len, skb->head, skb->data); | ||
| 558 | dnet_print_skb(skb); | ||
| 559 | |||
| 560 | /* frame size (words) */ | ||
| 561 | len = (skb->len + 3) >> 2; | ||
| 562 | |||
| 563 | spin_lock_irqsave(&bp->lock, flags); | ||
| 564 | |||
| 565 | tx_status = dnet_readl(bp, TX_STATUS); | ||
| 566 | |||
| 567 | bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL); | ||
| 568 | wrsz = (u32) skb->len + 3; | ||
| 569 | wrsz += ((unsigned long) skb->data) & 0x3; | ||
| 570 | wrsz >>= 2; | ||
| 571 | tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len; | ||
| 572 | |||
| 573 | /* check if there is enough room for the current frame */ | ||
| 574 | if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) { | ||
| 575 | for (i = 0; i < wrsz; i++) | ||
| 576 | dnet_writel(bp, *bufp++, TX_DATA_FIFO); | ||
| 577 | |||
| 578 | /* | ||
| 579 | * inform MAC that a packet's written and ready to be | ||
| 580 | * shipped out | ||
| 581 | */ | ||
| 582 | dnet_writel(bp, tx_cmd, TX_LEN_FIFO); | ||
| 583 | } | ||
| 584 | |||
| 585 | if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) { | ||
| 586 | netif_stop_queue(dev); | ||
| 587 | tx_status = dnet_readl(bp, INTR_SRC); | ||
| 588 | irq_enable = dnet_readl(bp, INTR_ENB); | ||
| 589 | irq_enable |= DNET_INTR_ENB_TX_FIFOAE; | ||
| 590 | dnet_writel(bp, irq_enable, INTR_ENB); | ||
| 591 | } | ||
| 592 | |||
| 593 | /* free the buffer */ | ||
| 594 | dev_kfree_skb(skb); | ||
| 595 | |||
| 596 | spin_unlock_irqrestore(&bp->lock, flags); | ||
| 597 | |||
| 598 | dev->trans_start = jiffies; | ||
| 599 | |||
| 600 | return 0; | ||
| 601 | } | ||
| 602 | |||
| 603 | static void dnet_reset_hw(struct dnet *bp) | ||
| 604 | { | ||
| 605 | /* put ts_mac in IDLE state i.e. disable rx/tx */ | ||
| 606 | dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN); | ||
| 607 | |||
| 608 | /* | ||
| 609 | * RX FIFO almost full threshold: only cmd FIFO almost full is | ||
| 610 | * implemented for RX side | ||
| 611 | */ | ||
| 612 | dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH); | ||
| 613 | /* | ||
| 614 | * TX FIFO almost empty threshold: only data FIFO almost empty | ||
| 615 | * is implemented for TX side | ||
| 616 | */ | ||
| 617 | dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH); | ||
| 618 | |||
| 619 | /* flush rx/tx fifos */ | ||
| 620 | dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH, | ||
| 621 | SYS_CTL); | ||
| 622 | msleep(1); | ||
| 623 | dnet_writel(bp, 0, SYS_CTL); | ||
| 624 | } | ||
| 625 | |||
| 626 | static void dnet_init_hw(struct dnet *bp) | ||
| 627 | { | ||
| 628 | u32 config; | ||
| 629 | |||
| 630 | dnet_reset_hw(bp); | ||
| 631 | __dnet_set_hwaddr(bp); | ||
| 632 | |||
| 633 | config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); | ||
| 634 | |||
| 635 | if (bp->dev->flags & IFF_PROMISC) | ||
| 636 | /* Copy All Frames */ | ||
| 637 | config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC; | ||
| 638 | if (!(bp->dev->flags & IFF_BROADCAST)) | ||
| 639 | /* No BroadCast */ | ||
| 640 | config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST; | ||
| 641 | |||
| 642 | config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE | | ||
| 643 | DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST | | ||
| 644 | DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL | | ||
| 645 | DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS; | ||
| 646 | |||
| 647 | dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config); | ||
| 648 | |||
| 649 | /* clear irq before enabling them */ | ||
| 650 | config = dnet_readl(bp, INTR_SRC); | ||
| 651 | |||
| 652 | /* enable RX/TX interrupt, recv packet ready interrupt */ | ||
| 653 | dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY | | ||
| 654 | DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR | | ||
| 655 | DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL | | ||
| 656 | DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM | | ||
| 657 | DNET_INTR_ENB_RX_PKTRDY, INTR_ENB); | ||
| 658 | } | ||
| 659 | |||
| 660 | static int dnet_open(struct net_device *dev) | ||
| 661 | { | ||
| 662 | struct dnet *bp = netdev_priv(dev); | ||
| 663 | |||
| 664 | /* if the phy is not yet register, retry later */ | ||
| 665 | if (!bp->phy_dev) | ||
| 666 | return -EAGAIN; | ||
| 667 | |||
| 668 | if (!is_valid_ether_addr(dev->dev_addr)) | ||
| 669 | return -EADDRNOTAVAIL; | ||
| 670 | |||
| 671 | napi_enable(&bp->napi); | ||
| 672 | dnet_init_hw(bp); | ||
| 673 | |||
| 674 | phy_start_aneg(bp->phy_dev); | ||
| 675 | |||
| 676 | /* schedule a link state check */ | ||
| 677 | phy_start(bp->phy_dev); | ||
| 678 | |||
| 679 | netif_start_queue(dev); | ||
| 680 | |||
| 681 | return 0; | ||
| 682 | } | ||
| 683 | |||
| 684 | static int dnet_close(struct net_device *dev) | ||
| 685 | { | ||
| 686 | struct dnet *bp = netdev_priv(dev); | ||
| 687 | |||
| 688 | netif_stop_queue(dev); | ||
| 689 | napi_disable(&bp->napi); | ||
| 690 | |||
| 691 | if (bp->phy_dev) | ||
| 692 | phy_stop(bp->phy_dev); | ||
| 693 | |||
| 694 | dnet_reset_hw(bp); | ||
| 695 | netif_carrier_off(dev); | ||
| 696 | |||
| 697 | return 0; | ||
| 698 | } | ||
| 699 | |||
| 700 | static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat) | ||
| 701 | { | ||
| 702 | pr_debug("%s\n", __func__); | ||
| 703 | pr_debug("----------------------------- RX statistics " | ||
| 704 | "-------------------------------\n"); | ||
| 705 | pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr); | ||
| 706 | pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err); | ||
| 707 | pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm); | ||
| 708 | pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm); | ||
| 709 | pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol); | ||
| 710 | pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err); | ||
| 711 | pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt); | ||
| 712 | pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm); | ||
| 713 | pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm); | ||
| 714 | pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast); | ||
| 715 | pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast); | ||
| 716 | pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag); | ||
| 717 | pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink); | ||
| 718 | pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib); | ||
| 719 | pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd); | ||
| 720 | pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte); | ||
| 721 | pr_debug("----------------------------- TX statistics " | ||
| 722 | "-------------------------------\n"); | ||
| 723 | pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast); | ||
| 724 | pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm); | ||
| 725 | pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast); | ||
| 726 | pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast); | ||
| 727 | pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag); | ||
| 728 | pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs); | ||
| 729 | pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo); | ||
| 730 | pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte); | ||
| 731 | } | ||
| 732 | |||
| 733 | static struct net_device_stats *dnet_get_stats(struct net_device *dev) | ||
| 734 | { | ||
| 735 | |||
| 736 | struct dnet *bp = netdev_priv(dev); | ||
| 737 | struct net_device_stats *nstat = &dev->stats; | ||
| 738 | struct dnet_stats *hwstat = &bp->hw_stats; | ||
| 739 | |||
| 740 | /* read stats from hardware */ | ||
| 741 | dnet_update_stats(bp); | ||
| 742 | |||
| 743 | /* Convert HW stats into netdevice stats */ | ||
| 744 | nstat->rx_errors = (hwstat->rx_len_chk_err + | ||
| 745 | hwstat->rx_lng_frm + hwstat->rx_shrt_frm + | ||
| 746 | /* ignore IGP violation error | ||
| 747 | hwstat->rx_ipg_viol + */ | ||
| 748 | hwstat->rx_crc_err + | ||
| 749 | hwstat->rx_pre_shrink + | ||
| 750 | hwstat->rx_drib_nib + hwstat->rx_unsup_opcd); | ||
| 751 | nstat->tx_errors = hwstat->tx_bad_fcs; | ||
| 752 | nstat->rx_length_errors = (hwstat->rx_len_chk_err + | ||
| 753 | hwstat->rx_lng_frm + | ||
| 754 | hwstat->rx_shrt_frm + hwstat->rx_pre_shrink); | ||
| 755 | nstat->rx_crc_errors = hwstat->rx_crc_err; | ||
| 756 | nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib; | ||
| 757 | nstat->rx_packets = hwstat->rx_ok_pkt; | ||
| 758 | nstat->tx_packets = (hwstat->tx_unicast + | ||
| 759 | hwstat->tx_multicast + hwstat->tx_brdcast); | ||
| 760 | nstat->rx_bytes = hwstat->rx_byte; | ||
| 761 | nstat->tx_bytes = hwstat->tx_byte; | ||
| 762 | nstat->multicast = hwstat->rx_multicast; | ||
| 763 | nstat->rx_missed_errors = hwstat->rx_pkt_ignr; | ||
| 764 | |||
| 765 | dnet_print_pretty_hwstats(hwstat); | ||
| 766 | |||
| 767 | return nstat; | ||
| 768 | } | ||
| 769 | |||
| 770 | static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
| 771 | { | ||
| 772 | struct dnet *bp = netdev_priv(dev); | ||
| 773 | struct phy_device *phydev = bp->phy_dev; | ||
| 774 | |||
| 775 | if (!phydev) | ||
| 776 | return -ENODEV; | ||
| 777 | |||
| 778 | return phy_ethtool_gset(phydev, cmd); | ||
| 779 | } | ||
| 780 | |||
| 781 | static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
| 782 | { | ||
| 783 | struct dnet *bp = netdev_priv(dev); | ||
| 784 | struct phy_device *phydev = bp->phy_dev; | ||
| 785 | |||
| 786 | if (!phydev) | ||
| 787 | return -ENODEV; | ||
| 788 | |||
| 789 | return phy_ethtool_sset(phydev, cmd); | ||
| 790 | } | ||
| 791 | |||
| 792 | static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | ||
| 793 | { | ||
| 794 | struct dnet *bp = netdev_priv(dev); | ||
| 795 | struct phy_device *phydev = bp->phy_dev; | ||
| 796 | |||
| 797 | if (!netif_running(dev)) | ||
| 798 | return -EINVAL; | ||
| 799 | |||
| 800 | if (!phydev) | ||
| 801 | return -ENODEV; | ||
| 802 | |||
| 803 | return phy_mii_ioctl(phydev, if_mii(rq), cmd); | ||
| 804 | } | ||
| 805 | |||
| 806 | static void dnet_get_drvinfo(struct net_device *dev, | ||
| 807 | struct ethtool_drvinfo *info) | ||
| 808 | { | ||
| 809 | strcpy(info->driver, DRV_NAME); | ||
| 810 | strcpy(info->version, DRV_VERSION); | ||
| 811 | strcpy(info->bus_info, "0"); | ||
| 812 | } | ||
| 813 | |||
| 814 | static const struct ethtool_ops dnet_ethtool_ops = { | ||
| 815 | .get_settings = dnet_get_settings, | ||
| 816 | .set_settings = dnet_set_settings, | ||
| 817 | .get_drvinfo = dnet_get_drvinfo, | ||
| 818 | .get_link = ethtool_op_get_link, | ||
| 819 | }; | ||
| 820 | |||
| 821 | static const struct net_device_ops dnet_netdev_ops = { | ||
| 822 | .ndo_open = dnet_open, | ||
| 823 | .ndo_stop = dnet_close, | ||
| 824 | .ndo_get_stats = dnet_get_stats, | ||
| 825 | .ndo_start_xmit = dnet_start_xmit, | ||
| 826 | .ndo_do_ioctl = dnet_ioctl, | ||
| 827 | .ndo_set_mac_address = eth_mac_addr, | ||
| 828 | .ndo_validate_addr = eth_validate_addr, | ||
| 829 | .ndo_change_mtu = eth_change_mtu, | ||
| 830 | }; | ||
| 831 | |||
| 832 | static int __devinit dnet_probe(struct platform_device *pdev) | ||
| 833 | { | ||
| 834 | struct resource *res; | ||
| 835 | struct net_device *dev; | ||
| 836 | struct dnet *bp; | ||
| 837 | struct phy_device *phydev; | ||
| 838 | int err = -ENXIO; | ||
| 839 | unsigned int mem_base, mem_size, irq; | ||
| 840 | |||
| 841 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 842 | if (!res) { | ||
| 843 | dev_err(&pdev->dev, "no mmio resource defined\n"); | ||
| 844 | goto err_out; | ||
| 845 | } | ||
| 846 | mem_base = res->start; | ||
| 847 | mem_size = resource_size(res); | ||
| 848 | irq = platform_get_irq(pdev, 0); | ||
| 849 | |||
| 850 | if (!request_mem_region(mem_base, mem_size, DRV_NAME)) { | ||
| 851 | dev_err(&pdev->dev, "no memory region available\n"); | ||
| 852 | err = -EBUSY; | ||
| 853 | goto err_out; | ||
| 854 | } | ||
| 855 | |||
| 856 | err = -ENOMEM; | ||
| 857 | dev = alloc_etherdev(sizeof(*bp)); | ||
| 858 | if (!dev) { | ||
| 859 | dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n"); | ||
| 860 | goto err_out; | ||
| 861 | } | ||
| 862 | |||
| 863 | /* TODO: Actually, we have some interesting features... */ | ||
| 864 | dev->features |= 0; | ||
| 865 | |||
| 866 | bp = netdev_priv(dev); | ||
| 867 | bp->dev = dev; | ||
| 868 | |||
| 869 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
| 870 | |||
| 871 | spin_lock_init(&bp->lock); | ||
| 872 | |||
| 873 | bp->regs = ioremap(mem_base, mem_size); | ||
| 874 | if (!bp->regs) { | ||
| 875 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | ||
| 876 | err = -ENOMEM; | ||
| 877 | goto err_out_free_dev; | ||
| 878 | } | ||
| 879 | |||
| 880 | dev->irq = irq; | ||
| 881 | err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev); | ||
| 882 | if (err) { | ||
| 883 | dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", | ||
| 884 | irq, err); | ||
| 885 | goto err_out_iounmap; | ||
| 886 | } | ||
| 887 | |||
| 888 | dev->netdev_ops = &dnet_netdev_ops; | ||
| 889 | netif_napi_add(dev, &bp->napi, dnet_poll, 64); | ||
| 890 | dev->ethtool_ops = &dnet_ethtool_ops; | ||
| 891 | |||
| 892 | dev->base_addr = (unsigned long)bp->regs; | ||
| 893 | |||
| 894 | bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK; | ||
| 895 | |||
| 896 | dnet_get_hwaddr(bp); | ||
| 897 | |||
| 898 | if (!is_valid_ether_addr(dev->dev_addr)) { | ||
| 899 | /* choose a random ethernet address */ | ||
| 900 | random_ether_addr(dev->dev_addr); | ||
| 901 | __dnet_set_hwaddr(bp); | ||
| 902 | } | ||
| 903 | |||
| 904 | err = register_netdev(dev); | ||
| 905 | if (err) { | ||
| 906 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | ||
| 907 | goto err_out_free_irq; | ||
| 908 | } | ||
| 909 | |||
| 910 | /* register the PHY board fixup (for Marvell 88E1111) */ | ||
| 911 | err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0, | ||
| 912 | dnet_phy_marvell_fixup); | ||
| 913 | /* we can live without it, so just issue a warning */ | ||
| 914 | if (err) | ||
| 915 | dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n"); | ||
| 916 | |||
| 917 | if (dnet_mii_init(bp) != 0) | ||
| 918 | goto err_out_unregister_netdev; | ||
| 919 | |||
| 920 | dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n", | ||
| 921 | bp->regs, mem_base, dev->irq, dev->dev_addr); | ||
| 922 | dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma \n", | ||
| 923 | (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ", | ||
| 924 | (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ", | ||
| 925 | (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ", | ||
| 926 | (bp->capabilities & DNET_HAS_DMA) ? "" : "no "); | ||
| 927 | phydev = bp->phy_dev; | ||
| 928 | dev_info(&pdev->dev, "attached PHY driver [%s] " | ||
| 929 | "(mii_bus:phy_addr=%s, irq=%d)\n", | ||
| 930 | phydev->drv->name, phydev->dev.bus_id, phydev->irq); | ||
| 931 | |||
| 932 | return 0; | ||
| 933 | |||
| 934 | err_out_unregister_netdev: | ||
| 935 | unregister_netdev(dev); | ||
| 936 | err_out_free_irq: | ||
| 937 | free_irq(dev->irq, dev); | ||
| 938 | err_out_iounmap: | ||
| 939 | iounmap(bp->regs); | ||
| 940 | err_out_free_dev: | ||
| 941 | free_netdev(dev); | ||
| 942 | err_out: | ||
| 943 | return err; | ||
| 944 | } | ||
| 945 | |||
| 946 | static int __devexit dnet_remove(struct platform_device *pdev) | ||
| 947 | { | ||
| 948 | |||
| 949 | struct net_device *dev; | ||
| 950 | struct dnet *bp; | ||
| 951 | |||
| 952 | dev = platform_get_drvdata(pdev); | ||
| 953 | |||
| 954 | if (dev) { | ||
| 955 | bp = netdev_priv(dev); | ||
| 956 | if (bp->phy_dev) | ||
| 957 | phy_disconnect(bp->phy_dev); | ||
| 958 | mdiobus_unregister(bp->mii_bus); | ||
| 959 | kfree(bp->mii_bus->irq); | ||
| 960 | mdiobus_free(bp->mii_bus); | ||
| 961 | unregister_netdev(dev); | ||
| 962 | free_irq(dev->irq, dev); | ||
| 963 | iounmap(bp->regs); | ||
| 964 | free_netdev(dev); | ||
| 965 | } | ||
| 966 | |||
| 967 | return 0; | ||
| 968 | } | ||
| 969 | |||
| 970 | static struct platform_driver dnet_driver = { | ||
| 971 | .probe = dnet_probe, | ||
| 972 | .remove = __devexit_p(dnet_remove), | ||
| 973 | .driver = { | ||
| 974 | .name = "dnet", | ||
| 975 | }, | ||
| 976 | }; | ||
| 977 | |||
| 978 | static int __init dnet_init(void) | ||
| 979 | { | ||
| 980 | return platform_driver_register(&dnet_driver); | ||
| 981 | } | ||
| 982 | |||
| 983 | static void __exit dnet_exit(void) | ||
| 984 | { | ||
| 985 | platform_driver_unregister(&dnet_driver); | ||
| 986 | } | ||
| 987 | |||
| 988 | module_init(dnet_init); | ||
| 989 | module_exit(dnet_exit); | ||
| 990 | |||
| 991 | MODULE_LICENSE("GPL"); | ||
| 992 | MODULE_DESCRIPTION("Dave DNET Ethernet driver"); | ||
| 993 | MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, " | ||
| 994 | "Matteo Vit <matteo.vit@dave.eu>"); | ||
diff --git a/drivers/net/dnet.h b/drivers/net/dnet.h new file mode 100644 index 000000000000..37f5b30fa78b --- /dev/null +++ b/drivers/net/dnet.h | |||
| @@ -0,0 +1,225 @@ | |||
| 1 | /* | ||
| 2 | * Dave DNET Ethernet Controller driver | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #ifndef _DNET_H | ||
| 11 | #define _DNET_H | ||
| 12 | |||
| 13 | #define DRV_NAME "dnet" | ||
| 14 | #define DRV_VERSION "0.9.1" | ||
| 15 | #define PFX DRV_NAME ": " | ||
| 16 | |||
| 17 | /* Register access macros */ | ||
| 18 | #define dnet_writel(port, value, reg) \ | ||
| 19 | writel((value), (port)->regs + DNET_##reg) | ||
| 20 | #define dnet_readl(port, reg) readl((port)->regs + DNET_##reg) | ||
| 21 | |||
| 22 | /* ALL DNET FIFO REGISTERS */ | ||
| 23 | #define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */ | ||
| 24 | #define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */ | ||
| 25 | #define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */ | ||
| 26 | #define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */ | ||
| 27 | |||
| 28 | /* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */ | ||
| 29 | #define DNET_VERCAPS 0x100 /* VERCAPS */ | ||
| 30 | #define DNET_INTR_SRC 0x104 /* INTR_SRC */ | ||
| 31 | #define DNET_INTR_ENB 0x108 /* INTR_ENB */ | ||
| 32 | #define DNET_RX_STATUS 0x10C /* RX_STATUS */ | ||
| 33 | #define DNET_TX_STATUS 0x110 /* TX_STATUS */ | ||
| 34 | #define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */ | ||
| 35 | #define DNET_TX_FRAMES_CNT 0x118 /* TX_FRAMES_CNT */ | ||
| 36 | #define DNET_RX_FIFO_TH 0x11C /* RX_FIFO_TH */ | ||
| 37 | #define DNET_TX_FIFO_TH 0x120 /* TX_FIFO_TH */ | ||
| 38 | #define DNET_SYS_CTL 0x124 /* SYS_CTL */ | ||
| 39 | #define DNET_PAUSE_TMR 0x128 /* PAUSE_TMR */ | ||
| 40 | #define DNET_RX_FIFO_WCNT 0x12C /* RX_FIFO_WCNT */ | ||
| 41 | #define DNET_TX_FIFO_WCNT 0x130 /* TX_FIFO_WCNT */ | ||
| 42 | |||
| 43 | /* ALL DNET MAC REGISTERS */ | ||
| 44 | #define DNET_MACREG_DATA 0x200 /* Mac-Reg Data */ | ||
| 45 | #define DNET_MACREG_ADDR 0x204 /* Mac-Reg Addr */ | ||
| 46 | |||
| 47 | /* ALL DNET RX STATISTICS COUNTERS */ | ||
| 48 | #define DNET_RX_PKT_IGNR_CNT 0x300 | ||
| 49 | #define DNET_RX_LEN_CHK_ERR_CNT 0x304 | ||
| 50 | #define DNET_RX_LNG_FRM_CNT 0x308 | ||
| 51 | #define DNET_RX_SHRT_FRM_CNT 0x30C | ||
| 52 | #define DNET_RX_IPG_VIOL_CNT 0x310 | ||
| 53 | #define DNET_RX_CRC_ERR_CNT 0x314 | ||
| 54 | #define DNET_RX_OK_PKT_CNT 0x318 | ||
| 55 | #define DNET_RX_CTL_FRM_CNT 0x31C | ||
| 56 | #define DNET_RX_PAUSE_FRM_CNT 0x320 | ||
| 57 | #define DNET_RX_MULTICAST_CNT 0x324 | ||
| 58 | #define DNET_RX_BROADCAST_CNT 0x328 | ||
| 59 | #define DNET_RX_VLAN_TAG_CNT 0x32C | ||
| 60 | #define DNET_RX_PRE_SHRINK_CNT 0x330 | ||
| 61 | #define DNET_RX_DRIB_NIB_CNT 0x334 | ||
| 62 | #define DNET_RX_UNSUP_OPCD_CNT 0x338 | ||
| 63 | #define DNET_RX_BYTE_CNT 0x33C | ||
| 64 | |||
| 65 | /* DNET TX STATISTICS COUNTERS */ | ||
| 66 | #define DNET_TX_UNICAST_CNT 0x400 | ||
| 67 | #define DNET_TX_PAUSE_FRM_CNT 0x404 | ||
| 68 | #define DNET_TX_MULTICAST_CNT 0x408 | ||
| 69 | #define DNET_TX_BRDCAST_CNT 0x40C | ||
| 70 | #define DNET_TX_VLAN_TAG_CNT 0x410 | ||
| 71 | #define DNET_TX_BAD_FCS_CNT 0x414 | ||
| 72 | #define DNET_TX_JUMBO_CNT 0x418 | ||
| 73 | #define DNET_TX_BYTE_CNT 0x41C | ||
| 74 | |||
| 75 | /* SOME INTERNAL MAC-CORE REGISTER */ | ||
| 76 | #define DNET_INTERNAL_MODE_REG 0x0 | ||
| 77 | #define DNET_INTERNAL_RXTX_CONTROL_REG 0x2 | ||
| 78 | #define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4 | ||
| 79 | #define DNET_INTERNAL_IGP_REG 0x8 | ||
| 80 | #define DNET_INTERNAL_MAC_ADDR_0_REG 0xa | ||
| 81 | #define DNET_INTERNAL_MAC_ADDR_1_REG 0xc | ||
| 82 | #define DNET_INTERNAL_MAC_ADDR_2_REG 0xe | ||
| 83 | #define DNET_INTERNAL_TX_RX_STS_REG 0x12 | ||
| 84 | #define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14 | ||
| 85 | #define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16 | ||
| 86 | |||
| 87 | #define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14) | ||
| 88 | |||
| 89 | #define DNET_INTERNAL_WRITE (1 << 31) | ||
| 90 | |||
| 91 | /* MAC-CORE REGISTER FIELDS */ | ||
| 92 | |||
| 93 | /* MAC-CORE MODE REGISTER FIELDS */ | ||
| 94 | #define DNET_INTERNAL_MODE_GBITEN (1 << 0) | ||
| 95 | #define DNET_INTERNAL_MODE_FCEN (1 << 1) | ||
| 96 | #define DNET_INTERNAL_MODE_RXEN (1 << 2) | ||
| 97 | #define DNET_INTERNAL_MODE_TXEN (1 << 3) | ||
| 98 | |||
| 99 | /* MAC-CORE RXTX CONTROL REGISTER FIELDS */ | ||
| 100 | #define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8) | ||
| 101 | #define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7) | ||
| 102 | #define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4) | ||
| 103 | #define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3) | ||
| 104 | #define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2) | ||
| 105 | #define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1) | ||
| 106 | #define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0) | ||
| 107 | #define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6) | ||
| 108 | #define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5) | ||
| 109 | |||
| 110 | /* SYSTEM CONTROL REGISTER FIELDS */ | ||
| 111 | #define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0) | ||
| 112 | #define DNET_SYS_CTL_SENDPAUSE (1 << 2) | ||
| 113 | #define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3) | ||
| 114 | #define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4) | ||
| 115 | |||
| 116 | /* TX STATUS REGISTER FIELDS */ | ||
| 117 | #define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2) | ||
| 118 | #define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1) | ||
| 119 | |||
| 120 | /* INTERRUPT SOURCE REGISTER FIELDS */ | ||
| 121 | #define DNET_INTR_SRC_TX_PKTSENT (1 << 0) | ||
| 122 | #define DNET_INTR_SRC_TX_FIFOAF (1 << 1) | ||
| 123 | #define DNET_INTR_SRC_TX_FIFOAE (1 << 2) | ||
| 124 | #define DNET_INTR_SRC_TX_DISCFRM (1 << 3) | ||
| 125 | #define DNET_INTR_SRC_TX_FIFOFULL (1 << 4) | ||
| 126 | #define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8) | ||
| 127 | #define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9) | ||
| 128 | #define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10) | ||
| 129 | #define DNET_INTR_SRC_TX_SUMMARY (1 << 16) | ||
| 130 | #define DNET_INTR_SRC_RX_SUMMARY (1 << 17) | ||
| 131 | #define DNET_INTR_SRC_PHY (1 << 19) | ||
| 132 | |||
| 133 | /* INTERRUPT ENABLE REGISTER FIELDS */ | ||
| 134 | #define DNET_INTR_ENB_TX_PKTSENT (1 << 0) | ||
| 135 | #define DNET_INTR_ENB_TX_FIFOAF (1 << 1) | ||
| 136 | #define DNET_INTR_ENB_TX_FIFOAE (1 << 2) | ||
| 137 | #define DNET_INTR_ENB_TX_DISCFRM (1 << 3) | ||
| 138 | #define DNET_INTR_ENB_TX_FIFOFULL (1 << 4) | ||
| 139 | #define DNET_INTR_ENB_RX_PKTRDY (1 << 8) | ||
| 140 | #define DNET_INTR_ENB_RX_FIFOAF (1 << 9) | ||
| 141 | #define DNET_INTR_ENB_RX_FIFOERR (1 << 10) | ||
| 142 | #define DNET_INTR_ENB_RX_ERROR (1 << 11) | ||
| 143 | #define DNET_INTR_ENB_RX_FIFOFULL (1 << 12) | ||
| 144 | #define DNET_INTR_ENB_RX_FIFOAE (1 << 13) | ||
| 145 | #define DNET_INTR_ENB_TX_SUMMARY (1 << 16) | ||
| 146 | #define DNET_INTR_ENB_RX_SUMMARY (1 << 17) | ||
| 147 | #define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18) | ||
| 148 | |||
| 149 | /* default values: | ||
| 150 | * almost empty = less than one full sized ethernet frame (no jumbo) inside | ||
| 151 | * the fifo almost full = can write less than one full sized ethernet frame | ||
| 152 | * (no jumbo) inside the fifo | ||
| 153 | */ | ||
| 154 | #define DNET_CFG_TX_FIFO_FULL_THRES 25 | ||
| 155 | #define DNET_CFG_RX_FIFO_FULL_THRES 20 | ||
| 156 | |||
| 157 | /* | ||
| 158 | * Capabilities. Used by the driver to know the capabilities that the ethernet | ||
| 159 | * controller inside the FPGA have. | ||
| 160 | */ | ||
| 161 | |||
| 162 | #define DNET_HAS_MDIO (1 << 0) | ||
| 163 | #define DNET_HAS_IRQ (1 << 1) | ||
| 164 | #define DNET_HAS_GIGABIT (1 << 2) | ||
| 165 | #define DNET_HAS_DMA (1 << 3) | ||
| 166 | |||
| 167 | #define DNET_HAS_MII (1 << 4) /* or GMII */ | ||
| 168 | #define DNET_HAS_RMII (1 << 5) /* or RGMII */ | ||
| 169 | |||
| 170 | #define DNET_CAPS_MASK 0xFFFF | ||
| 171 | |||
| 172 | #define DNET_FIFO_SIZE 1024 /* 1K x 32 bit */ | ||
| 173 | #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */ | ||
| 174 | #define DNET_FIFO_TX_DATA_AE_TH 384 | ||
| 175 | |||
| 176 | #define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */ | ||
| 177 | |||
| 178 | /* | ||
| 179 | * Hardware-collected statistics. | ||
| 180 | */ | ||
| 181 | struct dnet_stats { | ||
| 182 | u32 rx_pkt_ignr; | ||
| 183 | u32 rx_len_chk_err; | ||
| 184 | u32 rx_lng_frm; | ||
| 185 | u32 rx_shrt_frm; | ||
| 186 | u32 rx_ipg_viol; | ||
| 187 | u32 rx_crc_err; | ||
| 188 | u32 rx_ok_pkt; | ||
| 189 | u32 rx_ctl_frm; | ||
| 190 | u32 rx_pause_frm; | ||
| 191 | u32 rx_multicast; | ||
| 192 | u32 rx_broadcast; | ||
| 193 | u32 rx_vlan_tag; | ||
| 194 | u32 rx_pre_shrink; | ||
| 195 | u32 rx_drib_nib; | ||
| 196 | u32 rx_unsup_opcd; | ||
| 197 | u32 rx_byte; | ||
| 198 | u32 tx_unicast; | ||
| 199 | u32 tx_pause_frm; | ||
| 200 | u32 tx_multicast; | ||
| 201 | u32 tx_brdcast; | ||
| 202 | u32 tx_vlan_tag; | ||
| 203 | u32 tx_bad_fcs; | ||
| 204 | u32 tx_jumbo; | ||
| 205 | u32 tx_byte; | ||
| 206 | }; | ||
| 207 | |||
| 208 | struct dnet { | ||
| 209 | void __iomem *regs; | ||
| 210 | spinlock_t lock; | ||
| 211 | struct platform_device *pdev; | ||
| 212 | struct net_device *dev; | ||
| 213 | struct dnet_stats hw_stats; | ||
| 214 | unsigned int capabilities; /* read from FPGA */ | ||
| 215 | struct napi_struct napi; | ||
| 216 | |||
| 217 | /* PHY stuff */ | ||
| 218 | struct mii_bus *mii_bus; | ||
| 219 | struct phy_device *phy_dev; | ||
| 220 | unsigned int link; | ||
| 221 | unsigned int speed; | ||
| 222 | unsigned int duplex; | ||
| 223 | }; | ||
| 224 | |||
| 225 | #endif /* _DNET_H */ | ||
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c index 87a706694fb3..6fd7aa61736e 100644 --- a/drivers/net/ibm_newemac/core.c +++ b/drivers/net/ibm_newemac/core.c | |||
| @@ -2594,6 +2594,9 @@ static int __devinit emac_init_config(struct emac_instance *dev) | |||
| 2594 | if (of_device_is_compatible(np, "ibm,emac-460ex") || | 2594 | if (of_device_is_compatible(np, "ibm,emac-460ex") || |
| 2595 | of_device_is_compatible(np, "ibm,emac-460gt")) | 2595 | of_device_is_compatible(np, "ibm,emac-460gt")) |
| 2596 | dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX; | 2596 | dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX; |
| 2597 | if (of_device_is_compatible(np, "ibm,emac-405ex") || | ||
| 2598 | of_device_is_compatible(np, "ibm,emac-405exr")) | ||
| 2599 | dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; | ||
| 2597 | } else if (of_device_is_compatible(np, "ibm,emac4")) { | 2600 | } else if (of_device_is_compatible(np, "ibm,emac4")) { |
| 2598 | dev->features |= EMAC_FTR_EMAC4; | 2601 | dev->features |= EMAC_FTR_EMAC4; |
| 2599 | if (of_device_is_compatible(np, "ibm,emac-440gx")) | 2602 | if (of_device_is_compatible(np, "ibm,emac-440gx")) |
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index a50db5398fa5..9dd13ad12ce4 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c | |||
| @@ -1023,11 +1023,10 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
| 1023 | struct net_device *netdev; | 1023 | struct net_device *netdev; |
| 1024 | struct igb_adapter *adapter; | 1024 | struct igb_adapter *adapter; |
| 1025 | struct e1000_hw *hw; | 1025 | struct e1000_hw *hw; |
| 1026 | struct pci_dev *us_dev; | ||
| 1027 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; | 1026 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
| 1028 | unsigned long mmio_start, mmio_len; | 1027 | unsigned long mmio_start, mmio_len; |
| 1029 | int i, err, pci_using_dac, pos; | 1028 | int i, err, pci_using_dac; |
| 1030 | u16 eeprom_data = 0, state = 0; | 1029 | u16 eeprom_data = 0; |
| 1031 | u16 eeprom_apme_mask = IGB_EEPROM_APME; | 1030 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
| 1032 | u32 part_num; | 1031 | u32 part_num; |
| 1033 | int bars, need_ioport; | 1032 | int bars, need_ioport; |
| @@ -1062,27 +1061,6 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
| 1062 | } | 1061 | } |
| 1063 | } | 1062 | } |
| 1064 | 1063 | ||
| 1065 | /* 82575 requires that the pci-e link partner disable the L0s state */ | ||
| 1066 | switch (pdev->device) { | ||
| 1067 | case E1000_DEV_ID_82575EB_COPPER: | ||
| 1068 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | ||
| 1069 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | ||
| 1070 | us_dev = pdev->bus->self; | ||
| 1071 | pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP); | ||
| 1072 | if (pos) { | ||
| 1073 | pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL, | ||
| 1074 | &state); | ||
| 1075 | state &= ~PCIE_LINK_STATE_L0S; | ||
| 1076 | pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL, | ||
| 1077 | state); | ||
| 1078 | dev_info(&pdev->dev, | ||
| 1079 | "Disabling ASPM L0s upstream switch port %s\n", | ||
| 1080 | pci_name(us_dev)); | ||
| 1081 | } | ||
| 1082 | default: | ||
| 1083 | break; | ||
| 1084 | } | ||
| 1085 | |||
| 1086 | err = pci_request_selected_regions(pdev, bars, igb_driver_name); | 1064 | err = pci_request_selected_regions(pdev, bars, igb_driver_name); |
| 1087 | if (err) | 1065 | if (err) |
| 1088 | goto err_pci_reg; | 1066 | goto err_pci_reg; |
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index d2f4d5f508b7..5d364a96e35d 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c | |||
| @@ -3973,6 +3973,7 @@ static const struct net_device_ops ixgbe_netdev_ops = { | |||
| 3973 | .ndo_stop = ixgbe_close, | 3973 | .ndo_stop = ixgbe_close, |
| 3974 | .ndo_start_xmit = ixgbe_xmit_frame, | 3974 | .ndo_start_xmit = ixgbe_xmit_frame, |
| 3975 | .ndo_get_stats = ixgbe_get_stats, | 3975 | .ndo_get_stats = ixgbe_get_stats, |
| 3976 | .ndo_set_rx_mode = ixgbe_set_rx_mode, | ||
| 3976 | .ndo_set_multicast_list = ixgbe_set_rx_mode, | 3977 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
| 3977 | .ndo_validate_addr = eth_validate_addr, | 3978 | .ndo_validate_addr = eth_validate_addr, |
| 3978 | .ndo_set_mac_address = ixgbe_set_mac, | 3979 | .ndo_set_mac_address = ixgbe_set_mac, |
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 13f11f402a99..b0bc3bc18e9c 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c | |||
| @@ -2030,11 +2030,6 @@ static void port_start(struct mv643xx_eth_private *mp) | |||
| 2030 | } | 2030 | } |
| 2031 | 2031 | ||
| 2032 | /* | 2032 | /* |
| 2033 | * Add configured unicast address to address filter table. | ||
| 2034 | */ | ||
| 2035 | mv643xx_eth_program_unicast_filter(mp->dev); | ||
| 2036 | |||
| 2037 | /* | ||
| 2038 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | 2033 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast |
| 2039 | * frames to RX queue #0, and include the pseudo-header when | 2034 | * frames to RX queue #0, and include the pseudo-header when |
| 2040 | * calculating receive checksums. | 2035 | * calculating receive checksums. |
| @@ -2047,6 +2042,11 @@ static void port_start(struct mv643xx_eth_private *mp) | |||
| 2047 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); | 2042 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); |
| 2048 | 2043 | ||
| 2049 | /* | 2044 | /* |
| 2045 | * Add configured unicast addresses to address filter table. | ||
| 2046 | */ | ||
| 2047 | mv643xx_eth_program_unicast_filter(mp->dev); | ||
| 2048 | |||
| 2049 | /* | ||
| 2050 | * Enable the receive queues. | 2050 | * Enable the receive queues. |
| 2051 | */ | 2051 | */ |
| 2052 | for (i = 0; i < mp->rxq_count; i++) { | 2052 | for (i = 0; i < mp->rxq_count; i++) { |
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h index f4dd9acb6877..1ff066b2281a 100644 --- a/drivers/net/netxen/netxen_nic.h +++ b/drivers/net/netxen/netxen_nic.h | |||
| @@ -1595,7 +1595,6 @@ dma_watchdog_wakeup(struct netxen_adapter *adapter) | |||
| 1595 | } | 1595 | } |
| 1596 | 1596 | ||
| 1597 | 1597 | ||
| 1598 | int netxen_is_flash_supported(struct netxen_adapter *adapter); | ||
| 1599 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); | 1598 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
| 1600 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); | 1599 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
| 1601 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); | 1600 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c index 821cff68b3f3..7fea77088108 100644 --- a/drivers/net/netxen/netxen_nic_hw.c +++ b/drivers/net/netxen/netxen_nic_hw.c | |||
| @@ -706,28 +706,6 @@ int netxen_nic_change_mtu(struct net_device *netdev, int mtu) | |||
| 706 | return rc; | 706 | return rc; |
| 707 | } | 707 | } |
| 708 | 708 | ||
| 709 | int netxen_is_flash_supported(struct netxen_adapter *adapter) | ||
| 710 | { | ||
| 711 | const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 }; | ||
| 712 | int addr, val01, val02, i, j; | ||
| 713 | |||
| 714 | /* if the flash size less than 4Mb, make huge war cry and die */ | ||
| 715 | for (j = 1; j < 4; j++) { | ||
| 716 | addr = j * NETXEN_NIC_WINDOW_MARGIN; | ||
| 717 | for (i = 0; i < ARRAY_SIZE(locs); i++) { | ||
| 718 | if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0 | ||
| 719 | && netxen_rom_fast_read(adapter, (addr + locs[i]), | ||
| 720 | &val02) == 0) { | ||
| 721 | if (val01 == val02) | ||
| 722 | return -1; | ||
| 723 | } else | ||
| 724 | return -1; | ||
| 725 | } | ||
| 726 | } | ||
| 727 | |||
| 728 | return 0; | ||
| 729 | } | ||
| 730 | |||
| 731 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, | 709 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, |
| 732 | int size, __le32 * buf) | 710 | int size, __le32 * buf) |
| 733 | { | 711 | { |
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c index 13087782ac40..c172b6e24a96 100644 --- a/drivers/net/netxen/netxen_nic_main.c +++ b/drivers/net/netxen/netxen_nic_main.c | |||
| @@ -405,9 +405,6 @@ netxen_read_mac_addr(struct netxen_adapter *adapter) | |||
| 405 | struct net_device *netdev = adapter->netdev; | 405 | struct net_device *netdev = adapter->netdev; |
| 406 | struct pci_dev *pdev = adapter->pdev; | 406 | struct pci_dev *pdev = adapter->pdev; |
| 407 | 407 | ||
| 408 | if (netxen_is_flash_supported(adapter) != 0) | ||
| 409 | return -EIO; | ||
| 410 | |||
| 411 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | 408 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
| 412 | if (netxen_p3_get_mac_addr(adapter, &mac_addr) != 0) | 409 | if (netxen_p3_get_mac_addr(adapter, &mac_addr) != 0) |
| 413 | return -EIO; | 410 | return -EIO; |
diff --git a/drivers/net/qlge/qlge.h b/drivers/net/qlge/qlge.h index e6fdce9206cc..aff9c5fec738 100644 --- a/drivers/net/qlge/qlge.h +++ b/drivers/net/qlge/qlge.h | |||
| @@ -927,6 +927,7 @@ struct ib_mac_iocb_rsp { | |||
| 927 | u8 flags1; | 927 | u8 flags1; |
| 928 | #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */ | 928 | #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */ |
| 929 | #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */ | 929 | #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */ |
| 930 | #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */ | ||
| 930 | #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */ | 931 | #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */ |
| 931 | #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */ | 932 | #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */ |
| 932 | #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */ | 933 | #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */ |
diff --git a/drivers/net/qlge/qlge_main.c b/drivers/net/qlge/qlge_main.c index 8ea72dc60f79..91191f761fba 100644 --- a/drivers/net/qlge/qlge_main.c +++ b/drivers/net/qlge/qlge_main.c | |||
| @@ -1436,18 +1436,32 @@ static void ql_process_mac_rx_intr(struct ql_adapter *qdev, | |||
| 1436 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) { | 1436 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) { |
| 1437 | QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n"); | 1437 | QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n"); |
| 1438 | } | 1438 | } |
| 1439 | if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) { | 1439 | |
| 1440 | QPRINTK(qdev, RX_STATUS, ERR, | 1440 | skb->protocol = eth_type_trans(skb, ndev); |
| 1441 | "Bad checksum for this %s packet.\n", | 1441 | skb->ip_summed = CHECKSUM_NONE; |
| 1442 | ((ib_mac_rsp-> | 1442 | |
| 1443 | flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP")); | 1443 | /* If rx checksum is on, and there are no |
| 1444 | skb->ip_summed = CHECKSUM_NONE; | 1444 | * csum or frame errors. |
| 1445 | } else if (qdev->rx_csum && | 1445 | */ |
| 1446 | ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) || | 1446 | if (qdev->rx_csum && |
| 1447 | ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && | 1447 | !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) && |
| 1448 | !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) { | 1448 | !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) { |
| 1449 | QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n"); | 1449 | /* TCP frame. */ |
| 1450 | skb->ip_summed = CHECKSUM_UNNECESSARY; | 1450 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) { |
| 1451 | QPRINTK(qdev, RX_STATUS, DEBUG, | ||
| 1452 | "TCP checksum done!\n"); | ||
| 1453 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 1454 | } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && | ||
| 1455 | (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { | ||
| 1456 | /* Unfragmented ipv4 UDP frame. */ | ||
| 1457 | struct iphdr *iph = (struct iphdr *) skb->data; | ||
| 1458 | if (!(iph->frag_off & | ||
| 1459 | cpu_to_be16(IP_MF|IP_OFFSET))) { | ||
| 1460 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 1461 | QPRINTK(qdev, RX_STATUS, DEBUG, | ||
| 1462 | "TCP checksum done!\n"); | ||
| 1463 | } | ||
| 1464 | } | ||
| 1451 | } | 1465 | } |
| 1452 | qdev->stats.rx_packets++; | 1466 | qdev->stats.rx_packets++; |
| 1453 | qdev->stats.rx_bytes += skb->len; | 1467 | qdev->stats.rx_bytes += skb->len; |
| @@ -1927,6 +1941,9 @@ static int qlge_send(struct sk_buff *skb, struct net_device *ndev) | |||
| 1927 | 1941 | ||
| 1928 | tx_ring = &qdev->tx_ring[tx_ring_idx]; | 1942 | tx_ring = &qdev->tx_ring[tx_ring_idx]; |
| 1929 | 1943 | ||
| 1944 | if (skb_padto(skb, ETH_ZLEN)) | ||
| 1945 | return NETDEV_TX_OK; | ||
| 1946 | |||
| 1930 | if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) { | 1947 | if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) { |
| 1931 | QPRINTK(qdev, TX_QUEUED, INFO, | 1948 | QPRINTK(qdev, TX_QUEUED, INFO, |
| 1932 | "%s: shutting down tx queue %d du to lack of resources.\n", | 1949 | "%s: shutting down tx queue %d du to lack of resources.\n", |
| @@ -2970,9 +2987,9 @@ static int ql_adapter_initialize(struct ql_adapter *qdev) | |||
| 2970 | mask = value << 16; | 2987 | mask = value << 16; |
| 2971 | ql_write32(qdev, SYS, mask | value); | 2988 | ql_write32(qdev, SYS, mask | value); |
| 2972 | 2989 | ||
| 2973 | /* Set the default queue. */ | 2990 | /* Set the default queue, and VLAN behavior. */ |
| 2974 | value = NIC_RCV_CFG_DFQ; | 2991 | value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV; |
| 2975 | mask = NIC_RCV_CFG_DFQ_MASK; | 2992 | mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16); |
| 2976 | ql_write32(qdev, NIC_RCV_CFG, (mask | value)); | 2993 | ql_write32(qdev, NIC_RCV_CFG, (mask | value)); |
| 2977 | 2994 | ||
| 2978 | /* Set the MPI interrupt to enabled. */ | 2995 | /* Set the MPI interrupt to enabled. */ |
| @@ -3149,6 +3166,11 @@ static int ql_adapter_down(struct ql_adapter *qdev) | |||
| 3149 | 3166 | ||
| 3150 | ql_tx_ring_clean(qdev); | 3167 | ql_tx_ring_clean(qdev); |
| 3151 | 3168 | ||
| 3169 | /* Call netif_napi_del() from common point. | ||
| 3170 | */ | ||
| 3171 | for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) | ||
| 3172 | netif_napi_del(&qdev->rx_ring[i].napi); | ||
| 3173 | |||
| 3152 | spin_lock(&qdev->hw_lock); | 3174 | spin_lock(&qdev->hw_lock); |
| 3153 | status = ql_adapter_reset(qdev); | 3175 | status = ql_adapter_reset(qdev); |
| 3154 | if (status) | 3176 | if (status) |
| @@ -3853,7 +3875,7 @@ static int qlge_suspend(struct pci_dev *pdev, pm_message_t state) | |||
| 3853 | { | 3875 | { |
| 3854 | struct net_device *ndev = pci_get_drvdata(pdev); | 3876 | struct net_device *ndev = pci_get_drvdata(pdev); |
| 3855 | struct ql_adapter *qdev = netdev_priv(ndev); | 3877 | struct ql_adapter *qdev = netdev_priv(ndev); |
| 3856 | int err, i; | 3878 | int err; |
| 3857 | 3879 | ||
| 3858 | netif_device_detach(ndev); | 3880 | netif_device_detach(ndev); |
| 3859 | 3881 | ||
| @@ -3863,9 +3885,6 @@ static int qlge_suspend(struct pci_dev *pdev, pm_message_t state) | |||
| 3863 | return err; | 3885 | return err; |
| 3864 | } | 3886 | } |
| 3865 | 3887 | ||
| 3866 | for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) | ||
| 3867 | netif_napi_del(&qdev->rx_ring[i].napi); | ||
| 3868 | |||
| 3869 | err = pci_save_state(pdev); | 3888 | err = pci_save_state(pdev); |
| 3870 | if (err) | 3889 | if (err) |
| 3871 | return err; | 3890 | return err; |
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index b3473401c83a..43fedb9ecedb 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c | |||
| @@ -81,9 +81,9 @@ static const int multicast_filter_limit = 32; | |||
| 81 | #define RTL8169_TX_TIMEOUT (6*HZ) | 81 | #define RTL8169_TX_TIMEOUT (6*HZ) |
| 82 | #define RTL8169_PHY_TIMEOUT (10*HZ) | 82 | #define RTL8169_PHY_TIMEOUT (10*HZ) |
| 83 | 83 | ||
| 84 | #define RTL_EEPROM_SIG 0x8129 | 84 | #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
| 85 | #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) | ||
| 85 | #define RTL_EEPROM_SIG_ADDR 0x0000 | 86 | #define RTL_EEPROM_SIG_ADDR 0x0000 |
| 86 | #define RTL_EEPROM_MAC_ADDR 0x0007 | ||
| 87 | 87 | ||
| 88 | /* write/read MMIO register */ | 88 | /* write/read MMIO register */ |
| 89 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | 89 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
| @@ -293,11 +293,6 @@ enum rtl_register_content { | |||
| 293 | /* Cfg9346Bits */ | 293 | /* Cfg9346Bits */ |
| 294 | Cfg9346_Lock = 0x00, | 294 | Cfg9346_Lock = 0x00, |
| 295 | Cfg9346_Unlock = 0xc0, | 295 | Cfg9346_Unlock = 0xc0, |
| 296 | Cfg9346_Program = 0x80, /* Programming mode */ | ||
| 297 | Cfg9346_EECS = 0x08, /* Chip select */ | ||
| 298 | Cfg9346_EESK = 0x04, /* Serial data clock */ | ||
| 299 | Cfg9346_EEDI = 0x02, /* Data input */ | ||
| 300 | Cfg9346_EEDO = 0x01, /* Data output */ | ||
| 301 | 296 | ||
| 302 | /* rx_mode_bits */ | 297 | /* rx_mode_bits */ |
| 303 | AcceptErr = 0x20, | 298 | AcceptErr = 0x20, |
| @@ -310,7 +305,6 @@ enum rtl_register_content { | |||
| 310 | /* RxConfigBits */ | 305 | /* RxConfigBits */ |
| 311 | RxCfgFIFOShift = 13, | 306 | RxCfgFIFOShift = 13, |
| 312 | RxCfgDMAShift = 8, | 307 | RxCfgDMAShift = 8, |
| 313 | RxCfg9356SEL = 6, /* EEPROM type: 0 = 9346, 1 = 9356 */ | ||
| 314 | 308 | ||
| 315 | /* TxConfigBits */ | 309 | /* TxConfigBits */ |
| 316 | TxInterFrameGapShift = 24, | 310 | TxInterFrameGapShift = 24, |
| @@ -1969,108 +1963,6 @@ static const struct net_device_ops rtl8169_netdev_ops = { | |||
| 1969 | 1963 | ||
| 1970 | }; | 1964 | }; |
| 1971 | 1965 | ||
| 1972 | /* Delay between EEPROM clock transitions. Force out buffered PCI writes. */ | ||
| 1973 | #define RTL_EEPROM_DELAY() RTL_R8(Cfg9346) | ||
| 1974 | #define RTL_EEPROM_READ_CMD 6 | ||
| 1975 | |||
| 1976 | /* read 16bit word stored in EEPROM. EEPROM is addressed by words. */ | ||
| 1977 | static u16 rtl_eeprom_read(void __iomem *ioaddr, int addr) | ||
| 1978 | { | ||
| 1979 | u16 result = 0; | ||
| 1980 | int cmd, cmd_len, i; | ||
| 1981 | |||
| 1982 | /* check for EEPROM address size (in bits) */ | ||
| 1983 | if (RTL_R32(RxConfig) & (1 << RxCfg9356SEL)) { | ||
| 1984 | /* EEPROM is 93C56 */ | ||
| 1985 | cmd_len = 3 + 8; /* 3 bits for command id and 8 for address */ | ||
| 1986 | cmd = (RTL_EEPROM_READ_CMD << 8) | (addr & 0xff); | ||
| 1987 | } else { | ||
| 1988 | /* EEPROM is 93C46 */ | ||
| 1989 | cmd_len = 3 + 6; /* 3 bits for command id and 6 for address */ | ||
| 1990 | cmd = (RTL_EEPROM_READ_CMD << 6) | (addr & 0x3f); | ||
| 1991 | } | ||
| 1992 | |||
| 1993 | /* enter programming mode */ | ||
| 1994 | RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS); | ||
| 1995 | RTL_EEPROM_DELAY(); | ||
| 1996 | |||
| 1997 | /* write command and requested address */ | ||
| 1998 | while (cmd_len--) { | ||
| 1999 | u8 x = Cfg9346_Program | Cfg9346_EECS; | ||
| 2000 | |||
| 2001 | x |= (cmd & (1 << cmd_len)) ? Cfg9346_EEDI : 0; | ||
| 2002 | |||
| 2003 | /* write a bit */ | ||
| 2004 | RTL_W8(Cfg9346, x); | ||
| 2005 | RTL_EEPROM_DELAY(); | ||
| 2006 | |||
| 2007 | /* raise clock */ | ||
| 2008 | RTL_W8(Cfg9346, x | Cfg9346_EESK); | ||
| 2009 | RTL_EEPROM_DELAY(); | ||
| 2010 | } | ||
| 2011 | |||
| 2012 | /* lower clock */ | ||
| 2013 | RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS); | ||
| 2014 | RTL_EEPROM_DELAY(); | ||
| 2015 | |||
| 2016 | /* read back 16bit value */ | ||
| 2017 | for (i = 16; i > 0; i--) { | ||
| 2018 | /* raise clock */ | ||
| 2019 | RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS | Cfg9346_EESK); | ||
| 2020 | RTL_EEPROM_DELAY(); | ||
| 2021 | |||
| 2022 | result <<= 1; | ||
| 2023 | result |= (RTL_R8(Cfg9346) & Cfg9346_EEDO) ? 1 : 0; | ||
| 2024 | |||
| 2025 | /* lower clock */ | ||
| 2026 | RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS); | ||
| 2027 | RTL_EEPROM_DELAY(); | ||
| 2028 | } | ||
| 2029 | |||
| 2030 | RTL_W8(Cfg9346, Cfg9346_Program); | ||
| 2031 | /* leave programming mode */ | ||
| 2032 | RTL_W8(Cfg9346, Cfg9346_Lock); | ||
| 2033 | |||
| 2034 | return result; | ||
| 2035 | } | ||
| 2036 | |||
| 2037 | static void rtl_init_mac_address(struct rtl8169_private *tp, | ||
| 2038 | void __iomem *ioaddr) | ||
| 2039 | { | ||
| 2040 | struct pci_dev *pdev = tp->pci_dev; | ||
| 2041 | u16 x; | ||
| 2042 | u8 mac[8]; | ||
| 2043 | |||
| 2044 | /* read EEPROM signature */ | ||
| 2045 | x = rtl_eeprom_read(ioaddr, RTL_EEPROM_SIG_ADDR); | ||
| 2046 | |||
| 2047 | if (x != RTL_EEPROM_SIG) { | ||
| 2048 | dev_info(&pdev->dev, "Missing EEPROM signature: %04x\n", x); | ||
| 2049 | return; | ||
| 2050 | } | ||
| 2051 | |||
| 2052 | /* read MAC address */ | ||
| 2053 | x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR); | ||
| 2054 | mac[0] = x & 0xff; | ||
| 2055 | mac[1] = x >> 8; | ||
| 2056 | x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR + 1); | ||
| 2057 | mac[2] = x & 0xff; | ||
| 2058 | mac[3] = x >> 8; | ||
| 2059 | x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR + 2); | ||
| 2060 | mac[4] = x & 0xff; | ||
| 2061 | mac[5] = x >> 8; | ||
| 2062 | |||
| 2063 | if (netif_msg_probe(tp)) { | ||
| 2064 | DECLARE_MAC_BUF(buf); | ||
| 2065 | |||
| 2066 | dev_info(&pdev->dev, "MAC address found in EEPROM: %s\n", | ||
| 2067 | print_mac(buf, mac)); | ||
| 2068 | } | ||
| 2069 | |||
| 2070 | if (is_valid_ether_addr(mac)) | ||
| 2071 | rtl_rar_set(tp, mac); | ||
| 2072 | } | ||
| 2073 | |||
| 2074 | static int __devinit | 1966 | static int __devinit |
| 2075 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | 1967 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 2076 | { | 1968 | { |
| @@ -2249,8 +2141,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 2249 | 2141 | ||
| 2250 | tp->mmio_addr = ioaddr; | 2142 | tp->mmio_addr = ioaddr; |
| 2251 | 2143 | ||
| 2252 | rtl_init_mac_address(tp, ioaddr); | ||
| 2253 | |||
| 2254 | /* Get MAC address */ | 2144 | /* Get MAC address */ |
| 2255 | for (i = 0; i < MAC_ADDR_LEN; i++) | 2145 | for (i = 0; i < MAC_ADDR_LEN; i++) |
| 2256 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | 2146 | dev->dev_addr[i] = RTL_R8(MAC0 + i); |
| @@ -3363,13 +3253,6 @@ static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 3363 | opts1 |= FirstFrag; | 3253 | opts1 |= FirstFrag; |
| 3364 | } else { | 3254 | } else { |
| 3365 | len = skb->len; | 3255 | len = skb->len; |
| 3366 | |||
| 3367 | if (unlikely(len < ETH_ZLEN)) { | ||
| 3368 | if (skb_padto(skb, ETH_ZLEN)) | ||
| 3369 | goto err_update_stats; | ||
| 3370 | len = ETH_ZLEN; | ||
| 3371 | } | ||
| 3372 | |||
| 3373 | opts1 |= FirstFrag | LastFrag; | 3256 | opts1 |= FirstFrag | LastFrag; |
| 3374 | tp->tx_skb[entry].skb = skb; | 3257 | tp->tx_skb[entry].skb = skb; |
| 3375 | } | 3258 | } |
| @@ -3407,7 +3290,6 @@ out: | |||
| 3407 | err_stop: | 3290 | err_stop: |
| 3408 | netif_stop_queue(dev); | 3291 | netif_stop_queue(dev); |
| 3409 | ret = NETDEV_TX_BUSY; | 3292 | ret = NETDEV_TX_BUSY; |
| 3410 | err_update_stats: | ||
| 3411 | dev->stats.tx_dropped++; | 3293 | dev->stats.tx_dropped++; |
| 3412 | goto out; | 3294 | goto out; |
| 3413 | } | 3295 | } |
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c index c5691fdb7079..fb53ef872df3 100644 --- a/drivers/net/via-velocity.c +++ b/drivers/net/via-velocity.c | |||
| @@ -1838,17 +1838,19 @@ static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_ | |||
| 1838 | { | 1838 | { |
| 1839 | struct sk_buff *skb = tdinfo->skb; | 1839 | struct sk_buff *skb = tdinfo->skb; |
| 1840 | int i; | 1840 | int i; |
| 1841 | int pktlen; | ||
| 1841 | 1842 | ||
| 1842 | /* | 1843 | /* |
| 1843 | * Don't unmap the pre-allocated tx_bufs | 1844 | * Don't unmap the pre-allocated tx_bufs |
| 1844 | */ | 1845 | */ |
| 1845 | if (tdinfo->skb_dma) { | 1846 | if (tdinfo->skb_dma) { |
| 1846 | 1847 | ||
| 1848 | pktlen = (skb->len > ETH_ZLEN ? : ETH_ZLEN); | ||
| 1847 | for (i = 0; i < tdinfo->nskb_dma; i++) { | 1849 | for (i = 0; i < tdinfo->nskb_dma; i++) { |
| 1848 | #ifdef VELOCITY_ZERO_COPY_SUPPORT | 1850 | #ifdef VELOCITY_ZERO_COPY_SUPPORT |
| 1849 | pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], le16_to_cpu(td->tdesc1.len), PCI_DMA_TODEVICE); | 1851 | pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], le16_to_cpu(td->tdesc1.len), PCI_DMA_TODEVICE); |
| 1850 | #else | 1852 | #else |
| 1851 | pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], skb->len, PCI_DMA_TODEVICE); | 1853 | pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], pktlen, PCI_DMA_TODEVICE); |
| 1852 | #endif | 1854 | #endif |
| 1853 | tdinfo->skb_dma[i] = 0; | 1855 | tdinfo->skb_dma[i] = 0; |
| 1854 | } | 1856 | } |
| @@ -2080,17 +2082,14 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 2080 | struct tx_desc *td_ptr; | 2082 | struct tx_desc *td_ptr; |
| 2081 | struct velocity_td_info *tdinfo; | 2083 | struct velocity_td_info *tdinfo; |
| 2082 | unsigned long flags; | 2084 | unsigned long flags; |
| 2083 | int pktlen = skb->len; | 2085 | int pktlen; |
| 2084 | __le16 len; | 2086 | __le16 len; |
| 2085 | int index; | 2087 | int index; |
| 2086 | 2088 | ||
| 2087 | 2089 | ||
| 2088 | 2090 | if (skb_padto(skb, ETH_ZLEN)) | |
| 2089 | if (skb->len < ETH_ZLEN) { | 2091 | goto out; |
| 2090 | if (skb_padto(skb, ETH_ZLEN)) | 2092 | pktlen = max_t(unsigned int, skb->len, ETH_ZLEN); |
| 2091 | goto out; | ||
| 2092 | pktlen = ETH_ZLEN; | ||
| 2093 | } | ||
| 2094 | 2093 | ||
| 2095 | len = cpu_to_le16(pktlen); | 2094 | len = cpu_to_le16(pktlen); |
| 2096 | 2095 | ||
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index b3866ad50227..3608081bc3e0 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig | |||
| @@ -15,8 +15,7 @@ menuconfig X86_PLATFORM_DEVICES | |||
| 15 | if X86_PLATFORM_DEVICES | 15 | if X86_PLATFORM_DEVICES |
| 16 | 16 | ||
| 17 | config ACER_WMI | 17 | config ACER_WMI |
| 18 | tristate "Acer WMI Laptop Extras (EXPERIMENTAL)" | 18 | tristate "Acer WMI Laptop Extras" |
| 19 | depends on EXPERIMENTAL | ||
| 20 | depends on ACPI | 19 | depends on ACPI |
| 21 | depends on LEDS_CLASS | 20 | depends on LEDS_CLASS |
| 22 | depends on NEW_LEDS | 21 | depends on NEW_LEDS |
| @@ -39,9 +38,9 @@ config ASUS_LAPTOP | |||
| 39 | tristate "Asus Laptop Extras (EXPERIMENTAL)" | 38 | tristate "Asus Laptop Extras (EXPERIMENTAL)" |
| 40 | depends on ACPI | 39 | depends on ACPI |
| 41 | depends on EXPERIMENTAL && !ACPI_ASUS | 40 | depends on EXPERIMENTAL && !ACPI_ASUS |
| 42 | depends on LEDS_CLASS | 41 | select LEDS_CLASS |
| 43 | depends on NEW_LEDS | 42 | select NEW_LEDS |
| 44 | depends on BACKLIGHT_CLASS_DEVICE | 43 | select BACKLIGHT_CLASS_DEVICE |
| 45 | depends on INPUT | 44 | depends on INPUT |
| 46 | ---help--- | 45 | ---help--- |
| 47 | This is the new Linux driver for Asus laptops. It may also support some | 46 | This is the new Linux driver for Asus laptops. It may also support some |
| @@ -185,11 +184,11 @@ config SONYPI_COMPAT | |||
| 185 | config THINKPAD_ACPI | 184 | config THINKPAD_ACPI |
| 186 | tristate "ThinkPad ACPI Laptop Extras" | 185 | tristate "ThinkPad ACPI Laptop Extras" |
| 187 | depends on ACPI | 186 | depends on ACPI |
| 187 | depends on INPUT | ||
| 188 | select BACKLIGHT_LCD_SUPPORT | 188 | select BACKLIGHT_LCD_SUPPORT |
| 189 | select BACKLIGHT_CLASS_DEVICE | 189 | select BACKLIGHT_CLASS_DEVICE |
| 190 | select HWMON | 190 | select HWMON |
| 191 | select NVRAM | 191 | select NVRAM |
| 192 | select INPUT | ||
| 193 | select NEW_LEDS | 192 | select NEW_LEDS |
| 194 | select LEDS_CLASS | 193 | select LEDS_CLASS |
| 195 | select NET | 194 | select NET |
| @@ -315,9 +314,8 @@ config EEEPC_LAPTOP | |||
| 315 | 314 | ||
| 316 | 315 | ||
| 317 | config ACPI_WMI | 316 | config ACPI_WMI |
| 318 | tristate "WMI (EXPERIMENTAL)" | 317 | tristate "WMI" |
| 319 | depends on ACPI | 318 | depends on ACPI |
| 320 | depends on EXPERIMENTAL | ||
| 321 | help | 319 | help |
| 322 | This driver adds support for the ACPI-WMI (Windows Management | 320 | This driver adds support for the ACPI-WMI (Windows Management |
| 323 | Instrumentation) mapper device (PNP0C14) found on some systems. | 321 | Instrumentation) mapper device (PNP0C14) found on some systems. |
diff --git a/drivers/platform/x86/acer-wmi.c b/drivers/platform/x86/acer-wmi.c index 6bcca616a704..a6a42e8c060b 100644 --- a/drivers/platform/x86/acer-wmi.c +++ b/drivers/platform/x86/acer-wmi.c | |||
| @@ -1026,7 +1026,7 @@ static void acer_rfkill_exit(void) | |||
| 1026 | kfree(wireless_rfkill->data); | 1026 | kfree(wireless_rfkill->data); |
| 1027 | rfkill_unregister(wireless_rfkill); | 1027 | rfkill_unregister(wireless_rfkill); |
| 1028 | if (has_cap(ACER_CAP_BLUETOOTH)) { | 1028 | if (has_cap(ACER_CAP_BLUETOOTH)) { |
| 1029 | kfree(wireless_rfkill->data); | 1029 | kfree(bluetooth_rfkill->data); |
| 1030 | rfkill_unregister(bluetooth_rfkill); | 1030 | rfkill_unregister(bluetooth_rfkill); |
| 1031 | } | 1031 | } |
| 1032 | return; | 1032 | return; |
diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index 56af6cf385b0..eeafc6c0160d 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c | |||
| @@ -815,6 +815,7 @@ static int asus_setkeycode(struct input_dev *dev, int scancode, int keycode) | |||
| 815 | static void asus_hotk_notify(acpi_handle handle, u32 event, void *data) | 815 | static void asus_hotk_notify(acpi_handle handle, u32 event, void *data) |
| 816 | { | 816 | { |
| 817 | static struct key_entry *key; | 817 | static struct key_entry *key; |
| 818 | u16 count; | ||
| 818 | 819 | ||
| 819 | /* TODO Find a better way to handle events count. */ | 820 | /* TODO Find a better way to handle events count. */ |
| 820 | if (!hotk) | 821 | if (!hotk) |
| @@ -832,9 +833,11 @@ static void asus_hotk_notify(acpi_handle handle, u32 event, void *data) | |||
| 832 | lcd_blank(FB_BLANK_POWERDOWN); | 833 | lcd_blank(FB_BLANK_POWERDOWN); |
| 833 | } | 834 | } |
| 834 | 835 | ||
| 836 | count = hotk->event_count[event % 128]++; | ||
| 837 | acpi_bus_generate_proc_event(hotk->device, event, count); | ||
| 835 | acpi_bus_generate_netlink_event(hotk->device->pnp.device_class, | 838 | acpi_bus_generate_netlink_event(hotk->device->pnp.device_class, |
| 836 | dev_name(&hotk->device->dev), event, | 839 | dev_name(&hotk->device->dev), event, |
| 837 | hotk->event_count[event % 128]++); | 840 | count); |
| 838 | 841 | ||
| 839 | if (hotk->inputdev) { | 842 | if (hotk->inputdev) { |
| 840 | key = asus_get_entry_by_scancode(event); | 843 | key = asus_get_entry_by_scancode(event); |
diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 786ed8661cb0..6f54fd1757cd 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c | |||
| @@ -557,13 +557,17 @@ static void eeepc_rfkill_notify(acpi_handle handle, u32 event, void *data) | |||
| 557 | static void eeepc_hotk_notify(acpi_handle handle, u32 event, void *data) | 557 | static void eeepc_hotk_notify(acpi_handle handle, u32 event, void *data) |
| 558 | { | 558 | { |
| 559 | static struct key_entry *key; | 559 | static struct key_entry *key; |
| 560 | u16 count; | ||
| 561 | |||
| 560 | if (!ehotk) | 562 | if (!ehotk) |
| 561 | return; | 563 | return; |
| 562 | if (event >= NOTIFY_BRN_MIN && event <= NOTIFY_BRN_MAX) | 564 | if (event >= NOTIFY_BRN_MIN && event <= NOTIFY_BRN_MAX) |
| 563 | notify_brn(); | 565 | notify_brn(); |
| 566 | count = ehotk->event_count[event % 128]++; | ||
| 567 | acpi_bus_generate_proc_event(ehotk->device, event, count); | ||
| 564 | acpi_bus_generate_netlink_event(ehotk->device->pnp.device_class, | 568 | acpi_bus_generate_netlink_event(ehotk->device->pnp.device_class, |
| 565 | dev_name(&ehotk->device->dev), event, | 569 | dev_name(&ehotk->device->dev), event, |
| 566 | ehotk->event_count[event % 128]++); | 570 | count); |
| 567 | if (ehotk->inputdev) { | 571 | if (ehotk->inputdev) { |
| 568 | key = eepc_get_entry_by_scancode(event); | 572 | key = eepc_get_entry_by_scancode(event); |
| 569 | if (key) { | 573 | if (key) { |
diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c index bcbc05107ba8..d2433204a40c 100644 --- a/drivers/platform/x86/thinkpad_acpi.c +++ b/drivers/platform/x86/thinkpad_acpi.c | |||
| @@ -7532,7 +7532,7 @@ MODULE_ALIAS(TPACPI_DRVR_SHORTNAME); | |||
| 7532 | * if it is not there yet. | 7532 | * if it is not there yet. |
| 7533 | */ | 7533 | */ |
| 7534 | #define IBM_BIOS_MODULE_ALIAS(__type) \ | 7534 | #define IBM_BIOS_MODULE_ALIAS(__type) \ |
| 7535 | MODULE_ALIAS("dmi:bvnIBM:bvr" __type "ET??WW") | 7535 | MODULE_ALIAS("dmi:bvnIBM:bvr" __type "ET??WW*") |
| 7536 | 7536 | ||
| 7537 | /* Non-ancient thinkpads */ | 7537 | /* Non-ancient thinkpads */ |
| 7538 | MODULE_ALIAS("dmi:bvnIBM:*:svnIBM:*:pvrThinkPad*:rvnIBM:*"); | 7538 | MODULE_ALIAS("dmi:bvnIBM:*:svnIBM:*:pvrThinkPad*:rvnIBM:*"); |
| @@ -7541,9 +7541,9 @@ MODULE_ALIAS("dmi:bvnLENOVO:*:svnLENOVO:*:pvrThinkPad*:rvnLENOVO:*"); | |||
| 7541 | /* Ancient thinkpad BIOSes have to be identified by | 7541 | /* Ancient thinkpad BIOSes have to be identified by |
| 7542 | * BIOS type or model number, and there are far less | 7542 | * BIOS type or model number, and there are far less |
| 7543 | * BIOS types than model numbers... */ | 7543 | * BIOS types than model numbers... */ |
| 7544 | IBM_BIOS_MODULE_ALIAS("I[B,D,H,I,M,N,O,T,W,V,Y,Z]"); | 7544 | IBM_BIOS_MODULE_ALIAS("I[BDHIMNOTWVYZ]"); |
| 7545 | IBM_BIOS_MODULE_ALIAS("1[0,3,6,8,A-G,I,K,M-P,S,T]"); | 7545 | IBM_BIOS_MODULE_ALIAS("1[0368A-GIKM-PST]"); |
| 7546 | IBM_BIOS_MODULE_ALIAS("K[U,X-Z]"); | 7546 | IBM_BIOS_MODULE_ALIAS("K[UX-Z]"); |
| 7547 | 7547 | ||
| 7548 | MODULE_AUTHOR("Borislav Deianov, Henrique de Moraes Holschuh"); | 7548 | MODULE_AUTHOR("Borislav Deianov, Henrique de Moraes Holschuh"); |
| 7549 | MODULE_DESCRIPTION(TPACPI_DESC); | 7549 | MODULE_DESCRIPTION(TPACPI_DESC); |
diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c index 8a8b377712c9..2f269e117b8f 100644 --- a/drivers/platform/x86/wmi.c +++ b/drivers/platform/x86/wmi.c | |||
| @@ -708,7 +708,7 @@ static int __init acpi_wmi_add(struct acpi_device *device) | |||
| 708 | 708 | ||
| 709 | static int __init acpi_wmi_init(void) | 709 | static int __init acpi_wmi_init(void) |
| 710 | { | 710 | { |
| 711 | acpi_status result; | 711 | int result; |
| 712 | 712 | ||
| 713 | INIT_LIST_HEAD(&wmi_blocks.list); | 713 | INIT_LIST_HEAD(&wmi_blocks.list); |
| 714 | 714 | ||
diff --git a/drivers/video/logo/logo_linux_clut224.ppm b/drivers/video/logo/logo_linux_clut224.ppm index 3c14e43b82fe..de93ff3fc1ad 100644 --- a/drivers/video/logo/logo_linux_clut224.ppm +++ b/drivers/video/logo/logo_linux_clut224.ppm | |||
| @@ -1,1604 +1,2828 @@ | |||
| 1 | P3 | 1 | P3 |
| 2 | # Standard 224-color Linux logo | 2 | 145 113 |
| 3 | 80 80 | ||
| 4 | 255 | 3 | 255 |
| 5 | 0 0 0 0 0 0 0 0 0 0 0 0 | 4 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 6 | 0 0 0 0 0 0 0 0 0 0 0 0 | 5 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 7 | 0 0 0 0 0 0 0 0 0 0 0 0 | 6 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 8 | 0 0 0 0 0 0 0 0 0 0 0 0 | 7 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 9 | 0 0 0 0 0 0 0 0 0 0 0 0 | 8 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 10 | 0 0 0 0 0 0 0 0 0 0 0 0 | 9 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 11 | 0 0 0 0 0 0 0 0 0 0 0 0 | 10 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 12 | 0 0 0 0 0 0 0 0 0 0 0 0 | 11 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 13 | 0 0 0 0 0 0 0 0 0 0 0 0 | 12 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 14 | 6 6 6 6 6 6 10 10 10 10 10 10 | 13 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 15 | 10 10 10 6 6 6 6 6 6 6 6 6 | 14 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 16 | 0 0 0 0 0 0 0 0 0 0 0 0 | 15 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 17 | 0 0 0 0 0 0 0 0 0 0 0 0 | 16 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 18 | 0 0 0 0 0 0 0 0 0 0 0 0 | 17 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 19 | 0 0 0 0 0 0 0 0 0 0 0 0 | 18 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 20 | 0 0 0 0 0 0 0 0 0 0 0 0 | 19 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 21 | 0 0 0 0 0 0 0 0 0 0 0 0 | 20 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 22 | 0 0 0 0 0 0 0 0 0 0 0 0 | 21 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 23 | 0 0 0 0 0 0 0 0 0 0 0 0 | 22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 24 | 0 0 0 0 0 0 0 0 0 0 0 0 | 23 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 25 | 0 0 0 0 0 0 0 0 0 0 0 0 | 24 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 26 | 0 0 0 0 0 0 0 0 0 0 0 0 | 25 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 27 | 0 0 0 0 0 0 0 0 0 0 0 0 | 26 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 28 | 0 0 0 0 0 0 0 0 0 0 0 0 | 27 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 29 | 0 0 0 0 0 0 0 0 0 0 0 0 | 28 | 0 0 0 |
| 30 | 0 0 0 0 0 0 0 0 0 0 0 0 | 29 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 31 | 0 0 0 0 0 0 0 0 0 0 0 0 | 30 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 32 | 0 0 0 0 0 0 0 0 0 0 0 0 | 31 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 33 | 0 0 0 6 6 6 10 10 10 14 14 14 | 32 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 34 | 22 22 22 26 26 26 30 30 30 34 34 34 | 33 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 35 | 30 30 30 30 30 30 26 26 26 18 18 18 | 34 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 36 | 14 14 14 10 10 10 6 6 6 0 0 0 | 35 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 37 | 0 0 0 0 0 0 0 0 0 0 0 0 | 36 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 38 | 0 0 0 0 0 0 0 0 0 0 0 0 | 37 | 0 0 0 0 0 0 0 0 0 0 0 0 3 4 4 6 7 7 |
| 39 | 0 0 0 0 0 0 0 0 0 0 0 0 | 38 | 8 10 10 8 10 10 6 8 8 6 7 7 3 4 4 2 2 2 |
| 40 | 0 0 0 0 0 0 0 0 0 0 0 0 | 39 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 41 | 0 0 0 0 0 0 0 0 0 0 0 0 | 40 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 42 | 0 0 0 0 0 0 0 0 0 0 0 0 | 41 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 43 | 0 0 0 0 0 0 0 0 0 0 0 0 | 42 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 44 | 0 0 0 0 0 0 0 0 0 0 0 0 | 43 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 45 | 0 0 0 0 0 0 0 0 0 0 0 0 | 44 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 46 | 0 0 0 0 0 1 0 0 1 0 0 0 | 45 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 47 | 0 0 0 0 0 0 0 0 0 0 0 0 | 46 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 48 | 0 0 0 0 0 0 0 0 0 0 0 0 | 47 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 49 | 0 0 0 0 0 0 0 0 0 0 0 0 | 48 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 50 | 0 0 0 0 0 0 0 0 0 0 0 0 | 49 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 51 | 0 0 0 0 0 0 0 0 0 0 0 0 | 50 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 52 | 0 0 0 0 0 0 0 0 0 0 0 0 | 51 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 53 | 6 6 6 14 14 14 26 26 26 42 42 42 | 52 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 54 | 54 54 54 66 66 66 78 78 78 78 78 78 | 53 | 0 0 0 |
| 55 | 78 78 78 74 74 74 66 66 66 54 54 54 | 54 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 56 | 42 42 42 26 26 26 18 18 18 10 10 10 | 55 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 57 | 6 6 6 0 0 0 0 0 0 0 0 0 | 56 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 58 | 0 0 0 0 0 0 0 0 0 0 0 0 | 57 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 59 | 0 0 0 0 0 0 0 0 0 0 0 0 | 58 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 60 | 0 0 0 0 0 0 0 0 0 0 0 0 | 59 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 61 | 0 0 0 0 0 0 0 0 0 0 0 0 | 60 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 62 | 0 0 0 0 0 0 0 0 0 0 0 0 | 61 | 0 0 0 0 0 0 0 0 0 0 0 0 4 5 5 17 18 17 |
| 63 | 0 0 0 0 0 0 0 0 0 0 0 0 | 62 | 27 29 28 35 37 36 40 43 41 43 45 43 40 43 41 37 39 37 |
| 64 | 0 0 0 0 0 0 0 0 0 0 0 0 | 63 | 32 34 33 27 30 29 23 25 24 17 21 21 15 18 18 12 15 15 |
| 65 | 0 0 0 0 0 0 0 0 0 0 0 0 | 64 | 11 13 13 8 10 10 6 7 7 3 4 4 1 1 1 0 0 0 |
| 66 | 0 0 1 0 0 0 0 0 0 0 0 0 | 65 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 67 | 0 0 0 0 0 0 0 0 0 0 0 0 | 66 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 68 | 0 0 0 0 0 0 0 0 0 0 0 0 | 67 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 69 | 0 0 0 0 0 0 0 0 0 0 0 0 | 68 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 70 | 0 0 0 0 0 0 0 0 0 0 0 0 | 69 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 71 | 0 0 0 0 0 0 0 0 0 0 0 0 | 70 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 72 | 0 0 0 0 0 0 0 0 0 10 10 10 | 71 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 73 | 22 22 22 42 42 42 66 66 66 86 86 86 | 72 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 74 | 66 66 66 38 38 38 38 38 38 22 22 22 | 73 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 75 | 26 26 26 34 34 34 54 54 54 66 66 66 | 74 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 76 | 86 86 86 70 70 70 46 46 46 26 26 26 | 75 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 77 | 14 14 14 6 6 6 0 0 0 0 0 0 | 76 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 78 | 0 0 0 0 0 0 0 0 0 0 0 0 | 77 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 79 | 0 0 0 0 0 0 0 0 0 0 0 0 | 78 | 0 0 0 |
| 80 | 0 0 0 0 0 0 0 0 0 0 0 0 | 79 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 81 | 0 0 0 0 0 0 0 0 0 0 0 0 | 80 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 82 | 0 0 0 0 0 0 0 0 0 0 0 0 | 81 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 83 | 0 0 0 0 0 0 0 0 0 0 0 0 | 82 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 84 | 0 0 0 0 0 0 0 0 0 0 0 0 | 83 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 85 | 0 0 0 0 0 0 0 0 0 0 0 0 | 84 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 86 | 0 0 1 0 0 1 0 0 1 0 0 0 | 85 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 87 | 0 0 0 0 0 0 0 0 0 0 0 0 | 86 | 0 0 0 13 13 13 32 34 33 49 51 48 60 60 56 58 59 55 |
| 88 | 0 0 0 0 0 0 0 0 0 0 0 0 | 87 | 55 57 54 55 56 53 49 51 48 43 45 43 39 40 39 33 37 35 |
| 89 | 0 0 0 0 0 0 0 0 0 0 0 0 | 88 | 28 31 30 23 27 26 20 23 23 17 20 20 14 17 17 13 16 16 |
| 90 | 0 0 0 0 0 0 0 0 0 0 0 0 | 89 | 11 14 14 10 13 13 10 12 12 9 11 11 8 10 10 6 7 7 |
| 91 | 0 0 0 0 0 0 0 0 0 0 0 0 | 90 | 2 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 92 | 0 0 0 0 0 0 10 10 10 26 26 26 | 91 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 93 | 50 50 50 82 82 82 58 58 58 6 6 6 | 92 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 94 | 2 2 6 2 2 6 2 2 6 2 2 6 | 93 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 95 | 2 2 6 2 2 6 2 2 6 2 2 6 | 94 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 96 | 6 6 6 54 54 54 86 86 86 66 66 66 | 95 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 97 | 38 38 38 18 18 18 6 6 6 0 0 0 | 96 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 98 | 0 0 0 0 0 0 0 0 0 0 0 0 | 97 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 99 | 0 0 0 0 0 0 0 0 0 0 0 0 | 98 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 100 | 0 0 0 0 0 0 0 0 0 0 0 0 | 99 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 101 | 0 0 0 0 0 0 0 0 0 0 0 0 | 100 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 102 | 0 0 0 0 0 0 0 0 0 0 0 0 | 101 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 103 | 0 0 0 0 0 0 0 0 0 0 0 0 | 102 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 104 | 0 0 0 0 0 0 0 0 0 0 0 0 | 103 | 0 0 0 |
| 105 | 0 0 0 0 0 0 0 0 0 0 0 0 | 104 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 106 | 0 0 0 0 0 0 0 0 0 0 0 0 | 105 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 107 | 0 0 0 0 0 0 0 0 0 0 0 0 | 106 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 108 | 0 0 0 0 0 0 0 0 0 0 0 0 | 107 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 109 | 0 0 0 0 0 0 0 0 0 0 0 0 | 108 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 110 | 0 0 0 0 0 0 0 0 0 0 0 0 | 109 | 0 0 0 0 0 0 0 0 0 0 0 0 6 7 7 12 15 15 |
| 111 | 0 0 0 0 0 0 0 0 0 0 0 0 | 110 | 12 15 15 8 9 9 2 3 3 0 0 0 1 1 1 25 27 26 |
| 112 | 0 0 0 6 6 6 22 22 22 50 50 50 | 111 | 55 56 53 68 70 65 65 66 61 65 66 61 63 64 60 63 64 60 |
| 113 | 78 78 78 34 34 34 2 2 6 2 2 6 | 112 | 58 59 55 51 52 50 47 48 46 41 42 42 35 37 36 30 32 31 |
| 114 | 2 2 6 2 2 6 2 2 6 2 2 6 | 113 | 26 28 27 20 24 24 18 22 22 16 19 19 14 17 17 13 16 16 |
| 115 | 2 2 6 2 2 6 2 2 6 2 2 6 | 114 | 12 15 15 11 14 14 10 13 13 10 12 12 9 11 11 8 10 10 |
| 116 | 2 2 6 2 2 6 6 6 6 70 70 70 | 115 | 8 9 9 6 8 8 3 3 3 0 0 0 0 0 0 0 0 0 |
| 117 | 78 78 78 46 46 46 22 22 22 6 6 6 | 116 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 118 | 0 0 0 0 0 0 0 0 0 0 0 0 | 117 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 119 | 0 0 0 0 0 0 0 0 0 0 0 0 | 118 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 120 | 0 0 0 0 0 0 0 0 0 0 0 0 | 119 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 121 | 0 0 0 0 0 0 0 0 0 0 0 0 | 120 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 122 | 0 0 0 0 0 0 0 0 0 0 0 0 | 121 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 123 | 0 0 0 0 0 0 0 0 0 0 0 0 | 122 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 124 | 0 0 0 0 0 0 0 0 0 0 0 0 | 123 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 125 | 0 0 0 0 0 0 0 0 0 0 0 0 | 124 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 126 | 0 0 1 0 0 1 0 0 1 0 0 0 | 125 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 127 | 0 0 0 0 0 0 0 0 0 0 0 0 | 126 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 128 | 0 0 0 0 0 0 0 0 0 0 0 0 | 127 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 129 | 0 0 0 0 0 0 0 0 0 0 0 0 | 128 | 0 0 0 |
| 130 | 0 0 0 0 0 0 0 0 0 0 0 0 | 129 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 131 | 0 0 0 0 0 0 0 0 0 0 0 0 | 130 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 132 | 6 6 6 18 18 18 42 42 42 82 82 82 | 131 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 133 | 26 26 26 2 2 6 2 2 6 2 2 6 | 132 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 134 | 2 2 6 2 2 6 2 2 6 2 2 6 | 133 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 135 | 2 2 6 2 2 6 2 2 6 14 14 14 | 134 | 0 0 0 0 0 0 0 0 0 6 7 7 20 24 24 23 27 26 |
| 136 | 46 46 46 34 34 34 6 6 6 2 2 6 | 135 | 23 27 26 18 22 22 11 13 13 23 24 24 61 63 57 72 73 67 |
| 137 | 42 42 42 78 78 78 42 42 42 18 18 18 | 136 | 72 73 67 68 70 65 68 70 65 68 70 65 63 64 60 58 59 55 |
| 138 | 6 6 6 0 0 0 0 0 0 0 0 0 | 137 | 55 56 53 47 48 46 41 42 42 35 37 36 30 32 31 26 28 27 |
| 139 | 0 0 0 0 0 0 0 0 0 0 0 0 | 138 | 20 24 24 18 22 22 16 20 20 15 19 19 14 17 17 13 16 16 |
| 140 | 0 0 0 0 0 0 0 0 0 0 0 0 | 139 | 12 15 15 12 15 15 11 14 14 10 13 13 10 12 12 9 11 11 |
| 141 | 0 0 0 0 0 0 0 0 0 0 0 0 | 140 | 8 10 10 8 9 9 7 9 9 6 7 7 1 2 2 0 0 0 |
| 142 | 0 0 0 0 0 0 0 0 0 0 0 0 | 141 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 143 | 0 0 0 0 0 0 0 0 0 0 0 0 | 142 | 0 0 0 0 0 0 1 1 1 4 5 5 5 6 5 4 5 5 |
| 144 | 0 0 0 0 0 0 0 0 0 0 0 0 | 143 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 145 | 0 0 0 0 0 0 0 0 0 0 0 0 | 144 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 146 | 0 0 1 0 0 0 0 0 1 0 0 0 | 145 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 147 | 0 0 0 0 0 0 0 0 0 0 0 0 | 146 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 148 | 0 0 0 0 0 0 0 0 0 0 0 0 | 147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 149 | 0 0 0 0 0 0 0 0 0 0 0 0 | 148 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 150 | 0 0 0 0 0 0 0 0 0 0 0 0 | 149 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 151 | 0 0 0 0 0 0 0 0 0 0 0 0 | 150 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 152 | 10 10 10 30 30 30 66 66 66 58 58 58 | 151 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 153 | 2 2 6 2 2 6 2 2 6 2 2 6 | 152 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 154 | 2 2 6 2 2 6 2 2 6 2 2 6 | 153 | 0 0 0 |
| 155 | 2 2 6 2 2 6 2 2 6 26 26 26 | 154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 156 | 86 86 86 101 101 101 46 46 46 10 10 10 | 155 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 157 | 2 2 6 58 58 58 70 70 70 34 34 34 | 156 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 158 | 10 10 10 0 0 0 0 0 0 0 0 0 | 157 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 159 | 0 0 0 0 0 0 0 0 0 0 0 0 | 158 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 160 | 0 0 0 0 0 0 0 0 0 0 0 0 | 159 | 0 0 0 0 0 0 0 0 0 15 19 19 40 41 39 53 55 47 |
| 161 | 0 0 0 0 0 0 0 0 0 0 0 0 | 160 | 33 36 34 27 30 29 51 52 50 72 73 67 72 73 67 72 73 67 |
| 162 | 0 0 0 0 0 0 0 0 0 0 0 0 | 161 | 72 73 67 68 70 65 68 70 65 63 64 60 58 59 55 51 52 50 |
| 163 | 0 0 0 0 0 0 0 0 0 0 0 0 | 162 | 47 48 46 40 43 41 33 37 35 30 32 31 26 28 27 20 24 24 |
| 164 | 0 0 0 0 0 0 0 0 0 0 0 0 | 163 | 18 22 22 17 21 21 16 19 19 14 18 18 14 17 17 13 17 17 |
| 165 | 0 0 0 0 0 0 0 0 0 0 0 0 | 164 | 13 16 16 12 15 15 12 15 15 11 14 14 10 13 13 10 12 12 |
| 166 | 0 0 1 0 0 1 0 0 1 0 0 0 | 165 | 9 11 11 8 10 10 8 9 9 7 9 9 6 8 8 3 4 4 |
| 167 | 0 0 0 0 0 0 0 0 0 0 0 0 | 166 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 168 | 0 0 0 0 0 0 0 0 0 0 0 0 | 167 | 2 2 2 6 8 8 10 12 12 10 12 12 10 12 12 10 12 12 |
| 169 | 0 0 0 0 0 0 0 0 0 0 0 0 | 168 | 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 170 | 0 0 0 0 0 0 0 0 0 0 0 0 | 169 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 171 | 0 0 0 0 0 0 0 0 0 0 0 0 | 170 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 172 | 14 14 14 42 42 42 86 86 86 10 10 10 | 171 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 173 | 2 2 6 2 2 6 2 2 6 2 2 6 | 172 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 174 | 2 2 6 2 2 6 2 2 6 2 2 6 | 173 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 175 | 2 2 6 2 2 6 2 2 6 30 30 30 | 174 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 176 | 94 94 94 94 94 94 58 58 58 26 26 26 | 175 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 177 | 2 2 6 6 6 6 78 78 78 54 54 54 | 176 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 178 | 22 22 22 6 6 6 0 0 0 0 0 0 | 177 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 179 | 0 0 0 0 0 0 0 0 0 0 0 0 | 178 | 0 0 0 |
| 180 | 0 0 0 0 0 0 0 0 0 0 0 0 | 179 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 181 | 0 0 0 0 0 0 0 0 0 0 0 0 | 180 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 182 | 0 0 0 0 0 0 0 0 0 0 0 0 | 181 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 183 | 0 0 0 0 0 0 0 0 0 0 0 0 | 182 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 184 | 0 0 0 0 0 0 0 0 0 0 0 0 | 183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 185 | 0 0 0 0 0 0 0 0 0 0 0 0 | 184 | 0 0 0 0 0 0 0 0 0 20 23 23 71 71 57 131 127 93 |
| 186 | 0 0 0 0 0 0 0 0 0 0 0 0 | 185 | 115 113 82 63 64 60 72 73 67 72 73 67 72 73 67 72 73 67 |
| 187 | 0 0 0 0 0 0 0 0 0 0 0 0 | 186 | 68 70 65 65 66 61 61 63 57 55 57 54 49 51 48 43 45 43 |
| 188 | 0 0 0 0 0 0 0 0 0 0 0 0 | 187 | 39 40 39 33 36 34 28 31 30 23 27 26 20 24 24 20 23 23 |
| 189 | 0 0 0 0 0 0 0 0 0 0 0 0 | 188 | 17 21 21 16 20 20 15 19 19 15 18 18 14 18 18 14 17 17 |
| 190 | 0 0 0 0 0 0 0 0 0 0 0 0 | 189 | 13 17 17 13 16 16 12 15 15 12 15 15 11 14 14 10 13 13 |
| 191 | 0 0 0 0 0 0 0 0 0 6 6 6 | 190 | 10 12 12 9 11 11 8 10 10 7 9 9 7 9 9 6 8 8 |
| 192 | 22 22 22 62 62 62 62 62 62 2 2 6 | 191 | 4 5 5 0 0 0 0 0 0 0 0 0 1 1 1 6 7 7 |
| 193 | 2 2 6 2 2 6 2 2 6 2 2 6 | 192 | 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 |
| 194 | 2 2 6 2 2 6 2 2 6 2 2 6 | 193 | 10 12 12 3 4 4 0 0 0 0 0 0 0 0 0 0 0 0 |
| 195 | 2 2 6 2 2 6 2 2 6 26 26 26 | 194 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 196 | 54 54 54 38 38 38 18 18 18 10 10 10 | 195 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 197 | 2 2 6 2 2 6 34 34 34 82 82 82 | 196 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 198 | 38 38 38 14 14 14 0 0 0 0 0 0 | 197 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 199 | 0 0 0 0 0 0 0 0 0 0 0 0 | 198 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 200 | 0 0 0 0 0 0 0 0 0 0 0 0 | 199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 201 | 0 0 0 0 0 0 0 0 0 0 0 0 | 200 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 202 | 0 0 0 0 0 0 0 0 0 0 0 0 | 201 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 203 | 0 0 0 0 0 0 0 0 0 0 0 0 | 202 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 204 | 0 0 0 0 0 0 0 0 0 0 0 0 | 203 | 0 0 0 |
| 205 | 0 0 0 0 0 0 0 0 0 0 0 0 | 204 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 206 | 0 0 0 0 0 1 0 0 1 0 0 0 | 205 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 207 | 0 0 0 0 0 0 0 0 0 0 0 0 | 206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 208 | 0 0 0 0 0 0 0 0 0 0 0 0 | 207 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 209 | 0 0 0 0 0 0 0 0 0 0 0 0 | 208 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 210 | 0 0 0 0 0 0 0 0 0 0 0 0 | 209 | 0 0 0 0 0 0 0 0 0 18 22 22 71 71 57 144 139 99 |
| 211 | 0 0 0 0 0 0 0 0 0 6 6 6 | 210 | 84 83 72 68 70 65 72 73 67 72 73 67 68 70 65 65 66 61 |
| 212 | 30 30 30 78 78 78 30 30 30 2 2 6 | 211 | 63 64 60 55 57 54 51 52 50 47 48 46 40 43 41 35 37 36 |
| 213 | 2 2 6 2 2 6 2 2 6 2 2 6 | 212 | 30 32 31 27 29 28 23 27 26 20 24 24 18 22 22 17 21 21 |
| 214 | 2 2 6 2 2 6 2 2 6 2 2 6 | 213 | 16 20 20 15 19 19 15 19 19 15 19 19 15 18 18 14 18 18 |
| 215 | 2 2 6 2 2 6 2 2 6 10 10 10 | 214 | 14 17 17 13 17 17 13 16 16 12 15 15 12 15 15 11 14 14 |
| 216 | 10 10 10 2 2 6 2 2 6 2 2 6 | 215 | 10 13 13 9 12 12 9 11 11 8 10 10 7 9 9 6 8 8 |
| 217 | 2 2 6 2 2 6 2 2 6 78 78 78 | 216 | 6 8 8 3 4 4 0 0 0 2 2 2 8 10 10 10 12 12 |
| 218 | 50 50 50 18 18 18 6 6 6 0 0 0 | 217 | 10 12 12 10 12 12 11 13 13 36 38 35 61 61 53 48 49 45 |
| 219 | 0 0 0 0 0 0 0 0 0 0 0 0 | 218 | 10 12 12 7 9 9 0 0 0 0 0 0 0 0 0 0 0 0 |
| 220 | 0 0 0 0 0 0 0 0 0 0 0 0 | 219 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 221 | 0 0 0 0 0 0 0 0 0 0 0 0 | 220 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 222 | 0 0 0 0 0 0 0 0 0 0 0 0 | 221 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 223 | 0 0 0 0 0 0 0 0 0 0 0 0 | 222 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 224 | 0 0 0 0 0 0 0 0 0 0 0 0 | 223 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 225 | 0 0 0 0 0 0 0 0 0 0 0 0 | 224 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 226 | 0 0 1 0 0 0 0 0 0 0 0 0 | 225 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 227 | 0 0 0 0 0 0 0 0 0 0 0 0 | 226 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 228 | 0 0 0 0 0 0 0 0 0 0 0 0 | 227 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 229 | 0 0 0 0 0 0 0 0 0 0 0 0 | 228 | 0 0 0 |
| 230 | 0 0 0 0 0 0 0 0 0 0 0 0 | 229 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 231 | 0 0 0 0 0 0 0 0 0 10 10 10 | 230 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 232 | 38 38 38 86 86 86 14 14 14 2 2 6 | 231 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 233 | 2 2 6 2 2 6 2 2 6 2 2 6 | 232 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 234 | 2 2 6 2 2 6 2 2 6 2 2 6 | 233 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 235 | 2 2 6 2 2 6 2 2 6 2 2 6 | 234 | 0 0 0 0 0 0 0 0 0 15 19 19 61 61 53 84 83 72 |
| 236 | 2 2 6 2 2 6 2 2 6 2 2 6 | 235 | 68 70 65 72 73 67 68 70 65 68 70 65 63 64 60 58 59 55 |
| 237 | 2 2 6 2 2 6 2 2 6 54 54 54 | 236 | 51 52 50 47 48 46 41 42 42 37 39 37 32 35 33 28 31 30 |
| 238 | 66 66 66 26 26 26 6 6 6 0 0 0 | 237 | 23 27 26 20 24 24 20 23 23 18 22 22 17 21 21 17 21 21 |
| 239 | 0 0 0 0 0 0 0 0 0 0 0 0 | 238 | 17 21 21 17 21 21 17 20 20 16 20 20 16 20 20 16 19 19 |
| 240 | 0 0 0 0 0 0 0 0 0 0 0 0 | 239 | 15 18 18 14 18 18 13 17 17 13 16 16 12 15 15 12 15 15 |
| 241 | 0 0 0 0 0 0 0 0 0 0 0 0 | 240 | 11 14 14 10 13 13 9 12 12 9 11 11 8 10 10 7 9 9 |
| 242 | 0 0 0 0 0 0 0 0 0 0 0 0 | 241 | 6 8 8 6 8 8 5 6 5 9 11 11 10 12 12 10 12 12 |
| 243 | 0 0 0 0 0 0 0 0 0 0 0 0 | 242 | 19 20 18 82 81 62 149 145 103 160 154 106 142 137 94 96 95 69 |
| 244 | 0 0 0 0 0 0 0 0 0 0 0 0 | 243 | 10 12 12 10 12 12 1 1 1 0 0 0 0 0 0 0 0 0 |
| 245 | 0 0 0 0 0 0 0 0 0 0 0 0 | 244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 246 | 0 0 0 0 0 1 0 0 1 0 0 0 | 245 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 247 | 0 0 0 0 0 0 0 0 0 0 0 0 | 246 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 248 | 0 0 0 0 0 0 0 0 0 0 0 0 | 247 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 249 | 0 0 0 0 0 0 0 0 0 0 0 0 | 248 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 250 | 0 0 0 0 0 0 0 0 0 0 0 0 | 249 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 251 | 0 0 0 0 0 0 0 0 0 14 14 14 | 250 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 252 | 42 42 42 82 82 82 2 2 6 2 2 6 | 251 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 253 | 2 2 6 6 6 6 10 10 10 2 2 6 | 252 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 254 | 2 2 6 2 2 6 2 2 6 2 2 6 | 253 | 0 0 0 |
| 255 | 2 2 6 2 2 6 2 2 6 6 6 6 | 254 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 256 | 14 14 14 10 10 10 2 2 6 2 2 6 | 255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 257 | 2 2 6 2 2 6 2 2 6 18 18 18 | 256 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 258 | 82 82 82 34 34 34 10 10 10 0 0 0 | 257 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 259 | 0 0 0 0 0 0 0 0 0 0 0 0 | 258 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 260 | 0 0 0 0 0 0 0 0 0 0 0 0 | 259 | 0 0 0 0 0 0 0 0 0 10 12 12 44 46 43 68 70 65 |
| 261 | 0 0 0 0 0 0 0 0 0 0 0 0 | 260 | 72 73 67 68 70 65 68 70 65 63 64 60 55 57 54 49 51 48 |
| 262 | 0 0 0 0 0 0 0 0 0 0 0 0 | 261 | 43 45 43 39 40 39 33 37 35 30 32 31 26 28 27 23 27 26 |
| 263 | 0 0 0 0 0 0 0 0 0 0 0 0 | 262 | 20 24 24 18 22 22 18 22 22 18 22 22 18 22 22 20 23 23 |
| 264 | 0 0 0 0 0 0 0 0 0 0 0 0 | 263 | 20 24 24 23 25 24 23 25 24 22 24 23 20 23 23 18 22 22 |
| 265 | 0 0 0 0 0 0 0 0 0 0 0 0 | 264 | 17 20 20 15 19 19 15 18 18 14 17 17 13 16 16 12 15 15 |
| 266 | 0 0 1 0 0 0 0 0 0 0 0 0 | 265 | 11 14 14 11 13 13 10 12 12 9 11 11 8 10 10 8 9 9 |
| 267 | 0 0 0 0 0 0 0 0 0 0 0 0 | 266 | 7 9 9 7 9 9 10 12 12 10 12 12 10 12 12 71 71 57 |
| 268 | 0 0 0 0 0 0 0 0 0 0 0 0 | 267 | 164 159 111 186 182 128 186 182 128 171 165 117 151 147 98 96 95 69 |
| 269 | 0 0 0 0 0 0 0 0 0 0 0 0 | 268 | 10 12 12 10 12 12 3 3 3 0 0 0 0 0 0 0 0 0 |
| 270 | 0 0 0 0 0 0 0 0 0 0 0 0 | 269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 271 | 0 0 0 0 0 0 0 0 0 14 14 14 | 270 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 272 | 46 46 46 86 86 86 2 2 6 2 2 6 | 271 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 273 | 6 6 6 6 6 6 22 22 22 34 34 34 | 272 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 274 | 6 6 6 2 2 6 2 2 6 2 2 6 | 273 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 275 | 2 2 6 2 2 6 18 18 18 34 34 34 | 274 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 276 | 10 10 10 50 50 50 22 22 22 2 2 6 | 275 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 277 | 2 2 6 2 2 6 2 2 6 10 10 10 | 276 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 278 | 86 86 86 42 42 42 14 14 14 0 0 0 | 277 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 279 | 0 0 0 0 0 0 0 0 0 0 0 0 | 278 | 0 0 0 |
| 280 | 0 0 0 0 0 0 0 0 0 0 0 0 | 279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 281 | 0 0 0 0 0 0 0 0 0 0 0 0 | 280 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 282 | 0 0 0 0 0 0 0 0 0 0 0 0 | 281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 283 | 0 0 0 0 0 0 0 0 0 0 0 0 | 282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 284 | 0 0 0 0 0 0 0 0 0 0 0 0 | 283 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 285 | 0 0 0 0 0 0 0 0 0 0 0 0 | 284 | 0 0 0 0 0 0 0 0 0 8 10 10 63 64 60 68 70 65 |
| 286 | 0 0 1 0 0 1 0 0 1 0 0 0 | 285 | 72 73 67 68 70 65 63 64 60 55 57 54 47 48 46 40 43 41 |
| 287 | 0 0 0 0 0 0 0 0 0 0 0 0 | 286 | 33 37 35 30 32 31 27 29 28 23 27 26 20 24 24 20 23 23 |
| 288 | 0 0 0 0 0 0 0 0 0 0 0 0 | 287 | 18 22 22 18 22 22 20 23 22 21 25 23 23 27 26 27 29 28 |
| 289 | 0 0 0 0 0 0 0 0 0 0 0 0 | 288 | 28 31 30 31 33 31 31 33 31 31 33 31 28 31 30 26 28 27 |
| 290 | 0 0 0 0 0 0 0 0 0 0 0 0 | 289 | 23 25 24 20 23 22 16 20 20 15 18 18 14 17 17 13 16 16 |
| 291 | 0 0 0 0 0 0 0 0 0 14 14 14 | 290 | 12 15 15 11 14 14 10 13 13 10 12 12 9 11 11 8 10 10 |
| 292 | 46 46 46 86 86 86 2 2 6 2 2 6 | 291 | 10 12 12 10 13 13 10 12 12 12 14 14 96 95 69 165 161 109 |
| 293 | 38 38 38 116 116 116 94 94 94 22 22 22 | 292 | 186 182 128 192 187 134 192 187 134 176 171 126 160 154 106 103 101 77 |
| 294 | 22 22 22 2 2 6 2 2 6 2 2 6 | 293 | 10 12 12 10 12 12 5 6 5 0 0 0 0 0 0 0 0 0 |
| 295 | 14 14 14 86 86 86 138 138 138 162 162 162 | 294 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 296 | 154 154 154 38 38 38 26 26 26 6 6 6 | 295 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 297 | 2 2 6 2 2 6 2 2 6 2 2 6 | 296 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 298 | 86 86 86 46 46 46 14 14 14 0 0 0 | 297 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 299 | 0 0 0 0 0 0 0 0 0 0 0 0 | 298 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 300 | 0 0 0 0 0 0 0 0 0 0 0 0 | 299 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 301 | 0 0 0 0 0 0 0 0 0 0 0 0 | 300 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 302 | 0 0 0 0 0 0 0 0 0 0 0 0 | 301 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 303 | 0 0 0 0 0 0 0 0 0 0 0 0 | 302 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 304 | 0 0 0 0 0 0 0 0 0 0 0 0 | 303 | 0 0 0 |
| 305 | 0 0 0 0 0 0 0 0 0 0 0 0 | 304 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 306 | 0 0 0 0 0 0 0 0 0 0 0 0 | 305 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 307 | 0 0 0 0 0 0 0 0 0 0 0 0 | 306 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 308 | 0 0 0 0 0 0 0 0 0 0 0 0 | 307 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 309 | 0 0 0 0 0 0 0 0 0 0 0 0 | 308 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 310 | 0 0 0 0 0 0 0 0 0 0 0 0 | 309 | 0 0 0 0 0 0 0 0 0 35 37 36 68 70 65 72 73 67 |
| 311 | 0 0 0 0 0 0 0 0 0 14 14 14 | 310 | 68 70 65 65 66 61 58 59 55 49 51 48 40 43 41 33 37 35 |
| 312 | 46 46 46 86 86 86 2 2 6 14 14 14 | 311 | 28 31 30 23 27 26 20 24 24 20 23 23 18 22 22 18 22 22 |
| 313 | 134 134 134 198 198 198 195 195 195 116 116 116 | 312 | 18 22 22 20 23 23 23 27 26 27 30 29 32 35 33 37 39 37 |
| 314 | 10 10 10 2 2 6 2 2 6 6 6 6 | 313 | 40 43 41 44 46 43 46 47 43 44 46 43 40 43 41 36 38 35 |
| 315 | 101 98 89 187 187 187 210 210 210 218 218 218 | 314 | 31 33 31 27 29 28 22 24 23 17 21 21 15 18 18 14 17 17 |
| 316 | 214 214 214 134 134 134 14 14 14 6 6 6 | 315 | 13 16 16 12 15 15 11 14 14 11 14 14 11 13 13 13 16 16 |
| 317 | 2 2 6 2 2 6 2 2 6 2 2 6 | 316 | 13 16 16 11 14 14 10 12 12 79 78 62 142 137 94 164 159 111 |
| 318 | 86 86 86 50 50 50 18 18 18 6 6 6 | 317 | 178 174 128 192 187 134 192 187 134 176 171 126 160 154 106 96 95 69 |
| 319 | 0 0 0 0 0 0 0 0 0 0 0 0 | 318 | 10 12 12 10 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 320 | 0 0 0 0 0 0 0 0 0 0 0 0 | 319 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 321 | 0 0 0 0 0 0 0 0 0 0 0 0 | 320 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 322 | 0 0 0 0 0 0 0 0 0 0 0 0 | 321 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 323 | 0 0 0 0 0 0 0 0 0 0 0 0 | 322 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 324 | 0 0 0 0 0 0 0 0 0 0 0 0 | 323 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 325 | 0 0 0 0 0 0 0 0 1 0 0 0 | 324 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 326 | 0 0 1 0 0 1 0 0 1 0 0 0 | 325 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 327 | 0 0 0 0 0 0 0 0 0 0 0 0 | 326 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 328 | 0 0 0 0 0 0 0 0 0 0 0 0 | 327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 329 | 0 0 0 0 0 0 0 0 0 0 0 0 | 328 | 0 0 0 |
| 330 | 0 0 0 0 0 0 0 0 0 0 0 0 | 329 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 331 | 0 0 0 0 0 0 0 0 0 14 14 14 | 330 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 332 | 46 46 46 86 86 86 2 2 6 54 54 54 | 331 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 333 | 218 218 218 195 195 195 226 226 226 246 246 246 | 332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 334 | 58 58 58 2 2 6 2 2 6 30 30 30 | 333 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 335 | 210 210 210 253 253 253 174 174 174 123 123 123 | 334 | 0 0 0 0 0 0 0 0 0 55 57 54 68 70 65 72 73 67 |
| 336 | 221 221 221 234 234 234 74 74 74 2 2 6 | 335 | 68 70 65 63 64 60 55 56 53 43 45 43 35 37 36 28 31 30 |
| 337 | 2 2 6 2 2 6 2 2 6 2 2 6 | 336 | 23 27 26 20 24 24 18 22 22 17 21 21 17 21 21 17 21 21 |
| 338 | 70 70 70 58 58 58 22 22 22 6 6 6 | 337 | 20 24 24 25 27 26 31 33 31 38 39 37 46 47 43 53 55 47 |
| 339 | 0 0 0 0 0 0 0 0 0 0 0 0 | 338 | 61 61 53 66 65 55 66 65 55 66 65 55 61 61 53 53 55 47 |
| 340 | 0 0 0 0 0 0 0 0 0 0 0 0 | 339 | 46 47 43 37 39 37 30 33 30 24 26 24 17 21 21 15 18 18 |
| 341 | 0 0 0 0 0 0 0 0 0 0 0 0 | 340 | 13 17 17 12 15 15 12 15 15 13 16 16 14 18 18 14 18 18 |
| 342 | 0 0 0 0 0 0 0 0 0 0 0 0 | 341 | 14 17 17 12 15 15 30 31 28 118 116 76 134 131 96 160 154 106 |
| 343 | 0 0 0 0 0 0 0 0 0 0 0 0 | 342 | 174 170 121 178 174 128 178 174 128 171 165 117 151 147 98 96 95 69 |
| 344 | 0 0 0 0 0 0 0 0 0 0 0 0 | 343 | 10 12 12 10 12 12 6 8 8 0 0 0 0 0 0 0 0 0 |
| 345 | 0 0 0 0 0 0 0 0 0 0 0 0 | 344 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 346 | 0 0 0 0 0 0 0 0 0 0 0 0 | 345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 347 | 0 0 0 0 0 0 0 0 0 0 0 0 | 346 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 348 | 0 0 0 0 0 0 0 0 0 0 0 0 | 347 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 349 | 0 0 0 0 0 0 0 0 0 0 0 0 | 348 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 350 | 0 0 0 0 0 0 0 0 0 0 0 0 | 349 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 351 | 0 0 0 0 0 0 0 0 0 14 14 14 | 350 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 352 | 46 46 46 82 82 82 2 2 6 106 106 106 | 351 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 353 | 170 170 170 26 26 26 86 86 86 226 226 226 | 352 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 354 | 123 123 123 10 10 10 14 14 14 46 46 46 | 353 | 0 0 0 |
| 355 | 231 231 231 190 190 190 6 6 6 70 70 70 | 354 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 356 | 90 90 90 238 238 238 158 158 158 2 2 6 | 355 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 357 | 2 2 6 2 2 6 2 2 6 2 2 6 | 356 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 358 | 70 70 70 58 58 58 22 22 22 6 6 6 | 357 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 359 | 0 0 0 0 0 0 0 0 0 0 0 0 | 358 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 360 | 0 0 0 0 0 0 0 0 0 0 0 0 | 359 | 0 0 0 0 0 0 0 0 0 63 64 60 68 70 65 68 70 65 |
| 361 | 0 0 0 0 0 0 0 0 0 0 0 0 | 360 | 65 66 61 58 59 55 49 51 48 39 40 39 30 32 31 23 27 26 |
| 362 | 0 0 0 0 0 0 0 0 0 0 0 0 | 361 | 20 24 24 18 22 22 17 21 21 16 20 20 17 21 21 20 23 23 |
| 363 | 0 0 0 0 0 0 0 0 0 0 0 0 | 362 | 25 27 26 32 35 33 43 44 41 53 55 47 66 65 55 75 75 61 |
| 364 | 0 0 0 0 0 0 0 0 0 0 0 0 | 363 | 82 81 62 84 83 72 87 86 72 87 86 72 82 81 62 75 75 61 |
| 365 | 0 0 0 0 0 0 0 0 1 0 0 0 | 364 | 66 65 55 53 55 47 40 41 39 31 33 31 23 25 24 17 20 20 |
| 366 | 0 0 1 0 0 1 0 0 1 0 0 0 | 365 | 14 18 18 13 16 16 12 15 15 12 15 15 13 17 17 14 18 18 |
| 367 | 0 0 0 0 0 0 0 0 0 0 0 0 | 366 | 14 18 18 13 16 16 46 47 43 96 95 69 125 122 87 142 137 94 |
| 368 | 0 0 0 0 0 0 0 0 0 0 0 0 | 367 | 160 154 106 165 161 109 164 159 111 155 149 109 142 137 94 75 75 61 |
| 369 | 0 0 0 0 0 0 0 0 0 0 0 0 | 368 | 10 12 12 10 12 12 6 8 8 0 0 0 0 0 0 0 0 0 |
| 370 | 0 0 0 0 0 0 0 0 0 0 0 0 | 369 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 371 | 0 0 0 0 0 0 0 0 0 14 14 14 | 370 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 372 | 42 42 42 86 86 86 6 6 6 116 116 116 | 371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 373 | 106 106 106 6 6 6 70 70 70 149 149 149 | 372 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 374 | 128 128 128 18 18 18 38 38 38 54 54 54 | 373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 375 | 221 221 221 106 106 106 2 2 6 14 14 14 | 374 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 376 | 46 46 46 190 190 190 198 198 198 2 2 6 | 375 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 377 | 2 2 6 2 2 6 2 2 6 2 2 6 | 376 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 378 | 74 74 74 62 62 62 22 22 22 6 6 6 | 377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 379 | 0 0 0 0 0 0 0 0 0 0 0 0 | 378 | 0 0 0 |
| 380 | 0 0 0 0 0 0 0 0 0 0 0 0 | 379 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 381 | 0 0 0 0 0 0 0 0 0 0 0 0 | 380 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 382 | 0 0 0 0 0 0 0 0 0 0 0 0 | 381 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 383 | 0 0 0 0 0 0 0 0 0 0 0 0 | 382 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 384 | 0 0 0 0 0 0 0 0 0 0 0 0 | 383 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 385 | 0 0 0 0 0 0 0 0 1 0 0 0 | 384 | 0 0 0 0 0 0 0 0 0 60 60 56 68 70 65 68 70 65 |
| 386 | 0 0 1 0 0 0 0 0 1 0 0 0 | 385 | 63 64 60 55 57 54 46 47 45 35 37 36 27 30 29 23 25 24 |
| 387 | 0 0 0 0 0 0 0 0 0 0 0 0 | 386 | 18 22 22 17 21 21 16 20 20 17 21 21 18 22 22 23 27 26 |
| 388 | 0 0 0 0 0 0 0 0 0 0 0 0 | 387 | 31 33 31 43 44 41 55 56 53 71 71 57 84 83 72 92 91 72 |
| 389 | 0 0 0 0 0 0 0 0 0 0 0 0 | 388 | 103 101 77 92 91 72 82 81 62 82 81 62 87 86 72 92 91 72 |
| 390 | 0 0 0 0 0 0 0 0 0 0 0 0 | 389 | 84 83 72 71 71 57 55 56 53 43 44 41 30 33 30 22 24 23 |
| 391 | 0 0 0 0 0 0 0 0 0 14 14 14 | 390 | 16 19 19 14 17 17 12 15 15 12 15 15 13 16 16 14 18 18 |
| 392 | 42 42 42 94 94 94 14 14 14 101 101 101 | 391 | 14 18 18 14 17 17 43 44 41 82 81 62 118 116 76 125 122 87 |
| 393 | 128 128 128 2 2 6 18 18 18 116 116 116 | 392 | 142 137 94 144 139 99 144 139 99 134 131 96 118 116 76 53 55 47 |
| 394 | 118 98 46 121 92 8 121 92 8 98 78 10 | 393 | 10 12 12 10 12 12 6 8 8 0 0 0 0 0 0 0 0 0 |
| 395 | 162 162 162 106 106 106 2 2 6 2 2 6 | 394 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 396 | 2 2 6 195 195 195 195 195 195 6 6 6 | 395 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 397 | 2 2 6 2 2 6 2 2 6 2 2 6 | 396 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 398 | 74 74 74 62 62 62 22 22 22 6 6 6 | 397 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 399 | 0 0 0 0 0 0 0 0 0 0 0 0 | 398 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 400 | 0 0 0 0 0 0 0 0 0 0 0 0 | 399 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 401 | 0 0 0 0 0 0 0 0 0 0 0 0 | 400 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 402 | 0 0 0 0 0 0 0 0 0 0 0 0 | 401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 403 | 0 0 0 0 0 0 0 0 0 0 0 0 | 402 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 404 | 0 0 0 0 0 0 0 0 0 0 0 0 | 403 | 0 0 0 |
| 405 | 0 0 0 0 0 0 0 0 1 0 0 1 | 404 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 406 | 0 0 1 0 0 0 0 0 1 0 0 0 | 405 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 407 | 0 0 0 0 0 0 0 0 0 0 0 0 | 406 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 408 | 0 0 0 0 0 0 0 0 0 0 0 0 | 407 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 409 | 0 0 0 0 0 0 0 0 0 0 0 0 | 408 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 410 | 0 0 0 0 0 0 0 0 0 0 0 0 | 409 | 0 0 0 0 0 0 0 0 0 47 48 46 63 64 60 63 64 60 |
| 411 | 0 0 0 0 0 0 0 0 0 10 10 10 | 410 | 55 57 54 49 51 48 40 43 41 32 34 33 26 28 27 20 24 24 |
| 412 | 38 38 38 90 90 90 14 14 14 58 58 58 | 411 | 18 22 22 16 20 20 16 20 20 17 21 21 20 24 24 28 31 30 |
| 413 | 210 210 210 26 26 26 54 38 6 154 114 10 | 412 | 40 41 39 53 55 47 75 75 61 90 89 73 87 86 72 48 49 45 |
| 414 | 226 170 11 236 186 11 225 175 15 184 144 12 | 413 | 14 14 13 2 2 2 1 2 2 1 1 1 1 1 1 2 2 2 |
| 415 | 215 174 15 175 146 61 37 26 9 2 2 6 | 414 | 19 20 18 43 44 41 66 65 55 53 55 47 38 39 37 26 28 27 |
| 416 | 70 70 70 246 246 246 138 138 138 2 2 6 | 415 | 18 22 22 14 18 18 13 16 16 12 15 15 12 15 15 13 17 17 |
| 417 | 2 2 6 2 2 6 2 2 6 2 2 6 | 416 | 14 18 18 14 18 18 30 31 28 66 65 55 96 95 69 103 101 77 |
| 418 | 70 70 70 66 66 66 26 26 26 6 6 6 | 417 | 118 116 76 118 116 76 118 116 76 118 116 76 103 101 77 36 38 35 |
| 419 | 0 0 0 0 0 0 0 0 0 0 0 0 | 418 | 10 12 12 10 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 420 | 0 0 0 0 0 0 0 0 0 0 0 0 | 419 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 421 | 0 0 0 0 0 0 0 0 0 0 0 0 | 420 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 422 | 0 0 0 0 0 0 0 0 0 0 0 0 | 421 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 423 | 0 0 0 0 0 0 0 0 0 0 0 0 | 422 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 424 | 0 0 0 0 0 0 0 0 0 0 0 0 | 423 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
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| 429 | 0 0 0 0 0 0 0 0 0 0 0 0 | 428 | 0 0 0 |
| 430 | 0 0 0 0 0 0 0 0 0 0 0 0 | 429 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 431 | 0 0 0 0 0 0 0 0 0 10 10 10 | 430 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 432 | 38 38 38 86 86 86 14 14 14 10 10 10 | 431 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 433 | 195 195 195 188 164 115 192 133 9 225 175 15 | 432 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 434 | 239 182 13 234 190 10 232 195 16 232 200 30 | 433 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 435 | 245 207 45 241 208 19 232 195 16 184 144 12 | 434 | 0 0 0 0 0 0 0 0 0 28 31 30 55 57 54 51 52 50 |
| 436 | 218 194 134 211 206 186 42 42 42 2 2 6 | 435 | 49 51 48 41 42 42 35 37 36 28 31 30 23 27 26 20 23 23 |
| 437 | 2 2 6 2 2 6 2 2 6 2 2 6 | 436 | 17 21 21 16 20 20 16 20 20 18 22 22 23 27 26 33 36 34 |
| 438 | 50 50 50 74 74 74 30 30 30 6 6 6 | 437 | 48 49 45 71 71 57 82 81 62 43 44 41 8 9 9 6 7 7 |
| 439 | 0 0 0 0 0 0 0 0 0 0 0 0 | 438 | 6 7 7 6 7 7 6 7 7 5 6 5 4 5 5 3 4 4 |
| 440 | 0 0 0 0 0 0 0 0 0 0 0 0 | 439 | 2 3 3 1 2 2 4 5 4 36 38 35 48 49 45 32 35 33 |
| 441 | 0 0 0 0 0 0 0 0 0 0 0 0 | 440 | 21 25 23 16 19 19 13 17 17 12 15 15 12 15 15 13 16 16 |
| 442 | 0 0 0 0 0 0 0 0 0 0 0 0 | 441 | 14 18 18 14 18 18 16 18 16 36 38 35 61 61 53 82 81 62 |
| 443 | 0 0 0 0 0 0 0 0 0 0 0 0 | 442 | 96 95 69 96 95 69 96 95 69 96 95 69 79 78 62 19 20 18 |
| 444 | 0 0 0 0 0 0 0 0 0 0 0 0 | 443 | 10 12 12 10 12 12 4 5 5 0 0 0 0 0 0 0 0 0 |
| 445 | 0 0 0 0 0 0 0 0 0 0 0 0 | 444 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 446 | 0 0 0 0 0 0 0 0 0 0 0 0 | 445 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
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| 448 | 0 0 0 0 0 0 0 0 0 0 0 0 | 447 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 449 | 0 0 0 0 0 0 0 0 0 0 0 0 | 448 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 450 | 0 0 0 0 0 0 0 0 0 0 0 0 | 449 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 451 | 0 0 0 0 0 0 0 0 0 10 10 10 | 450 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 452 | 34 34 34 86 86 86 14 14 14 2 2 6 | 451 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 453 | 121 87 25 192 133 9 219 162 10 239 182 13 | 452 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 454 | 236 186 11 232 195 16 241 208 19 244 214 54 | 453 | 0 0 0 |
| 455 | 246 218 60 246 218 38 246 215 20 241 208 19 | 454 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 456 | 241 208 19 226 184 13 121 87 25 2 2 6 | 455 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 457 | 2 2 6 2 2 6 2 2 6 2 2 6 | 456 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 458 | 50 50 50 82 82 82 34 34 34 10 10 10 | 457 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 459 | 0 0 0 0 0 0 0 0 0 0 0 0 | 458 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 460 | 0 0 0 0 0 0 0 0 0 0 0 0 | 459 | 0 0 0 0 0 0 0 0 0 13 13 13 46 47 45 43 45 43 |
| 461 | 0 0 0 0 0 0 0 0 0 0 0 0 | 460 | 40 43 41 35 37 36 30 32 31 23 27 26 20 24 24 18 22 22 |
| 462 | 0 0 0 0 0 0 0 0 0 0 0 0 | 461 | 17 21 21 16 20 20 17 21 21 20 23 23 27 30 29 40 41 39 |
| 463 | 0 0 0 0 0 0 0 0 0 0 0 0 | 462 | 61 61 53 53 55 47 16 17 16 9 11 11 10 12 12 10 12 12 |
| 464 | 0 0 0 0 0 0 0 0 0 0 0 0 | 463 | 10 12 12 10 12 12 10 12 12 9 11 11 8 10 10 8 9 9 |
| 465 | 0 0 0 0 0 0 0 0 0 0 0 0 | 464 | 6 8 8 5 6 5 4 5 5 2 3 3 19 20 18 38 39 37 |
| 466 | 0 0 0 0 0 0 0 0 0 0 0 0 | 465 | 26 28 27 17 21 21 14 17 17 13 16 16 12 15 15 12 15 15 |
| 467 | 0 0 0 0 0 0 0 0 0 0 0 0 | 466 | 13 17 17 14 18 18 12 15 15 13 12 7 30 31 28 46 47 43 |
| 468 | 0 0 0 0 0 0 0 0 0 0 0 0 | 467 | 53 55 47 66 65 55 66 65 55 53 55 47 36 38 35 10 12 12 |
| 469 | 0 0 0 0 0 0 0 0 0 0 0 0 | 468 | 10 12 12 10 12 12 2 3 3 0 0 0 0 0 0 0 0 0 |
| 470 | 0 0 0 0 0 0 0 0 0 0 0 0 | 469 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 471 | 0 0 0 0 0 0 0 0 0 10 10 10 | 470 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 472 | 34 34 34 82 82 82 30 30 30 61 42 6 | 471 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 473 | 180 123 7 206 145 10 230 174 11 239 182 13 | 472 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 474 | 234 190 10 238 202 15 241 208 19 246 218 74 | 473 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 475 | 246 218 38 246 215 20 246 215 20 246 215 20 | 474 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 476 | 226 184 13 215 174 15 184 144 12 6 6 6 | 475 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 477 | 2 2 6 2 2 6 2 2 6 2 2 6 | 476 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 478 | 26 26 26 94 94 94 42 42 42 14 14 14 | 477 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 479 | 0 0 0 0 0 0 0 0 0 0 0 0 | 478 | 0 0 0 |
| 480 | 0 0 0 0 0 0 0 0 0 0 0 0 | 479 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 481 | 0 0 0 0 0 0 0 0 0 0 0 0 | 480 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 482 | 0 0 0 0 0 0 0 0 0 0 0 0 | 481 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 483 | 0 0 0 0 0 0 0 0 0 0 0 0 | 482 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 484 | 0 0 0 0 0 0 0 0 0 0 0 0 | 483 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 485 | 0 0 0 0 0 0 0 0 0 0 0 0 | 484 | 0 0 0 0 0 0 0 0 0 1 1 1 33 37 35 35 37 36 |
| 486 | 0 0 0 0 0 0 0 0 0 0 0 0 | 485 | 32 35 33 28 31 30 23 27 26 20 24 24 18 22 22 17 21 21 |
| 487 | 0 0 0 0 0 0 0 0 0 0 0 0 | 486 | 16 20 20 16 20 20 17 21 21 21 25 23 31 33 31 44 46 43 |
| 488 | 0 0 0 0 0 0 0 0 0 0 0 0 | 487 | 31 33 31 11 13 13 12 14 14 12 15 15 13 16 16 14 17 17 |
| 489 | 0 0 0 0 0 0 0 0 0 0 0 0 | 488 | 14 17 17 14 17 17 14 17 17 13 16 16 12 15 15 12 14 14 |
| 490 | 0 0 0 0 0 0 0 0 0 0 0 0 | 489 | 11 13 13 9 11 11 8 10 10 6 8 8 4 5 5 17 18 17 |
| 491 | 0 0 0 0 0 0 0 0 0 10 10 10 | 490 | 30 33 30 20 23 22 15 18 18 13 16 16 12 15 15 12 14 14 |
| 492 | 30 30 30 78 78 78 50 50 50 104 69 6 | 491 | 13 16 16 14 17 17 14 18 18 11 12 11 7 7 5 16 17 12 |
| 493 | 192 133 9 216 158 10 236 178 12 236 186 11 | 492 | 21 22 20 30 31 28 25 27 25 21 22 20 14 14 13 10 12 12 |
| 494 | 232 195 16 241 208 19 244 214 54 245 215 43 | 493 | 10 12 12 9 11 11 0 0 0 0 0 0 0 0 0 0 0 0 |
| 495 | 246 215 20 246 215 20 241 208 19 198 155 10 | 494 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 496 | 200 144 11 216 158 10 156 118 10 2 2 6 | 495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 497 | 2 2 6 2 2 6 2 2 6 2 2 6 | 496 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 498 | 6 6 6 90 90 90 54 54 54 18 18 18 | 497 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 499 | 6 6 6 0 0 0 0 0 0 0 0 0 | 498 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 500 | 0 0 0 0 0 0 0 0 0 0 0 0 | 499 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 501 | 0 0 0 0 0 0 0 0 0 0 0 0 | 500 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 502 | 0 0 0 0 0 0 0 0 0 0 0 0 | 501 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 503 | 0 0 0 0 0 0 0 0 0 0 0 0 | 502 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 504 | 0 0 0 0 0 0 0 0 0 0 0 0 | 503 | 0 0 0 |
| 505 | 0 0 0 0 0 0 0 0 0 0 0 0 | 504 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 506 | 0 0 0 0 0 0 0 0 0 0 0 0 | 505 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 507 | 0 0 0 0 0 0 0 0 0 0 0 0 | 506 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 508 | 0 0 0 0 0 0 0 0 0 0 0 0 | 507 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 509 | 0 0 0 0 0 0 0 0 0 0 0 0 | 508 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 510 | 0 0 0 0 0 0 0 0 0 0 0 0 | 509 | 0 0 0 0 0 0 0 0 0 0 0 0 18 22 22 27 30 29 |
| 511 | 0 0 0 0 0 0 0 0 0 10 10 10 | 510 | 27 29 28 40 41 39 53 55 47 53 55 47 53 55 47 46 47 43 |
| 512 | 30 30 30 78 78 78 46 46 46 22 22 22 | 511 | 25 27 25 16 20 20 17 21 21 23 25 24 31 33 31 20 20 20 |
| 513 | 137 92 6 210 162 10 239 182 13 238 190 10 | 512 | 12 15 15 14 17 17 15 19 19 16 20 20 17 21 21 18 22 22 |
| 514 | 238 202 15 241 208 19 246 215 20 246 215 20 | 513 | 18 22 22 18 22 22 18 22 22 17 21 21 17 21 21 16 19 19 |
| 515 | 241 208 19 203 166 17 185 133 11 210 150 10 | 514 | 15 18 18 13 16 16 12 15 15 10 12 12 8 10 10 6 8 8 |
| 516 | 216 158 10 210 150 10 102 78 10 2 2 6 | 515 | 21 22 21 22 24 23 15 19 19 13 17 17 13 16 16 12 15 15 |
| 517 | 6 6 6 54 54 54 14 14 14 2 2 6 | 516 | 12 15 15 13 17 17 14 18 18 14 18 18 13 15 14 10 9 6 |
| 518 | 2 2 6 62 62 62 74 74 74 30 30 30 | 517 | 7 7 5 7 7 5 7 7 5 9 11 11 10 12 12 10 12 12 |
| 519 | 10 10 10 0 0 0 0 0 0 0 0 0 | 518 | 10 12 12 6 7 7 0 0 0 0 0 0 0 0 0 0 0 0 |
| 520 | 0 0 0 0 0 0 0 0 0 0 0 0 | 519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 521 | 0 0 0 0 0 0 0 0 0 0 0 0 | 520 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 522 | 0 0 0 0 0 0 0 0 0 0 0 0 | 521 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 523 | 0 0 0 0 0 0 0 0 0 0 0 0 | 522 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 524 | 0 0 0 0 0 0 0 0 0 0 0 0 | 523 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 525 | 0 0 0 0 0 0 0 0 0 0 0 0 | 524 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 526 | 0 0 0 0 0 0 0 0 0 0 0 0 | 525 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 527 | 0 0 0 0 0 0 0 0 0 0 0 0 | 526 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 528 | 0 0 0 0 0 0 0 0 0 0 0 0 | 527 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 529 | 0 0 0 0 0 0 0 0 0 0 0 0 | 528 | 0 0 0 |
| 530 | 0 0 0 0 0 0 0 0 0 0 0 0 | 529 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 531 | 0 0 0 0 0 0 0 0 0 10 10 10 | 530 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 532 | 34 34 34 78 78 78 50 50 50 6 6 6 | 531 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 533 | 94 70 30 139 102 15 190 146 13 226 184 13 | 532 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 534 | 232 200 30 232 195 16 215 174 15 190 146 13 | 533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 535 | 168 122 10 192 133 9 210 150 10 213 154 11 | 534 | 0 0 0 0 0 0 0 0 0 0 0 0 16 17 12 82 81 62 |
| 536 | 202 150 34 182 157 106 101 98 89 2 2 6 | 535 | 118 116 76 118 116 76 161 156 96 161 156 96 161 156 96 118 116 76 |
| 537 | 2 2 6 78 78 78 116 116 116 58 58 58 | 536 | 118 116 76 96 95 69 53 55 47 22 24 23 14 17 17 13 16 16 |
| 538 | 2 2 6 22 22 22 90 90 90 46 46 46 | 537 | 15 19 19 17 21 21 18 22 22 20 24 24 20 24 24 23 27 26 |
| 539 | 18 18 18 6 6 6 0 0 0 0 0 0 | 538 | 23 27 26 23 27 26 23 27 26 23 27 26 23 27 26 20 24 24 |
| 540 | 0 0 0 0 0 0 0 0 0 0 0 0 | 539 | 20 23 23 17 21 21 16 19 19 14 17 17 12 15 15 10 12 12 |
| 541 | 0 0 0 0 0 0 0 0 0 0 0 0 | 540 | 9 11 11 20 23 22 16 19 19 14 17 17 13 16 16 12 15 15 |
| 542 | 0 0 0 0 0 0 0 0 0 0 0 0 | 541 | 11 14 14 13 16 16 14 17 17 14 18 18 14 17 17 12 15 15 |
| 543 | 0 0 0 0 0 0 0 0 0 0 0 0 | 542 | 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 |
| 544 | 0 0 0 0 0 0 0 0 0 0 0 0 | 543 | 9 11 11 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 |
| 545 | 0 0 0 0 0 0 0 0 0 0 0 0 | 544 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 546 | 0 0 0 0 0 0 0 0 0 0 0 0 | 545 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 547 | 0 0 0 0 0 0 0 0 0 0 0 0 | 546 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 548 | 0 0 0 0 0 0 0 0 0 0 0 0 | 547 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 549 | 0 0 0 0 0 0 0 0 0 0 0 0 | 548 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 550 | 0 0 0 0 0 0 0 0 0 0 0 0 | 549 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 551 | 0 0 0 0 0 0 0 0 0 10 10 10 | 550 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 552 | 38 38 38 86 86 86 50 50 50 6 6 6 | 551 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 553 | 128 128 128 174 154 114 156 107 11 168 122 10 | 552 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 554 | 198 155 10 184 144 12 197 138 11 200 144 11 | 553 | 0 0 0 |
| 555 | 206 145 10 206 145 10 197 138 11 188 164 115 | 554 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 556 | 195 195 195 198 198 198 174 174 174 14 14 14 | 555 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 557 | 2 2 6 22 22 22 116 116 116 116 116 116 | 556 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 558 | 22 22 22 2 2 6 74 74 74 70 70 70 | 557 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 559 | 30 30 30 10 10 10 0 0 0 0 0 0 | 558 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 560 | 0 0 0 0 0 0 0 0 0 0 0 0 | 559 | 0 0 0 0 0 0 0 0 0 0 0 0 53 55 47 161 156 96 |
| 561 | 0 0 0 0 0 0 0 0 0 0 0 0 | 560 | 161 156 96 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 562 | 0 0 0 0 0 0 0 0 0 0 0 0 | 561 | 230 229 82 161 156 96 118 116 76 96 95 69 21 22 20 16 19 19 |
| 563 | 0 0 0 0 0 0 0 0 0 0 0 0 | 562 | 18 22 22 20 24 24 23 27 26 23 27 26 26 28 27 27 30 29 |
| 564 | 0 0 0 0 0 0 0 0 0 0 0 0 | 563 | 27 30 29 18 22 22 12 14 14 8 10 10 9 11 11 17 21 21 |
| 565 | 0 0 0 0 0 0 0 0 0 0 0 0 | 564 | 23 27 26 23 27 26 20 24 24 18 22 22 16 20 20 14 17 17 |
| 566 | 0 0 0 0 0 0 0 0 0 0 0 0 | 565 | 12 14 14 14 17 17 16 20 20 14 17 17 13 17 17 13 16 16 |
| 567 | 0 0 0 0 0 0 0 0 0 0 0 0 | 566 | 12 15 15 12 15 15 13 17 17 14 18 18 14 17 17 13 16 16 |
| 568 | 0 0 0 0 0 0 0 0 0 0 0 0 | 567 | 11 13 13 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 |
| 569 | 0 0 0 0 0 0 0 0 0 0 0 0 | 568 | 4 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 570 | 0 0 0 0 0 0 0 0 0 0 0 0 | 569 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 571 | 0 0 0 0 0 0 6 6 6 18 18 18 | 570 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 572 | 50 50 50 101 101 101 26 26 26 10 10 10 | 571 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 573 | 138 138 138 190 190 190 174 154 114 156 107 11 | 572 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 574 | 197 138 11 200 144 11 197 138 11 192 133 9 | 573 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 575 | 180 123 7 190 142 34 190 178 144 187 187 187 | 574 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 576 | 202 202 202 221 221 221 214 214 214 66 66 66 | 575 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 577 | 2 2 6 2 2 6 50 50 50 62 62 62 | 576 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 578 | 6 6 6 2 2 6 10 10 10 90 90 90 | 577 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 579 | 50 50 50 18 18 18 6 6 6 0 0 0 | 578 | 0 0 0 |
| 580 | 0 0 0 0 0 0 0 0 0 0 0 0 | 579 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 581 | 0 0 0 0 0 0 0 0 0 0 0 0 | 580 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 582 | 0 0 0 0 0 0 0 0 0 0 0 0 | 581 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 583 | 0 0 0 0 0 0 0 0 0 0 0 0 | 582 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 584 | 0 0 0 0 0 0 0 0 0 0 0 0 | 583 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 585 | 0 0 0 0 0 0 0 0 0 0 0 0 | 584 | 0 0 0 0 0 0 0 0 0 13 12 7 118 116 76 230 229 82 |
| 586 | 0 0 0 0 0 0 0 0 0 0 0 0 | 585 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 587 | 0 0 0 0 0 0 0 0 0 0 0 0 | 586 | 230 229 82 230 229 82 230 229 82 161 156 96 118 116 76 30 31 28 |
| 588 | 0 0 0 0 0 0 0 0 0 0 0 0 | 587 | 20 24 24 23 27 26 27 30 29 28 31 30 30 32 31 23 27 26 |
| 589 | 0 0 0 0 0 0 0 0 0 0 0 0 | 588 | 16 19 19 17 21 21 12 15 15 9 11 11 10 12 12 9 11 11 |
| 590 | 0 0 0 0 0 0 0 0 0 0 0 0 | 589 | 20 24 24 28 31 30 26 28 27 23 27 26 20 24 24 17 21 21 |
| 591 | 0 0 0 0 0 0 10 10 10 34 34 34 | 590 | 15 19 19 13 16 16 16 19 19 14 18 18 14 17 17 13 16 16 |
| 592 | 74 74 74 74 74 74 2 2 6 6 6 6 | 591 | 12 15 15 11 14 14 13 16 16 14 17 17 14 18 18 14 17 17 |
| 593 | 144 144 144 198 198 198 190 190 190 178 166 146 | 592 | 12 15 15 10 12 12 10 12 12 10 12 12 10 12 12 8 9 9 |
| 594 | 154 121 60 156 107 11 156 107 11 168 124 44 | 593 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 595 | 174 154 114 187 187 187 190 190 190 210 210 210 | 594 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 596 | 246 246 246 253 253 253 253 253 253 182 182 182 | 595 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 597 | 6 6 6 2 2 6 2 2 6 2 2 6 | 596 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 598 | 2 2 6 2 2 6 2 2 6 62 62 62 | 597 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 599 | 74 74 74 34 34 34 14 14 14 0 0 0 | 598 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 600 | 0 0 0 0 0 0 0 0 0 0 0 0 | 599 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 601 | 0 0 0 0 0 0 0 0 0 0 0 0 | 600 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 602 | 0 0 0 0 0 0 0 0 0 0 0 0 | 601 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 603 | 0 0 0 0 0 0 0 0 0 0 0 0 | 602 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 604 | 0 0 0 0 0 0 0 0 0 0 0 0 | 603 | 0 0 0 |
| 605 | 0 0 0 0 0 0 0 0 0 0 0 0 | 604 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 606 | 0 0 0 0 0 0 0 0 0 0 0 0 | 605 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 607 | 0 0 0 0 0 0 0 0 0 0 0 0 | 606 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 608 | 0 0 0 0 0 0 0 0 0 0 0 0 | 607 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 609 | 0 0 0 0 0 0 0 0 0 0 0 0 | 608 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 610 | 0 0 0 0 0 0 0 0 0 0 0 0 | 609 | 0 0 0 0 0 0 0 0 0 82 81 62 161 156 96 230 229 82 |
| 611 | 0 0 0 10 10 10 22 22 22 54 54 54 | 610 | 230 229 82 233 233 100 230 229 82 230 229 82 230 229 82 230 229 82 |
| 612 | 94 94 94 18 18 18 2 2 6 46 46 46 | 611 | 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 118 116 76 |
| 613 | 234 234 234 221 221 221 190 190 190 190 190 190 | 612 | 27 29 28 27 30 29 30 32 31 30 32 31 23 27 26 20 24 24 |
| 614 | 190 190 190 187 187 187 187 187 187 190 190 190 | 613 | 26 28 27 17 21 21 6 7 7 72 73 67 145 141 105 15 15 15 |
| 615 | 190 190 190 195 195 195 214 214 214 242 242 242 | 614 | 14 17 17 33 37 35 30 32 31 28 31 30 26 28 27 23 27 26 |
| 616 | 253 253 253 253 253 253 253 253 253 253 253 253 | 615 | 20 23 23 16 20 20 15 19 19 14 18 18 14 17 17 13 16 16 |
| 617 | 82 82 82 2 2 6 2 2 6 2 2 6 | 616 | 12 15 15 11 14 14 12 15 15 13 17 17 14 18 18 14 17 17 |
| 618 | 2 2 6 2 2 6 2 2 6 14 14 14 | 617 | 13 16 16 11 13 13 10 12 12 10 12 12 9 11 11 1 1 1 |
| 619 | 86 86 86 54 54 54 22 22 22 6 6 6 | 618 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 620 | 0 0 0 0 0 0 0 0 0 0 0 0 | 619 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 621 | 0 0 0 0 0 0 0 0 0 0 0 0 | 620 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 622 | 0 0 0 0 0 0 0 0 0 0 0 0 | 621 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 623 | 0 0 0 0 0 0 0 0 0 0 0 0 | 622 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 624 | 0 0 0 0 0 0 0 0 0 0 0 0 | 623 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 625 | 0 0 0 0 0 0 0 0 0 0 0 0 | 624 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 626 | 0 0 0 0 0 0 0 0 0 0 0 0 | 625 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 627 | 0 0 0 0 0 0 0 0 0 0 0 0 | 626 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 628 | 0 0 0 0 0 0 0 0 0 0 0 0 | 627 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 629 | 0 0 0 0 0 0 0 0 0 0 0 0 | 628 | 0 0 0 |
| 630 | 0 0 0 0 0 0 0 0 0 0 0 0 | 629 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 631 | 6 6 6 18 18 18 46 46 46 90 90 90 | 630 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 632 | 46 46 46 18 18 18 6 6 6 182 182 182 | 631 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 633 | 253 253 253 246 246 246 206 206 206 190 190 190 | 632 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 634 | 190 190 190 190 190 190 190 190 190 190 190 190 | 633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 635 | 206 206 206 231 231 231 250 250 250 253 253 253 | 634 | 0 0 0 0 0 0 16 17 12 161 156 96 230 229 82 230 229 82 |
| 636 | 253 253 253 253 253 253 253 253 253 253 253 253 | 635 | 243 242 120 235 234 117 230 229 82 230 229 82 230 229 82 230 229 82 |
| 637 | 202 202 202 14 14 14 2 2 6 2 2 6 | 636 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 |
| 638 | 2 2 6 2 2 6 2 2 6 2 2 6 | 637 | 82 81 62 28 31 30 28 31 30 27 30 29 28 31 30 30 32 31 |
| 639 | 42 42 42 86 86 86 42 42 42 18 18 18 | 638 | 33 37 35 13 16 16 3 3 3 105 104 92 210 208 158 12 14 14 |
| 640 | 6 6 6 0 0 0 0 0 0 0 0 0 | 639 | 17 21 21 33 37 35 33 37 35 32 35 33 30 32 31 27 30 29 |
| 641 | 0 0 0 0 0 0 0 0 0 0 0 0 | 640 | 23 27 26 20 23 23 17 20 20 15 18 18 14 18 18 13 17 17 |
| 642 | 0 0 0 0 0 0 0 0 0 0 0 0 | 641 | 13 16 16 12 15 15 11 14 14 13 16 16 14 17 17 14 18 18 |
| 643 | 0 0 0 0 0 0 0 0 0 0 0 0 | 642 | 13 17 17 12 15 15 10 12 12 10 12 12 3 4 4 0 0 0 |
| 644 | 0 0 0 0 0 0 0 0 0 0 0 0 | 643 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 645 | 0 0 0 0 0 0 0 0 0 0 0 0 | 644 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 646 | 0 0 0 0 0 0 0 0 0 0 0 0 | 645 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 647 | 0 0 0 0 0 0 0 0 0 0 0 0 | 646 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 648 | 0 0 0 0 0 0 0 0 0 0 0 0 | 647 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 649 | 0 0 0 0 0 0 0 0 0 0 0 0 | 648 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 650 | 0 0 0 0 0 0 0 0 0 6 6 6 | 649 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 651 | 14 14 14 38 38 38 74 74 74 66 66 66 | 650 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 652 | 2 2 6 6 6 6 90 90 90 250 250 250 | 651 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 653 | 253 253 253 253 253 253 238 238 238 198 198 198 | 652 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 654 | 190 190 190 190 190 190 195 195 195 221 221 221 | 653 | 0 0 0 |
| 655 | 246 246 246 253 253 253 253 253 253 253 253 253 | 654 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 656 | 253 253 253 253 253 253 253 253 253 253 253 253 | 655 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 657 | 253 253 253 82 82 82 2 2 6 2 2 6 | 656 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 658 | 2 2 6 2 2 6 2 2 6 2 2 6 | 657 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 659 | 2 2 6 78 78 78 70 70 70 34 34 34 | 658 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 660 | 14 14 14 6 6 6 0 0 0 0 0 0 | 659 | 0 0 0 0 0 0 96 95 69 230 229 82 230 229 82 244 244 132 |
| 661 | 0 0 0 0 0 0 0 0 0 0 0 0 | 660 | 241 241 143 243 242 120 230 229 82 230 229 82 230 229 82 230 229 82 |
| 662 | 0 0 0 0 0 0 0 0 0 0 0 0 | 661 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 663 | 0 0 0 0 0 0 0 0 0 0 0 0 | 662 | 161 156 96 46 47 43 32 35 33 33 37 35 33 37 35 33 37 35 |
| 664 | 0 0 0 0 0 0 0 0 0 0 0 0 | 663 | 40 43 41 23 27 26 1 1 1 2 2 2 24 26 24 14 17 17 |
| 665 | 0 0 0 0 0 0 0 0 0 0 0 0 | 664 | 23 27 26 33 37 35 33 37 35 33 37 35 33 37 35 30 32 31 |
| 666 | 0 0 0 0 0 0 0 0 0 0 0 0 | 665 | 27 30 29 23 27 26 20 23 23 15 18 18 14 18 18 14 17 17 |
| 667 | 0 0 0 0 0 0 0 0 0 0 0 0 | 666 | 13 16 16 12 15 15 11 14 14 12 15 15 13 17 17 14 17 17 |
| 668 | 0 0 0 0 0 0 0 0 0 0 0 0 | 667 | 14 17 17 13 16 16 11 13 13 6 8 8 0 0 0 0 0 0 |
| 669 | 0 0 0 0 0 0 0 0 0 0 0 0 | 668 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 670 | 0 0 0 0 0 0 0 0 0 14 14 14 | 669 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 671 | 34 34 34 66 66 66 78 78 78 6 6 6 | 670 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 672 | 2 2 6 18 18 18 218 218 218 253 253 253 | 671 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 673 | 253 253 253 253 253 253 253 253 253 246 246 246 | 672 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 674 | 226 226 226 231 231 231 246 246 246 253 253 253 | 673 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 675 | 253 253 253 253 253 253 253 253 253 253 253 253 | 674 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 676 | 253 253 253 253 253 253 253 253 253 253 253 253 | 675 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 677 | 253 253 253 178 178 178 2 2 6 2 2 6 | 676 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 678 | 2 2 6 2 2 6 2 2 6 2 2 6 | 677 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 679 | 2 2 6 18 18 18 90 90 90 62 62 62 | 678 | 0 0 0 |
| 680 | 30 30 30 10 10 10 0 0 0 0 0 0 | 679 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 681 | 0 0 0 0 0 0 0 0 0 0 0 0 | 680 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 682 | 0 0 0 0 0 0 0 0 0 0 0 0 | 681 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 683 | 0 0 0 0 0 0 0 0 0 0 0 0 | 682 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 684 | 0 0 0 0 0 0 0 0 0 0 0 0 | 683 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 685 | 0 0 0 0 0 0 0 0 0 0 0 0 | 684 | 0 0 0 16 17 12 161 156 96 230 229 82 235 234 117 239 239 170 |
| 686 | 0 0 0 0 0 0 0 0 0 0 0 0 | 685 | 239 239 170 236 236 101 230 229 82 230 229 82 230 229 82 230 229 82 |
| 687 | 0 0 0 0 0 0 0 0 0 0 0 0 | 686 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 688 | 0 0 0 0 0 0 0 0 0 0 0 0 | 687 | 230 229 82 118 116 76 33 37 35 33 37 35 37 39 37 37 39 37 |
| 689 | 0 0 0 0 0 0 0 0 0 0 0 0 | 688 | 43 45 43 49 51 48 20 24 24 8 10 10 17 20 20 35 37 36 |
| 690 | 0 0 0 0 0 0 10 10 10 26 26 26 | 689 | 33 37 35 40 43 41 37 39 37 35 37 36 33 37 35 33 37 35 |
| 691 | 58 58 58 90 90 90 18 18 18 2 2 6 | 690 | 30 32 31 27 30 29 23 27 26 15 19 19 14 18 18 14 17 17 |
| 692 | 2 2 6 110 110 110 253 253 253 253 253 253 | 691 | 13 17 17 13 16 16 12 15 15 11 14 14 13 16 16 14 17 17 |
| 693 | 253 253 253 253 253 253 253 253 253 253 253 253 | 692 | 14 17 17 13 17 17 11 14 14 4 5 5 0 0 0 0 0 0 |
| 694 | 250 250 250 253 253 253 253 253 253 253 253 253 | 693 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 695 | 253 253 253 253 253 253 253 253 253 253 253 253 | 694 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 696 | 253 253 253 253 253 253 253 253 253 253 253 253 | 695 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 697 | 253 253 253 231 231 231 18 18 18 2 2 6 | 696 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 698 | 2 2 6 2 2 6 2 2 6 2 2 6 | 697 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 699 | 2 2 6 2 2 6 18 18 18 94 94 94 | 698 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 700 | 54 54 54 26 26 26 10 10 10 0 0 0 | 699 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 701 | 0 0 0 0 0 0 0 0 0 0 0 0 | 700 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 702 | 0 0 0 0 0 0 0 0 0 0 0 0 | 701 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 703 | 0 0 0 0 0 0 0 0 0 0 0 0 | 702 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 704 | 0 0 0 0 0 0 0 0 0 0 0 0 | 703 | 0 0 0 |
| 705 | 0 0 0 0 0 0 0 0 0 0 0 0 | 704 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 706 | 0 0 0 0 0 0 0 0 0 0 0 0 | 705 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 707 | 0 0 0 0 0 0 0 0 0 0 0 0 | 706 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 708 | 0 0 0 0 0 0 0 0 0 0 0 0 | 707 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 709 | 0 0 0 0 0 0 0 0 0 0 0 0 | 708 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 710 | 0 0 0 6 6 6 22 22 22 50 50 50 | 709 | 0 0 0 96 95 69 230 229 82 230 229 82 239 239 170 251 251 187 |
| 711 | 90 90 90 26 26 26 2 2 6 2 2 6 | 710 | 241 241 143 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 712 | 14 14 14 195 195 195 250 250 250 253 253 253 | 711 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 713 | 253 253 253 253 253 253 253 253 253 253 253 253 | 712 | 230 229 82 161 156 96 36 38 35 33 37 35 33 37 35 33 37 35 |
| 714 | 253 253 253 253 253 253 253 253 253 253 253 253 | 713 | 37 39 37 47 48 46 55 57 54 55 57 54 49 51 48 43 45 43 |
| 715 | 253 253 253 253 253 253 253 253 253 253 253 253 | 714 | 43 45 43 43 45 43 40 43 41 40 43 41 37 39 37 33 37 35 |
| 716 | 253 253 253 253 253 253 253 253 253 253 253 253 | 715 | 33 37 35 28 31 30 26 28 27 16 20 20 15 18 18 14 18 18 |
| 717 | 250 250 250 242 242 242 54 54 54 2 2 6 | 716 | 14 17 17 13 16 16 12 15 15 11 14 14 12 15 15 13 17 17 |
| 718 | 2 2 6 2 2 6 2 2 6 2 2 6 | 717 | 14 17 17 14 17 17 8 10 10 5 7 7 0 0 0 0 0 0 |
| 719 | 2 2 6 2 2 6 2 2 6 38 38 38 | 718 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 720 | 86 86 86 50 50 50 22 22 22 6 6 6 | 719 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 721 | 0 0 0 0 0 0 0 0 0 0 0 0 | 720 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 722 | 0 0 0 0 0 0 0 0 0 0 0 0 | 721 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 723 | 0 0 0 0 0 0 0 0 0 0 0 0 | 722 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 724 | 0 0 0 0 0 0 0 0 0 0 0 0 | 723 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 725 | 0 0 0 0 0 0 0 0 0 0 0 0 | 724 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 726 | 0 0 0 0 0 0 0 0 0 0 0 0 | 725 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 727 | 0 0 0 0 0 0 0 0 0 0 0 0 | 726 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 728 | 0 0 0 0 0 0 0 0 0 0 0 0 | 727 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 729 | 0 0 0 0 0 0 0 0 0 0 0 0 | 728 | 0 0 0 |
| 730 | 6 6 6 14 14 14 38 38 38 82 82 82 | 729 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 731 | 34 34 34 2 2 6 2 2 6 2 2 6 | 730 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 732 | 42 42 42 195 195 195 246 246 246 253 253 253 | 731 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 733 | 253 253 253 253 253 253 253 253 253 250 250 250 | 732 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 734 | 242 242 242 242 242 242 250 250 250 253 253 253 | 733 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 735 | 253 253 253 253 253 253 253 253 253 253 253 253 | 734 | 16 17 12 230 229 82 230 229 82 243 242 120 251 251 187 251 251 187 |
| 736 | 253 253 253 250 250 250 246 246 246 238 238 238 | 735 | 246 246 123 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 737 | 226 226 226 231 231 231 101 101 101 6 6 6 | 736 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 738 | 2 2 6 2 2 6 2 2 6 2 2 6 | 737 | 230 229 82 230 229 82 66 65 55 30 32 31 32 35 33 33 37 35 |
| 739 | 2 2 6 2 2 6 2 2 6 2 2 6 | 738 | 33 37 35 37 39 37 40 43 41 47 48 46 49 51 48 51 52 50 |
| 740 | 38 38 38 82 82 82 42 42 42 14 14 14 | 739 | 55 57 54 55 57 54 51 52 50 47 48 46 43 45 43 39 40 39 |
| 741 | 6 6 6 0 0 0 0 0 0 0 0 0 | 740 | 33 37 35 30 32 31 26 28 27 17 21 21 15 19 19 14 18 18 |
| 742 | 0 0 0 0 0 0 0 0 0 0 0 0 | 741 | 14 17 17 13 16 16 12 15 15 12 14 14 11 14 14 13 16 16 |
| 743 | 0 0 0 0 0 0 0 0 0 0 0 0 | 742 | 14 17 17 12 15 15 7 9 9 6 8 8 1 1 1 0 0 0 |
| 744 | 0 0 0 0 0 0 0 0 0 0 0 0 | 743 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 745 | 0 0 0 0 0 0 0 0 0 0 0 0 | 744 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 746 | 0 0 0 0 0 0 0 0 0 0 0 0 | 745 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 747 | 0 0 0 0 0 0 0 0 0 0 0 0 | 746 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 748 | 0 0 0 0 0 0 0 0 0 0 0 0 | 747 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 749 | 0 0 0 0 0 0 0 0 0 0 0 0 | 748 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 750 | 10 10 10 26 26 26 62 62 62 66 66 66 | 749 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 751 | 2 2 6 2 2 6 2 2 6 6 6 6 | 750 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 752 | 70 70 70 170 170 170 206 206 206 234 234 234 | 751 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 753 | 246 246 246 250 250 250 250 250 250 238 238 238 | 752 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 754 | 226 226 226 231 231 231 238 238 238 250 250 250 | 753 | 0 0 0 |
| 755 | 250 250 250 250 250 250 246 246 246 231 231 231 | 754 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 756 | 214 214 214 206 206 206 202 202 202 202 202 202 | 755 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 757 | 198 198 198 202 202 202 182 182 182 18 18 18 | 756 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 758 | 2 2 6 2 2 6 2 2 6 2 2 6 | 757 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 759 | 2 2 6 2 2 6 2 2 6 2 2 6 | 758 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 760 | 2 2 6 62 62 62 66 66 66 30 30 30 | 759 | 96 95 69 230 229 82 230 229 82 239 239 170 251 251 187 239 239 170 |
| 761 | 10 10 10 0 0 0 0 0 0 0 0 0 | 760 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 762 | 0 0 0 0 0 0 0 0 0 0 0 0 | 761 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 763 | 0 0 0 0 0 0 0 0 0 0 0 0 | 762 | 230 229 82 230 229 82 96 95 69 27 30 29 28 31 30 30 32 31 |
| 764 | 0 0 0 0 0 0 0 0 0 0 0 0 | 763 | 33 37 35 40 43 41 46 47 45 55 57 54 63 64 60 72 73 67 |
| 765 | 0 0 0 0 0 0 0 0 0 0 0 0 | 764 | 72 73 67 72 73 67 72 73 67 65 66 61 55 57 54 47 48 46 |
| 766 | 0 0 0 0 0 0 0 0 0 0 0 0 | 765 | 39 40 39 32 35 33 27 30 29 17 21 21 15 19 19 15 18 18 |
| 767 | 0 0 0 0 0 0 0 0 0 0 0 0 | 766 | 14 18 18 13 17 17 13 16 16 12 15 15 11 14 14 12 14 14 |
| 768 | 0 0 0 0 0 0 0 0 0 0 0 0 | 767 | 13 16 16 9 11 11 7 9 9 9 11 11 66 65 55 115 113 82 |
| 769 | 0 0 0 0 0 0 0 0 0 0 0 0 | 768 | 21 22 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 770 | 14 14 14 42 42 42 82 82 82 18 18 18 | 769 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 771 | 2 2 6 2 2 6 2 2 6 10 10 10 | 770 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 772 | 94 94 94 182 182 182 218 218 218 242 242 242 | 771 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 773 | 250 250 250 253 253 253 253 253 253 250 250 250 | 772 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 774 | 234 234 234 253 253 253 253 253 253 253 253 253 | 773 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 775 | 253 253 253 253 253 253 253 253 253 246 246 246 | 774 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 776 | 238 238 238 226 226 226 210 210 210 202 202 202 | 775 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 777 | 195 195 195 195 195 195 210 210 210 158 158 158 | 776 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 778 | 6 6 6 14 14 14 50 50 50 14 14 14 | 777 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 779 | 2 2 6 2 2 6 2 2 6 2 2 6 | 778 | 0 0 0 |
| 780 | 2 2 6 6 6 6 86 86 86 46 46 46 | 779 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 781 | 18 18 18 6 6 6 0 0 0 0 0 0 | 780 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 782 | 0 0 0 0 0 0 0 0 0 0 0 0 | 781 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 783 | 0 0 0 0 0 0 0 0 0 0 0 0 | 782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 784 | 0 0 0 0 0 0 0 0 0 0 0 0 | 783 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 7 |
| 785 | 0 0 0 0 0 0 0 0 0 0 0 0 | 784 | 230 229 82 230 229 82 236 236 101 251 251 187 251 251 187 246 246 123 |
| 786 | 0 0 0 0 0 0 0 0 0 0 0 0 | 785 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 787 | 0 0 0 0 0 0 0 0 0 0 0 0 | 786 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 788 | 0 0 0 0 0 0 0 0 0 0 0 0 | 787 | 230 229 82 230 229 82 118 116 76 23 27 26 26 28 27 32 35 33 |
| 789 | 0 0 0 0 0 0 0 0 0 6 6 6 | 788 | 51 52 50 90 89 73 110 109 94 145 141 105 168 163 120 177 172 135 |
| 790 | 22 22 22 54 54 54 70 70 70 2 2 6 | 789 | 177 172 135 188 184 146 188 184 146 181 176 137 194 191 148 188 184 146 |
| 791 | 2 2 6 10 10 10 2 2 6 22 22 22 | 790 | 184 179 149 188 184 146 188 184 146 156 151 111 177 172 135 181 176 137 |
| 792 | 166 166 166 231 231 231 250 250 250 253 253 253 | 791 | 177 172 135 168 163 120 168 163 120 158 153 112 156 151 111 158 153 112 |
| 793 | 253 253 253 253 253 253 253 253 253 250 250 250 | 792 | 156 151 111 158 153 112 177 172 135 188 184 146 188 184 146 194 189 146 |
| 794 | 242 242 242 253 253 253 253 253 253 253 253 253 | 793 | 36 38 35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 795 | 253 253 253 253 253 253 253 253 253 253 253 253 | 794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 796 | 253 253 253 253 253 253 253 253 253 246 246 246 | 795 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 797 | 231 231 231 206 206 206 198 198 198 226 226 226 | 796 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 798 | 94 94 94 2 2 6 6 6 6 38 38 38 | 797 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 799 | 30 30 30 2 2 6 2 2 6 2 2 6 | 798 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 800 | 2 2 6 2 2 6 62 62 62 66 66 66 | 799 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 801 | 26 26 26 10 10 10 0 0 0 0 0 0 | 800 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 802 | 0 0 0 0 0 0 0 0 0 0 0 0 | 801 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 803 | 0 0 0 0 0 0 0 0 0 0 0 0 | 802 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 804 | 0 0 0 0 0 0 0 0 0 0 0 0 | 803 | 0 0 0 |
| 805 | 0 0 0 0 0 0 0 0 0 0 0 0 | 804 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 806 | 0 0 0 0 0 0 0 0 0 0 0 0 | 805 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 807 | 0 0 0 0 0 0 0 0 0 0 0 0 | 806 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 808 | 0 0 0 0 0 0 0 0 0 0 0 0 | 807 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 809 | 0 0 0 0 0 0 0 0 0 10 10 10 | 808 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 81 62 |
| 810 | 30 30 30 74 74 74 50 50 50 2 2 6 | 809 | 230 229 82 230 229 82 244 244 132 251 251 187 244 244 132 230 229 82 |
| 811 | 26 26 26 26 26 26 2 2 6 106 106 106 | 810 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 812 | 238 238 238 253 253 253 253 253 253 253 253 253 | 811 | 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 82 81 62 |
| 813 | 253 253 253 253 253 253 253 253 253 253 253 253 | 812 | 96 95 69 230 229 82 181 178 103 110 109 94 156 151 111 188 184 146 |
| 814 | 253 253 253 253 253 253 253 253 253 253 253 253 | 813 | 188 184 146 197 193 154 188 184 146 184 181 136 188 184 146 168 163 120 |
| 815 | 253 253 253 253 253 253 253 253 253 253 253 253 | 814 | 168 163 120 178 174 128 156 151 111 158 153 112 174 170 121 156 151 111 |
| 816 | 253 253 253 253 253 253 253 253 253 253 253 253 | 815 | 156 151 111 158 153 112 156 151 111 168 163 120 178 174 128 181 176 137 |
| 817 | 253 253 253 246 246 246 218 218 218 202 202 202 | 816 | 176 171 126 178 174 128 184 181 136 176 171 126 178 174 128 184 181 136 |
| 818 | 210 210 210 14 14 14 2 2 6 2 2 6 | 817 | 176 171 126 178 174 128 184 181 136 164 159 111 155 149 109 96 95 69 |
| 819 | 30 30 30 22 22 22 2 2 6 2 2 6 | 818 | 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 820 | 2 2 6 2 2 6 18 18 18 86 86 86 | 819 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 821 | 42 42 42 14 14 14 0 0 0 0 0 0 | 820 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 822 | 0 0 0 0 0 0 0 0 0 0 0 0 | 821 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 823 | 0 0 0 0 0 0 0 0 0 0 0 0 | 822 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 824 | 0 0 0 0 0 0 0 0 0 0 0 0 | 823 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 825 | 0 0 0 0 0 0 0 0 0 0 0 0 | 824 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 826 | 0 0 0 0 0 0 0 0 0 0 0 0 | 825 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 827 | 0 0 0 0 0 0 0 0 0 0 0 0 | 826 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 828 | 0 0 0 0 0 0 0 0 0 0 0 0 | 827 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 829 | 0 0 0 0 0 0 0 0 0 14 14 14 | 828 | 0 0 0 |
| 830 | 42 42 42 90 90 90 22 22 22 2 2 6 | 829 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 831 | 42 42 42 2 2 6 18 18 18 218 218 218 | 830 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 832 | 253 253 253 253 253 253 253 253 253 253 253 253 | 831 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 833 | 253 253 253 253 253 253 253 253 253 253 253 253 | 832 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 834 | 253 253 253 253 253 253 253 253 253 253 253 253 | 833 | 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 161 156 96 |
| 835 | 253 253 253 253 253 253 253 253 253 253 253 253 | 834 | 230 229 82 230 229 82 244 244 132 244 244 132 236 236 101 230 229 82 |
| 836 | 253 253 253 253 253 253 253 253 253 253 253 253 | 835 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 837 | 253 253 253 253 253 253 250 250 250 221 221 221 | 836 | 230 229 82 230 229 82 230 229 82 230 229 82 46 47 43 82 81 62 |
| 838 | 218 218 218 101 101 101 2 2 6 14 14 14 | 837 | 158 153 112 197 193 154 194 189 146 184 181 136 188 184 146 168 163 120 |
| 839 | 18 18 18 38 38 38 10 10 10 2 2 6 | 838 | 156 151 111 137 133 100 131 127 93 137 133 100 137 133 100 158 153 112 |
| 840 | 2 2 6 2 2 6 2 2 6 78 78 78 | 839 | 121 119 87 137 133 100 156 151 111 145 141 105 99 98 80 84 83 72 |
| 841 | 58 58 58 22 22 22 6 6 6 0 0 0 | 840 | 63 64 60 52 53 49 40 43 41 33 36 34 36 38 35 36 38 35 |
| 842 | 0 0 0 0 0 0 0 0 0 0 0 0 | 841 | 38 39 37 43 44 41 43 44 41 46 47 43 48 49 45 48 49 45 |
| 843 | 0 0 0 0 0 0 0 0 0 0 0 0 | 842 | 46 47 43 36 38 35 30 31 28 19 20 18 6 7 7 0 0 0 |
| 844 | 0 0 0 0 0 0 0 0 0 0 0 0 | 843 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 845 | 0 0 0 0 0 0 0 0 0 0 0 0 | 844 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 846 | 0 0 0 0 0 0 0 0 0 0 0 0 | 845 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 847 | 0 0 0 0 0 0 0 0 0 0 0 0 | 846 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 848 | 0 0 0 0 0 0 0 0 0 0 0 0 | 847 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 849 | 0 0 0 0 0 0 6 6 6 18 18 18 | 848 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 850 | 54 54 54 82 82 82 2 2 6 26 26 26 | 849 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 851 | 22 22 22 2 2 6 123 123 123 253 253 253 | 850 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 852 | 253 253 253 253 253 253 253 253 253 253 253 253 | 851 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 853 | 253 253 253 253 253 253 253 253 253 253 253 253 | 852 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 854 | 253 253 253 253 253 253 253 253 253 253 253 253 | 853 | 0 0 0 |
| 855 | 253 253 253 253 253 253 253 253 253 253 253 253 | 854 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 856 | 253 253 253 253 253 253 253 253 253 253 253 253 | 855 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 857 | 253 253 253 253 253 253 253 253 253 250 250 250 | 856 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 858 | 238 238 238 198 198 198 6 6 6 38 38 38 | 857 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 859 | 58 58 58 26 26 26 38 38 38 2 2 6 | 858 | 0 0 0 0 0 0 0 0 0 0 0 0 36 38 35 230 229 82 |
| 860 | 2 2 6 2 2 6 2 2 6 46 46 46 | 859 | 230 229 82 230 229 82 246 246 123 236 236 101 230 229 82 230 229 82 |
| 861 | 78 78 78 30 30 30 10 10 10 0 0 0 | 860 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 862 | 0 0 0 0 0 0 0 0 0 0 0 0 | 861 | 230 229 82 230 229 82 230 229 82 230 229 82 53 55 47 121 119 87 |
| 863 | 0 0 0 0 0 0 0 0 0 0 0 0 | 862 | 176 171 126 171 165 117 161 156 96 82 81 62 53 55 47 33 37 35 |
| 864 | 0 0 0 0 0 0 0 0 0 0 0 0 | 863 | 39 40 39 63 64 60 99 98 80 121 119 87 137 133 100 177 172 135 |
| 865 | 0 0 0 0 0 0 0 0 0 0 0 0 | 864 | 176 171 126 184 181 136 131 127 93 131 127 93 110 109 94 84 83 72 |
| 866 | 0 0 0 0 0 0 0 0 0 0 0 0 | 865 | 51 52 50 39 40 39 27 29 28 18 22 22 16 19 19 15 19 19 |
| 867 | 0 0 0 0 0 0 0 0 0 0 0 0 | 866 | 15 19 19 14 18 18 14 17 17 13 16 16 12 15 15 11 14 14 |
| 868 | 0 0 0 0 0 0 0 0 0 0 0 0 | 867 | 10 13 13 9 12 12 9 11 11 8 9 9 7 9 9 1 1 1 |
| 869 | 0 0 0 0 0 0 10 10 10 30 30 30 | 868 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 870 | 74 74 74 58 58 58 2 2 6 42 42 42 | 869 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 871 | 2 2 6 22 22 22 231 231 231 253 253 253 | 870 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 872 | 253 253 253 253 253 253 253 253 253 253 253 253 | 871 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 873 | 253 253 253 253 253 253 253 253 253 250 250 250 | 872 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 874 | 253 253 253 253 253 253 253 253 253 253 253 253 | 873 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 875 | 253 253 253 253 253 253 253 253 253 253 253 253 | 874 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 876 | 253 253 253 253 253 253 253 253 253 253 253 253 | 875 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 877 | 253 253 253 253 253 253 253 253 253 253 253 253 | 876 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 878 | 253 253 253 246 246 246 46 46 46 38 38 38 | 877 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 879 | 42 42 42 14 14 14 38 38 38 14 14 14 | 878 | 0 0 0 |
| 880 | 2 2 6 2 2 6 2 2 6 6 6 6 | 879 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 881 | 86 86 86 46 46 46 14 14 14 0 0 0 | 880 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 882 | 0 0 0 0 0 0 0 0 0 0 0 0 | 881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 883 | 0 0 0 0 0 0 0 0 0 0 0 0 | 882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 884 | 0 0 0 0 0 0 0 0 0 0 0 0 | 883 | 0 0 0 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 |
| 885 | 0 0 0 0 0 0 0 0 0 0 0 0 | 884 | 230 229 82 230 229 82 236 236 101 230 229 82 230 229 82 230 229 82 |
| 886 | 0 0 0 0 0 0 0 0 0 0 0 0 | 885 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 887 | 0 0 0 0 0 0 0 0 0 0 0 0 | 886 | 230 229 82 230 229 82 230 229 82 230 229 82 96 95 69 71 71 57 |
| 888 | 0 0 0 0 0 0 0 0 0 0 0 0 | 887 | 36 38 35 118 116 76 118 116 76 12 15 15 15 18 18 20 24 24 |
| 889 | 0 0 0 6 6 6 14 14 14 42 42 42 | 888 | 33 37 35 55 56 53 84 83 72 110 109 94 145 141 105 110 109 94 |
| 890 | 90 90 90 18 18 18 18 18 18 26 26 26 | 889 | 168 163 120 121 119 87 156 151 111 131 127 93 87 86 72 61 63 57 |
| 891 | 2 2 6 116 116 116 253 253 253 253 253 253 | 890 | 47 48 46 28 31 30 18 22 22 15 19 19 15 18 18 15 19 19 |
| 892 | 253 253 253 253 253 253 253 253 253 253 253 253 | 891 | 15 19 19 14 18 18 14 17 17 13 17 17 13 16 16 12 15 15 |
| 893 | 253 253 253 253 253 253 250 250 250 238 238 238 | 892 | 11 13 13 10 12 12 9 11 11 8 10 10 7 9 9 3 3 3 |
| 894 | 253 253 253 253 253 253 253 253 253 253 253 253 | 893 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 895 | 253 253 253 253 253 253 253 253 253 253 253 253 | 894 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 896 | 253 253 253 253 253 253 253 253 253 253 253 253 | 895 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 897 | 253 253 253 253 253 253 253 253 253 253 253 253 | 896 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 898 | 253 253 253 253 253 253 94 94 94 6 6 6 | 897 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 899 | 2 2 6 2 2 6 10 10 10 34 34 34 | 898 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 900 | 2 2 6 2 2 6 2 2 6 2 2 6 | 899 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 901 | 74 74 74 58 58 58 22 22 22 6 6 6 | 900 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 902 | 0 0 0 0 0 0 0 0 0 0 0 0 | 901 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 903 | 0 0 0 0 0 0 0 0 0 0 0 0 | 902 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 904 | 0 0 0 0 0 0 0 0 0 0 0 0 | 903 | 0 0 0 |
| 905 | 0 0 0 0 0 0 0 0 0 0 0 0 | 904 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 906 | 0 0 0 0 0 0 0 0 0 0 0 0 | 905 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 907 | 0 0 0 0 0 0 0 0 0 0 0 0 | 906 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 908 | 0 0 0 0 0 0 0 0 0 0 0 0 | 907 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 909 | 0 0 0 10 10 10 26 26 26 66 66 66 | 908 | 0 0 0 0 0 0 0 0 0 1 1 0 230 229 82 230 229 82 |
| 910 | 82 82 82 2 2 6 38 38 38 6 6 6 | 909 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 911 | 14 14 14 210 210 210 253 253 253 253 253 253 | 910 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 912 | 253 253 253 253 253 253 253 253 253 253 253 253 | 911 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 |
| 913 | 253 253 253 253 253 253 246 246 246 242 242 242 | 912 | 161 156 96 230 229 82 118 116 76 11 14 14 14 17 17 18 22 22 |
| 914 | 253 253 253 253 253 253 253 253 253 253 253 253 | 913 | 27 30 29 40 43 41 60 60 56 84 83 72 105 104 92 110 109 94 |
| 915 | 253 253 253 253 253 253 253 253 253 253 253 253 | 914 | 110 109 94 110 109 94 99 98 80 90 89 73 68 70 65 47 48 46 |
| 916 | 253 253 253 253 253 253 253 253 253 253 253 253 | 915 | 32 34 33 23 25 24 20 23 23 17 21 21 15 19 19 14 17 17 |
| 917 | 253 253 253 253 253 253 253 253 253 253 253 253 | 916 | 15 19 19 15 18 18 14 18 18 13 17 17 13 16 16 12 15 15 |
| 918 | 253 253 253 253 253 253 144 144 144 2 2 6 | 917 | 11 14 14 10 12 12 9 11 11 8 10 10 7 9 9 4 5 5 |
| 919 | 2 2 6 2 2 6 2 2 6 46 46 46 | 918 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 920 | 2 2 6 2 2 6 2 2 6 2 2 6 | 919 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 921 | 42 42 42 74 74 74 30 30 30 10 10 10 | 920 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 922 | 0 0 0 0 0 0 0 0 0 0 0 0 | 921 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 923 | 0 0 0 0 0 0 0 0 0 0 0 0 | 922 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 924 | 0 0 0 0 0 0 0 0 0 0 0 0 | 923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 925 | 0 0 0 0 0 0 0 0 0 0 0 0 | 924 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 926 | 0 0 0 0 0 0 0 0 0 0 0 0 | 925 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 927 | 0 0 0 0 0 0 0 0 0 0 0 0 | 926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 928 | 0 0 0 0 0 0 0 0 0 0 0 0 | 927 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 929 | 6 6 6 14 14 14 42 42 42 90 90 90 | 928 | 0 0 0 |
| 930 | 26 26 26 6 6 6 42 42 42 2 2 6 | 929 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 931 | 74 74 74 250 250 250 253 253 253 253 253 253 | 930 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 932 | 253 253 253 253 253 253 253 253 253 253 253 253 | 931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 933 | 253 253 253 253 253 253 242 242 242 242 242 242 | 932 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 934 | 253 253 253 253 253 253 253 253 253 253 253 253 | 933 | 0 0 0 0 0 0 0 0 0 16 17 12 230 229 82 230 229 82 |
| 935 | 253 253 253 253 253 253 253 253 253 253 253 253 | 934 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 936 | 253 253 253 253 253 253 253 253 253 253 253 253 | 935 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 937 | 253 253 253 253 253 253 253 253 253 253 253 253 | 936 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 938 | 253 253 253 253 253 253 182 182 182 2 2 6 | 937 | 230 229 82 161 156 96 118 116 76 11 13 13 13 16 16 15 19 19 |
| 939 | 2 2 6 2 2 6 2 2 6 46 46 46 | 938 | 20 24 24 30 32 31 40 43 41 51 52 50 63 64 60 72 73 67 |
| 940 | 2 2 6 2 2 6 2 2 6 2 2 6 | 939 | 65 66 61 65 66 61 65 66 61 55 57 54 46 47 45 33 37 35 |
| 941 | 10 10 10 86 86 86 38 38 38 10 10 10 | 940 | 27 29 28 20 24 24 17 21 21 16 20 20 16 20 20 15 19 19 |
| 942 | 0 0 0 0 0 0 0 0 0 0 0 0 | 941 | 15 19 19 15 19 19 14 18 18 14 17 17 13 16 16 12 15 15 |
| 943 | 0 0 0 0 0 0 0 0 0 0 0 0 | 942 | 11 14 14 10 13 13 9 12 12 8 10 10 7 9 9 6 7 7 |
| 944 | 0 0 0 0 0 0 0 0 0 0 0 0 | 943 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 945 | 0 0 0 0 0 0 0 0 0 0 0 0 | 944 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 946 | 0 0 0 0 0 0 0 0 0 0 0 0 | 945 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 947 | 0 0 0 0 0 0 0 0 0 0 0 0 | 946 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 948 | 0 0 0 0 0 0 0 0 0 0 0 0 | 947 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 949 | 10 10 10 26 26 26 66 66 66 82 82 82 | 948 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 950 | 2 2 6 22 22 22 18 18 18 2 2 6 | 949 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 951 | 149 149 149 253 253 253 253 253 253 253 253 253 | 950 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 952 | 253 253 253 253 253 253 253 253 253 253 253 253 | 951 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 953 | 253 253 253 253 253 253 234 234 234 242 242 242 | 952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 954 | 253 253 253 253 253 253 253 253 253 253 253 253 | 953 | 0 0 0 |
| 955 | 253 253 253 253 253 253 253 253 253 253 253 253 | 954 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 956 | 253 253 253 253 253 253 253 253 253 253 253 253 | 955 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 957 | 253 253 253 253 253 253 253 253 253 253 253 253 | 956 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 958 | 253 253 253 253 253 253 206 206 206 2 2 6 | 957 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 959 | 2 2 6 2 2 6 2 2 6 38 38 38 | 958 | 0 0 0 0 0 0 0 0 0 53 55 47 230 229 82 230 229 82 |
| 960 | 2 2 6 2 2 6 2 2 6 2 2 6 | 959 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 961 | 6 6 6 86 86 86 46 46 46 14 14 14 | 960 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 962 | 0 0 0 0 0 0 0 0 0 0 0 0 | 961 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 963 | 0 0 0 0 0 0 0 0 0 0 0 0 | 962 | 161 156 96 118 116 76 53 55 47 10 13 13 12 15 15 14 17 17 |
| 964 | 0 0 0 0 0 0 0 0 0 0 0 0 | 963 | 17 20 20 20 24 24 27 29 28 32 34 33 37 39 37 40 43 41 |
| 965 | 0 0 0 0 0 0 0 0 0 0 0 0 | 964 | 43 45 43 41 42 42 35 37 36 30 32 31 28 31 30 23 27 26 |
| 966 | 0 0 0 0 0 0 0 0 0 0 0 0 | 965 | 20 23 23 17 21 21 16 20 20 16 20 20 16 20 20 16 19 19 |
| 967 | 0 0 0 0 0 0 0 0 0 0 0 0 | 966 | 15 19 19 15 19 19 14 18 18 14 17 17 13 16 16 12 15 15 |
| 968 | 0 0 0 0 0 0 0 0 0 6 6 6 | 967 | 11 14 14 10 13 13 9 12 12 9 11 11 8 10 10 10 12 12 |
| 969 | 18 18 18 46 46 46 86 86 86 18 18 18 | 968 | 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 970 | 2 2 6 34 34 34 10 10 10 6 6 6 | 969 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 971 | 210 210 210 253 253 253 253 253 253 253 253 253 | 970 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 972 | 253 253 253 253 253 253 253 253 253 253 253 253 | 971 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 973 | 253 253 253 253 253 253 234 234 234 242 242 242 | 972 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 974 | 253 253 253 253 253 253 253 253 253 253 253 253 | 973 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 975 | 253 253 253 253 253 253 253 253 253 253 253 253 | 974 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 976 | 253 253 253 253 253 253 253 253 253 253 253 253 | 975 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 977 | 253 253 253 253 253 253 253 253 253 253 253 253 | 976 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 978 | 253 253 253 253 253 253 221 221 221 6 6 6 | 977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 979 | 2 2 6 2 2 6 6 6 6 30 30 30 | 978 | 0 0 0 |
| 980 | 2 2 6 2 2 6 2 2 6 2 2 6 | 979 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 981 | 2 2 6 82 82 82 54 54 54 18 18 18 | 980 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 982 | 6 6 6 0 0 0 0 0 0 0 0 0 | 981 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 983 | 0 0 0 0 0 0 0 0 0 0 0 0 | 982 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 984 | 0 0 0 0 0 0 0 0 0 0 0 0 | 983 | 0 0 0 0 0 0 0 0 0 82 81 62 230 229 82 230 229 82 |
| 985 | 0 0 0 0 0 0 0 0 0 0 0 0 | 984 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 986 | 0 0 0 0 0 0 0 0 0 0 0 0 | 985 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 987 | 0 0 0 0 0 0 0 0 0 0 0 0 | 986 | 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 161 156 96 |
| 988 | 0 0 0 0 0 0 0 0 0 10 10 10 | 987 | 118 116 76 82 81 62 13 14 12 10 13 13 12 15 15 13 17 17 |
| 989 | 26 26 26 66 66 66 62 62 62 2 2 6 | 988 | 15 19 19 16 20 20 20 23 23 20 24 24 23 27 26 26 28 27 |
| 990 | 2 2 6 38 38 38 10 10 10 26 26 26 | 989 | 26 28 27 26 28 27 23 27 26 18 22 22 20 23 23 17 21 21 |
| 991 | 238 238 238 253 253 253 253 253 253 253 253 253 | 990 | 17 21 21 16 20 20 16 20 20 16 20 20 16 20 20 16 19 19 |
| 992 | 253 253 253 253 253 253 253 253 253 253 253 253 | 991 | 15 19 19 15 19 19 15 18 18 14 17 17 13 17 17 13 16 16 |
| 993 | 253 253 253 253 253 253 231 231 231 238 238 238 | 992 | 12 15 15 12 14 14 12 14 14 12 14 14 12 14 14 23 24 24 |
| 994 | 253 253 253 253 253 253 253 253 253 253 253 253 | 993 | 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 995 | 253 253 253 253 253 253 253 253 253 253 253 253 | 994 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 996 | 253 253 253 253 253 253 253 253 253 253 253 253 | 995 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 997 | 253 253 253 253 253 253 253 253 253 253 253 253 | 996 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 998 | 253 253 253 253 253 253 231 231 231 6 6 6 | 997 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 999 | 2 2 6 2 2 6 10 10 10 30 30 30 | 998 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1000 | 2 2 6 2 2 6 2 2 6 2 2 6 | 999 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1001 | 2 2 6 66 66 66 58 58 58 22 22 22 | 1000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1002 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1001 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1003 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1002 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1004 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1003 | 0 0 0 |
| 1005 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1004 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1006 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1005 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1007 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1006 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1008 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1007 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1009 | 38 38 38 78 78 78 6 6 6 2 2 6 | 1008 | 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 230 229 82 |
| 1010 | 2 2 6 46 46 46 14 14 14 42 42 42 | 1009 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1011 | 246 246 246 253 253 253 253 253 253 253 253 253 | 1010 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1012 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1011 | 230 229 82 230 229 82 230 229 82 161 156 96 161 156 96 118 116 76 |
| 1013 | 253 253 253 253 253 253 231 231 231 242 242 242 | 1012 | 71 71 57 13 14 12 9 12 12 10 13 13 12 15 15 13 17 17 |
| 1014 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1013 | 15 18 18 15 19 19 16 20 20 17 21 21 17 21 21 18 22 22 |
| 1015 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1014 | 18 22 22 18 22 22 17 21 21 16 19 19 15 18 18 14 18 18 |
| 1016 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1015 | 16 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1017 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1016 | 15 19 19 15 19 19 15 18 18 14 18 18 16 20 20 23 25 24 |
| 1018 | 253 253 253 253 253 253 234 234 234 10 10 10 | 1017 | 17 21 21 25 27 26 47 48 46 47 48 46 51 52 50 72 73 67 |
| 1019 | 2 2 6 2 2 6 22 22 22 14 14 14 | 1018 | 33 36 34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1020 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1019 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1021 | 2 2 6 66 66 66 62 62 62 22 22 22 | 1020 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1022 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1021 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1023 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1022 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1024 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1023 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1025 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1024 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1026 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1025 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1027 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1026 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1028 | 0 0 0 0 0 0 6 6 6 18 18 18 | 1027 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1029 | 50 50 50 74 74 74 2 2 6 2 2 6 | 1028 | 0 0 0 |
| 1030 | 14 14 14 70 70 70 34 34 34 62 62 62 | 1029 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1031 | 250 250 250 253 253 253 253 253 253 253 253 253 | 1030 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1032 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1031 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1033 | 253 253 253 253 253 253 231 231 231 246 246 246 | 1032 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1034 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1033 | 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 230 229 82 |
| 1035 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1034 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1036 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1035 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1037 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1036 | 230 229 82 230 229 82 161 156 96 118 116 76 118 116 76 46 47 43 |
| 1038 | 253 253 253 253 253 253 234 234 234 14 14 14 | 1037 | 9 11 11 9 11 11 10 12 12 11 13 13 12 15 15 14 17 17 |
| 1039 | 2 2 6 2 2 6 30 30 30 2 2 6 | 1038 | 15 18 18 15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1040 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1039 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1041 | 2 2 6 66 66 66 62 62 62 22 22 22 | 1040 | 15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1042 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1041 | 15 19 19 16 20 20 20 24 24 55 56 53 32 34 33 84 83 72 |
| 1043 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1042 | 90 89 73 110 109 94 110 109 94 105 104 92 110 109 94 110 109 94 |
| 1044 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1043 | 72 73 67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1045 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1044 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1046 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1045 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1047 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1046 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1048 | 0 0 0 0 0 0 6 6 6 18 18 18 | 1047 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1049 | 54 54 54 62 62 62 2 2 6 2 2 6 | 1048 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1050 | 2 2 6 30 30 30 46 46 46 70 70 70 | 1049 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1051 | 250 250 250 253 253 253 253 253 253 253 253 253 | 1050 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1052 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1051 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1053 | 253 253 253 253 253 253 231 231 231 246 246 246 | 1052 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1054 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1053 | 0 0 0 |
| 1055 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1054 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1056 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1055 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1057 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1056 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1058 | 253 253 253 253 253 253 226 226 226 10 10 10 | 1057 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1059 | 2 2 6 6 6 6 30 30 30 2 2 6 | 1058 | 0 0 0 0 0 0 0 0 0 96 95 69 230 229 82 230 229 82 |
| 1060 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1059 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1061 | 2 2 6 66 66 66 58 58 58 22 22 22 | 1060 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1062 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1061 | 230 229 82 161 156 96 118 116 76 82 81 62 16 17 12 9 11 11 |
| 1063 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1062 | 9 11 11 9 12 12 10 13 13 12 14 14 13 16 16 14 18 18 |
| 1064 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1063 | 15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1065 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1064 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1066 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1065 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1067 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1066 | 16 19 19 33 36 34 99 98 80 156 151 111 145 141 105 184 179 149 |
| 1068 | 0 0 0 0 0 0 6 6 6 22 22 22 | 1067 | 168 163 120 184 179 149 177 172 135 156 151 111 145 141 105 110 109 94 |
| 1069 | 58 58 58 62 62 62 2 2 6 2 2 6 | 1068 | 90 89 73 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1070 | 2 2 6 2 2 6 30 30 30 78 78 78 | 1069 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1071 | 250 250 250 253 253 253 253 253 253 253 253 253 | 1070 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1072 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1071 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1073 | 253 253 253 253 253 253 231 231 231 246 246 246 | 1072 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1074 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1073 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1075 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1074 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1076 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1075 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1077 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1076 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1078 | 253 253 253 253 253 253 206 206 206 2 2 6 | 1077 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1079 | 22 22 22 34 34 34 18 14 6 22 22 22 | 1078 | 0 0 0 |
| 1080 | 26 26 26 18 18 18 6 6 6 2 2 6 | 1079 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1081 | 2 2 6 82 82 82 54 54 54 18 18 18 | 1080 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1082 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1081 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1083 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1082 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1084 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1083 | 0 0 0 0 0 0 0 0 0 71 71 57 230 229 82 230 229 82 |
| 1085 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1084 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1086 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1085 | 230 229 82 161 156 96 230 229 82 230 229 82 230 229 82 161 156 96 |
| 1087 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1086 | 118 116 76 82 81 62 30 31 28 9 11 11 9 11 11 9 11 11 |
| 1088 | 0 0 0 0 0 0 6 6 6 26 26 26 | 1087 | 10 12 12 10 13 13 11 14 14 13 16 16 14 17 17 15 18 18 |
| 1089 | 62 62 62 106 106 106 74 54 14 185 133 11 | 1088 | 15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1090 | 210 162 10 121 92 8 6 6 6 62 62 62 | 1089 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1091 | 238 238 238 253 253 253 253 253 253 253 253 253 | 1090 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1092 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1091 | 18 22 22 58 59 55 137 133 100 197 193 154 214 212 158 210 208 158 |
| 1093 | 253 253 253 253 253 253 231 231 231 246 246 246 | 1092 | 197 193 154 184 179 149 184 179 149 137 133 100 110 109 94 99 98 80 |
| 1094 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1093 | 84 83 72 10 10 9 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1095 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1094 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1096 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1095 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1097 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1096 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1098 | 253 253 253 253 253 253 158 158 158 18 18 18 | 1097 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1099 | 14 14 14 2 2 6 2 2 6 2 2 6 | 1098 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1100 | 6 6 6 18 18 18 66 66 66 38 38 38 | 1099 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1101 | 6 6 6 94 94 94 50 50 50 18 18 18 | 1100 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1102 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1101 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1103 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1102 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1104 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1103 | 0 0 0 |
| 1105 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1104 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1106 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1105 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1107 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1106 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1108 | 10 10 10 10 10 10 18 18 18 38 38 38 | 1107 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1109 | 78 78 78 142 134 106 216 158 10 242 186 14 | 1108 | 0 0 0 0 0 0 0 0 0 16 17 12 230 229 82 230 229 82 |
| 1110 | 246 190 14 246 190 14 156 118 10 10 10 10 | 1109 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 |
| 1111 | 90 90 90 238 238 238 253 253 253 253 253 253 | 1110 | 161 156 96 161 156 96 161 156 96 161 156 96 118 116 76 71 71 57 |
| 1112 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1111 | 21 22 20 12 14 14 11 13 13 10 12 12 10 12 12 10 13 13 |
| 1113 | 253 253 253 253 253 253 231 231 231 250 250 250 | 1112 | 11 13 13 12 15 15 13 16 16 14 17 17 14 18 18 15 19 19 |
| 1114 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1113 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1115 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1114 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1116 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1115 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 17 21 21 |
| 1117 | 253 253 253 253 253 253 253 253 253 246 230 190 | 1116 | 23 27 26 84 83 72 184 179 149 251 251 187 210 208 158 184 179 149 |
| 1118 | 238 204 91 238 204 91 181 142 44 37 26 9 | 1117 | 184 179 149 156 151 111 110 109 94 84 83 72 63 64 60 51 52 50 |
| 1119 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1118 | 18 22 22 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1120 | 2 2 6 2 2 6 38 38 38 46 46 46 | 1119 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1121 | 26 26 26 106 106 106 54 54 54 18 18 18 | 1120 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1122 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1121 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1123 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1122 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1124 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1123 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1125 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1124 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1126 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1125 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1127 | 0 0 0 6 6 6 14 14 14 22 22 22 | 1126 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1128 | 30 30 30 38 38 38 50 50 50 70 70 70 | 1127 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1129 | 106 106 106 190 142 34 226 170 11 242 186 14 | 1128 | 0 0 0 |
| 1130 | 246 190 14 246 190 14 246 190 14 154 114 10 | 1129 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1131 | 6 6 6 74 74 74 226 226 226 253 253 253 | 1130 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1132 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1131 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1133 | 253 253 253 253 253 253 231 231 231 250 250 250 | 1132 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1134 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1133 | 0 0 0 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 |
| 1135 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1134 | 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 161 156 96 |
| 1136 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1135 | 161 156 96 161 156 96 118 116 76 53 55 47 20 23 22 16 19 19 |
| 1137 | 253 253 253 253 253 253 253 253 253 228 184 62 | 1136 | 13 16 16 12 15 15 12 14 14 11 14 14 11 14 14 11 14 14 |
| 1138 | 241 196 14 241 208 19 232 195 16 38 30 10 | 1137 | 12 15 15 13 16 16 14 17 17 15 19 19 16 20 20 17 21 21 |
| 1139 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1138 | 23 27 26 18 22 22 20 24 24 23 27 26 30 32 31 17 21 21 |
| 1140 | 2 2 6 6 6 6 30 30 30 26 26 26 | 1139 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1141 | 203 166 17 154 142 90 66 66 66 26 26 26 | 1140 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1142 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1141 | 23 27 26 33 37 35 137 133 100 156 151 111 158 153 112 105 104 92 |
| 1143 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1142 | 105 104 92 68 70 65 39 40 39 18 22 22 12 14 14 12 15 15 |
| 1144 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1143 | 9 11 11 4 5 5 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1145 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1144 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1146 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1145 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1147 | 6 6 6 18 18 18 38 38 38 58 58 58 | 1146 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1148 | 78 78 78 86 86 86 101 101 101 123 123 123 | 1147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1149 | 175 146 61 210 150 10 234 174 13 246 186 14 | 1148 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1150 | 246 190 14 246 190 14 246 190 14 238 190 10 | 1149 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1151 | 102 78 10 2 2 6 46 46 46 198 198 198 | 1150 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1152 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1151 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1153 | 253 253 253 253 253 253 234 234 234 242 242 242 | 1152 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1154 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1153 | 0 0 0 |
| 1155 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1156 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1155 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1157 | 253 253 253 253 253 253 253 253 253 224 178 62 | 1156 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1158 | 242 186 14 241 196 14 210 166 10 22 18 6 | 1157 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1159 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1158 | 0 0 0 0 0 0 0 0 0 0 0 0 16 17 12 230 229 82 |
| 1160 | 2 2 6 2 2 6 6 6 6 121 92 8 | 1159 | 230 229 82 230 229 82 230 229 82 161 156 96 118 116 76 118 116 76 |
| 1161 | 238 202 15 232 195 16 82 82 82 34 34 34 | 1160 | 118 116 76 66 65 55 43 45 43 32 34 33 25 27 26 20 23 22 |
| 1162 | 10 10 10 0 0 0 0 0 0 0 0 0 | 1161 | 17 20 20 15 18 18 14 17 17 15 18 18 13 16 16 14 17 17 |
| 1163 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1162 | 14 18 18 16 20 20 32 34 33 55 57 54 58 59 55 72 73 67 |
| 1164 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1163 | 105 104 92 55 57 54 65 66 61 63 64 60 40 43 41 33 37 35 |
| 1165 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1164 | 41 42 42 20 24 24 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1166 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1165 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1167 | 14 14 14 38 38 38 70 70 70 154 122 46 | 1166 | 17 21 21 26 28 27 30 32 31 35 37 36 68 70 65 39 40 39 |
| 1168 | 190 142 34 200 144 11 197 138 11 197 138 11 | 1167 | 23 27 26 15 18 18 13 16 16 11 14 14 9 12 12 8 10 10 |
| 1169 | 213 154 11 226 170 11 242 186 14 246 190 14 | 1168 | 7 9 9 6 7 7 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1170 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1169 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1171 | 225 175 15 46 32 6 2 2 6 22 22 22 | 1170 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1172 | 158 158 158 250 250 250 253 253 253 253 253 253 | 1171 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1173 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1172 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1174 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1173 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1175 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1174 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1176 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1175 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1177 | 253 253 253 250 250 250 242 242 242 224 178 62 | 1176 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1178 | 239 182 13 236 186 11 213 154 11 46 32 6 | 1177 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1179 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1178 | 0 0 0 |
| 1180 | 2 2 6 2 2 6 61 42 6 225 175 15 | 1179 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1181 | 238 190 10 236 186 11 112 100 78 42 42 42 | 1180 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1182 | 14 14 14 0 0 0 0 0 0 0 0 0 | 1181 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1183 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1182 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1184 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 38 35 |
| 1185 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1184 | 230 229 82 230 229 82 230 229 82 96 95 69 30 31 28 49 51 48 |
| 1186 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1185 | 90 89 73 68 70 65 55 57 54 47 48 46 47 48 46 43 45 43 |
| 1187 | 22 22 22 54 54 54 154 122 46 213 154 11 | 1186 | 32 34 33 43 45 43 43 45 43 23 27 26 25 27 26 40 43 41 |
| 1188 | 226 170 11 230 174 11 226 170 11 226 170 11 | 1187 | 40 43 41 90 89 73 110 109 94 145 141 105 156 151 111 156 151 111 |
| 1189 | 236 178 12 242 186 14 246 190 14 246 190 14 | 1188 | 184 179 149 184 179 149 177 172 135 184 179 149 137 133 100 84 83 72 |
| 1190 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1189 | 105 104 92 63 64 60 49 51 48 47 48 46 28 31 30 18 22 22 |
| 1191 | 241 196 14 184 144 12 10 10 10 2 2 6 | 1190 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1192 | 6 6 6 116 116 116 242 242 242 253 253 253 | 1191 | 16 20 20 15 19 19 15 19 19 15 19 19 18 22 22 15 19 19 |
| 1193 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1192 | 13 16 16 12 15 15 11 14 14 10 13 13 9 12 12 9 11 11 |
| 1194 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1193 | 8 10 10 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1195 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1194 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1196 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1195 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1197 | 253 253 253 231 231 231 198 198 198 214 170 54 | 1196 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1198 | 236 178 12 236 178 12 210 150 10 137 92 6 | 1197 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1199 | 18 14 6 2 2 6 2 2 6 2 2 6 | 1198 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1200 | 6 6 6 70 47 6 200 144 11 236 178 12 | 1199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1201 | 239 182 13 239 182 13 124 112 88 58 58 58 | 1200 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1202 | 22 22 22 6 6 6 0 0 0 0 0 0 | 1201 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1203 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1202 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1204 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1203 | 0 0 0 |
| 1205 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1204 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1206 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1205 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1207 | 30 30 30 70 70 70 180 133 36 226 170 11 | 1206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1208 | 239 182 13 242 186 14 242 186 14 246 186 14 | 1207 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1209 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1208 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1210 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1209 | 30 31 28 230 229 82 71 71 57 2 2 1 0 0 0 58 59 55 |
| 1211 | 246 190 14 232 195 16 98 70 6 2 2 6 | 1210 | 105 104 92 84 83 72 65 66 61 84 83 72 110 109 94 110 109 94 |
| 1212 | 2 2 6 2 2 6 66 66 66 221 221 221 | 1211 | 145 141 105 105 104 92 110 109 94 110 109 94 84 83 72 110 109 94 |
| 1213 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1212 | 158 153 112 197 193 154 197 193 154 239 239 170 251 251 187 251 251 187 |
| 1214 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1213 | 251 251 187 251 251 187 251 251 187 251 251 187 210 208 158 197 193 154 |
| 1215 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1214 | 197 193 154 184 179 149 145 141 105 137 133 100 105 104 92 47 48 46 |
| 1216 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1215 | 20 23 23 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1217 | 253 253 253 206 206 206 198 198 198 214 166 58 | 1216 | 16 20 20 16 19 19 15 19 19 15 19 19 14 18 18 14 17 17 |
| 1218 | 230 174 11 230 174 11 216 158 10 192 133 9 | 1217 | 13 17 17 13 16 16 12 14 14 12 14 14 13 13 13 13 13 13 |
| 1219 | 163 110 8 116 81 8 102 78 10 116 81 8 | 1218 | 13 13 13 12 12 12 10 10 9 6 7 7 2 2 2 0 0 0 |
| 1220 | 167 114 7 197 138 11 226 170 11 239 182 13 | 1219 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1221 | 242 186 14 242 186 14 162 146 94 78 78 78 | 1220 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1222 | 34 34 34 14 14 14 6 6 6 0 0 0 | 1221 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1223 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1222 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1224 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1223 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1225 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1224 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1226 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1225 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1227 | 30 30 30 78 78 78 190 142 34 226 170 11 | 1226 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1228 | 239 182 13 246 190 14 246 190 14 246 190 14 | 1227 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1229 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1228 | 0 0 0 |
| 1230 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1229 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1231 | 246 190 14 241 196 14 203 166 17 22 18 6 | 1230 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1232 | 2 2 6 2 2 6 2 2 6 38 38 38 | 1231 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1233 | 218 218 218 253 253 253 253 253 253 253 253 253 | 1232 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1234 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1233 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1235 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1234 | 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 65 66 61 |
| 1236 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1235 | 105 104 92 84 83 72 84 83 72 110 109 94 184 179 149 210 208 158 |
| 1237 | 250 250 250 206 206 206 198 198 198 202 162 69 | 1236 | 210 208 158 210 208 158 214 212 158 197 193 154 214 212 158 210 208 158 |
| 1238 | 226 170 11 236 178 12 224 166 10 210 150 10 | 1237 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1239 | 200 144 11 197 138 11 192 133 9 197 138 11 | 1238 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1240 | 210 150 10 226 170 11 242 186 14 246 190 14 | 1239 | 251 251 187 251 251 187 239 239 170 251 251 187 184 179 149 84 83 72 |
| 1241 | 246 190 14 246 186 14 225 175 15 124 112 88 | 1240 | 26 28 27 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1242 | 62 62 62 30 30 30 14 14 14 6 6 6 | 1241 | 16 20 20 16 20 20 15 19 19 15 19 19 15 18 18 14 18 18 |
| 1243 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1242 | 13 17 17 13 16 16 15 15 15 14 14 13 14 14 13 14 14 13 |
| 1244 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1243 | 13 13 13 13 13 13 12 12 12 12 12 12 12 12 12 3 4 4 |
| 1245 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1246 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1245 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1247 | 30 30 30 78 78 78 174 135 50 224 166 10 | 1246 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1248 | 239 182 13 246 190 14 246 190 14 246 190 14 | 1247 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1249 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1248 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1250 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1249 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1251 | 246 190 14 246 190 14 241 196 14 139 102 15 | 1250 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1252 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1251 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1253 | 78 78 78 250 250 250 253 253 253 253 253 253 | 1252 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1254 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1253 | 0 0 0 |
| 1255 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1254 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1256 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1257 | 250 250 250 214 214 214 198 198 198 190 150 46 | 1256 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1258 | 219 162 10 236 178 12 234 174 13 224 166 10 | 1257 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1259 | 216 158 10 213 154 11 213 154 11 216 158 10 | 1258 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1260 | 226 170 11 239 182 13 246 190 14 246 190 14 | 1259 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 72 73 67 |
| 1261 | 246 190 14 246 190 14 242 186 14 206 162 42 | 1260 | 105 104 92 99 98 80 84 83 72 99 98 80 177 172 135 197 193 154 |
| 1262 | 101 101 101 58 58 58 30 30 30 14 14 14 | 1261 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1263 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1262 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1264 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1263 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1265 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1264 | 251 251 187 251 251 187 251 251 187 214 212 158 197 193 154 99 98 80 |
| 1266 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1265 | 23 27 26 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1267 | 30 30 30 74 74 74 174 135 50 216 158 10 | 1266 | 16 20 20 16 20 20 15 19 19 15 19 19 15 18 18 14 18 18 |
| 1268 | 236 178 12 246 190 14 246 190 14 246 190 14 | 1267 | 14 17 17 16 16 16 16 16 16 16 16 16 15 15 15 14 14 13 |
| 1269 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1268 | 14 14 13 13 13 13 13 13 13 12 12 12 12 12 12 12 12 12 |
| 1270 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1269 | 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1271 | 246 190 14 246 190 14 241 196 14 226 184 13 | 1270 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1272 | 61 42 6 2 2 6 2 2 6 2 2 6 | 1271 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1273 | 22 22 22 238 238 238 253 253 253 253 253 253 | 1272 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1274 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1273 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1275 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1274 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1276 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1275 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1277 | 253 253 253 226 226 226 187 187 187 180 133 36 | 1276 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1278 | 216 158 10 236 178 12 239 182 13 236 178 12 | 1277 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1279 | 230 174 11 226 170 11 226 170 11 230 174 11 | 1278 | 0 0 0 |
| 1280 | 236 178 12 242 186 14 246 190 14 246 190 14 | 1279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1281 | 246 190 14 246 190 14 246 186 14 239 182 13 | 1280 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1282 | 206 162 42 106 106 106 66 66 66 34 34 34 | 1281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1283 | 14 14 14 6 6 6 0 0 0 0 0 0 | 1282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1284 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1283 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1285 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1284 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84 83 72 |
| 1286 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1285 | 110 109 94 99 98 80 72 73 67 63 64 60 99 98 80 177 172 135 |
| 1287 | 26 26 26 70 70 70 163 133 67 213 154 11 | 1286 | 184 179 149 210 208 158 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1288 | 236 178 12 246 190 14 246 190 14 246 190 14 | 1287 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1289 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1288 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1290 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1289 | 251 251 187 210 208 158 184 179 149 177 172 135 110 109 94 33 37 35 |
| 1291 | 246 190 14 246 190 14 246 190 14 241 196 14 | 1290 | 17 21 21 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1292 | 190 146 13 18 14 6 2 2 6 2 2 6 | 1291 | 16 20 20 16 20 20 15 19 19 15 19 19 15 19 19 14 18 18 |
| 1293 | 46 46 46 246 246 246 253 253 253 253 253 253 | 1292 | 15 18 18 18 19 18 18 19 18 17 17 17 16 16 16 15 15 15 |
| 1294 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1293 | 14 14 13 13 13 13 13 13 13 12 12 12 12 12 12 12 12 12 |
| 1295 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1294 | 10 10 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1296 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1295 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1297 | 253 253 253 221 221 221 86 86 86 156 107 11 | 1296 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1298 | 216 158 10 236 178 12 242 186 14 246 186 14 | 1297 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1299 | 242 186 14 239 182 13 239 182 13 242 186 14 | 1298 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1300 | 242 186 14 246 186 14 246 190 14 246 190 14 | 1299 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1301 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1300 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1302 | 242 186 14 225 175 15 142 122 72 66 66 66 | 1301 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1303 | 30 30 30 10 10 10 0 0 0 0 0 0 | 1302 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1304 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1303 | 0 0 0 |
| 1305 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1304 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1306 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1305 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1307 | 26 26 26 70 70 70 163 133 67 210 150 10 | 1306 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1308 | 236 178 12 246 190 14 246 190 14 246 190 14 | 1307 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1309 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1308 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1310 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1309 | 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 105 104 92 |
| 1311 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1310 | 108 107 93 99 98 80 72 73 67 63 64 60 51 52 50 87 86 72 |
| 1312 | 232 195 16 121 92 8 34 34 34 106 106 106 | 1311 | 105 104 92 110 109 94 108 107 93 156 151 111 184 179 149 184 179 149 |
| 1313 | 221 221 221 253 253 253 253 253 253 253 253 253 | 1312 | 197 193 154 197 193 154 197 193 154 184 179 149 184 179 149 177 172 135 |
| 1314 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1313 | 197 193 154 156 151 111 177 172 135 184 179 149 168 163 120 137 133 100 |
| 1315 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1314 | 145 141 105 110 109 94 99 98 80 47 48 46 55 57 54 15 19 19 |
| 1316 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1315 | 16 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1317 | 242 242 242 82 82 82 18 14 6 163 110 8 | 1316 | 17 20 20 17 21 21 16 20 20 16 19 19 15 19 19 16 19 19 |
| 1318 | 216 158 10 236 178 12 242 186 14 246 190 14 | 1317 | 20 20 20 21 22 21 20 20 20 19 20 19 18 19 18 16 16 16 |
| 1319 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1318 | 15 15 15 14 14 13 13 13 13 13 13 13 12 12 12 12 12 12 |
| 1320 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1319 | 12 12 12 4 5 5 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1321 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1320 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1322 | 246 190 14 246 190 14 242 186 14 163 133 67 | 1321 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1323 | 46 46 46 18 18 18 6 6 6 0 0 0 | 1322 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1324 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1323 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1325 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1324 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1326 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1325 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1327 | 30 30 30 78 78 78 163 133 67 210 150 10 | 1326 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1328 | 236 178 12 246 186 14 246 190 14 246 190 14 | 1327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1329 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1328 | 0 0 0 |
| 1330 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1329 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1331 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1330 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1332 | 241 196 14 215 174 15 190 178 144 253 253 253 | 1331 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1333 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1334 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1333 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1335 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1334 | 0 0 0 0 0 0 0 0 0 0 0 0 58 59 55 110 109 94 |
| 1336 | 253 253 253 253 253 253 253 253 253 218 218 218 | 1335 | 105 104 92 90 89 73 72 73 67 55 57 54 43 45 43 39 40 39 |
| 1337 | 58 58 58 2 2 6 22 18 6 167 114 7 | 1336 | 43 45 43 46 47 45 43 45 43 68 70 65 65 66 61 63 64 60 |
| 1338 | 216 158 10 236 178 12 246 186 14 246 190 14 | 1337 | 108 107 93 72 73 67 105 104 92 90 89 73 72 73 67 40 43 41 |
| 1339 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1338 | 72 73 67 68 70 65 68 70 65 58 59 55 63 64 60 49 51 48 |
| 1340 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1339 | 43 45 43 33 36 34 27 30 29 20 24 24 16 20 20 15 19 19 |
| 1341 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1340 | 15 19 19 15 19 19 15 19 19 16 19 19 16 20 20 16 20 20 |
| 1342 | 246 190 14 246 186 14 242 186 14 190 150 46 | 1341 | 17 21 21 20 24 24 20 23 22 17 21 21 17 20 20 20 20 20 |
| 1343 | 54 54 54 22 22 22 6 6 6 0 0 0 | 1342 | 21 22 21 21 22 21 21 22 21 21 22 21 20 20 20 18 19 18 |
| 1344 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1343 | 16 16 16 15 15 15 13 13 13 13 13 13 12 12 12 12 12 12 |
| 1345 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1344 | 12 12 12 10 10 9 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1346 | 0 0 0 0 0 0 0 0 0 14 14 14 | 1345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1347 | 38 38 38 86 86 86 180 133 36 213 154 11 | 1346 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1348 | 236 178 12 246 186 14 246 190 14 246 190 14 | 1347 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1349 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1348 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1350 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1349 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1351 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1350 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1352 | 246 190 14 232 195 16 190 146 13 214 214 214 | 1351 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1353 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1352 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1354 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1353 | 0 0 0 |
| 1355 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1354 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1356 | 253 253 253 250 250 250 170 170 170 26 26 26 | 1355 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1357 | 2 2 6 2 2 6 37 26 9 163 110 8 | 1356 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1358 | 219 162 10 239 182 13 246 186 14 246 190 14 | 1357 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1359 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1358 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1360 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1359 | 0 0 0 0 0 0 0 0 0 21 22 21 110 109 94 110 109 94 |
| 1361 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1360 | 105 104 92 84 83 72 68 70 65 51 52 50 41 42 42 33 37 35 |
| 1362 | 246 186 14 236 178 12 224 166 10 142 122 72 | 1361 | 28 31 30 23 27 26 20 23 23 18 22 22 17 20 20 25 27 26 |
| 1363 | 46 46 46 18 18 18 6 6 6 0 0 0 | 1362 | 26 28 27 27 30 29 25 27 26 20 23 23 23 27 26 30 32 31 |
| 1364 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1363 | 20 24 24 17 21 21 18 22 22 15 19 19 26 28 27 20 23 23 |
| 1365 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1364 | 14 18 18 15 19 19 15 18 18 15 19 19 15 19 19 15 19 19 |
| 1366 | 0 0 0 0 0 0 6 6 6 18 18 18 | 1365 | 15 19 19 15 19 19 15 19 19 15 19 19 15 19 19 16 19 19 |
| 1367 | 50 50 50 109 106 95 192 133 9 224 166 10 | 1366 | 16 20 20 22 24 23 24 26 24 22 24 23 20 23 22 22 24 23 |
| 1368 | 242 186 14 246 190 14 246 190 14 246 190 14 | 1367 | 24 26 24 24 26 24 23 24 24 22 24 23 21 22 21 19 20 19 |
| 1369 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1368 | 17 17 17 15 15 15 14 14 13 13 13 13 12 12 12 12 12 12 |
| 1370 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1369 | 12 12 12 12 12 12 2 2 2 0 0 0 0 0 0 0 0 0 |
| 1371 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1370 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1372 | 242 186 14 226 184 13 210 162 10 142 110 46 | 1371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1373 | 226 226 226 253 253 253 253 253 253 253 253 253 | 1372 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1374 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1375 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1374 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1376 | 198 198 198 66 66 66 2 2 6 2 2 6 | 1375 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1377 | 2 2 6 2 2 6 50 34 6 156 107 11 | 1376 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1378 | 219 162 10 239 182 13 246 186 14 246 190 14 | 1377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1379 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1378 | 0 0 0 |
| 1380 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1379 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1381 | 246 190 14 246 190 14 246 190 14 242 186 14 | 1380 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1382 | 234 174 13 213 154 11 154 122 46 66 66 66 | 1381 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1383 | 30 30 30 10 10 10 0 0 0 0 0 0 | 1382 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1384 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1383 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1385 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1384 | 0 0 0 0 0 0 2 2 2 99 98 80 110 109 94 108 107 93 |
| 1386 | 0 0 0 0 0 0 6 6 6 22 22 22 | 1385 | 105 104 92 84 83 72 63 64 60 49 51 48 39 40 39 32 34 33 |
| 1387 | 58 58 58 154 121 60 206 145 10 234 174 13 | 1386 | 27 30 29 23 25 24 20 23 23 17 20 20 15 19 19 14 18 18 |
| 1388 | 242 186 14 246 186 14 246 190 14 246 190 14 | 1387 | 14 17 17 13 17 17 13 17 17 13 17 17 13 17 17 13 17 17 |
| 1389 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1388 | 14 17 17 14 17 17 14 17 17 14 17 17 14 17 17 14 17 17 |
| 1390 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1389 | 14 18 18 14 18 18 14 18 18 14 18 18 15 18 18 15 19 19 |
| 1391 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1390 | 15 19 19 15 19 19 15 19 19 15 19 19 15 19 19 15 19 19 |
| 1392 | 246 186 14 236 178 12 210 162 10 163 110 8 | 1391 | 15 19 19 17 21 21 27 29 28 26 28 27 25 27 26 25 27 26 |
| 1393 | 61 42 6 138 138 138 218 218 218 250 250 250 | 1392 | 27 29 28 27 29 28 26 28 27 24 26 24 21 22 21 20 20 20 |
| 1394 | 253 253 253 253 253 253 253 253 253 250 250 250 | 1393 | 18 19 18 16 16 16 14 14 13 13 13 13 12 12 12 12 12 12 |
| 1395 | 242 242 242 210 210 210 144 144 144 66 66 66 | 1394 | 12 12 12 12 12 12 4 5 5 0 0 0 0 0 0 0 0 0 |
| 1396 | 6 6 6 2 2 6 2 2 6 2 2 6 | 1395 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1397 | 2 2 6 2 2 6 61 42 6 163 110 8 | 1396 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1398 | 216 158 10 236 178 12 246 190 14 246 190 14 | 1397 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1399 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1398 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1400 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1399 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1401 | 246 190 14 239 182 13 230 174 11 216 158 10 | 1400 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1402 | 190 142 34 124 112 88 70 70 70 38 38 38 | 1401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1403 | 18 18 18 6 6 6 0 0 0 0 0 0 | 1402 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1404 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1403 | 0 0 0 |
| 1405 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1404 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1406 | 0 0 0 0 0 0 6 6 6 22 22 22 | 1405 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1407 | 62 62 62 168 124 44 206 145 10 224 166 10 | 1406 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1408 | 236 178 12 239 182 13 242 186 14 242 186 14 | 1407 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1409 | 246 186 14 246 190 14 246 190 14 246 190 14 | 1408 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1410 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1409 | 0 0 0 0 0 0 51 52 50 110 109 94 110 109 94 105 104 92 |
| 1411 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1410 | 90 89 73 72 73 67 55 57 54 43 45 43 35 37 36 30 32 31 |
| 1412 | 246 190 14 236 178 12 216 158 10 175 118 6 | 1411 | 26 28 27 20 24 24 17 21 21 16 19 19 15 18 18 14 17 17 |
| 1413 | 80 54 7 2 2 6 6 6 6 30 30 30 | 1412 | 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 |
| 1414 | 54 54 54 62 62 62 50 50 50 38 38 38 | 1413 | 13 16 16 13 16 16 13 16 16 13 17 17 13 17 17 14 17 17 |
| 1415 | 14 14 14 2 2 6 2 2 6 2 2 6 | 1414 | 14 17 17 14 17 17 14 17 17 14 18 18 14 18 18 14 18 18 |
| 1416 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1415 | 15 18 18 15 18 18 15 19 19 15 19 19 15 19 19 15 19 19 |
| 1417 | 2 2 6 6 6 6 80 54 7 167 114 7 | 1416 | 15 19 19 15 19 19 27 29 28 32 34 33 28 31 30 27 29 28 |
| 1418 | 213 154 11 236 178 12 246 190 14 246 190 14 | 1417 | 30 32 31 30 32 31 30 31 28 26 28 27 23 24 24 21 22 21 |
| 1419 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1418 | 19 20 19 16 16 16 14 14 13 13 13 13 12 12 12 12 12 12 |
| 1420 | 246 190 14 242 186 14 239 182 13 239 182 13 | 1419 | 12 12 12 12 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 1421 | 230 174 11 210 150 10 174 135 50 124 112 88 | 1420 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1422 | 82 82 82 54 54 54 34 34 34 18 18 18 | 1421 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1423 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1422 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1424 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1423 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1425 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1424 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1426 | 0 0 0 0 0 0 6 6 6 18 18 18 | 1425 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1427 | 50 50 50 158 118 36 192 133 9 200 144 11 | 1426 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1428 | 216 158 10 219 162 10 224 166 10 226 170 11 | 1427 | 0 0 0 0 0 0 0 0 0 3 3 3 0 0 0 0 0 0 |
| 1429 | 230 174 11 236 178 12 239 182 13 239 182 13 | 1428 | 0 0 0 |
| 1430 | 242 186 14 246 186 14 246 190 14 246 190 14 | 1429 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1431 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1430 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1432 | 246 186 14 230 174 11 210 150 10 163 110 8 | 1431 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1433 | 104 69 6 10 10 10 2 2 6 2 2 6 | 1432 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1434 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1433 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1435 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1434 | 0 0 0 10 10 9 108 107 93 110 109 94 108 107 93 99 98 80 |
| 1436 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1435 | 84 83 72 63 64 60 49 51 48 40 43 41 33 36 34 27 30 29 |
| 1437 | 2 2 6 6 6 6 91 60 6 167 114 7 | 1436 | 23 27 26 18 22 22 17 20 20 15 18 18 14 17 17 13 16 16 |
| 1438 | 206 145 10 230 174 11 242 186 14 246 190 14 | 1437 | 13 16 16 13 16 16 12 15 15 12 15 15 12 15 15 12 15 15 |
| 1439 | 246 190 14 246 190 14 246 186 14 242 186 14 | 1438 | 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 |
| 1440 | 239 182 13 230 174 11 224 166 10 213 154 11 | 1439 | 13 17 17 13 17 17 14 17 17 14 17 17 14 17 17 14 18 18 |
| 1441 | 180 133 36 124 112 88 86 86 86 58 58 58 | 1440 | 14 18 18 14 18 18 15 18 18 15 18 18 15 19 19 15 19 19 |
| 1442 | 38 38 38 22 22 22 10 10 10 6 6 6 | 1441 | 15 19 19 15 19 19 17 21 21 33 36 34 32 34 33 31 33 31 |
| 1443 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1442 | 33 36 34 33 36 34 31 33 31 27 29 28 25 27 26 21 22 21 |
| 1444 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1443 | 19 20 19 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1445 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1444 | 12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0 |
| 1446 | 0 0 0 0 0 0 0 0 0 14 14 14 | 1445 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1447 | 34 34 34 70 70 70 138 110 50 158 118 36 | 1446 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1448 | 167 114 7 180 123 7 192 133 9 197 138 11 | 1447 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1449 | 200 144 11 206 145 10 213 154 11 219 162 10 | 1448 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1450 | 224 166 10 230 174 11 239 182 13 242 186 14 | 1449 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1451 | 246 186 14 246 186 14 246 186 14 246 186 14 | 1450 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1452 | 239 182 13 216 158 10 185 133 11 152 99 6 | 1451 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1453 | 104 69 6 18 14 6 2 2 6 2 2 6 | 1452 | 0 0 0 0 0 0 63 64 60 137 133 100 43 45 43 0 0 0 |
| 1454 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1453 | 0 0 0 |
| 1455 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1454 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1456 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1455 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1457 | 2 2 6 6 6 6 80 54 7 152 99 6 | 1456 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1458 | 192 133 9 219 162 10 236 178 12 239 182 13 | 1457 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1459 | 246 186 14 242 186 14 239 182 13 236 178 12 | 1458 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1460 | 224 166 10 206 145 10 192 133 9 154 121 60 | 1459 | 0 0 0 68 70 65 110 109 94 110 109 94 105 104 92 84 83 72 |
| 1461 | 94 94 94 62 62 62 42 42 42 22 22 22 | 1460 | 68 70 65 55 57 54 43 45 43 35 37 36 30 32 31 26 28 27 |
| 1462 | 14 14 14 6 6 6 0 0 0 0 0 0 | 1461 | 20 24 24 17 21 21 16 19 19 14 17 17 13 16 16 12 15 15 |
| 1463 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1462 | 12 15 15 12 15 15 12 15 15 12 15 15 12 15 15 12 15 15 |
| 1464 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1463 | 12 15 15 12 15 15 12 15 15 12 15 15 12 15 15 13 16 16 |
| 1465 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1464 | 13 16 16 13 16 16 13 16 16 13 17 17 13 17 17 14 17 17 |
| 1466 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1465 | 14 17 17 14 17 17 14 18 18 14 18 18 14 18 18 15 18 18 |
| 1467 | 18 18 18 34 34 34 58 58 58 78 78 78 | 1466 | 15 19 19 15 19 19 15 19 19 20 24 24 32 34 33 35 37 36 |
| 1468 | 101 98 89 124 112 88 142 110 46 156 107 11 | 1467 | 37 39 37 35 37 36 33 36 34 30 32 31 26 28 27 22 24 23 |
| 1469 | 163 110 8 167 114 7 175 118 6 180 123 7 | 1468 | 20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1470 | 185 133 11 197 138 11 210 150 10 219 162 10 | 1469 | 12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0 |
| 1471 | 226 170 11 236 178 12 236 178 12 234 174 13 | 1470 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1472 | 219 162 10 197 138 11 163 110 8 130 83 6 | 1471 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1473 | 91 60 6 10 10 10 2 2 6 2 2 6 | 1472 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1474 | 18 18 18 38 38 38 38 38 38 38 38 38 | 1473 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1475 | 38 38 38 38 38 38 38 38 38 38 38 38 | 1474 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1476 | 38 38 38 38 38 38 26 26 26 2 2 6 | 1475 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1477 | 2 2 6 6 6 6 70 47 6 137 92 6 | 1476 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1478 | 175 118 6 200 144 11 219 162 10 230 174 11 | 1477 | 1 1 1 99 98 80 184 179 149 184 179 149 68 70 65 0 0 0 |
| 1479 | 234 174 13 230 174 11 219 162 10 210 150 10 | 1478 | 0 0 0 |
| 1480 | 192 133 9 163 110 8 124 112 88 82 82 82 | 1479 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1481 | 50 50 50 30 30 30 14 14 14 6 6 6 | 1480 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1482 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1481 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1483 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1482 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1484 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1483 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1485 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1484 | 15 15 15 110 109 94 110 109 94 108 107 93 99 98 80 72 73 67 |
| 1486 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1485 | 61 63 57 49 51 48 39 40 39 33 36 34 27 30 29 23 25 24 |
| 1487 | 6 6 6 14 14 14 22 22 22 34 34 34 | 1486 | 18 22 22 16 19 19 14 17 17 13 16 16 12 15 15 12 15 15 |
| 1488 | 42 42 42 58 58 58 74 74 74 86 86 86 | 1487 | 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 |
| 1489 | 101 98 89 122 102 70 130 98 46 121 87 25 | 1488 | 11 14 14 11 14 14 12 14 14 12 15 15 12 15 15 12 15 15 |
| 1490 | 137 92 6 152 99 6 163 110 8 180 123 7 | 1489 | 12 15 15 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 |
| 1491 | 185 133 11 197 138 11 206 145 10 200 144 11 | 1490 | 13 17 17 14 17 17 14 17 17 14 17 17 14 18 18 14 18 18 |
| 1492 | 180 123 7 156 107 11 130 83 6 104 69 6 | 1491 | 14 18 18 15 18 18 15 19 19 15 19 19 30 32 31 38 39 37 |
| 1493 | 50 34 6 54 54 54 110 110 110 101 98 89 | 1492 | 39 40 39 39 40 39 35 37 36 31 33 31 27 29 28 22 24 23 |
| 1494 | 86 86 86 82 82 82 78 78 78 78 78 78 | 1493 | 20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1495 | 78 78 78 78 78 78 78 78 78 78 78 78 | 1494 | 12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0 |
| 1496 | 78 78 78 82 82 82 86 86 86 94 94 94 | 1495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1497 | 106 106 106 101 101 101 86 66 34 124 80 6 | 1496 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1498 | 156 107 11 180 123 7 192 133 9 200 144 11 | 1497 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1499 | 206 145 10 200 144 11 192 133 9 175 118 6 | 1498 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1500 | 139 102 15 109 106 95 70 70 70 42 42 42 | 1499 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1501 | 22 22 22 10 10 10 0 0 0 0 0 0 | 1500 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1502 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1501 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 |
| 1503 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1502 | 110 109 94 197 193 154 210 208 158 184 179 149 68 70 65 0 0 0 |
| 1504 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1503 | 0 0 0 |
| 1505 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1504 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1506 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1505 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1507 | 0 0 0 0 0 0 6 6 6 10 10 10 | 1506 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1508 | 14 14 14 22 22 22 30 30 30 38 38 38 | 1507 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1509 | 50 50 50 62 62 62 74 74 74 90 90 90 | 1508 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1510 | 101 98 89 112 100 78 121 87 25 124 80 6 | 1509 | 68 70 65 110 109 94 110 109 94 105 104 92 84 83 72 65 66 61 |
| 1511 | 137 92 6 152 99 6 152 99 6 152 99 6 | 1510 | 51 52 50 43 45 43 35 37 36 30 32 31 25 27 26 20 23 23 |
| 1512 | 138 86 6 124 80 6 98 70 6 86 66 30 | 1511 | 17 20 20 15 18 18 13 16 16 12 15 15 12 15 15 11 14 14 |
| 1513 | 101 98 89 82 82 82 58 58 58 46 46 46 | 1512 | 11 14 14 11 14 14 11 13 13 11 13 13 11 13 13 11 13 13 |
| 1514 | 38 38 38 34 34 34 34 34 34 34 34 34 | 1513 | 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 |
| 1515 | 34 34 34 34 34 34 34 34 34 34 34 34 | 1514 | 12 15 15 12 15 15 12 15 15 12 15 15 13 16 16 13 16 16 |
| 1516 | 34 34 34 34 34 34 38 38 38 42 42 42 | 1515 | 13 16 16 13 16 16 13 17 17 13 17 17 14 17 17 14 17 17 |
| 1517 | 54 54 54 82 82 82 94 86 76 91 60 6 | 1516 | 14 18 18 14 18 18 14 18 18 16 19 19 37 39 37 41 42 42 |
| 1518 | 134 86 6 156 107 11 167 114 7 175 118 6 | 1517 | 41 42 42 41 42 42 38 39 37 32 34 33 27 29 28 23 24 24 |
| 1519 | 175 118 6 167 114 7 152 99 6 121 87 25 | 1518 | 21 22 21 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1520 | 101 98 89 62 62 62 34 34 34 18 18 18 | 1519 | 12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0 |
| 1521 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1520 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1522 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1521 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1523 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1522 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1524 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1523 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1525 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1524 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1526 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1525 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1527 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1526 | 0 0 0 0 0 0 0 0 0 0 0 0 11 11 11 137 133 100 |
| 1528 | 0 0 0 6 6 6 6 6 6 10 10 10 | 1527 | 197 193 154 251 251 187 239 239 170 184 179 149 31 33 31 0 0 0 |
| 1529 | 18 18 18 22 22 22 30 30 30 42 42 42 | 1528 | 0 0 0 |
| 1530 | 50 50 50 66 66 66 86 86 86 101 98 89 | 1529 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1531 | 106 86 58 98 70 6 104 69 6 104 69 6 | 1530 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1532 | 104 69 6 91 60 6 82 62 34 90 90 90 | 1531 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1533 | 62 62 62 38 38 38 22 22 22 14 14 14 | 1532 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1534 | 10 10 10 10 10 10 10 10 10 10 10 10 | 1533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 12 12 |
| 1535 | 10 10 10 10 10 10 6 6 6 10 10 10 | 1534 | 110 109 94 110 109 94 105 104 92 90 89 73 72 73 67 58 59 55 |
| 1536 | 10 10 10 10 10 10 10 10 10 14 14 14 | 1535 | 46 47 45 37 39 37 31 33 31 26 28 27 20 24 24 17 21 21 |
| 1537 | 22 22 22 42 42 42 70 70 70 89 81 66 | 1536 | 15 18 18 13 16 16 12 15 15 12 14 14 11 13 13 11 13 13 |
| 1538 | 80 54 7 104 69 6 124 80 6 137 92 6 | 1537 | 10 13 13 10 13 13 10 13 13 10 13 13 10 13 13 10 13 13 |
| 1539 | 134 86 6 116 81 8 100 82 52 86 86 86 | 1538 | 10 13 13 10 13 13 11 13 13 11 13 13 11 14 14 11 14 14 |
| 1540 | 58 58 58 30 30 30 14 14 14 6 6 6 | 1539 | 11 14 14 11 14 14 12 14 14 12 15 15 12 15 15 12 15 15 |
| 1541 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1540 | 13 16 16 13 16 16 13 16 16 13 16 16 13 17 17 13 17 17 |
| 1542 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1541 | 14 17 17 14 17 17 14 18 18 23 27 26 41 42 42 41 42 42 |
| 1543 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1542 | 43 45 43 41 42 42 39 40 39 33 36 34 27 29 28 23 24 24 |
| 1544 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1543 | 21 22 21 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1545 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1544 | 12 12 12 12 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 1546 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1545 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1547 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1546 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1548 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1547 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1549 | 0 0 0 6 6 6 10 10 10 14 14 14 | 1548 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1550 | 18 18 18 26 26 26 38 38 38 54 54 54 | 1549 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1551 | 70 70 70 86 86 86 94 86 76 89 81 66 | 1550 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1552 | 89 81 66 86 86 86 74 74 74 50 50 50 | 1551 | 0 0 0 0 0 0 0 0 0 27 29 28 168 163 120 210 208 158 |
| 1553 | 30 30 30 14 14 14 6 6 6 0 0 0 | 1552 | 251 251 187 251 251 187 210 208 158 137 133 100 1 1 1 0 0 0 |
| 1554 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1553 | 0 0 0 |
| 1555 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1554 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1556 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1555 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1557 | 6 6 6 18 18 18 34 34 34 58 58 58 | 1556 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1558 | 82 82 82 89 81 66 89 81 66 89 81 66 | 1557 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1559 | 94 86 66 94 86 76 74 74 74 50 50 50 | 1558 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 60 56 |
| 1560 | 26 26 26 14 14 14 6 6 6 0 0 0 | 1559 | 110 109 94 105 104 92 105 104 92 84 83 72 65 66 61 51 52 50 |
| 1561 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1560 | 40 43 41 33 36 34 27 30 29 23 25 24 18 22 22 16 19 19 |
| 1562 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1561 | 14 17 17 12 15 15 11 14 14 11 14 14 10 13 13 10 13 13 |
| 1563 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1562 | 10 13 13 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 |
| 1564 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1563 | 10 12 12 10 12 12 10 13 13 10 13 13 10 13 13 11 13 13 |
| 1565 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1564 | 11 13 13 11 14 14 11 14 14 11 14 14 11 14 14 12 15 15 |
| 1566 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1565 | 12 15 15 12 15 15 12 15 15 13 16 16 13 16 16 13 16 16 |
| 1567 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1566 | 13 17 17 13 17 17 14 17 17 32 34 33 43 45 43 43 45 43 |
| 1568 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1567 | 43 45 43 43 45 43 39 40 39 33 36 34 27 29 28 23 24 24 |
| 1569 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1568 | 21 22 21 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1570 | 6 6 6 6 6 6 14 14 14 18 18 18 | 1569 | 12 12 12 12 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 1571 | 30 30 30 38 38 38 46 46 46 54 54 54 | 1570 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1572 | 50 50 50 42 42 42 30 30 30 18 18 18 | 1571 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1573 | 10 10 10 0 0 0 0 0 0 0 0 0 | 1572 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1574 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1573 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1575 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1574 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1576 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1575 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1577 | 0 0 0 6 6 6 14 14 14 26 26 26 | 1576 | 0 0 0 1 1 1 68 70 65 184 179 149 210 208 158 251 251 187 |
| 1578 | 38 38 38 50 50 50 58 58 58 58 58 58 | 1577 | 251 251 187 214 212 158 184 179 149 37 39 37 0 0 0 0 0 0 |
| 1579 | 54 54 54 42 42 42 30 30 30 18 18 18 | 1578 | 0 0 0 |
| 1580 | 10 10 10 0 0 0 0 0 0 0 0 0 | 1579 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1581 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1580 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1582 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1581 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1583 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1582 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1584 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1583 | 0 0 0 0 0 0 0 0 0 0 0 0 6 7 7 105 104 92 |
| 1585 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1584 | 105 104 92 105 104 92 99 98 80 72 73 67 58 59 55 46 47 45 |
| 1586 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1585 | 35 37 36 30 32 31 25 27 26 20 23 23 16 19 19 14 17 17 |
| 1587 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1586 | 12 15 15 12 14 14 11 13 13 10 13 13 10 12 12 10 12 12 |
| 1588 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1587 | 10 12 12 10 12 12 9 12 12 9 12 12 9 12 12 9 12 12 |
| 1589 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1588 | 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 10 13 13 |
| 1590 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1589 | 10 13 13 10 13 13 11 13 13 11 13 13 11 14 14 11 14 14 |
| 1591 | 6 6 6 10 10 10 14 14 14 18 18 18 | 1590 | 11 14 14 12 15 15 12 15 15 12 15 15 12 15 15 13 16 16 |
| 1592 | 18 18 18 14 14 14 10 10 10 6 6 6 | 1591 | 13 16 16 13 16 16 17 20 20 41 42 42 46 47 45 46 47 45 |
| 1593 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1592 | 46 47 45 43 45 43 40 41 39 33 36 34 27 29 28 23 24 24 |
| 1594 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1593 | 20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1595 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1594 | 12 12 12 12 12 12 4 5 5 0 0 0 0 0 0 0 0 0 |
| 1596 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1595 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1597 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1596 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1598 | 14 14 14 18 18 18 22 22 22 22 22 22 | 1597 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1599 | 18 18 18 14 14 14 10 10 10 6 6 6 | 1598 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1600 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1599 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1601 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1600 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1602 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1601 | 15 15 15 110 109 94 197 193 154 214 212 158 251 251 187 251 251 187 |
| 1603 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1602 | 239 239 170 184 179 149 84 83 72 0 0 0 0 0 0 0 0 0 |
| 1604 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1603 | 0 0 0 |
| 1604 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1605 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1606 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1607 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1608 | 0 0 0 0 0 0 0 0 0 0 0 0 47 48 46 105 104 92 | ||
| 1609 | 105 104 92 99 98 80 84 83 72 68 70 65 51 52 50 40 43 41 | ||
| 1610 | 32 34 33 27 29 28 22 24 23 17 21 21 15 18 18 13 16 16 | ||
| 1611 | 12 15 15 11 13 13 10 13 13 10 12 12 9 12 12 9 12 12 | ||
| 1612 | 9 12 12 9 12 12 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1613 | 9 12 12 9 12 12 9 12 12 9 12 12 10 12 12 10 12 12 | ||
| 1614 | 10 12 12 10 12 12 10 13 13 10 13 13 10 13 13 11 13 13 | ||
| 1615 | 11 14 14 11 14 14 11 14 14 12 14 14 12 15 15 12 15 15 | ||
| 1616 | 12 15 15 13 16 16 28 31 30 43 45 43 47 48 46 47 48 46 | ||
| 1617 | 47 48 46 43 45 43 40 41 39 33 36 34 27 29 28 22 24 23 | ||
| 1618 | 20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 | ||
| 1619 | 12 12 12 12 12 12 3 4 4 0 0 0 0 0 0 0 0 0 | ||
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| 1625 | 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 60 60 56 | ||
| 1626 | 177 172 135 197 193 154 251 251 187 251 251 187 251 251 187 251 251 187 | ||
| 1627 | 184 179 149 110 109 94 3 4 4 0 0 0 0 0 0 0 0 0 | ||
| 1628 | 0 0 0 | ||
| 1629 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 1633 | 0 0 0 0 0 0 0 0 0 1 1 1 99 98 80 105 104 92 | ||
| 1634 | 99 98 80 87 86 72 84 83 72 63 64 60 46 47 45 35 37 36 | ||
| 1635 | 30 32 31 25 27 26 18 22 22 16 19 19 14 17 17 12 15 15 | ||
| 1636 | 11 14 14 10 13 13 9 12 12 9 12 12 9 11 11 9 11 11 | ||
| 1637 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1638 | 9 11 11 9 11 11 9 11 11 9 11 11 9 12 12 9 12 12 | ||
| 1639 | 9 12 12 10 12 12 10 12 12 10 12 12 10 13 13 10 13 13 | ||
| 1640 | 10 13 13 11 13 13 11 14 14 11 14 14 11 14 14 12 15 15 | ||
| 1641 | 12 15 15 14 17 17 41 42 42 47 48 46 49 51 48 51 52 50 | ||
| 1642 | 47 48 46 43 45 43 40 41 39 33 36 34 27 29 28 22 24 23 | ||
| 1643 | 19 20 19 16 16 16 14 14 13 13 13 13 12 12 12 12 12 12 | ||
| 1644 | 12 12 12 12 12 12 2 2 2 0 0 0 0 0 0 0 0 0 | ||
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| 1650 | 0 0 0 0 0 0 0 0 0 23 24 24 137 133 100 184 179 149 | ||
| 1651 | 210 208 158 251 251 187 251 251 187 251 251 187 251 251 187 184 179 149 | ||
| 1652 | 110 109 94 13 13 13 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1653 | 0 0 0 | ||
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| 1658 | 0 0 0 0 0 0 0 0 0 30 32 31 105 104 92 99 98 80 | ||
| 1659 | 84 83 72 84 83 72 72 73 67 55 57 54 41 42 42 32 34 33 | ||
| 1660 | 27 29 28 20 24 24 17 20 20 14 17 17 13 16 16 12 14 14 | ||
| 1661 | 10 13 13 10 12 12 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1662 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1663 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1664 | 9 11 11 9 12 12 9 12 12 10 12 12 10 12 12 10 12 12 | ||
| 1665 | 10 13 13 10 13 13 10 13 13 11 13 13 11 14 14 11 14 14 | ||
| 1666 | 11 14 14 27 29 28 55 56 53 72 73 67 51 52 50 51 52 50 | ||
| 1667 | 49 51 48 43 45 43 39 40 39 32 34 33 26 28 27 21 22 21 | ||
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| 1677 | 19 20 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 1683 | 0 0 0 0 0 0 0 0 0 72 73 67 105 104 92 84 83 72 | ||
| 1684 | 72 73 67 84 83 72 68 70 65 49 51 48 39 40 39 30 32 31 | ||
| 1685 | 25 27 26 18 22 22 15 18 18 13 16 16 12 15 15 11 13 13 | ||
| 1686 | 10 12 12 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1687 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1688 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1689 | 9 11 11 9 11 11 9 11 11 9 12 12 9 12 12 9 12 12 | ||
| 1690 | 10 12 12 10 12 12 10 12 12 10 13 13 10 13 13 11 13 13 | ||
| 1691 | 13 16 16 41 42 42 99 98 80 158 153 112 65 66 61 51 52 50 | ||
| 1692 | 49 51 48 43 45 43 39 40 39 31 33 31 25 27 26 21 22 21 | ||
| 1693 | 21 22 21 68 70 65 55 56 53 13 13 13 12 12 12 12 12 12 | ||
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| 1709 | 68 70 65 84 83 72 63 64 60 46 47 45 35 37 36 27 29 28 | ||
| 1710 | 22 24 23 17 20 20 14 17 17 12 15 15 11 14 14 10 12 12 | ||
| 1711 | 10 12 12 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1712 | 9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1713 | 8 10 10 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1714 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1715 | 9 12 12 9 12 12 10 12 12 10 12 12 10 13 13 10 13 13 | ||
| 1716 | 30 32 31 47 48 46 177 172 135 210 208 158 137 133 100 55 56 53 | ||
| 1717 | 49 51 48 43 45 43 38 39 37 31 33 31 25 27 26 22 24 23 | ||
| 1718 | 110 109 94 184 179 149 63 64 60 13 13 13 12 12 12 12 12 12 | ||
| 1719 | 12 12 12 8 9 9 0 0 0 1 1 1 0 0 0 0 0 0 | ||
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| 1725 | 184 179 149 210 208 158 251 251 187 251 251 187 251 251 187 251 251 187 | ||
| 1726 | 251 251 187 251 251 187 184 179 149 145 141 105 23 24 24 0 0 0 | ||
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| 1733 | 0 0 0 0 0 0 51 52 50 99 98 80 84 83 72 63 64 60 | ||
| 1734 | 68 70 65 72 73 67 55 57 54 41 42 42 32 34 33 25 27 26 | ||
| 1735 | 20 23 23 16 19 19 13 16 16 12 14 14 10 13 13 10 12 12 | ||
| 1736 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 8 10 10 | ||
| 1737 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1738 | 8 10 10 8 10 10 8 10 10 8 10 10 9 11 11 9 11 11 | ||
| 1739 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1740 | 9 11 11 9 11 11 9 12 12 9 12 12 10 12 12 17 20 20 | ||
| 1741 | 46 47 45 72 73 67 210 208 158 251 251 187 210 208 158 63 64 60 | ||
| 1742 | 49 51 48 43 45 43 37 39 37 30 32 31 24 26 24 105 104 92 | ||
| 1743 | 210 208 158 197 193 154 47 48 46 13 13 13 12 12 12 12 12 12 | ||
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| 1860 | 14 17 17 12 15 15 11 13 13 10 12 12 9 11 11 9 11 11 | ||
| 1861 | 9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
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| 1863 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1864 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1865 | 9 11 11 28 31 30 41 42 42 47 48 46 55 56 53 58 59 55 | ||
| 1866 | 137 133 100 251 251 187 251 251 187 251 251 187 210 208 158 137 133 100 | ||
| 1867 | 47 48 46 40 41 39 32 34 33 75 75 61 184 179 149 239 239 170 | ||
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| 1869 | 197 193 154 251 251 187 210 208 158 10 10 9 0 0 0 84 83 72 | ||
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| 1881 | 251 251 187 251 251 187 145 141 105 3 3 3 0 0 0 0 0 0 | ||
| 1882 | 48 49 45 184 179 149 239 239 170 251 251 187 239 239 170 177 172 135 | ||
| 1883 | 84 83 72 72 73 67 55 56 53 39 40 39 26 28 27 39 40 39 | ||
| 1884 | 68 70 65 51 52 50 39 40 39 28 31 30 22 24 23 17 20 20 | ||
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| 1889 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1890 | 27 29 28 40 41 39 46 47 45 51 52 50 55 57 54 63 64 60 | ||
| 1891 | 131 127 93 197 193 154 210 208 158 197 193 154 168 163 120 96 95 69 | ||
| 1892 | 47 48 46 40 41 39 32 34 33 71 71 57 145 141 105 184 179 149 | ||
| 1893 | 184 179 149 131 127 93 13 13 13 12 12 12 12 12 12 48 49 45 | ||
| 1894 | 168 163 120 184 179 149 156 151 111 6 7 7 14 14 13 177 172 135 | ||
| 1895 | 239 239 170 40 41 39 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 1899 | 51 52 50 49 51 48 46 47 45 40 41 39 32 34 33 25 27 26 | ||
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| 1905 | 41 42 42 0 0 0 0 0 0 0 0 0 3 3 3 184 179 149 | ||
| 1906 | 251 251 187 251 251 187 184 179 149 48 49 45 0 0 0 0 0 0 | ||
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| 1908 | 82 81 62 63 64 60 46 47 45 31 33 31 21 22 21 35 37 36 | ||
| 1909 | 68 70 65 51 52 50 37 39 37 27 30 29 22 24 23 17 20 20 | ||
| 1910 | 13 16 16 12 14 14 10 13 13 9 11 11 8 10 10 8 10 10 | ||
| 1911 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1912 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1913 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1914 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 25 27 26 | ||
| 1915 | 38 39 37 43 45 43 51 52 50 55 56 53 60 60 56 63 64 60 | ||
| 1916 | 92 91 72 158 153 112 176 171 126 171 165 117 149 143 98 82 81 62 | ||
| 1917 | 44 46 43 38 39 37 30 32 31 71 71 57 131 127 93 160 154 106 | ||
| 1918 | 149 143 98 82 81 62 13 13 13 12 12 12 12 12 12 46 47 43 | ||
| 1919 | 121 119 87 134 131 96 96 95 69 7 7 6 38 39 37 131 127 93 | ||
| 1920 | 145 141 105 12 13 12 0 0 0 1 1 1 3 3 3 6 7 7 | ||
| 1921 | 10 10 9 12 12 12 14 14 13 16 16 16 18 19 18 21 22 21 | ||
| 1922 | 22 24 23 26 28 27 30 31 28 33 36 34 37 39 37 40 41 39 | ||
| 1923 | 41 42 42 43 45 43 46 47 45 46 47 45 46 47 45 43 45 43 | ||
| 1924 | 41 42 42 37 39 37 31 33 31 26 28 27 21 22 21 16 16 16 | ||
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| 1929 | 0 0 0 0 0 0 0 0 0 0 0 0 177 172 135 251 251 187 | ||
| 1930 | 197 193 154 27 29 28 0 0 0 0 0 0 0 0 0 110 109 94 | ||
| 1931 | 239 239 170 239 239 170 184 179 149 87 86 72 2 2 1 0 0 0 | ||
| 1932 | 1 1 1 82 81 62 142 137 94 165 161 109 165 161 109 131 127 93 | ||
| 1933 | 75 75 61 55 56 53 37 39 37 25 27 26 19 20 19 32 34 33 | ||
| 1934 | 65 66 61 49 51 48 35 37 36 27 29 28 20 23 23 16 19 19 | ||
| 1935 | 13 16 16 13 13 13 10 12 12 9 11 11 8 10 10 8 10 10 | ||
| 1936 | 8 9 9 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1937 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1938 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1939 | 8 10 10 8 10 10 8 10 10 8 10 10 22 24 23 35 37 36 | ||
| 1940 | 41 42 42 47 48 46 55 56 53 58 59 55 63 64 60 65 66 61 | ||
| 1941 | 71 71 57 131 127 93 160 154 106 160 154 106 142 137 94 82 81 62 | ||
| 1942 | 46 47 43 40 41 39 33 36 34 66 65 55 125 122 87 149 143 98 | ||
| 1943 | 142 137 94 82 81 62 17 17 17 18 19 17 14 14 13 46 47 43 | ||
| 1944 | 118 116 76 125 122 87 96 95 69 16 17 12 71 71 57 103 101 77 | ||
| 1945 | 82 81 62 11 11 11 11 11 11 13 13 13 14 14 13 14 14 13 | ||
| 1946 | 15 15 15 16 16 16 17 17 17 19 20 19 21 22 21 23 24 24 | ||
| 1947 | 26 28 27 27 29 28 31 33 31 33 36 34 35 37 36 38 39 37 | ||
| 1948 | 39 40 39 39 40 39 38 39 37 37 39 37 35 37 36 31 33 31 | ||
| 1949 | 27 29 28 24 26 24 21 22 21 17 17 17 12 12 12 2 2 2 | ||
| 1950 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 1954 | 0 0 0 0 0 0 0 0 0 0 0 0 68 70 65 251 251 187 | ||
| 1955 | 251 251 187 156 151 111 2 2 1 0 0 0 0 0 0 43 44 41 | ||
| 1956 | 177 172 135 184 179 149 158 153 112 103 101 77 19 20 18 0 0 0 | ||
| 1957 | 0 0 0 46 47 43 131 127 93 160 154 106 160 154 106 131 127 93 | ||
| 1958 | 71 71 57 43 45 43 30 32 31 21 22 21 16 16 16 26 28 27 | ||
| 1959 | 63 64 60 47 48 46 35 37 36 26 28 27 20 23 23 16 19 19 | ||
| 1960 | 13 16 16 13 13 13 10 12 12 9 11 11 8 10 10 8 10 10 | ||
| 1961 | 7 9 9 7 9 9 8 9 9 8 10 10 8 10 10 8 10 10 | ||
| 1962 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1963 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1964 | 8 10 10 8 10 10 8 10 10 20 20 20 33 36 34 40 41 39 | ||
| 1965 | 46 47 45 51 52 50 55 57 54 60 60 56 63 64 60 65 66 61 | ||
| 1966 | 66 65 55 118 116 76 151 147 98 165 161 109 151 147 98 121 119 87 | ||
| 1967 | 96 95 69 96 95 69 96 95 69 103 101 77 142 137 94 151 147 98 | ||
| 1968 | 142 137 94 103 101 77 82 81 62 82 81 62 82 81 62 96 95 69 | ||
| 1969 | 131 127 93 142 137 94 103 101 77 46 47 43 96 95 69 118 116 76 | ||
| 1970 | 71 71 57 14 14 13 14 14 13 15 15 15 15 15 15 16 16 16 | ||
| 1971 | 16 16 16 17 17 17 18 19 18 20 20 20 21 22 21 23 24 24 | ||
| 1972 | 25 27 26 27 29 28 30 31 28 30 32 31 31 33 31 31 33 31 | ||
| 1973 | 31 33 31 31 33 31 30 31 28 27 29 28 25 27 26 22 24 23 | ||
| 1974 | 20 20 20 16 16 16 13 13 13 6 7 7 0 0 0 0 0 0 | ||
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| 1978 | 0 0 0 | ||
| 1979 | 58 59 55 68 70 65 8 8 7 0 0 0 10 10 9 210 208 158 | ||
| 1980 | 251 251 187 184 179 149 38 39 37 0 0 0 0 0 0 8 8 7 | ||
| 1981 | 103 101 77 149 143 98 149 143 98 118 116 76 40 41 39 25 27 25 | ||
| 1982 | 53 55 47 82 81 62 144 139 99 165 161 109 165 161 109 142 137 94 | ||
| 1983 | 71 71 57 35 37 36 24 26 24 18 19 18 15 15 15 22 24 23 | ||
| 1984 | 63 64 60 46 47 45 33 36 34 26 28 27 20 23 22 17 18 17 | ||
| 1985 | 12 15 15 11 13 13 10 12 12 9 11 11 8 10 10 8 10 10 | ||
| 1986 | 7 9 9 7 9 9 7 9 9 7 9 9 8 9 9 8 10 10 | ||
| 1987 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1988 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1989 | 8 10 10 8 10 10 16 16 16 30 31 28 35 37 36 41 42 42 | ||
| 1990 | 47 48 46 55 56 53 58 59 55 63 64 60 65 66 61 65 66 61 | ||
| 1991 | 61 61 53 103 101 77 151 147 98 171 165 117 171 165 117 168 163 120 | ||
| 1992 | 158 153 112 158 153 112 155 149 109 151 147 98 151 147 98 160 154 106 | ||
| 1993 | 151 147 98 149 143 98 142 137 94 149 143 98 149 143 98 149 143 98 | ||
| 1994 | 155 149 109 151 147 98 131 127 93 103 101 77 125 122 87 118 116 76 | ||
| 1995 | 71 71 57 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17 | ||
| 1996 | 17 17 17 17 17 17 18 19 18 19 20 19 20 20 20 21 22 21 | ||
| 1997 | 23 24 24 24 26 24 25 27 26 26 28 27 26 28 27 26 28 27 | ||
| 1998 | 25 27 26 24 26 24 22 24 23 21 22 21 19 20 19 16 16 16 | ||
| 1999 | 14 14 13 8 8 7 1 1 1 0 0 0 0 0 0 0 0 0 | ||
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| 2003 | 0 0 0 | ||
| 2004 | 20 20 20 184 179 149 168 163 120 21 22 21 0 0 0 105 104 92 | ||
| 2005 | 177 172 135 145 141 105 71 71 57 0 0 0 0 0 0 0 0 0 | ||
| 2006 | 66 65 55 131 127 93 151 147 98 142 137 94 118 116 76 121 119 87 | ||
| 2007 | 145 141 105 158 153 112 176 171 126 178 174 128 176 171 126 149 145 103 | ||
| 2008 | 96 95 69 31 33 31 21 22 21 16 16 16 14 14 13 18 19 18 | ||
| 2009 | 60 60 56 46 47 45 33 36 34 25 27 26 21 22 21 15 18 18 | ||
| 2010 | 12 15 15 11 13 13 9 11 11 8 10 10 8 10 10 8 9 9 | ||
| 2011 | 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 8 9 9 | ||
| 2012 | 8 9 9 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 2013 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 2014 | 8 10 10 10 12 12 26 28 27 31 33 31 38 39 37 43 45 43 | ||
| 2015 | 51 52 50 55 56 53 60 60 56 63 64 60 65 66 61 68 70 65 | ||
| 2016 | 63 64 60 96 95 69 158 153 112 178 174 128 188 184 146 194 189 146 | ||
| 2017 | 194 189 146 188 184 146 184 181 136 176 171 126 171 165 117 173 167 111 | ||
| 2018 | 173 167 111 165 161 109 171 165 117 174 170 121 176 171 126 178 174 128 | ||
| 2019 | 178 174 128 174 170 121 160 154 106 149 143 98 149 143 98 125 122 87 | ||
| 2020 | 71 71 57 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17 | ||
| 2021 | 17 17 17 17 17 17 17 17 17 18 19 18 19 20 19 20 20 20 | ||
| 2022 | 21 22 21 21 22 21 21 22 21 22 24 23 21 22 21 21 22 21 | ||
| 2023 | 21 22 21 19 20 19 18 19 18 16 16 16 14 14 13 11 11 11 | ||
| 2024 | 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 2028 | 0 0 0 | ||
| 2029 | 0 0 0 105 104 92 197 193 154 110 109 94 9 9 8 36 38 35 | ||
| 2030 | 121 119 87 131 127 93 96 95 69 18 19 17 30 31 28 66 65 55 | ||
| 2031 | 96 95 69 142 137 94 160 154 106 160 154 106 160 154 106 168 163 120 | ||
| 2032 | 184 181 136 194 191 148 197 193 154 197 193 154 194 189 146 168 163 120 | ||
| 2033 | 125 122 87 46 47 43 18 19 18 15 15 15 13 13 13 14 14 13 | ||
| 2034 | 55 57 54 43 45 43 32 34 33 25 27 26 18 22 22 17 17 17 | ||
| 2035 | 12 14 14 10 12 12 9 11 11 8 10 10 8 9 9 7 9 9 | ||
| 2036 | 6 8 8 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 | ||
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| 2040 | 35 37 36 55 57 54 60 60 56 63 64 60 65 66 61 65 66 61 | ||
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| 2043 | 174 170 121 176 171 126 186 182 128 190 186 136 194 191 148 197 193 154 | ||
| 2044 | 197 193 154 188 184 146 181 176 137 174 170 121 165 161 109 142 137 94 | ||
| 2045 | 82 81 62 24 26 24 16 16 16 16 16 16 16 16 16 16 16 16 | ||
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| 2058 | 158 153 112 87 86 72 17 17 17 13 13 13 13 13 13 15 15 15 | ||
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| 2070 | 118 116 76 36 38 35 15 15 15 16 16 16 16 16 16 16 16 16 | ||
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| 2091 | 71 71 57 155 149 109 194 191 148 214 212 158 251 251 187 251 251 187 | ||
| 2092 | 251 251 187 251 251 187 239 239 170 210 208 158 197 193 154 190 186 136 | ||
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| 2094 | 239 239 170 224 223 159 210 208 158 204 201 155 190 186 136 164 159 111 | ||
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| 2118 | 190 186 136 197 193 154 210 208 158 224 223 159 251 251 187 251 251 187 | ||
| 2119 | 251 251 187 251 251 187 239 239 170 210 208 158 197 193 154 176 171 126 | ||
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| 2140 | 41 42 42 47 48 46 51 52 50 51 52 50 55 56 53 55 56 53 | ||
| 2141 | 71 71 57 158 153 112 197 193 154 224 223 159 251 251 187 251 251 187 | ||
| 2142 | 251 251 187 251 251 187 239 239 170 214 212 158 204 201 155 194 189 146 | ||
| 2143 | 190 186 136 197 193 154 210 208 158 239 239 170 251 251 187 251 251 187 | ||
| 2144 | 251 251 187 251 251 187 251 251 187 224 223 159 204 201 155 177 172 135 | ||
| 2145 | 121 119 87 30 31 28 13 13 13 14 14 13 14 14 13 14 14 13 | ||
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| 2156 | 251 251 187 214 212 158 204 201 155 197 193 154 204 201 155 210 208 158 | ||
| 2157 | 239 239 170 251 251 187 251 251 187 251 251 187 239 239 170 214 212 158 | ||
| 2158 | 194 191 148 156 151 111 71 71 57 19 20 19 51 52 50 51 52 50 | ||
| 2159 | 51 52 50 41 42 42 30 32 31 21 22 21 17 17 17 13 13 13 | ||
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| 2162 | 6 8 8 6 8 8 6 8 8 6 7 7 6 7 7 6 7 7 | ||
| 2163 | 6 7 7 6 8 8 6 8 8 6 8 8 6 8 8 6 8 8 | ||
| 2164 | 55 56 53 43 45 43 6 8 8 6 8 8 6 8 8 47 48 46 | ||
| 2165 | 60 60 56 47 48 46 46 47 45 47 48 46 38 39 37 10 12 12 | ||
| 2166 | 66 65 55 145 141 105 197 193 154 214 212 158 251 251 187 251 251 187 | ||
| 2167 | 251 251 187 251 251 187 224 223 159 210 208 158 194 191 148 184 181 136 | ||
| 2168 | 184 181 136 194 189 146 204 201 155 224 223 159 251 251 187 251 251 187 | ||
| 2169 | 251 251 187 251 251 187 251 251 187 239 239 170 210 208 158 181 176 137 | ||
| 2170 | 115 113 82 21 22 20 13 13 13 13 13 13 13 13 13 13 13 13 | ||
| 2171 | 14 14 13 13 13 13 13 13 13 13 13 13 12 12 12 11 11 11 | ||
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| 2181 | 251 251 187 214 212 158 204 201 155 194 191 148 197 193 154 204 201 155 | ||
| 2182 | 214 212 158 239 239 170 239 239 170 239 239 170 214 212 158 210 208 158 | ||
| 2183 | 184 181 136 149 145 103 66 65 55 41 42 42 47 48 46 46 47 45 | ||
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| 2186 | 5 6 5 5 6 5 5 6 5 5 6 5 5 7 7 5 7 7 | ||
| 2187 | 6 7 7 6 7 7 6 7 7 5 7 7 5 7 7 5 7 7 | ||
| 2188 | 5 7 7 6 7 7 6 7 7 6 7 7 6 7 7 6 8 8 | ||
| 2189 | 6 8 8 6 8 8 6 7 7 6 7 7 46 47 45 156 151 111 | ||
| 2190 | 105 104 92 58 59 55 43 45 43 32 34 33 6 8 8 6 8 8 | ||
| 2191 | 49 51 48 125 122 87 181 176 137 204 201 155 214 212 158 239 239 170 | ||
| 2192 | 239 239 170 214 212 158 210 208 158 197 193 154 181 176 137 176 171 126 | ||
| 2193 | 176 171 126 184 181 136 197 193 154 210 208 158 239 239 170 251 251 187 | ||
| 2194 | 251 251 187 251 251 187 251 251 187 251 251 187 210 208 158 177 172 135 | ||
| 2195 | 99 98 80 13 13 13 12 12 12 12 12 12 13 13 13 12 12 12 | ||
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| 2206 | 251 251 187 214 212 158 197 193 154 190 186 136 184 181 136 188 184 146 | ||
| 2207 | 197 193 154 204 201 155 210 208 158 210 208 158 204 201 155 194 189 146 | ||
| 2208 | 176 171 126 134 131 96 66 65 55 43 45 43 41 42 42 39 40 39 | ||
| 2209 | 35 37 36 33 36 34 27 29 28 20 20 20 15 15 15 9 11 11 | ||
| 2210 | 8 9 9 6 7 7 5 6 5 5 6 5 4 5 5 4 5 5 | ||
| 2211 | 4 5 5 4 5 5 4 5 5 4 5 5 5 6 5 4 5 5 | ||
| 2212 | 4 5 5 5 6 5 4 5 5 5 6 5 5 6 5 5 6 5 | ||
| 2213 | 5 7 7 5 7 7 5 7 7 5 7 7 5 7 7 5 7 7 | ||
| 2214 | 6 7 7 6 7 7 6 7 7 28 31 30 184 179 149 184 179 149 | ||
| 2215 | 145 141 105 84 83 72 27 29 28 5 7 7 5 6 5 16 16 16 | ||
| 2216 | 43 44 41 96 95 69 158 153 112 188 184 146 204 201 155 210 208 158 | ||
| 2217 | 204 201 155 197 193 154 184 179 149 177 172 135 168 163 120 164 159 111 | ||
| 2218 | 164 159 111 174 170 121 184 181 136 197 193 154 214 212 158 251 251 187 | ||
| 2219 | 251 251 187 251 251 187 251 251 187 251 251 187 210 208 158 177 172 135 | ||
| 2220 | 71 71 57 11 11 11 12 12 12 11 11 11 11 11 11 11 11 11 | ||
| 2221 | 10 10 9 10 10 9 8 8 7 3 4 4 0 0 0 0 0 0 | ||
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| 2230 | 197 193 154 214 212 158 251 251 187 251 251 187 251 251 187 251 251 187 | ||
| 2231 | 239 239 170 210 208 158 194 189 146 178 174 128 174 170 121 176 171 126 | ||
| 2232 | 177 172 135 181 176 137 184 179 149 184 179 149 181 176 137 178 174 128 | ||
| 2233 | 158 153 112 121 119 87 53 55 47 37 39 37 33 36 34 30 32 31 | ||
| 2234 | 27 29 28 25 27 26 24 26 24 19 20 19 13 13 13 8 10 10 | ||
| 2235 | 6 8 8 6 7 7 5 6 5 4 5 5 4 5 5 4 5 5 | ||
| 2236 | 4 5 5 4 5 5 4 5 5 3 4 4 3 4 4 4 5 5 | ||
| 2237 | 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2238 | 5 6 5 5 6 5 5 6 5 5 6 5 5 6 5 5 6 5 | ||
| 2239 | 5 6 5 5 6 5 12 14 14 145 141 105 184 179 149 177 172 135 | ||
| 2240 | 90 89 73 21 22 21 5 6 5 5 6 5 4 5 5 37 39 37 | ||
| 2241 | 38 39 37 61 61 53 134 131 96 168 163 120 184 181 136 188 184 146 | ||
| 2242 | 184 179 149 177 172 135 168 163 120 164 159 111 155 149 109 151 147 98 | ||
| 2243 | 151 147 98 164 159 111 176 171 126 184 179 149 210 208 158 239 239 170 | ||
| 2244 | 251 251 187 251 251 187 251 251 187 239 239 170 210 208 158 158 153 112 | ||
| 2245 | 46 47 43 10 10 9 10 10 9 10 10 9 8 9 9 8 9 9 | ||
| 2246 | 6 7 7 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 2253 | 0 0 0 | ||
| 2254 | 0 0 0 0 0 0 0 0 0 13 12 7 82 81 62 158 153 112 | ||
| 2255 | 188 184 146 210 208 158 239 239 170 251 251 187 251 251 187 251 251 187 | ||
| 2256 | 224 223 159 204 201 155 184 181 136 171 165 117 164 159 111 160 154 106 | ||
| 2257 | 158 153 112 164 159 111 168 163 120 168 163 120 168 163 120 164 159 111 | ||
| 2258 | 142 137 94 96 95 69 43 44 41 27 29 28 26 28 27 23 24 24 | ||
| 2259 | 21 22 21 18 19 18 17 17 17 18 19 18 13 13 13 8 8 7 | ||
| 2260 | 6 7 7 5 6 5 4 5 5 3 4 4 3 4 4 3 4 4 | ||
| 2261 | 3 4 4 3 4 4 3 3 3 3 3 3 3 4 4 3 4 4 | ||
| 2262 | 3 4 4 3 4 4 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2263 | 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2264 | 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2265 | 4 5 5 4 5 5 4 5 5 4 5 5 31 33 31 65 66 61 | ||
| 2266 | 37 39 37 38 39 37 96 95 69 144 139 99 168 163 120 174 170 121 | ||
| 2267 | 168 163 120 164 159 111 155 149 109 149 145 103 149 143 98 142 137 94 | ||
| 2268 | 149 143 98 151 147 98 164 159 111 177 172 135 197 193 154 210 208 158 | ||
| 2269 | 251 251 187 251 251 187 251 251 187 239 239 170 197 193 154 137 133 100 | ||
| 2270 | 24 26 24 8 9 9 8 9 9 8 8 7 6 7 7 2 2 2 | ||
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| 2278 | 0 0 0 | ||
| 2279 | 0 0 0 0 0 0 0 0 0 0 0 0 46 47 43 125 122 87 | ||
| 2280 | 176 171 126 197 193 154 210 208 158 239 239 170 251 251 187 239 239 170 | ||
| 2281 | 214 212 158 197 193 154 181 176 137 164 159 111 151 147 98 149 143 98 | ||
| 2282 | 149 143 98 149 143 98 149 145 103 155 149 109 160 154 106 149 143 98 | ||
| 2283 | 118 116 76 82 81 62 30 31 28 21 22 21 19 20 19 17 17 17 | ||
| 2284 | 14 14 13 12 12 12 10 10 9 12 12 12 10 12 12 6 8 8 | ||
| 2285 | 4 5 5 3 4 4 3 4 4 3 4 4 3 3 3 3 3 3 | ||
| 2286 | 3 3 3 3 3 3 3 3 3 3 3 3 2 3 3 2 3 3 | ||
| 2287 | 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 4 5 5 | ||
| 2288 | 4 5 5 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 | ||
| 2289 | 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2290 | 4 5 5 3 4 4 3 4 4 23 24 24 110 109 94 72 73 67 | ||
| 2291 | 39 40 39 22 24 23 46 47 43 103 101 77 142 137 94 155 149 109 | ||
| 2292 | 160 154 106 155 149 109 149 143 98 142 137 94 142 137 94 142 137 94 | ||
| 2293 | 142 137 94 149 143 98 155 149 109 176 171 126 184 179 149 210 208 158 | ||
| 2294 | 239 239 170 251 251 187 251 251 187 214 212 158 184 179 149 105 104 92 | ||
| 2295 | 10 10 9 6 7 7 3 4 4 1 1 1 0 0 0 0 0 0 | ||
| 2296 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2297 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 2301 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2302 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2303 | 0 0 0 | ||
| 2304 | 0 0 0 0 0 0 0 0 0 0 0 0 12 12 9 82 81 62 | ||
| 2305 | 149 145 103 181 176 137 197 193 154 210 208 158 214 212 158 214 212 158 | ||
| 2306 | 210 208 158 197 193 154 177 172 135 158 153 112 149 143 98 142 137 94 | ||
| 2307 | 142 137 94 142 137 94 149 143 98 151 147 98 151 147 98 131 127 93 | ||
| 2308 | 103 101 77 71 71 57 22 24 23 15 15 15 13 13 13 11 11 11 | ||
| 2309 | 8 9 9 6 7 7 6 7 7 4 5 5 8 9 9 6 7 7 | ||
| 2310 | 4 5 5 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 | ||
| 2311 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 | ||
| 2312 | 2 3 3 2 3 3 2 3 3 3 4 4 3 4 4 3 4 4 | ||
| 2313 | 3 4 4 3 4 4 3 3 3 3 4 4 3 4 4 3 4 4 | ||
| 2314 | 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 | ||
| 2315 | 3 4 4 3 4 4 21 22 21 145 141 105 145 141 105 72 73 67 | ||
| 2316 | 17 18 17 3 4 4 21 22 20 66 65 55 118 116 76 142 137 94 | ||
| 2317 | 149 143 98 151 147 98 149 143 98 142 137 94 142 137 94 142 137 94 | ||
| 2318 | 142 137 94 149 143 98 155 149 109 168 163 120 184 179 149 210 208 158 | ||
| 2319 | 239 239 170 251 251 187 251 251 187 210 208 158 177 172 135 71 71 57 | ||
| 2320 | 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2321 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2322 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2323 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2324 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2325 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2326 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2328 | 0 0 0 | ||
| 2329 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 38 35 | ||
| 2330 | 115 113 82 158 153 112 181 176 137 197 193 154 204 201 155 210 208 158 | ||
| 2331 | 204 201 155 188 184 146 177 172 135 164 159 111 149 145 103 142 137 94 | ||
| 2332 | 142 137 94 142 137 94 149 143 98 151 147 98 149 143 98 125 122 87 | ||
| 2333 | 96 95 69 61 61 53 16 17 12 8 9 9 8 8 7 6 7 7 | ||
| 2334 | 4 5 5 3 4 4 3 3 3 3 3 3 3 3 3 5 6 5 | ||
| 2335 | 3 4 4 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2336 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 | ||
| 2337 | 2 2 2 2 2 2 2 3 3 2 3 3 2 3 3 2 3 3 | ||
| 2338 | 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 | ||
| 2339 | 3 3 3 2 3 3 2 3 3 3 4 4 3 4 4 3 4 4 | ||
| 2340 | 3 4 4 3 4 4 3 4 4 8 9 9 8 8 7 3 3 3 | ||
| 2341 | 3 3 3 3 3 3 9 9 8 36 38 35 82 81 62 118 116 76 | ||
| 2342 | 142 137 94 151 147 98 151 147 98 151 147 98 149 143 98 149 143 98 | ||
| 2343 | 149 143 98 151 147 98 160 154 106 176 171 126 188 184 146 210 208 158 | ||
| 2344 | 239 239 170 251 251 187 239 239 170 210 208 158 156 151 111 31 33 31 | ||
| 2345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2346 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2347 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2348 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2349 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2350 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2351 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2352 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2353 | 0 0 0 | ||
| 2354 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 5 | ||
| 2355 | 66 65 55 125 122 87 158 153 112 181 176 137 194 189 146 197 193 154 | ||
| 2356 | 197 193 154 184 179 149 177 172 135 168 163 120 156 151 111 151 147 98 | ||
| 2357 | 151 147 98 151 147 98 151 147 98 161 156 96 149 143 98 118 116 76 | ||
| 2358 | 82 81 62 53 55 47 12 12 9 4 5 5 3 4 4 3 3 3 | ||
| 2359 | 3 3 3 3 3 3 2 2 2 2 2 2 1 1 1 1 2 2 | ||
| 2360 | 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2361 | 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2 | ||
| 2362 | 1 2 2 1 2 2 1 2 2 2 2 2 2 2 2 2 3 3 | ||
| 2363 | 2 3 3 2 3 3 2 3 3 2 3 3 2 2 2 2 2 2 | ||
| 2364 | 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 | ||
| 2365 | 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 3 3 3 | ||
| 2366 | 3 3 3 3 3 3 72 73 67 61 61 53 53 55 47 96 95 69 | ||
| 2367 | 131 127 93 151 147 98 161 156 96 161 156 96 151 147 98 151 147 98 | ||
| 2368 | 161 156 96 160 154 106 164 159 111 177 172 135 197 193 154 210 208 158 | ||
| 2369 | 239 239 170 251 251 187 224 223 159 197 193 154 131 127 93 9 9 8 | ||
| 2370 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2372 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2374 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2375 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2376 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2378 | 0 0 0 | ||
| 2379 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2380 | 24 26 24 82 81 62 131 127 93 164 159 111 178 174 128 188 184 146 | ||
| 2381 | 188 184 146 188 184 146 181 176 137 176 171 126 168 163 120 164 159 111 | ||
| 2382 | 160 154 106 160 154 106 160 154 106 160 154 106 151 147 98 125 122 87 | ||
| 2383 | 82 81 62 61 61 53 12 12 9 3 3 3 3 3 3 2 2 2 | ||
| 2384 | 2 2 2 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 | ||
| 2385 | 0 0 0 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2386 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2387 | 1 1 1 1 1 1 1 2 2 1 2 2 1 2 2 1 2 2 | ||
| 2388 | 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2389 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2390 | 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 | ||
| 2391 | 2 3 3 30 32 31 72 73 67 31 33 31 36 38 35 82 81 62 | ||
| 2392 | 118 116 76 149 143 98 161 156 96 161 156 96 161 156 96 160 154 106 | ||
| 2393 | 165 161 109 165 161 109 176 171 126 188 184 146 204 201 155 214 212 158 | ||
| 2394 | 239 239 170 239 239 170 214 212 158 184 179 149 82 81 62 0 0 0 | ||
| 2395 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 2405 | 2 2 2 43 44 41 96 95 69 131 127 93 160 154 106 176 171 126 | ||
| 2406 | 184 181 136 184 181 136 184 181 136 181 176 137 178 174 128 174 170 121 | ||
| 2407 | 171 165 117 173 167 111 173 167 111 173 167 111 160 154 106 131 127 93 | ||
| 2408 | 96 95 69 66 65 55 16 17 12 2 2 2 1 1 1 1 1 1 | ||
| 2409 | 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 2413 | 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 | ||
| 2414 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2415 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2416 | 2 2 2 2 2 2 2 2 2 10 9 6 30 31 28 71 71 57 | ||
| 2417 | 118 116 76 149 143 98 165 161 109 165 161 109 165 161 109 173 167 111 | ||
| 2418 | 173 167 111 176 171 126 184 181 136 197 193 154 210 208 158 224 223 159 | ||
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| 2431 | 176 171 126 184 181 136 184 181 136 188 184 146 184 181 136 184 181 136 | ||
| 2432 | 184 181 136 186 182 128 186 182 128 178 174 128 174 170 121 149 145 103 | ||
| 2433 | 118 116 76 82 81 62 21 22 20 1 1 1 1 1 1 0 0 0 | ||
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| 2437 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2438 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 | ||
| 2439 | 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 | ||
| 2440 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
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| 2442 | 118 116 76 149 143 98 165 161 109 173 167 111 173 167 111 174 170 121 | ||
| 2443 | 186 182 128 190 186 136 197 193 154 210 208 158 224 223 159 251 251 187 | ||
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| 2464 | 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2 | ||
| 2465 | 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 | ||
| 2466 | 1 2 2 1 2 2 1 2 2 1 2 2 30 31 28 71 71 57 | ||
| 2467 | 118 116 76 160 154 106 173 167 111 178 174 128 186 182 128 190 186 136 | ||
| 2468 | 194 191 148 204 201 155 210 208 158 224 223 159 251 251 187 251 251 187 | ||
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| 1853 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 | ||
| 1854 | 255 255 255 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 | ||
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| 1888 | 85 85 85 170 85 0 85 255 85 170 85 0 170 170 170 85 85 85 | ||
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| 1891 | 85 85 85 85 85 85 170 85 0 0 0 0 85 85 85 85 85 85 | ||
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| 1895 | 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 | ||
| 1896 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 | ||
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| 1901 | 255 255 255 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 1911 | 85 85 85 0 0 0 85 85 85 85 85 85 85 85 85 0 0 0 | ||
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| 1915 | 170 85 0 85 255 85 85 85 85 85 85 85 85 85 85 170 85 0 | ||
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| 1936 | 85 85 85 85 85 85 85 255 85 255 85 85 170 170 170 170 170 170 | ||
| 1937 | 170 170 170 85 255 85 170 170 170 170 85 0 170 170 170 170 85 0 | ||
| 1938 | 170 170 170 85 85 85 85 255 85 170 85 0 170 170 170 170 85 0 | ||
| 1939 | 170 170 170 170 170 170 170 85 0 85 85 85 85 85 85 85 255 85 | ||
| 1940 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 1943 | 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 | ||
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| 1949 | 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 | ||
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| 1951 | 85 255 85 255 85 85 170 170 170 170 85 0 170 170 170 85 255 85 | ||
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| 1961 | 170 170 170 255 85 85 170 170 170 170 170 170 255 255 85 170 170 170 | ||
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| 2009 | 170 170 170 255 255 255 255 255 85 170 170 170 255 255 85 170 170 170 | ||
| 2010 | 255 255 85 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 | ||
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| 2012 | 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 | ||
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| 2020 | 0 0 0 0 0 0 85 85 85 85 85 85 170 85 0 85 85 85 | ||
| 2021 | 85 85 85 255 255 85 170 170 170 170 170 170 170 170 170 170 170 170 | ||
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| 2474 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2475 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2476 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2477 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2478 | 85 85 85 85 85 85 85 85 85 170 85 0 170 170 170 170 170 170 | ||
| 2479 | 255 255 85 170 170 170 255 255 255 255 255 85 255 255 255 255 255 255 | ||
| 2480 | 170 170 170 255 255 85 170 170 170 85 85 85 0 0 0 0 0 0 | ||
| 2481 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2482 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2483 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2484 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2485 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2486 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2487 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2488 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 | ||
| 2489 | 170 170 170 170 170 170 170 170 170 255 255 255 170 170 170 255 255 255 | ||
| 2490 | 170 170 170 255 255 255 170 170 170 255 255 255 255 255 85 255 255 255 | ||
| 2491 | 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2492 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2493 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2494 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2496 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2497 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2498 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2499 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2500 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2501 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2502 | 85 85 85 170 85 0 85 85 85 170 170 170 170 170 170 170 170 170 | ||
| 2503 | 170 170 170 255 255 255 170 170 170 255 255 255 255 255 255 170 170 170 | ||
| 2504 | 255 255 85 170 170 170 170 170 170 170 85 0 85 85 85 0 0 0 | ||
| 2505 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2506 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2507 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2508 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2509 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2510 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2511 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2512 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 | ||
| 2513 | 255 255 85 170 170 170 255 255 85 170 170 170 255 255 255 255 255 255 | ||
| 2514 | 255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170 | ||
| 2515 | 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2516 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2517 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2518 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2520 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2521 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2522 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2523 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2524 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2525 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2526 | 0 0 0 85 85 85 85 85 85 85 85 85 170 85 0 170 170 170 | ||
| 2527 | 255 255 85 170 170 170 255 255 85 255 255 255 170 170 170 255 255 255 | ||
| 2528 | 170 170 170 170 170 170 170 170 170 170 170 170 0 0 0 0 0 0 | ||
| 2529 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2530 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2531 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2532 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2534 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2535 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2536 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 | ||
| 2537 | 170 85 0 170 170 170 255 255 255 170 170 170 255 255 255 170 170 170 | ||
| 2538 | 255 255 255 255 255 255 170 170 170 255 255 255 255 255 85 170 170 170 | ||
| 2539 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2540 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2541 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2542 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2544 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2545 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2546 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2547 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2548 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2549 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2550 | 0 0 0 0 0 0 85 85 85 170 85 0 85 85 85 170 170 170 | ||
| 2551 | 170 170 170 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170 | ||
| 2552 | 255 255 85 170 170 170 170 85 0 85 255 85 85 85 85 0 0 0 | ||
| 2553 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2554 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2555 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2556 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2557 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2558 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2559 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2560 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 | ||
| 2561 | 170 170 170 170 170 170 255 255 85 170 170 170 255 255 255 255 255 255 | ||
| 2562 | 255 255 85 255 255 255 170 170 170 255 255 255 170 170 170 85 85 85 | ||
| 2563 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2564 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2565 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2566 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2567 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2568 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2569 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2570 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2571 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2572 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2573 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2574 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 | ||
| 2575 | 170 85 0 170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 | ||
| 2576 | 170 170 170 170 170 170 170 170 170 170 85 0 0 0 0 0 0 0 | ||
| 2577 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2578 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2579 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2580 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2581 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2582 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2583 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2584 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 | ||
| 2585 | 255 255 85 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170 | ||
| 2586 | 255 255 255 170 170 170 255 255 85 170 170 170 85 85 85 85 85 85 | ||
| 2587 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2588 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2589 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2590 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2591 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2592 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2593 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2594 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2595 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2596 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2597 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2598 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 | ||
| 2599 | 85 85 85 170 85 0 170 170 170 170 170 170 170 170 170 170 170 170 | ||
| 2600 | 170 85 0 170 170 170 170 85 0 85 85 85 0 0 0 0 0 0 | ||
| 2601 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2602 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2603 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2604 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2605 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2606 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2607 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2608 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 | ||
| 2609 | 170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 | ||
| 2610 | 170 170 170 255 255 255 170 170 170 170 170 170 85 85 85 0 0 0 | ||
| 2611 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2612 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2613 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2614 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2615 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2616 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2617 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2618 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2619 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2620 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2621 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2622 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2623 | 85 85 85 85 85 85 85 85 85 170 85 0 85 85 85 170 85 0 | ||
| 2624 | 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 2625 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2626 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2627 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2628 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2629 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2630 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2631 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2632 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170 85 0 | ||
| 2633 | 85 85 85 170 85 0 170 170 170 170 170 170 170 170 170 255 255 85 | ||
| 2634 | 170 170 170 170 170 170 170 85 0 85 85 85 0 0 0 0 0 0 | ||
| 2635 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2636 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2637 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2638 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2639 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2640 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2641 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2642 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2643 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2644 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2645 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2646 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2647 | 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 | ||
| 2648 | 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2649 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2650 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2651 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2652 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2654 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2655 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2656 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 2657 | 85 85 85 85 255 85 170 85 0 170 170 170 170 85 0 170 170 170 | ||
| 2658 | 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 2659 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2660 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2661 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2662 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2663 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2664 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2665 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2666 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2667 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2668 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2669 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2670 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2671 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2672 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2673 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2674 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2675 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2676 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2677 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2678 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2679 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2680 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2681 | 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 | ||
| 2682 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2683 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2684 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2685 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2686 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2687 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2688 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2690 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2691 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2692 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2693 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2694 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2695 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2696 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2697 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2698 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2699 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2700 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2701 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2702 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2703 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2704 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2705 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2706 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2707 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2708 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2709 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2710 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2711 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2712 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2713 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2714 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2715 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2716 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2717 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2718 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2719 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2720 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2721 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2722 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2723 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2724 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2725 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2726 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2727 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2728 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2729 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2730 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2731 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2732 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2733 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2734 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2735 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2736 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2737 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2738 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2739 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
diff --git a/fs/proc/base.c b/fs/proc/base.c index 0c9de19a1633..beaa0ce3b82e 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c | |||
| @@ -3066,7 +3066,6 @@ static int proc_task_readdir(struct file * filp, void * dirent, filldir_t filldi | |||
| 3066 | int retval = -ENOENT; | 3066 | int retval = -ENOENT; |
| 3067 | ino_t ino; | 3067 | ino_t ino; |
| 3068 | int tid; | 3068 | int tid; |
| 3069 | unsigned long pos = filp->f_pos; /* avoiding "long long" filp->f_pos */ | ||
| 3070 | struct pid_namespace *ns; | 3069 | struct pid_namespace *ns; |
| 3071 | 3070 | ||
| 3072 | task = get_proc_task(inode); | 3071 | task = get_proc_task(inode); |
| @@ -3083,18 +3082,18 @@ static int proc_task_readdir(struct file * filp, void * dirent, filldir_t filldi | |||
| 3083 | goto out_no_task; | 3082 | goto out_no_task; |
| 3084 | retval = 0; | 3083 | retval = 0; |
| 3085 | 3084 | ||
| 3086 | switch (pos) { | 3085 | switch ((unsigned long)filp->f_pos) { |
| 3087 | case 0: | 3086 | case 0: |
| 3088 | ino = inode->i_ino; | 3087 | ino = inode->i_ino; |
| 3089 | if (filldir(dirent, ".", 1, pos, ino, DT_DIR) < 0) | 3088 | if (filldir(dirent, ".", 1, filp->f_pos, ino, DT_DIR) < 0) |
| 3090 | goto out; | 3089 | goto out; |
| 3091 | pos++; | 3090 | filp->f_pos++; |
| 3092 | /* fall through */ | 3091 | /* fall through */ |
| 3093 | case 1: | 3092 | case 1: |
| 3094 | ino = parent_ino(dentry); | 3093 | ino = parent_ino(dentry); |
| 3095 | if (filldir(dirent, "..", 2, pos, ino, DT_DIR) < 0) | 3094 | if (filldir(dirent, "..", 2, filp->f_pos, ino, DT_DIR) < 0) |
| 3096 | goto out; | 3095 | goto out; |
| 3097 | pos++; | 3096 | filp->f_pos++; |
| 3098 | /* fall through */ | 3097 | /* fall through */ |
| 3099 | } | 3098 | } |
| 3100 | 3099 | ||
| @@ -3104,9 +3103,9 @@ static int proc_task_readdir(struct file * filp, void * dirent, filldir_t filldi | |||
| 3104 | ns = filp->f_dentry->d_sb->s_fs_info; | 3103 | ns = filp->f_dentry->d_sb->s_fs_info; |
| 3105 | tid = (int)filp->f_version; | 3104 | tid = (int)filp->f_version; |
| 3106 | filp->f_version = 0; | 3105 | filp->f_version = 0; |
| 3107 | for (task = first_tid(leader, tid, pos - 2, ns); | 3106 | for (task = first_tid(leader, tid, filp->f_pos - 2, ns); |
| 3108 | task; | 3107 | task; |
| 3109 | task = next_tid(task), pos++) { | 3108 | task = next_tid(task), filp->f_pos++) { |
| 3110 | tid = task_pid_nr_ns(task, ns); | 3109 | tid = task_pid_nr_ns(task, ns); |
| 3111 | if (proc_task_fill_cache(filp, dirent, filldir, task, tid) < 0) { | 3110 | if (proc_task_fill_cache(filp, dirent, filldir, task, tid) < 0) { |
| 3112 | /* returning this tgid failed, save it as the first | 3111 | /* returning this tgid failed, save it as the first |
| @@ -3117,7 +3116,6 @@ static int proc_task_readdir(struct file * filp, void * dirent, filldir_t filldi | |||
| 3117 | } | 3116 | } |
| 3118 | } | 3117 | } |
| 3119 | out: | 3118 | out: |
| 3120 | filp->f_pos = pos; | ||
| 3121 | put_task_struct(leader); | 3119 | put_task_struct(leader); |
| 3122 | out_no_task: | 3120 | out_no_task: |
| 3123 | return retval; | 3121 | return retval; |
diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index da944eca2ca6..9c8309ed35cf 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c | |||
| @@ -1192,6 +1192,9 @@ module_init(inet6_init); | |||
| 1192 | 1192 | ||
| 1193 | static void __exit inet6_exit(void) | 1193 | static void __exit inet6_exit(void) |
| 1194 | { | 1194 | { |
| 1195 | if (disable_ipv6) | ||
| 1196 | return; | ||
| 1197 | |||
| 1195 | /* First of all disallow new sockets creation. */ | 1198 | /* First of all disallow new sockets creation. */ |
| 1196 | sock_unregister(PF_INET6); | 1199 | sock_unregister(PF_INET6); |
| 1197 | /* Disallow any further netlink messages */ | 1200 | /* Disallow any further netlink messages */ |
diff --git a/net/xfrm/xfrm_state.c b/net/xfrm/xfrm_state.c index e25ff62ab2a6..62a5425cc6aa 100644 --- a/net/xfrm/xfrm_state.c +++ b/net/xfrm/xfrm_state.c | |||
| @@ -748,12 +748,51 @@ static void xfrm_hash_grow_check(struct net *net, int have_hash_collision) | |||
| 748 | schedule_work(&net->xfrm.state_hash_work); | 748 | schedule_work(&net->xfrm.state_hash_work); |
| 749 | } | 749 | } |
| 750 | 750 | ||
| 751 | static void xfrm_state_look_at(struct xfrm_policy *pol, struct xfrm_state *x, | ||
| 752 | struct flowi *fl, unsigned short family, | ||
| 753 | xfrm_address_t *daddr, xfrm_address_t *saddr, | ||
| 754 | struct xfrm_state **best, int *acq_in_progress, | ||
| 755 | int *error) | ||
| 756 | { | ||
| 757 | /* Resolution logic: | ||
| 758 | * 1. There is a valid state with matching selector. Done. | ||
| 759 | * 2. Valid state with inappropriate selector. Skip. | ||
| 760 | * | ||
| 761 | * Entering area of "sysdeps". | ||
| 762 | * | ||
| 763 | * 3. If state is not valid, selector is temporary, it selects | ||
| 764 | * only session which triggered previous resolution. Key | ||
| 765 | * manager will do something to install a state with proper | ||
| 766 | * selector. | ||
| 767 | */ | ||
| 768 | if (x->km.state == XFRM_STATE_VALID) { | ||
| 769 | if ((x->sel.family && | ||
| 770 | !xfrm_selector_match(&x->sel, fl, x->sel.family)) || | ||
| 771 | !security_xfrm_state_pol_flow_match(x, pol, fl)) | ||
| 772 | return; | ||
| 773 | |||
| 774 | if (!*best || | ||
| 775 | (*best)->km.dying > x->km.dying || | ||
| 776 | ((*best)->km.dying == x->km.dying && | ||
| 777 | (*best)->curlft.add_time < x->curlft.add_time)) | ||
| 778 | *best = x; | ||
| 779 | } else if (x->km.state == XFRM_STATE_ACQ) { | ||
| 780 | *acq_in_progress = 1; | ||
| 781 | } else if (x->km.state == XFRM_STATE_ERROR || | ||
| 782 | x->km.state == XFRM_STATE_EXPIRED) { | ||
| 783 | if (xfrm_selector_match(&x->sel, fl, x->sel.family) && | ||
| 784 | security_xfrm_state_pol_flow_match(x, pol, fl)) | ||
| 785 | *error = -ESRCH; | ||
| 786 | } | ||
| 787 | } | ||
| 788 | |||
| 751 | struct xfrm_state * | 789 | struct xfrm_state * |
| 752 | xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr, | 790 | xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr, |
| 753 | struct flowi *fl, struct xfrm_tmpl *tmpl, | 791 | struct flowi *fl, struct xfrm_tmpl *tmpl, |
| 754 | struct xfrm_policy *pol, int *err, | 792 | struct xfrm_policy *pol, int *err, |
| 755 | unsigned short family) | 793 | unsigned short family) |
| 756 | { | 794 | { |
| 795 | static xfrm_address_t saddr_wildcard = { }; | ||
| 757 | struct net *net = xp_net(pol); | 796 | struct net *net = xp_net(pol); |
| 758 | unsigned int h; | 797 | unsigned int h; |
| 759 | struct hlist_node *entry; | 798 | struct hlist_node *entry; |
| @@ -773,40 +812,27 @@ xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr, | |||
| 773 | xfrm_state_addr_check(x, daddr, saddr, family) && | 812 | xfrm_state_addr_check(x, daddr, saddr, family) && |
| 774 | tmpl->mode == x->props.mode && | 813 | tmpl->mode == x->props.mode && |
| 775 | tmpl->id.proto == x->id.proto && | 814 | tmpl->id.proto == x->id.proto && |
| 776 | (tmpl->id.spi == x->id.spi || !tmpl->id.spi)) { | 815 | (tmpl->id.spi == x->id.spi || !tmpl->id.spi)) |
| 777 | /* Resolution logic: | 816 | xfrm_state_look_at(pol, x, fl, family, daddr, saddr, |
| 778 | 1. There is a valid state with matching selector. | 817 | &best, &acquire_in_progress, &error); |
| 779 | Done. | 818 | } |
| 780 | 2. Valid state with inappropriate selector. Skip. | 819 | if (best) |
| 781 | 820 | goto found; | |
| 782 | Entering area of "sysdeps". | 821 | |
| 783 | 822 | h = xfrm_dst_hash(net, daddr, &saddr_wildcard, tmpl->reqid, family); | |
| 784 | 3. If state is not valid, selector is temporary, | 823 | hlist_for_each_entry(x, entry, net->xfrm.state_bydst+h, bydst) { |
| 785 | it selects only session which triggered | 824 | if (x->props.family == family && |
| 786 | previous resolution. Key manager will do | 825 | x->props.reqid == tmpl->reqid && |
| 787 | something to install a state with proper | 826 | !(x->props.flags & XFRM_STATE_WILDRECV) && |
| 788 | selector. | 827 | xfrm_state_addr_check(x, daddr, saddr, family) && |
| 789 | */ | 828 | tmpl->mode == x->props.mode && |
| 790 | if (x->km.state == XFRM_STATE_VALID) { | 829 | tmpl->id.proto == x->id.proto && |
| 791 | if ((x->sel.family && !xfrm_selector_match(&x->sel, fl, x->sel.family)) || | 830 | (tmpl->id.spi == x->id.spi || !tmpl->id.spi)) |
| 792 | !security_xfrm_state_pol_flow_match(x, pol, fl)) | 831 | xfrm_state_look_at(pol, x, fl, family, daddr, saddr, |
| 793 | continue; | 832 | &best, &acquire_in_progress, &error); |
| 794 | if (!best || | ||
| 795 | best->km.dying > x->km.dying || | ||
| 796 | (best->km.dying == x->km.dying && | ||
| 797 | best->curlft.add_time < x->curlft.add_time)) | ||
| 798 | best = x; | ||
| 799 | } else if (x->km.state == XFRM_STATE_ACQ) { | ||
| 800 | acquire_in_progress = 1; | ||
| 801 | } else if (x->km.state == XFRM_STATE_ERROR || | ||
| 802 | x->km.state == XFRM_STATE_EXPIRED) { | ||
| 803 | if (xfrm_selector_match(&x->sel, fl, x->sel.family) && | ||
| 804 | security_xfrm_state_pol_flow_match(x, pol, fl)) | ||
| 805 | error = -ESRCH; | ||
| 806 | } | ||
| 807 | } | ||
| 808 | } | 833 | } |
| 809 | 834 | ||
| 835 | found: | ||
| 810 | x = best; | 836 | x = best; |
| 811 | if (!x && !error && !acquire_in_progress) { | 837 | if (!x && !error && !acquire_in_progress) { |
| 812 | if (tmpl->id.spi && | 838 | if (tmpl->id.spi && |
