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authorAlexander Duyck <alexander.h.duyck@intel.com>2008-08-26 07:25:05 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-08-27 05:16:30 -0400
commitfe59de38c58d3eedc025be61ff3055a41776bbd4 (patch)
tree058932d84ae9e88ba4f4a2f184222278c5cdcb99
parent7a6ea550f2f7592742ac765e5a3b4b5d1461e0bd (diff)
igb: ethtool -d reads EICR which is incorrect as it is read on clear
Ethtool -d is reading the EICR and ICR registers which is currently clearing these registers and masking off interrupts. To prevent this we read the EICS and ICS equivilents as they can be read without clearing or masking. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
-rw-r--r--drivers/net/igb/igb_ethtool.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/net/igb/igb_ethtool.c b/drivers/net/igb/igb_ethtool.c
index 11aee1309951..3eb78a66f8b6 100644
--- a/drivers/net/igb/igb_ethtool.c
+++ b/drivers/net/igb/igb_ethtool.c
@@ -373,13 +373,17 @@ static void igb_get_regs(struct net_device *netdev,
373 regs_buff[12] = rd32(E1000_EECD); 373 regs_buff[12] = rd32(E1000_EECD);
374 374
375 /* Interrupt */ 375 /* Interrupt */
376 regs_buff[13] = rd32(E1000_EICR); 376 /* Reading EICS for EICR because they read the
377 * same but EICS does not clear on read */
378 regs_buff[13] = rd32(E1000_EICS);
377 regs_buff[14] = rd32(E1000_EICS); 379 regs_buff[14] = rd32(E1000_EICS);
378 regs_buff[15] = rd32(E1000_EIMS); 380 regs_buff[15] = rd32(E1000_EIMS);
379 regs_buff[16] = rd32(E1000_EIMC); 381 regs_buff[16] = rd32(E1000_EIMC);
380 regs_buff[17] = rd32(E1000_EIAC); 382 regs_buff[17] = rd32(E1000_EIAC);
381 regs_buff[18] = rd32(E1000_EIAM); 383 regs_buff[18] = rd32(E1000_EIAM);
382 regs_buff[19] = rd32(E1000_ICR); 384 /* Reading ICS for ICR because they read the
385 * same but ICS does not clear on read */
386 regs_buff[19] = rd32(E1000_ICS);
383 regs_buff[20] = rd32(E1000_ICS); 387 regs_buff[20] = rd32(E1000_ICS);
384 regs_buff[21] = rd32(E1000_IMS); 388 regs_buff[21] = rd32(E1000_IMS);
385 regs_buff[22] = rd32(E1000_IMC); 389 regs_buff[22] = rd32(E1000_IMC);