Blackfin: fix detection of cached L2 SRAM

Make sure our bfin_addr_dcachable() function flags cached L2 SRAM properly
else memory easily goes unflushed when working with DMA.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

1 files changed, 5 insertions, 0 deletions

diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index d7726ab486ff..94697f0f6f40 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -108,6 +108,11 @@ static inline int bfin_addr_dcachable(unsigned long addr)
                 addr >= _ramend && addr < physical_mem_end)
                 return 1;
 
+#ifndef CONFIG_BFIN_L2_NOT_CACHED
+        if (addr >= L2_START && addr < L2_START + L2_LENGTH)
+                return 1;
+#endif
+
         return 0;
 }