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authorPaul Walmsley <paul@pwsan.com>2009-12-08 18:21:29 -0500
committerpaul <paul@twilight.(none)>2009-12-11 18:16:00 -0500
commitd8a944582da1a4d29a1487ff7f435643505a12a0 (patch)
tree1e1d946c578c4d5108c86f24f932f55da936ee5d
parent82e9bd588563c4e22ebb55b684ebec7e310cc715 (diff)
OMAP2 clock: convert clock24xx.h to clock2xxx_data.c, opp2xxx*
The OMAP2 clock code currently #includes a large .h file full of static data structures. Instead, define the data in a .c file. Russell King <linux@arm.linux.org.uk> proposed this new arrangement: http://marc.info/?l=linux-omap&m=125967425908895&w=2 This patch also deals with most of the flagrant checkpatch violations. While here, separate the prcm_config data structures out into their own files, opp2xxx.h and opp24{2,3}0_data.c, and only build in the OPP tables for the target device. This should save some memory. In the long run, these prcm_config tables should be replaced with OPP code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Nishanth Menon <nm@ti.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/clock.h30
-rw-r--r--arch/arm/mach-omap2/clock2xxx.c (renamed from arch/arm/mach-omap2/clock24xx.c)331
-rw-r--r--arch/arm/mach-omap2/clock2xxx.h41
-rw-r--r--arch/arm/mach-omap2/clock2xxx_data.c (renamed from arch/arm/mach-omap2/clock24xx.h)832
-rw-r--r--arch/arm/mach-omap2/opp2420_data.c126
-rw-r--r--arch/arm/mach-omap2/opp2430_data.c133
-rw-r--r--arch/arm/mach-omap2/opp2xxx.h424
-rw-r--r--arch/arm/mach-omap2/sdrc.h3
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
10 files changed, 1044 insertions, 884 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index cc56accee3ef..610da0515e1f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -7,7 +7,7 @@ obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
7 7
8omap-2-3-common = irq.o sdrc.o omap_hwmod.o 8omap-2-3-common = irq.o sdrc.o omap_hwmod.o
9prcm-common = prcm.o powerdomain.o 9prcm-common = prcm.o powerdomain.o
10clock-common = clock.o clockdomain.o 10clock-common = clock.o clock_common_data.o clockdomain.o
11 11
12obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) 12obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
13obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) 13obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common)
@@ -41,8 +41,10 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o
41obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o 41obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
42 42
43# Clock framework 43# Clock framework
44obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o 44obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o
45obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o
45obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o 46obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o
47obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
46 48
47# EMU peripherals 49# EMU peripherals
48obj-$(CONFIG_OMAP3_EMU) += emu.o 50obj-$(CONFIG_OMAP3_EMU) += emu.o
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b1991e39961a..87c08056b303 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/clock.h 2 * linux/arch/arm/mach-omap2/clock.h
3 * 3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation 5 * Copyright (C) 2004-2009 Nokia Corporation
6 * 6 *
7 * Contacts: 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
@@ -72,31 +72,17 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
72void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 72void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
73 u8 *idlest_bit); 73 u8 *idlest_bit);
74 74
75extern u8 cpu_mask;
76
75extern const struct clkops clkops_omap2_dflt_wait; 77extern const struct clkops clkops_omap2_dflt_wait;
76extern const struct clkops clkops_omap2_dflt; 78extern const struct clkops clkops_omap2_dflt;
77 79
78extern u8 cpu_mask;
79
80extern struct clk_functions omap2_clk_functions; 80extern struct clk_functions omap2_clk_functions;
81extern struct clk *vclk, *sclk;
81 82
82/* clksel_rate data common to 24xx/343x */ 83extern const struct clksel_rate gpt_32k_rates[];
83static const struct clksel_rate gpt_32k_rates[] = { 84extern const struct clksel_rate gpt_sys_rates[];
84 { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, 85extern const struct clksel_rate gfx_l3_rates[];
85 { .div = 0 }
86};
87
88static const struct clksel_rate gpt_sys_rates[] = {
89 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
90 { .div = 0 }
91};
92
93static const struct clksel_rate gfx_l3_rates[] = {
94 { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
95 { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
96 { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
97 { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
98 { .div = 0 }
99};
100 86
101 87
102#endif 88#endif
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock2xxx.c
index a4221741808e..d0e3fb7f9298 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock2xxx.c
@@ -37,183 +37,13 @@
37 37
38#include <plat/sdrc.h> 38#include <plat/sdrc.h>
39#include "clock.h" 39#include "clock.h"
40#include "clock2xxx.h"
41#include "opp2xxx.h"
40#include "prm.h" 42#include "prm.h"
41#include "prm-regbits-24xx.h" 43#include "prm-regbits-24xx.h"
42#include "cm.h" 44#include "cm.h"
43#include "cm-regbits-24xx.h" 45#include "cm-regbits-24xx.h"
44 46
45static const struct clkops clkops_oscck;
46static const struct clkops clkops_apll96;
47static const struct clkops clkops_apll54;
48
49static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
50 void __iomem **idlest_reg,
51 u8 *idlest_bit);
52
53/* 2430 I2CHS has non-standard IDLEST register */
54static const struct clkops clkops_omap2430_i2chs_wait = {
55 .enable = omap2_dflt_clk_enable,
56 .disable = omap2_dflt_clk_disable,
57 .find_idlest = omap2430_clk_i2chs_find_idlest,
58 .find_companion = omap2_clk_dflt_find_companion,
59};
60
61#include "clock24xx.h"
62
63static struct omap_clk omap24xx_clks[] = {
64 /* external root sources */
65 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
66 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
67 CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
68 CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
69 CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
70 /* internal analog sources */
71 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
72 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
73 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
74 /* internal prcm root sources */
75 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
76 CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
77 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
78 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
79 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
80 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
81 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
82 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
83 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
84 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
85 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
86 /* mpu domain clocks */
87 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
88 /* dsp domain clocks */
89 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
90 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
91 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
92 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
93 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
94 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
95 /* GFX domain clocks */
96 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
97 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
98 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
99 /* Modem domain clocks */
100 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
101 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
102 /* DSS domain clocks */
103 CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X),
104 CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
105 CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
106 CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
107 /* L3 domain clocks */
108 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
109 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
110 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
111 /* L4 domain clocks */
112 CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
113 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
114 /* virtual meta-group clock */
115 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
116 /* general l4 interface ck, multi-parent functional clk */
117 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
118 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
119 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
120 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
121 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
122 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
123 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
124 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
125 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
126 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
127 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
128 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
129 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
130 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
131 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
132 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
133 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
134 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
135 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
136 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
137 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
138 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
139 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
140 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
141 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
142 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
143 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
144 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
145 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
146 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
147 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
148 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
149 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
150 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
151 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
152 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
153 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
154 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
155 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
156 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
157 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
158 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
159 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
160 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
161 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
162 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
163 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
164 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
165 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
166 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
167 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
168 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
169 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
170 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
171 CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
172 CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
173 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
174 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
175 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
176 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
177 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
178 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
179 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
180 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
181 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
182 CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
183 CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
184 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
185 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
186 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
187 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
188 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
189 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
190 CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
191 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
192 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
193 CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
194 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
195 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
196 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
197 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
198 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
199 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
200 CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
201 CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
202 CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
203 CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
204 CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
205 CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
206 CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
207 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
208 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
209 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
210 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
211 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
212 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
213 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
214 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
215 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
216};
217 47
218/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ 48/* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
219#define EN_APLL_STOPPED 0 49#define EN_APLL_STOPPED 0
@@ -226,11 +56,12 @@ static struct omap_clk omap24xx_clks[] = {
226 56
227/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ 57/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
228 58
229static struct prcm_config *curr_prcm_set; 59const struct prcm_config *curr_prcm_set;
230static struct clk *vclk; 60const struct prcm_config *rate_table;
231static struct clk *sclk; 61
62struct clk *vclk, *sclk, *dclk;
232 63
233static void __iomem *prcm_clksrc_ctrl; 64void __iomem *prcm_clksrc_ctrl;
234 65
235/*------------------------------------------------------------------------- 66/*-------------------------------------------------------------------------
236 * Omap24xx specific clock functions 67 * Omap24xx specific clock functions
@@ -255,6 +86,13 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
255 *idlest_bit = clk->enable_bit; 86 *idlest_bit = clk->enable_bit;
256} 87}
257 88
89/* 2430 I2CHS has non-standard IDLEST register */
90const struct clkops clkops_omap2430_i2chs_wait = {
91 .enable = omap2_dflt_clk_enable,
92 .disable = omap2_dflt_clk_disable,
93 .find_idlest = omap2430_clk_i2chs_find_idlest,
94 .find_companion = omap2_clk_dflt_find_companion,
95};
258 96
259/** 97/**
260 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate 98 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
@@ -266,7 +104,7 @@ static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
266 * struct clk *dpll_ck, which is a composite clock of dpll_ck and 104 * struct clk *dpll_ck, which is a composite clock of dpll_ck and
267 * core_ck. 105 * core_ck.
268 */ 106 */
269static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) 107unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
270{ 108{
271 long long core_clk; 109 long long core_clk;
272 u32 v; 110 u32 v;
@@ -304,14 +142,14 @@ static void omap2_disable_osc_ck(struct clk *clk)
304 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); 142 __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
305} 143}
306 144
307static const struct clkops clkops_oscck = { 145const struct clkops clkops_oscck = {
308 .enable = &omap2_enable_osc_ck, 146 .enable = omap2_enable_osc_ck,
309 .disable = &omap2_disable_osc_ck, 147 .disable = omap2_disable_osc_ck,
310}; 148};
311 149
312#ifdef OLD_CK 150#ifdef OLD_CK
313/* Recalculate SYST_CLK */ 151/* Recalculate SYST_CLK */
314static void omap2_sys_clk_recalc(struct clk * clk) 152static void omap2_sys_clk_recalc(struct clk *clk)
315{ 153{
316 u32 div = PRCM_CLKSRC_CTRL; 154 u32 div = PRCM_CLKSRC_CTRL;
317 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ 155 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */
@@ -367,21 +205,21 @@ static void omap2_clk_apll_disable(struct clk *clk)
367 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); 205 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
368} 206}
369 207
370static const struct clkops clkops_apll96 = { 208const struct clkops clkops_apll96 = {
371 .enable = &omap2_clk_apll96_enable, 209 .enable = omap2_clk_apll96_enable,
372 .disable = &omap2_clk_apll_disable, 210 .disable = omap2_clk_apll_disable,
373}; 211};
374 212
375static const struct clkops clkops_apll54 = { 213const struct clkops clkops_apll54 = {
376 .enable = &omap2_clk_apll54_enable, 214 .enable = omap2_clk_apll54_enable,
377 .disable = &omap2_clk_apll_disable, 215 .disable = omap2_clk_apll_disable,
378}; 216};
379 217
380/* 218/*
381 * Uses the current prcm set to tell if a rate is valid. 219 * Uses the current prcm set to tell if a rate is valid.
382 * You can go slower, but not faster within a given rate set. 220 * You can go slower, but not faster within a given rate set.
383 */ 221 */
384static long omap2_dpllcore_round_rate(unsigned long target_rate) 222long omap2_dpllcore_round_rate(unsigned long target_rate)
385{ 223{
386 u32 high, low, core_clk_src; 224 u32 high, low, core_clk_src;
387 225
@@ -410,19 +248,19 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
410 248
411} 249}
412 250
413static unsigned long omap2_dpllcore_recalc(struct clk *clk) 251unsigned long omap2_dpllcore_recalc(struct clk *clk)
414{ 252{
415 return omap2xxx_clk_get_core_rate(clk); 253 return omap2xxx_clk_get_core_rate(clk);
416} 254}
417 255
418static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 256int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
419{ 257{
420 u32 cur_rate, low, mult, div, valid_rate, done_rate; 258 u32 cur_rate, low, mult, div, valid_rate, done_rate;
421 u32 bypass = 0; 259 u32 bypass = 0;
422 struct prcm_config tmpset; 260 struct prcm_config tmpset;
423 const struct dpll_data *dd; 261 const struct dpll_data *dd;
424 262
425 cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); 263 cur_rate = omap2xxx_clk_get_core_rate(dclk);
426 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); 264 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
427 mult &= OMAP24XX_CORE_CLK_SRC_MASK; 265 mult &= OMAP24XX_CORE_CLK_SRC_MASK;
428 266
@@ -489,7 +327,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
489 * 327 *
490 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. 328 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
491 */ 329 */
492static unsigned long omap2_table_mpu_recalc(struct clk *clk) 330unsigned long omap2_table_mpu_recalc(struct clk *clk)
493{ 331{
494 return curr_prcm_set->mpu_speed; 332 return curr_prcm_set->mpu_speed;
495} 333}
@@ -501,17 +339,20 @@ static unsigned long omap2_table_mpu_recalc(struct clk *clk)
501 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and 339 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and
502 * just uses the ARM rates. 340 * just uses the ARM rates.
503 */ 341 */
504static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) 342long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
505{ 343{
506 struct prcm_config *ptr; 344 const struct prcm_config *ptr;
507 long highest_rate; 345 long highest_rate;
346 long sys_ck_rate;
347
348 sys_ck_rate = clk_get_rate(sclk);
508 349
509 highest_rate = -EINVAL; 350 highest_rate = -EINVAL;
510 351
511 for (ptr = rate_table; ptr->mpu_speed; ptr++) { 352 for (ptr = rate_table; ptr->mpu_speed; ptr++) {
512 if (!(ptr->flags & cpu_mask)) 353 if (!(ptr->flags & cpu_mask))
513 continue; 354 continue;
514 if (ptr->xtal_speed != sys_ck.rate) 355 if (ptr->xtal_speed != sys_ck_rate)
515 continue; 356 continue;
516 357
517 highest_rate = ptr->mpu_speed; 358 highest_rate = ptr->mpu_speed;
@@ -524,18 +365,21 @@ static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
524} 365}
525 366
526/* Sets basic clocks based on the specified rate */ 367/* Sets basic clocks based on the specified rate */
527static int omap2_select_table_rate(struct clk *clk, unsigned long rate) 368int omap2_select_table_rate(struct clk *clk, unsigned long rate)
528{ 369{
529 u32 cur_rate, done_rate, bypass = 0, tmp; 370 u32 cur_rate, done_rate, bypass = 0, tmp;
530 struct prcm_config *prcm; 371 const struct prcm_config *prcm;
531 unsigned long found_speed = 0; 372 unsigned long found_speed = 0;
532 unsigned long flags; 373 unsigned long flags;
374 long sys_ck_rate;
375
376 sys_ck_rate = clk_get_rate(sclk);
533 377
534 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 378 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
535 if (!(prcm->flags & cpu_mask)) 379 if (!(prcm->flags & cpu_mask))
536 continue; 380 continue;
537 381
538 if (prcm->xtal_speed != sys_ck.rate) 382 if (prcm->xtal_speed != sys_ck_rate)
539 continue; 383 continue;
540 384
541 if (prcm->mpu_speed <= rate) { 385 if (prcm->mpu_speed <= rate) {
@@ -551,7 +395,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
551 } 395 }
552 396
553 curr_prcm_set = prcm; 397 curr_prcm_set = prcm;
554 cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); 398 cur_rate = omap2xxx_clk_get_core_rate(dclk);
555 399
556 if (prcm->dpll_speed == cur_rate / 2) { 400 if (prcm->dpll_speed == cur_rate / 2) {
557 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); 401 omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
@@ -682,12 +526,12 @@ static u32 omap2_get_sysclkdiv(void)
682 return div; 526 return div;
683} 527}
684 528
685static unsigned long omap2_osc_clk_recalc(struct clk *clk) 529unsigned long omap2_osc_clk_recalc(struct clk *clk)
686{ 530{
687 return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); 531 return omap2_get_apll_clkin() * omap2_get_sysclkdiv();
688} 532}
689 533
690static unsigned long omap2_sys_clk_recalc(struct clk *clk) 534unsigned long omap2_sys_clk_recalc(struct clk *clk)
691{ 535{
692 return clk->parent->rate / omap2_get_sysclkdiv(); 536 return clk->parent->rate / omap2_get_sysclkdiv();
693} 537}
@@ -712,85 +556,32 @@ void omap2_clk_prepare_for_reboot(void)
712 */ 556 */
713static int __init omap2_clk_arch_init(void) 557static int __init omap2_clk_arch_init(void)
714{ 558{
559 struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck;
560 unsigned long sys_ck_rate;
561
715 if (!mpurate) 562 if (!mpurate)
716 return -EINVAL; 563 return -EINVAL;
717 564
718 if (clk_set_rate(&virt_prcm_set, mpurate)) 565 virt_prcm_set = clk_get(NULL, "virt_prcm_set");
566 sys_ck = clk_get(NULL, "sys_ck");
567 dpll_ck = clk_get(NULL, "dpll_ck");
568 mpu_ck = clk_get(NULL, "mpu_ck");
569
570 if (clk_set_rate(virt_prcm_set, mpurate))
719 printk(KERN_ERR "Could not find matching MPU rate\n"); 571 printk(KERN_ERR "Could not find matching MPU rate\n");
720 572
721 recalculate_root_clocks(); 573 recalculate_root_clocks();
722 574
723 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " 575 sys_ck_rate = clk_get_rate(sys_ck);
724 "%ld.%01ld/%ld/%ld MHz\n", 576
725 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, 577 pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): "
726 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; 578 "%ld.%01ld/%ld/%ld MHz\n",
579 (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10,
580 (clk_get_rate(dpll_ck) / 1000000),
581 (clk_get_rate(mpu_ck) / 1000000));
727 582
728 return 0; 583 return 0;
729} 584}
730arch_initcall(omap2_clk_arch_init); 585arch_initcall(omap2_clk_arch_init);
731 586
732int __init omap2_clk_init(void)
733{
734 struct prcm_config *prcm;
735 struct omap_clk *c;
736 u32 clkrate;
737 u16 cpu_clkflg;
738
739 if (cpu_is_omap242x()) {
740 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
741 cpu_mask = RATE_IN_242X;
742 cpu_clkflg = CK_242X;
743 } else if (cpu_is_omap2430()) {
744 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
745 cpu_mask = RATE_IN_243X;
746 cpu_clkflg = CK_243X;
747 }
748
749 clk_init(&omap2_clk_functions);
750 587
751 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
752 clk_preinit(c->lk.clk);
753
754 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
755 propagate_rate(&osc_ck);
756 sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
757 propagate_rate(&sys_ck);
758
759 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
760 if (c->cpu & cpu_clkflg) {
761 clkdev_add(&c->lk);
762 clk_register(c->lk.clk);
763 omap2_init_clk_clkdm(c->lk.clk);
764 }
765
766 /* Check the MPU rate set by bootloader */
767 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
768 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
769 if (!(prcm->flags & cpu_mask))
770 continue;
771 if (prcm->xtal_speed != sys_ck.rate)
772 continue;
773 if (prcm->dpll_speed <= clkrate)
774 break;
775 }
776 curr_prcm_set = prcm;
777
778 recalculate_root_clocks();
779
780 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
781 "%ld.%01ld/%ld/%ld MHz\n",
782 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
783 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
784
785 /*
786 * Only enable those clocks we will need, let the drivers
787 * enable other clocks as necessary
788 */
789 clk_enable_init_clocks();
790
791 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
792 vclk = clk_get(NULL, "virt_prcm_set");
793 sclk = clk_get(NULL, "sys_ck");
794
795 return 0;
796}
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
new file mode 100644
index 000000000000..e35efde4bd80
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -0,0 +1,41 @@
1/*
2 * OMAP2 clock function prototypes and macros
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
6 */
7
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
10
11unsigned long omap2_table_mpu_recalc(struct clk *clk);
12int omap2_select_table_rate(struct clk *clk, unsigned long rate);
13long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
14unsigned long omap2_sys_clk_recalc(struct clk *clk);
15unsigned long omap2_osc_clk_recalc(struct clk *clk);
16unsigned long omap2_sys_clk_recalc(struct clk *clk);
17unsigned long omap2_dpllcore_recalc(struct clk *clk);
18int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
19unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
20
21/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
22#ifdef CONFIG_ARCH_OMAP2420
23#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
24#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL
25#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL
26#else
27#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
28#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL
29#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL
30#endif
31
32extern void __iomem *prcm_clksrc_ctrl;
33
34extern struct clk *dclk;
35
36extern const struct clkops clkops_omap2430_i2chs_wait;
37extern const struct clkops clkops_oscck;
38extern const struct clkops clkops_apll96;
39extern const struct clkops clkops_apll54;
40
41#endif
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock2xxx_data.c
index 21238d18fc80..97dc7cf7751d 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock2xxx_data.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/clock24xx.h 2 * linux/arch/arm/mach-omap2/clock2xxx_data.c
3 * 3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation 5 * Copyright (C) 2004-2009 Nokia Corporation
6 * 6 *
7 * Contacts: 7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com>
@@ -13,600 +13,21 @@
13 * published by the Free Software Foundation. 13 * published by the Free Software Foundation.
14 */ 14 */
15 15
16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H 16#include <linux/module.h>
17#define __ARCH_ARM_MACH_OMAP2_CLOCK24XX_H 17#include <linux/kernel.h>
18#include <linux/clk.h>
18 19
19#include "clock.h" 20#include <plat/clkdev_omap.h>
20 21
22#include "clock.h"
23#include "clock2xxx.h"
24#include "opp2xxx.h"
21#include "prm.h" 25#include "prm.h"
22#include "cm.h" 26#include "cm.h"
23#include "prm-regbits-24xx.h" 27#include "prm-regbits-24xx.h"
24#include "cm-regbits-24xx.h" 28#include "cm-regbits-24xx.h"
25#include "sdrc.h" 29#include "sdrc.h"
26 30
27/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
28#ifdef CONFIG_ARCH_OMAP2420
29#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
30#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL
31#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL
32#else
33#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
34#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL
35#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL
36#endif
37
38static unsigned long omap2_table_mpu_recalc(struct clk *clk);
39static int omap2_select_table_rate(struct clk *clk, unsigned long rate);
40static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
41static unsigned long omap2_sys_clk_recalc(struct clk *clk);
42static unsigned long omap2_osc_clk_recalc(struct clk *clk);
43static unsigned long omap2_sys_clk_recalc(struct clk *clk);
44static unsigned long omap2_dpllcore_recalc(struct clk *clk);
45static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
46
47/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
48 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
49 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
50 */
51struct prcm_config {
52 unsigned long xtal_speed; /* crystal rate */
53 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
54 unsigned long mpu_speed; /* speed of MPU */
55 unsigned long cm_clksel_mpu; /* mpu divider */
56 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
57 unsigned long cm_clksel_gfx; /* gfx dividers */
58 unsigned long cm_clksel1_core; /* major subsystem dividers */
59 unsigned long cm_clksel1_pll; /* m,n */
60 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
61 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
62 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
63 unsigned char flags;
64};
65
66/*
67 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
68 * These configurations are characterized by voltage and speed for clocks.
69 * The device is only validated for certain combinations. One way to express
70 * these combinations is via the 'ratio's' which the clocks operate with
71 * respect to each other. These ratio sets are for a given voltage/DPLL
72 * setting. All configurations can be described by a DPLL setting and a ratio
73 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
74 *
75 * 2430 differs from 2420 in that there are no more phase synchronizers used.
76 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
77 * 2430 (iva2.1, NOdsp, mdm)
78 */
79
80/* Core fields for cm_clksel, not ratio governed */
81#define RX_CLKSEL_DSS1 (0x10 << 8)
82#define RX_CLKSEL_DSS2 (0x0 << 13)
83#define RX_CLKSEL_SSI (0x5 << 20)
84
85/*-------------------------------------------------------------------------
86 * Voltage/DPLL ratios
87 *-------------------------------------------------------------------------*/
88
89/* 2430 Ratio's, 2430-Ratio Config 1 */
90#define R1_CLKSEL_L3 (4 << 0)
91#define R1_CLKSEL_L4 (2 << 5)
92#define R1_CLKSEL_USB (4 << 25)
93#define R1_CM_CLKSEL1_CORE_VAL R1_CLKSEL_USB | RX_CLKSEL_SSI | \
94 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
95 R1_CLKSEL_L4 | R1_CLKSEL_L3
96#define R1_CLKSEL_MPU (2 << 0)
97#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
98#define R1_CLKSEL_DSP (2 << 0)
99#define R1_CLKSEL_DSP_IF (2 << 5)
100#define R1_CM_CLKSEL_DSP_VAL R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF
101#define R1_CLKSEL_GFX (2 << 0)
102#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
103#define R1_CLKSEL_MDM (4 << 0)
104#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
105
106/* 2430-Ratio Config 2 */
107#define R2_CLKSEL_L3 (6 << 0)
108#define R2_CLKSEL_L4 (2 << 5)
109#define R2_CLKSEL_USB (2 << 25)
110#define R2_CM_CLKSEL1_CORE_VAL R2_CLKSEL_USB | RX_CLKSEL_SSI | \
111 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
112 R2_CLKSEL_L4 | R2_CLKSEL_L3
113#define R2_CLKSEL_MPU (2 << 0)
114#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
115#define R2_CLKSEL_DSP (2 << 0)
116#define R2_CLKSEL_DSP_IF (3 << 5)
117#define R2_CM_CLKSEL_DSP_VAL R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF
118#define R2_CLKSEL_GFX (2 << 0)
119#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
120#define R2_CLKSEL_MDM (6 << 0)
121#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
122
123/* 2430-Ratio Bootm (BYPASS) */
124#define RB_CLKSEL_L3 (1 << 0)
125#define RB_CLKSEL_L4 (1 << 5)
126#define RB_CLKSEL_USB (1 << 25)
127#define RB_CM_CLKSEL1_CORE_VAL RB_CLKSEL_USB | RX_CLKSEL_SSI | \
128 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
129 RB_CLKSEL_L4 | RB_CLKSEL_L3
130#define RB_CLKSEL_MPU (1 << 0)
131#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
132#define RB_CLKSEL_DSP (1 << 0)
133#define RB_CLKSEL_DSP_IF (1 << 5)
134#define RB_CM_CLKSEL_DSP_VAL RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF
135#define RB_CLKSEL_GFX (1 << 0)
136#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
137#define RB_CLKSEL_MDM (1 << 0)
138#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
139
140/* 2420 Ratio Equivalents */
141#define RXX_CLKSEL_VLYNQ (0x12 << 15)
142#define RXX_CLKSEL_SSI (0x8 << 20)
143
144/* 2420-PRCM III 532MHz core */
145#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
146#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
147#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
148#define RIII_CM_CLKSEL1_CORE_VAL RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
149 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
150 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
151 RIII_CLKSEL_L3
152#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
153#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
154#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
155#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
156#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
157#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
158#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
159#define RIII_CM_CLKSEL_DSP_VAL RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
160 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
161 RIII_CLKSEL_DSP
162#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
163#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
164
165/* 2420-PRCM II 600MHz core */
166#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
167#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
168#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
169#define RII_CM_CLKSEL1_CORE_VAL RII_CLKSEL_USB | \
170 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
171 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
172 RII_CLKSEL_L4 | RII_CLKSEL_L3
173#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
174#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
175#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
176#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
177#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
178#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
179#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
180#define RII_CM_CLKSEL_DSP_VAL RII_SYNC_IVA | RII_CLKSEL_IVA | \
181 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
182 RII_CLKSEL_DSP
183#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
184#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
185
186/* 2420-PRCM I 660MHz core */
187#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
188#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
189#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
190#define RI_CM_CLKSEL1_CORE_VAL RI_CLKSEL_USB | \
191 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
192 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
193 RI_CLKSEL_L4 | RI_CLKSEL_L3
194#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
195#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
196#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
197#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
198#define RI_SYNC_DSP (1 << 7) /* Activate sync */
199#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
200#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
201#define RI_CM_CLKSEL_DSP_VAL RI_SYNC_IVA | RI_CLKSEL_IVA | \
202 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
203 RI_CLKSEL_DSP
204#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
205#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
206
207/* 2420-PRCM VII (boot) */
208#define RVII_CLKSEL_L3 (1 << 0)
209#define RVII_CLKSEL_L4 (1 << 5)
210#define RVII_CLKSEL_DSS1 (1 << 8)
211#define RVII_CLKSEL_DSS2 (0 << 13)
212#define RVII_CLKSEL_VLYNQ (1 << 15)
213#define RVII_CLKSEL_SSI (1 << 20)
214#define RVII_CLKSEL_USB (1 << 25)
215
216#define RVII_CM_CLKSEL1_CORE_VAL RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
217 RVII_CLKSEL_VLYNQ | RVII_CLKSEL_DSS2 | \
218 RVII_CLKSEL_DSS1 | RVII_CLKSEL_L4 | RVII_CLKSEL_L3
219
220#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
221#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
222
223#define RVII_CLKSEL_DSP (1 << 0)
224#define RVII_CLKSEL_DSP_IF (1 << 5)
225#define RVII_SYNC_DSP (0 << 7)
226#define RVII_CLKSEL_IVA (1 << 8)
227#define RVII_SYNC_IVA (0 << 13)
228#define RVII_CM_CLKSEL_DSP_VAL RVII_SYNC_IVA | RVII_CLKSEL_IVA | RVII_SYNC_DSP | \
229 RVII_CLKSEL_DSP_IF | RVII_CLKSEL_DSP
230
231#define RVII_CLKSEL_GFX (1 << 0)
232#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
233
234/*-------------------------------------------------------------------------
235 * 2430 Target modes: Along with each configuration the CPU has several
236 * modes which goes along with them. Modes mainly are the addition of
237 * describe DPLL combinations to go along with a ratio.
238 *-------------------------------------------------------------------------*/
239
240/* Hardware governed */
241#define MX_48M_SRC (0 << 3)
242#define MX_54M_SRC (0 << 5)
243#define MX_APLLS_CLIKIN_12 (3 << 23)
244#define MX_APLLS_CLIKIN_13 (2 << 23)
245#define MX_APLLS_CLIKIN_19_2 (0 << 23)
246
247/*
248 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
249 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
250 */
251#define M5A_DPLL_MULT_12 (133 << 12)
252#define M5A_DPLL_DIV_12 (5 << 8)
253#define M5A_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
254 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
255 MX_APLLS_CLIKIN_12
256#define M5A_DPLL_MULT_13 (61 << 12)
257#define M5A_DPLL_DIV_13 (2 << 8)
258#define M5A_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
259 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
260 MX_APLLS_CLIKIN_13
261#define M5A_DPLL_MULT_19 (55 << 12)
262#define M5A_DPLL_DIV_19 (3 << 8)
263#define M5A_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
264 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
265 MX_APLLS_CLIKIN_19_2
266/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
267#define M5B_DPLL_MULT_12 (50 << 12)
268#define M5B_DPLL_DIV_12 (2 << 8)
269#define M5B_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
270 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
271 MX_APLLS_CLIKIN_12
272#define M5B_DPLL_MULT_13 (200 << 12)
273#define M5B_DPLL_DIV_13 (12 << 8)
274
275#define M5B_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
276 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
277 MX_APLLS_CLIKIN_13
278#define M5B_DPLL_MULT_19 (125 << 12)
279#define M5B_DPLL_DIV_19 (31 << 8)
280#define M5B_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
281 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
282 MX_APLLS_CLIKIN_19_2
283/*
284 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
285 */
286#define M4_DPLL_MULT_12 (133 << 12)
287#define M4_DPLL_DIV_12 (3 << 8)
288#define M4_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
289 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
290 MX_APLLS_CLIKIN_12
291
292#define M4_DPLL_MULT_13 (399 << 12)
293#define M4_DPLL_DIV_13 (12 << 8)
294#define M4_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
295 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
296 MX_APLLS_CLIKIN_13
297
298#define M4_DPLL_MULT_19 (145 << 12)
299#define M4_DPLL_DIV_19 (6 << 8)
300#define M4_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
301 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
302 MX_APLLS_CLIKIN_19_2
303
304/*
305 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
306 */
307#define M3_DPLL_MULT_12 (55 << 12)
308#define M3_DPLL_DIV_12 (1 << 8)
309#define M3_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
310 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
311 MX_APLLS_CLIKIN_12
312#define M3_DPLL_MULT_13 (76 << 12)
313#define M3_DPLL_DIV_13 (2 << 8)
314#define M3_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
315 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
316 MX_APLLS_CLIKIN_13
317#define M3_DPLL_MULT_19 (17 << 12)
318#define M3_DPLL_DIV_19 (0 << 8)
319#define M3_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
320 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
321 MX_APLLS_CLIKIN_19_2
322
323/*
324 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
325 */
326#define M2_DPLL_MULT_12 (55 << 12)
327#define M2_DPLL_DIV_12 (1 << 8)
328#define M2_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
329 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
330 MX_APLLS_CLIKIN_12
331
332/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
333 * relock time issue */
334/* Core frequency changed from 330/165 to 329/164 MHz*/
335#define M2_DPLL_MULT_13 (76 << 12)
336#define M2_DPLL_DIV_13 (2 << 8)
337#define M2_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
338 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
339 MX_APLLS_CLIKIN_13
340
341#define M2_DPLL_MULT_19 (17 << 12)
342#define M2_DPLL_DIV_19 (0 << 8)
343#define M2_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | \
344 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
345 MX_APLLS_CLIKIN_19_2
346
347/* boot (boot) */
348#define MB_DPLL_MULT (1 << 12)
349#define MB_DPLL_DIV (0 << 8)
350#define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
351 MB_DPLL_MULT | MX_APLLS_CLIKIN_12
352
353#define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
354 MB_DPLL_MULT | MX_APLLS_CLIKIN_13
355
356#define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
357 MB_DPLL_MULT | MX_APLLS_CLIKIN_19
358
359/*
360 * 2430 - chassis (sedna)
361 * 165 (ratio1) same as above #2
362 * 150 (ratio1)
363 * 133 (ratio2) same as above #4
364 * 110 (ratio2) same as above #3
365 * 104 (ratio2)
366 * boot (boot)
367 */
368
369/* PRCM I target DPLL = 2*330MHz = 660MHz */
370#define MI_DPLL_MULT_12 (55 << 12)
371#define MI_DPLL_DIV_12 (1 << 8)
372#define MI_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
373 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
374 MX_APLLS_CLIKIN_12
375
376/*
377 * 2420 Equivalent - mode registers
378 * PRCM II , target DPLL = 2*300MHz = 600MHz
379 */
380#define MII_DPLL_MULT_12 (50 << 12)
381#define MII_DPLL_DIV_12 (1 << 8)
382#define MII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
383 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
384 MX_APLLS_CLIKIN_12
385#define MII_DPLL_MULT_13 (300 << 12)
386#define MII_DPLL_DIV_13 (12 << 8)
387#define MII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
388 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
389 MX_APLLS_CLIKIN_13
390
391/* PRCM III target DPLL = 2*266 = 532MHz*/
392#define MIII_DPLL_MULT_12 (133 << 12)
393#define MIII_DPLL_DIV_12 (5 << 8)
394#define MIII_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | \
395 MIII_DPLL_DIV_12 | MIII_DPLL_MULT_12 | \
396 MX_APLLS_CLIKIN_12
397#define MIII_DPLL_MULT_13 (266 << 12)
398#define MIII_DPLL_DIV_13 (12 << 8)
399#define MIII_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | \
400 MIII_DPLL_DIV_13 | MIII_DPLL_MULT_13 | \
401 MX_APLLS_CLIKIN_13
402
403/* PRCM VII (boot bypass) */
404#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
405#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
406
407/* High and low operation value */
408#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
409#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
410
411/* MPU speed defines */
412#define S12M 12000000
413#define S13M 13000000
414#define S19M 19200000
415#define S26M 26000000
416#define S100M 100000000
417#define S133M 133000000
418#define S150M 150000000
419#define S164M 164000000
420#define S165M 165000000
421#define S199M 199000000
422#define S200M 200000000
423#define S266M 266000000
424#define S300M 300000000
425#define S329M 329000000
426#define S330M 330000000
427#define S399M 399000000
428#define S400M 400000000
429#define S532M 532000000
430#define S600M 600000000
431#define S658M 658000000
432#define S660M 660000000
433#define S798M 798000000
434
435/*-------------------------------------------------------------------------
436 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
437 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
438 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
439 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
440 *
441 * Filling in table based on H4 boards and 2430-SDPs variants available.
442 * There are quite a few more rates combinations which could be defined.
443 *
444 * When multiple values are defined the start up will try and choose the
445 * fastest one. If a 'fast' value is defined, then automatically, the /2
446 * one should be included as it can be used. Generally having more that
447 * one fast set does not make sense, as static timings need to be changed
448 * to change the set. The exception is the bypass setting which is
449 * availble for low power bypass.
450 *
451 * Note: This table needs to be sorted, fastest to slowest.
452 *-------------------------------------------------------------------------*/
453static struct prcm_config rate_table[] = {
454 /* PRCM I - FAST */
455 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
456 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
457 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
458 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
459 RATE_IN_242X},
460
461 /* PRCM II - FAST */
462 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
463 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
464 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
465 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
466 RATE_IN_242X},
467
468 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
469 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
470 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
471 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
472 RATE_IN_242X},
473
474 /* PRCM III - FAST */
475 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
476 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
477 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
478 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
479 RATE_IN_242X},
480
481 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
482 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
483 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
484 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
485 RATE_IN_242X},
486
487 /* PRCM II - SLOW */
488 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
489 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
490 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
491 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
492 RATE_IN_242X},
493
494 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
495 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
496 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
497 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
498 RATE_IN_242X},
499
500 /* PRCM III - SLOW */
501 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
502 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
503 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
504 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
505 RATE_IN_242X},
506
507 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
508 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
509 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
510 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
511 RATE_IN_242X},
512
513 /* PRCM-VII (boot-bypass) */
514 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
515 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
516 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
517 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
518 RATE_IN_242X},
519
520 /* PRCM-VII (boot-bypass) */
521 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
522 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
523 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
524 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
525 RATE_IN_242X},
526
527 /* PRCM #4 - ratio2 (ES2.1) - FAST */
528 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
529 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
530 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
531 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
532 SDRC_RFR_CTRL_133MHz,
533 RATE_IN_243X},
534
535 /* PRCM #2 - ratio1 (ES2) - FAST */
536 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
537 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
538 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
539 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
540 SDRC_RFR_CTRL_165MHz,
541 RATE_IN_243X},
542
543 /* PRCM #5a - ratio1 - FAST */
544 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
545 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
546 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
547 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
548 SDRC_RFR_CTRL_133MHz,
549 RATE_IN_243X},
550
551 /* PRCM #5b - ratio1 - FAST */
552 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
553 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
554 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
555 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
556 SDRC_RFR_CTRL_100MHz,
557 RATE_IN_243X},
558
559 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
560 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
561 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
562 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
563 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
564 SDRC_RFR_CTRL_133MHz,
565 RATE_IN_243X},
566
567 /* PRCM #2 - ratio1 (ES2) - SLOW */
568 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
569 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
570 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
571 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
572 SDRC_RFR_CTRL_165MHz,
573 RATE_IN_243X},
574
575 /* PRCM #5a - ratio1 - SLOW */
576 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
577 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
578 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
579 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
580 SDRC_RFR_CTRL_133MHz,
581 RATE_IN_243X},
582
583 /* PRCM #5b - ratio1 - SLOW*/
584 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
585 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
586 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
587 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
588 SDRC_RFR_CTRL_100MHz,
589 RATE_IN_243X},
590
591 /* PRCM-boot/bypass */
592 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
593 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
594 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
595 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
596 SDRC_RFR_CTRL_BYPASS,
597 RATE_IN_243X},
598
599 /* PRCM-boot/bypass */
600 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
601 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
602 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
603 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
604 SDRC_RFR_CTRL_BYPASS,
605 RATE_IN_243X},
606
607 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
608};
609
610/*------------------------------------------------------------------------- 31/*-------------------------------------------------------------------------
611 * 24xx clock tree. 32 * 24xx clock tree.
612 * 33 *
@@ -2653,5 +2074,236 @@ static struct clk virt_prcm_set = {
2653 .round_rate = &omap2_round_to_table_rate, 2074 .round_rate = &omap2_round_to_table_rate,
2654}; 2075};
2655 2076
2656#endif 2077
2078/*
2079 * clkdev integration
2080 */
2081
2082static struct omap_clk omap24xx_clks[] = {
2083 /* external root sources */
2084 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X),
2085 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),
2086 CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X),
2087 CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X),
2088 CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X),
2089 /* internal analog sources */
2090 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X),
2091 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X),
2092 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X),
2093 /* internal prcm root sources */
2094 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X),
2095 CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X),
2096 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X),
2097 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X),
2098 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X),
2099 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X),
2100 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X),
2101 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X),
2102 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
2103 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
2104 CLK(NULL, "emul_ck", &emul_ck, CK_242X),
2105 /* mpu domain clocks */
2106 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X),
2107 /* dsp domain clocks */
2108 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X),
2109 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X),
2110 CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
2111 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
2112 CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
2113 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
2114 /* GFX domain clocks */
2115 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X),
2116 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X),
2117 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X),
2118 /* Modem domain clocks */
2119 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
2120 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
2121 /* DSS domain clocks */
2122 CLK("omapdss", "ick", &dss_ick, CK_243X | CK_242X),
2123 CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
2124 CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
2125 CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
2126 /* L3 domain clocks */
2127 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
2128 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
2129 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X),
2130 /* L4 domain clocks */
2131 CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X),
2132 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X),
2133 /* virtual meta-group clock */
2134 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X),
2135 /* general l4 interface ck, multi-parent functional clk */
2136 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X),
2137 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X),
2138 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X),
2139 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X),
2140 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X),
2141 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X),
2142 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X),
2143 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X),
2144 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X),
2145 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X),
2146 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X),
2147 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X),
2148 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X),
2149 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X),
2150 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X),
2151 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X),
2152 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X),
2153 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X),
2154 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X),
2155 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X),
2156 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X),
2157 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X),
2158 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X),
2159 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X),
2160 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X),
2161 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X),
2162 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X),
2163 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X),
2164 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
2165 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
2166 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
2167 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
2168 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
2169 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
2170 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X),
2171 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X),
2172 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X),
2173 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X),
2174 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
2175 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
2176 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X),
2177 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X),
2178 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X),
2179 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X),
2180 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X),
2181 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X),
2182 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X),
2183 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X),
2184 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X),
2185 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X),
2186 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X),
2187 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X),
2188 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X),
2189 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
2190 CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X),
2191 CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X),
2192 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X),
2193 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X),
2194 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X),
2195 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
2196 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
2197 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X),
2198 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X),
2199 CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
2200 CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
2201 CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X),
2202 CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X),
2203 CLK(NULL, "eac_ick", &eac_ick, CK_242X),
2204 CLK(NULL, "eac_fck", &eac_fck, CK_242X),
2205 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X),
2206 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X),
2207 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X),
2208 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X),
2209 CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
2210 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X),
2211 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X),
2212 CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
2213 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X),
2214 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X),
2215 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X),
2216 CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
2217 CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
2218 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
2219 CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X),
2220 CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X),
2221 CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X),
2222 CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
2223 CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
2224 CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
2225 CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
2226 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
2227 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
2228 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
2229 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
2230 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
2231 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
2232 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
2233 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
2234 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
2235};
2236
2237/*
2238 * init code
2239 */
2240
2241int __init omap2_clk_init(void)
2242{
2243 const struct prcm_config *prcm;
2244 struct omap_clk *c;
2245 u32 clkrate;
2246 u16 cpu_clkflg;
2247
2248 if (cpu_is_omap242x()) {
2249 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
2250 cpu_mask = RATE_IN_242X;
2251 cpu_clkflg = CK_242X;
2252 rate_table = omap2420_rate_table;
2253 } else if (cpu_is_omap2430()) {
2254 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2255 cpu_mask = RATE_IN_243X;
2256 cpu_clkflg = CK_243X;
2257 rate_table = omap2430_rate_table;
2258 }
2259
2260 clk_init(&omap2_clk_functions);
2261
2262 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
2263 clk_preinit(c->lk.clk);
2264
2265 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
2266 propagate_rate(&osc_ck);
2267 sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);
2268 propagate_rate(&sys_ck);
2269
2270 for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
2271 if (c->cpu & cpu_clkflg) {
2272 clkdev_add(&c->lk);
2273 clk_register(c->lk.clk);
2274 omap2_init_clk_clkdm(c->lk.clk);
2275 }
2276
2277 /* Check the MPU rate set by bootloader */
2278 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
2279 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
2280 if (!(prcm->flags & cpu_mask))
2281 continue;
2282 if (prcm->xtal_speed != sys_ck.rate)
2283 continue;
2284 if (prcm->dpll_speed <= clkrate)
2285 break;
2286 }
2287 curr_prcm_set = prcm;
2288
2289 recalculate_root_clocks();
2290
2291 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): "
2292 "%ld.%01ld/%ld/%ld MHz\n",
2293 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
2294 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
2295
2296 /*
2297 * Only enable those clocks we will need, let the drivers
2298 * enable other clocks as necessary
2299 */
2300 clk_enable_init_clocks();
2301
2302 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
2303 vclk = clk_get(NULL, "virt_prcm_set");
2304 sclk = clk_get(NULL, "sys_ck");
2305 dclk = clk_get(NULL, "dpll_ck");
2306
2307 return 0;
2308}
2657 2309
diff --git a/arch/arm/mach-omap2/opp2420_data.c b/arch/arm/mach-omap2/opp2420_data.c
new file mode 100644
index 000000000000..126a9396b3a8
--- /dev/null
+++ b/arch/arm/mach-omap2/opp2420_data.c
@@ -0,0 +1,126 @@
1/*
2 * opp2420_data.c - old-style "OPP" table for OMAP2420
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
6 *
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
10 * These configurations are characterized by voltage and speed for clocks.
11 * The device is only validated for certain combinations. One way to express
12 * these combinations is via the 'ratio's' which the clocks operate with
13 * respect to each other. These ratio sets are for a given voltage/DPLL
14 * setting. All configurations can be described by a DPLL setting and a ratio
15 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
16 *
17 * 2430 differs from 2420 in that there are no more phase synchronizers used.
18 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
19 * 2430 (iva2.1, NOdsp, mdm)
20 *
21 * XXX Missing voltage data.
22 *
23 * THe format described in this file is deprecated. Once a reasonable
24 * OPP API exists, the data in this file should be converted to use it.
25 *
26 * This is technically part of the OMAP2xxx clock code.
27 */
28
29#include "opp2xxx.h"
30#include "sdrc.h"
31#include "clock.h"
32
33/*-------------------------------------------------------------------------
34 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
35 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
36 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
37 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
38 *
39 * Filling in table based on H4 boards and 2430-SDPs variants available.
40 * There are quite a few more rates combinations which could be defined.
41 *
42 * When multiple values are defined the start up will try and choose the
43 * fastest one. If a 'fast' value is defined, then automatically, the /2
44 * one should be included as it can be used. Generally having more that
45 * one fast set does not make sense, as static timings need to be changed
46 * to change the set. The exception is the bypass setting which is
47 * availble for low power bypass.
48 *
49 * Note: This table needs to be sorted, fastest to slowest.
50 *-------------------------------------------------------------------------*/
51const struct prcm_config omap2420_rate_table[] = {
52 /* PRCM I - FAST */
53 {S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
54 RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
55 RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
56 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
57 RATE_IN_242X},
58
59 /* PRCM II - FAST */
60 {S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
61 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
62 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
63 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
64 RATE_IN_242X},
65
66 {S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
67 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
68 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
69 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
70 RATE_IN_242X},
71
72 /* PRCM III - FAST */
73 {S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
74 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
75 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
76 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
77 RATE_IN_242X},
78
79 {S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
80 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
81 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
82 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
83 RATE_IN_242X},
84
85 /* PRCM II - SLOW */
86 {S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
87 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
88 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
89 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
90 RATE_IN_242X},
91
92 {S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
93 RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
94 RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
95 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
96 RATE_IN_242X},
97
98 /* PRCM III - SLOW */
99 {S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
100 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
101 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
102 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
103 RATE_IN_242X},
104
105 {S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
106 RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
107 RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
108 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
109 RATE_IN_242X},
110
111 /* PRCM-VII (boot-bypass) */
112 {S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
113 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
114 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
115 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
116 RATE_IN_242X},
117
118 /* PRCM-VII (boot-bypass) */
119 {S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
120 RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
121 RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
122 MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
123 RATE_IN_242X},
124
125 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
126};
diff --git a/arch/arm/mach-omap2/opp2430_data.c b/arch/arm/mach-omap2/opp2430_data.c
new file mode 100644
index 000000000000..edb81672c844
--- /dev/null
+++ b/arch/arm/mach-omap2/opp2430_data.c
@@ -0,0 +1,133 @@
1/*
2 * opp2420_data.c - old-style "OPP" table for OMAP2420
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
6 *
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
10 * These configurations are characterized by voltage and speed for clocks.
11 * The device is only validated for certain combinations. One way to express
12 * these combinations is via the 'ratio's' which the clocks operate with
13 * respect to each other. These ratio sets are for a given voltage/DPLL
14 * setting. All configurations can be described by a DPLL setting and a ratio
15 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
16 *
17 * 2430 differs from 2420 in that there are no more phase synchronizers used.
18 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
19 * 2430 (iva2.1, NOdsp, mdm)
20 *
21 * XXX Missing voltage data.
22 *
23 * THe format described in this file is deprecated. Once a reasonable
24 * OPP API exists, the data in this file should be converted to use it.
25 *
26 * This is technically part of the OMAP2xxx clock code.
27 */
28
29#include "opp2xxx.h"
30#include "sdrc.h"
31#include "clock.h"
32
33/*-------------------------------------------------------------------------
34 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
35 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
36 * CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
37 * CM_CLKSEL2_PLL, CM_CLKSEL_MDM
38 *
39 * Filling in table based on H4 boards and 2430-SDPs variants available.
40 * There are quite a few more rates combinations which could be defined.
41 *
42 * When multiple values are defined the start up will try and choose the
43 * fastest one. If a 'fast' value is defined, then automatically, the /2
44 * one should be included as it can be used. Generally having more that
45 * one fast set does not make sense, as static timings need to be changed
46 * to change the set. The exception is the bypass setting which is
47 * availble for low power bypass.
48 *
49 * Note: This table needs to be sorted, fastest to slowest.
50 *-------------------------------------------------------------------------*/
51const struct prcm_config omap2430_rate_table[] = {
52 /* PRCM #4 - ratio2 (ES2.1) - FAST */
53 {S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
54 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
55 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
56 MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
57 SDRC_RFR_CTRL_133MHz,
58 RATE_IN_243X},
59
60 /* PRCM #2 - ratio1 (ES2) - FAST */
61 {S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
62 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
63 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
64 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
65 SDRC_RFR_CTRL_165MHz,
66 RATE_IN_243X},
67
68 /* PRCM #5a - ratio1 - FAST */
69 {S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
70 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
71 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
72 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
73 SDRC_RFR_CTRL_133MHz,
74 RATE_IN_243X},
75
76 /* PRCM #5b - ratio1 - FAST */
77 {S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
78 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
79 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
80 MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
81 SDRC_RFR_CTRL_100MHz,
82 RATE_IN_243X},
83
84 /* PRCM #4 - ratio1 (ES2.1) - SLOW */
85 {S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
86 R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
87 R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
88 MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
89 SDRC_RFR_CTRL_133MHz,
90 RATE_IN_243X},
91
92 /* PRCM #2 - ratio1 (ES2) - SLOW */
93 {S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
94 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
95 R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
96 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
97 SDRC_RFR_CTRL_165MHz,
98 RATE_IN_243X},
99
100 /* PRCM #5a - ratio1 - SLOW */
101 {S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
102 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
103 R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
104 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
105 SDRC_RFR_CTRL_133MHz,
106 RATE_IN_243X},
107
108 /* PRCM #5b - ratio1 - SLOW*/
109 {S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
110 R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
111 R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
112 MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
113 SDRC_RFR_CTRL_100MHz,
114 RATE_IN_243X},
115
116 /* PRCM-boot/bypass */
117 {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
118 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
119 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
120 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
121 SDRC_RFR_CTRL_BYPASS,
122 RATE_IN_243X},
123
124 /* PRCM-boot/bypass */
125 {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
126 RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
127 RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
128 MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
129 SDRC_RFR_CTRL_BYPASS,
130 RATE_IN_243X},
131
132 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
133};
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
new file mode 100644
index 000000000000..ed6df04e2f29
--- /dev/null
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -0,0 +1,424 @@
1/*
2 * opp2xxx.h - macros for old-style OMAP2xxx "OPP" definitions
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2009 Nokia Corporation
6 *
7 * Richard Woodruff <r-woodruff2@ti.com>
8 *
9 * The OMAP2 processor can be run at several discrete 'PRCM configurations'.
10 * These configurations are characterized by voltage and speed for clocks.
11 * The device is only validated for certain combinations. One way to express
12 * these combinations is via the 'ratio's' which the clocks operate with
13 * respect to each other. These ratio sets are for a given voltage/DPLL
14 * setting. All configurations can be described by a DPLL setting and a ratio
15 * There are 3 ratio sets for the 2430 and X ratio sets for 2420.
16 *
17 * 2430 differs from 2420 in that there are no more phase synchronizers used.
18 * They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
19 * 2430 (iva2.1, NOdsp, mdm)
20 *
21 * XXX Missing voltage data.
22 *
23 * THe format described in this file is deprecated. Once a reasonable
24 * OPP API exists, the data in this file should be converted to use it.
25 *
26 * This is technically part of the OMAP2xxx clock code.
27 */
28
29#ifndef __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
30#define __ARCH_ARM_MACH_OMAP2_OPP2XXX_H
31
32/**
33 * struct prcm_config - define clock rates on a per-OPP basis (24xx)
34 *
35 * Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
36 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
37 * CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL CM_CLKSEL2_PLL, CM_CLKSEL_MDM
38 *
39 * This is deprecated. As soon as we have a decent OPP API, we should
40 * move all this stuff to it.
41 */
42struct prcm_config {
43 unsigned long xtal_speed; /* crystal rate */
44 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
45 unsigned long mpu_speed; /* speed of MPU */
46 unsigned long cm_clksel_mpu; /* mpu divider */
47 unsigned long cm_clksel_dsp; /* dsp+iva1 div(2420), iva2.1(2430) */
48 unsigned long cm_clksel_gfx; /* gfx dividers */
49 unsigned long cm_clksel1_core; /* major subsystem dividers */
50 unsigned long cm_clksel1_pll; /* m,n */
51 unsigned long cm_clksel2_pll; /* dpllx1 or x2 out */
52 unsigned long cm_clksel_mdm; /* modem dividers 2430 only */
53 unsigned long base_sdrc_rfr; /* base refresh timing for a set */
54 unsigned char flags;
55};
56
57
58/* Core fields for cm_clksel, not ratio governed */
59#define RX_CLKSEL_DSS1 (0x10 << 8)
60#define RX_CLKSEL_DSS2 (0x0 << 13)
61#define RX_CLKSEL_SSI (0x5 << 20)
62
63/*-------------------------------------------------------------------------
64 * Voltage/DPLL ratios
65 *-------------------------------------------------------------------------*/
66
67/* 2430 Ratio's, 2430-Ratio Config 1 */
68#define R1_CLKSEL_L3 (4 << 0)
69#define R1_CLKSEL_L4 (2 << 5)
70#define R1_CLKSEL_USB (4 << 25)
71#define R1_CM_CLKSEL1_CORE_VAL (R1_CLKSEL_USB | RX_CLKSEL_SSI | \
72 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
73 R1_CLKSEL_L4 | R1_CLKSEL_L3)
74#define R1_CLKSEL_MPU (2 << 0)
75#define R1_CM_CLKSEL_MPU_VAL R1_CLKSEL_MPU
76#define R1_CLKSEL_DSP (2 << 0)
77#define R1_CLKSEL_DSP_IF (2 << 5)
78#define R1_CM_CLKSEL_DSP_VAL (R1_CLKSEL_DSP | R1_CLKSEL_DSP_IF)
79#define R1_CLKSEL_GFX (2 << 0)
80#define R1_CM_CLKSEL_GFX_VAL R1_CLKSEL_GFX
81#define R1_CLKSEL_MDM (4 << 0)
82#define R1_CM_CLKSEL_MDM_VAL R1_CLKSEL_MDM
83
84/* 2430-Ratio Config 2 */
85#define R2_CLKSEL_L3 (6 << 0)
86#define R2_CLKSEL_L4 (2 << 5)
87#define R2_CLKSEL_USB (2 << 25)
88#define R2_CM_CLKSEL1_CORE_VAL (R2_CLKSEL_USB | RX_CLKSEL_SSI | \
89 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
90 R2_CLKSEL_L4 | R2_CLKSEL_L3)
91#define R2_CLKSEL_MPU (2 << 0)
92#define R2_CM_CLKSEL_MPU_VAL R2_CLKSEL_MPU
93#define R2_CLKSEL_DSP (2 << 0)
94#define R2_CLKSEL_DSP_IF (3 << 5)
95#define R2_CM_CLKSEL_DSP_VAL (R2_CLKSEL_DSP | R2_CLKSEL_DSP_IF)
96#define R2_CLKSEL_GFX (2 << 0)
97#define R2_CM_CLKSEL_GFX_VAL R2_CLKSEL_GFX
98#define R2_CLKSEL_MDM (6 << 0)
99#define R2_CM_CLKSEL_MDM_VAL R2_CLKSEL_MDM
100
101/* 2430-Ratio Bootm (BYPASS) */
102#define RB_CLKSEL_L3 (1 << 0)
103#define RB_CLKSEL_L4 (1 << 5)
104#define RB_CLKSEL_USB (1 << 25)
105#define RB_CM_CLKSEL1_CORE_VAL (RB_CLKSEL_USB | RX_CLKSEL_SSI | \
106 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
107 RB_CLKSEL_L4 | RB_CLKSEL_L3)
108#define RB_CLKSEL_MPU (1 << 0)
109#define RB_CM_CLKSEL_MPU_VAL RB_CLKSEL_MPU
110#define RB_CLKSEL_DSP (1 << 0)
111#define RB_CLKSEL_DSP_IF (1 << 5)
112#define RB_CM_CLKSEL_DSP_VAL (RB_CLKSEL_DSP | RB_CLKSEL_DSP_IF)
113#define RB_CLKSEL_GFX (1 << 0)
114#define RB_CM_CLKSEL_GFX_VAL RB_CLKSEL_GFX
115#define RB_CLKSEL_MDM (1 << 0)
116#define RB_CM_CLKSEL_MDM_VAL RB_CLKSEL_MDM
117
118/* 2420 Ratio Equivalents */
119#define RXX_CLKSEL_VLYNQ (0x12 << 15)
120#define RXX_CLKSEL_SSI (0x8 << 20)
121
122/* 2420-PRCM III 532MHz core */
123#define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
124#define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
125#define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
126#define RIII_CM_CLKSEL1_CORE_VAL (RIII_CLKSEL_USB | RXX_CLKSEL_SSI | \
127 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
128 RX_CLKSEL_DSS1 | RIII_CLKSEL_L4 | \
129 RIII_CLKSEL_L3)
130#define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
131#define RIII_CM_CLKSEL_MPU_VAL RIII_CLKSEL_MPU
132#define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
133#define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
134#define RIII_SYNC_DSP (1 << 7) /* Enable sync */
135#define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
136#define RIII_SYNC_IVA (1 << 13) /* Enable sync */
137#define RIII_CM_CLKSEL_DSP_VAL (RIII_SYNC_IVA | RIII_CLKSEL_IVA | \
138 RIII_SYNC_DSP | RIII_CLKSEL_DSP_IF | \
139 RIII_CLKSEL_DSP)
140#define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
141#define RIII_CM_CLKSEL_GFX_VAL RIII_CLKSEL_GFX
142
143/* 2420-PRCM II 600MHz core */
144#define RII_CLKSEL_L3 (6 << 0) /* 100MHz */
145#define RII_CLKSEL_L4 (2 << 5) /* 50MHz */
146#define RII_CLKSEL_USB (2 << 25) /* 50MHz */
147#define RII_CM_CLKSEL1_CORE_VAL (RII_CLKSEL_USB | RXX_CLKSEL_SSI | \
148 RXX_CLKSEL_VLYNQ | RX_CLKSEL_DSS2 | \
149 RX_CLKSEL_DSS1 | RII_CLKSEL_L4 | \
150 RII_CLKSEL_L3)
151#define RII_CLKSEL_MPU (2 << 0) /* 300MHz */
152#define RII_CM_CLKSEL_MPU_VAL RII_CLKSEL_MPU
153#define RII_CLKSEL_DSP (3 << 0) /* c5x - 200MHz */
154#define RII_CLKSEL_DSP_IF (2 << 5) /* c5x - 100MHz */
155#define RII_SYNC_DSP (0 << 7) /* Bypass sync */
156#define RII_CLKSEL_IVA (3 << 8) /* iva1 - 200MHz */
157#define RII_SYNC_IVA (0 << 13) /* Bypass sync */
158#define RII_CM_CLKSEL_DSP_VAL (RII_SYNC_IVA | RII_CLKSEL_IVA | \
159 RII_SYNC_DSP | RII_CLKSEL_DSP_IF | \
160 RII_CLKSEL_DSP)
161#define RII_CLKSEL_GFX (2 << 0) /* 50MHz */
162#define RII_CM_CLKSEL_GFX_VAL RII_CLKSEL_GFX
163
164/* 2420-PRCM I 660MHz core */
165#define RI_CLKSEL_L3 (4 << 0) /* 165MHz */
166#define RI_CLKSEL_L4 (2 << 5) /* 82.5MHz */
167#define RI_CLKSEL_USB (4 << 25) /* 41.25MHz */
168#define RI_CM_CLKSEL1_CORE_VAL (RI_CLKSEL_USB | \
169 RXX_CLKSEL_SSI | RXX_CLKSEL_VLYNQ | \
170 RX_CLKSEL_DSS2 | RX_CLKSEL_DSS1 | \
171 RI_CLKSEL_L4 | RI_CLKSEL_L3)
172#define RI_CLKSEL_MPU (2 << 0) /* 330MHz */
173#define RI_CM_CLKSEL_MPU_VAL RI_CLKSEL_MPU
174#define RI_CLKSEL_DSP (3 << 0) /* c5x - 220MHz */
175#define RI_CLKSEL_DSP_IF (2 << 5) /* c5x - 110MHz */
176#define RI_SYNC_DSP (1 << 7) /* Activate sync */
177#define RI_CLKSEL_IVA (4 << 8) /* iva1 - 165MHz */
178#define RI_SYNC_IVA (0 << 13) /* Bypass sync */
179#define RI_CM_CLKSEL_DSP_VAL (RI_SYNC_IVA | RI_CLKSEL_IVA | \
180 RI_SYNC_DSP | RI_CLKSEL_DSP_IF | \
181 RI_CLKSEL_DSP)
182#define RI_CLKSEL_GFX (1 << 0) /* 165MHz */
183#define RI_CM_CLKSEL_GFX_VAL RI_CLKSEL_GFX
184
185/* 2420-PRCM VII (boot) */
186#define RVII_CLKSEL_L3 (1 << 0)
187#define RVII_CLKSEL_L4 (1 << 5)
188#define RVII_CLKSEL_DSS1 (1 << 8)
189#define RVII_CLKSEL_DSS2 (0 << 13)
190#define RVII_CLKSEL_VLYNQ (1 << 15)
191#define RVII_CLKSEL_SSI (1 << 20)
192#define RVII_CLKSEL_USB (1 << 25)
193
194#define RVII_CM_CLKSEL1_CORE_VAL (RVII_CLKSEL_USB | RVII_CLKSEL_SSI | \
195 RVII_CLKSEL_VLYNQ | \
196 RVII_CLKSEL_DSS2 | RVII_CLKSEL_DSS1 | \
197 RVII_CLKSEL_L4 | RVII_CLKSEL_L3)
198
199#define RVII_CLKSEL_MPU (1 << 0) /* all divide by 1 */
200#define RVII_CM_CLKSEL_MPU_VAL RVII_CLKSEL_MPU
201
202#define RVII_CLKSEL_DSP (1 << 0)
203#define RVII_CLKSEL_DSP_IF (1 << 5)
204#define RVII_SYNC_DSP (0 << 7)
205#define RVII_CLKSEL_IVA (1 << 8)
206#define RVII_SYNC_IVA (0 << 13)
207#define RVII_CM_CLKSEL_DSP_VAL (RVII_SYNC_IVA | RVII_CLKSEL_IVA | \
208 RVII_SYNC_DSP | RVII_CLKSEL_DSP_IF | \
209 RVII_CLKSEL_DSP)
210
211#define RVII_CLKSEL_GFX (1 << 0)
212#define RVII_CM_CLKSEL_GFX_VAL RVII_CLKSEL_GFX
213
214/*-------------------------------------------------------------------------
215 * 2430 Target modes: Along with each configuration the CPU has several
216 * modes which goes along with them. Modes mainly are the addition of
217 * describe DPLL combinations to go along with a ratio.
218 *-------------------------------------------------------------------------*/
219
220/* Hardware governed */
221#define MX_48M_SRC (0 << 3)
222#define MX_54M_SRC (0 << 5)
223#define MX_APLLS_CLIKIN_12 (3 << 23)
224#define MX_APLLS_CLIKIN_13 (2 << 23)
225#define MX_APLLS_CLIKIN_19_2 (0 << 23)
226
227/*
228 * 2430 - standalone, 2*ref*M/(n+1), M/N is for exactness not relock speed
229 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
230 */
231#define M5A_DPLL_MULT_12 (133 << 12)
232#define M5A_DPLL_DIV_12 (5 << 8)
233#define M5A_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
234 M5A_DPLL_DIV_12 | M5A_DPLL_MULT_12 | \
235 MX_APLLS_CLIKIN_12)
236#define M5A_DPLL_MULT_13 (61 << 12)
237#define M5A_DPLL_DIV_13 (2 << 8)
238#define M5A_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
239 M5A_DPLL_DIV_13 | M5A_DPLL_MULT_13 | \
240 MX_APLLS_CLIKIN_13)
241#define M5A_DPLL_MULT_19 (55 << 12)
242#define M5A_DPLL_DIV_19 (3 << 8)
243#define M5A_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
244 M5A_DPLL_DIV_19 | M5A_DPLL_MULT_19 | \
245 MX_APLLS_CLIKIN_19_2)
246/* #5b (ratio1) target DPLL = 200*2 = 400MHz */
247#define M5B_DPLL_MULT_12 (50 << 12)
248#define M5B_DPLL_DIV_12 (2 << 8)
249#define M5B_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
250 M5B_DPLL_DIV_12 | M5B_DPLL_MULT_12 | \
251 MX_APLLS_CLIKIN_12)
252#define M5B_DPLL_MULT_13 (200 << 12)
253#define M5B_DPLL_DIV_13 (12 << 8)
254
255#define M5B_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
256 M5B_DPLL_DIV_13 | M5B_DPLL_MULT_13 | \
257 MX_APLLS_CLIKIN_13)
258#define M5B_DPLL_MULT_19 (125 << 12)
259#define M5B_DPLL_DIV_19 (31 << 8)
260#define M5B_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
261 M5B_DPLL_DIV_19 | M5B_DPLL_MULT_19 | \
262 MX_APLLS_CLIKIN_19_2)
263/*
264 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
265 */
266#define M4_DPLL_MULT_12 (133 << 12)
267#define M4_DPLL_DIV_12 (3 << 8)
268#define M4_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
269 M4_DPLL_DIV_12 | M4_DPLL_MULT_12 | \
270 MX_APLLS_CLIKIN_12)
271
272#define M4_DPLL_MULT_13 (399 << 12)
273#define M4_DPLL_DIV_13 (12 << 8)
274#define M4_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
275 M4_DPLL_DIV_13 | M4_DPLL_MULT_13 | \
276 MX_APLLS_CLIKIN_13)
277
278#define M4_DPLL_MULT_19 (145 << 12)
279#define M4_DPLL_DIV_19 (6 << 8)
280#define M4_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
281 M4_DPLL_DIV_19 | M4_DPLL_MULT_19 | \
282 MX_APLLS_CLIKIN_19_2)
283
284/*
285 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
286 */
287#define M3_DPLL_MULT_12 (55 << 12)
288#define M3_DPLL_DIV_12 (1 << 8)
289#define M3_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
290 M3_DPLL_DIV_12 | M3_DPLL_MULT_12 | \
291 MX_APLLS_CLIKIN_12)
292#define M3_DPLL_MULT_13 (76 << 12)
293#define M3_DPLL_DIV_13 (2 << 8)
294#define M3_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
295 M3_DPLL_DIV_13 | M3_DPLL_MULT_13 | \
296 MX_APLLS_CLIKIN_13)
297#define M3_DPLL_MULT_19 (17 << 12)
298#define M3_DPLL_DIV_19 (0 << 8)
299#define M3_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
300 M3_DPLL_DIV_19 | M3_DPLL_MULT_19 | \
301 MX_APLLS_CLIKIN_19_2)
302
303/*
304 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
305 */
306#define M2_DPLL_MULT_12 (55 << 12)
307#define M2_DPLL_DIV_12 (1 << 8)
308#define M2_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
309 M2_DPLL_DIV_12 | M2_DPLL_MULT_12 | \
310 MX_APLLS_CLIKIN_12)
311
312/* Speed changes - Used 658.7MHz instead of 660MHz for LP-Refresh M=76 N=2,
313 * relock time issue */
314/* Core frequency changed from 330/165 to 329/164 MHz*/
315#define M2_DPLL_MULT_13 (76 << 12)
316#define M2_DPLL_DIV_13 (2 << 8)
317#define M2_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
318 M2_DPLL_DIV_13 | M2_DPLL_MULT_13 | \
319 MX_APLLS_CLIKIN_13)
320
321#define M2_DPLL_MULT_19 (17 << 12)
322#define M2_DPLL_DIV_19 (0 << 8)
323#define M2_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
324 M2_DPLL_DIV_19 | M2_DPLL_MULT_19 | \
325 MX_APLLS_CLIKIN_19_2)
326
327/* boot (boot) */
328#define MB_DPLL_MULT (1 << 12)
329#define MB_DPLL_DIV (0 << 8)
330#define MB_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
331 MB_DPLL_DIV | MB_DPLL_MULT | \
332 MX_APLLS_CLIKIN_12)
333
334#define MB_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
335 MB_DPLL_DIV | MB_DPLL_MULT | \
336 MX_APLLS_CLIKIN_13)
337
338#define MB_CM_CLKSEL1_PLL_19_VAL (MX_48M_SRC | MX_54M_SRC | \
339 MB_DPLL_DIV | MB_DPLL_MULT | \
340 MX_APLLS_CLIKIN_19)
341
342/*
343 * 2430 - chassis (sedna)
344 * 165 (ratio1) same as above #2
345 * 150 (ratio1)
346 * 133 (ratio2) same as above #4
347 * 110 (ratio2) same as above #3
348 * 104 (ratio2)
349 * boot (boot)
350 */
351
352/* PRCM I target DPLL = 2*330MHz = 660MHz */
353#define MI_DPLL_MULT_12 (55 << 12)
354#define MI_DPLL_DIV_12 (1 << 8)
355#define MI_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
356 MI_DPLL_DIV_12 | MI_DPLL_MULT_12 | \
357 MX_APLLS_CLIKIN_12)
358
359/*
360 * 2420 Equivalent - mode registers
361 * PRCM II , target DPLL = 2*300MHz = 600MHz
362 */
363#define MII_DPLL_MULT_12 (50 << 12)
364#define MII_DPLL_DIV_12 (1 << 8)
365#define MII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
366 MII_DPLL_DIV_12 | MII_DPLL_MULT_12 | \
367 MX_APLLS_CLIKIN_12)
368#define MII_DPLL_MULT_13 (300 << 12)
369#define MII_DPLL_DIV_13 (12 << 8)
370#define MII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
371 MII_DPLL_DIV_13 | MII_DPLL_MULT_13 | \
372 MX_APLLS_CLIKIN_13)
373
374/* PRCM III target DPLL = 2*266 = 532MHz*/
375#define MIII_DPLL_MULT_12 (133 << 12)
376#define MIII_DPLL_DIV_12 (5 << 8)
377#define MIII_CM_CLKSEL1_PLL_12_VAL (MX_48M_SRC | MX_54M_SRC | \
378 MIII_DPLL_DIV_12 | \
379 MIII_DPLL_MULT_12 | MX_APLLS_CLIKIN_12)
380#define MIII_DPLL_MULT_13 (266 << 12)
381#define MIII_DPLL_DIV_13 (12 << 8)
382#define MIII_CM_CLKSEL1_PLL_13_VAL (MX_48M_SRC | MX_54M_SRC | \
383 MIII_DPLL_DIV_13 | \
384 MIII_DPLL_MULT_13 | MX_APLLS_CLIKIN_13)
385
386/* PRCM VII (boot bypass) */
387#define MVII_CM_CLKSEL1_PLL_12_VAL MB_CM_CLKSEL1_PLL_12_VAL
388#define MVII_CM_CLKSEL1_PLL_13_VAL MB_CM_CLKSEL1_PLL_13_VAL
389
390/* High and low operation value */
391#define MX_CLKSEL2_PLL_2x_VAL (2 << 0)
392#define MX_CLKSEL2_PLL_1x_VAL (1 << 0)
393
394/* MPU speed defines */
395#define S12M 12000000
396#define S13M 13000000
397#define S19M 19200000
398#define S26M 26000000
399#define S100M 100000000
400#define S133M 133000000
401#define S150M 150000000
402#define S164M 164000000
403#define S165M 165000000
404#define S199M 199000000
405#define S200M 200000000
406#define S266M 266000000
407#define S300M 300000000
408#define S329M 329000000
409#define S330M 330000000
410#define S399M 399000000
411#define S400M 400000000
412#define S532M 532000000
413#define S600M 600000000
414#define S658M 658000000
415#define S660M 660000000
416#define S798M 798000000
417
418
419extern const struct prcm_config omap2420_rate_table[];
420extern const struct prcm_config omap2430_rate_table[];
421extern const struct prcm_config *rate_table;
422extern const struct prcm_config *curr_prcm_set;
423
424#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 12fc7dafec2b..68f57bb67fc5 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -18,6 +18,9 @@
18#include <plat/sdrc.h> 18#include <plat/sdrc.h>
19 19
20#ifndef __ASSEMBLER__ 20#ifndef __ASSEMBLER__
21
22#include <linux/io.h>
23
21extern void __iomem *omap2_sdrc_base; 24extern void __iomem *omap2_sdrc_base;
22extern void __iomem *omap2_sms_base; 25extern void __iomem *omap2_sms_base;
23 26
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 4b8b0d65cbf2..00310f21e84f 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -13,6 +13,8 @@
13#ifndef __ARCH_ARM_OMAP_CLOCK_H 13#ifndef __ARCH_ARM_OMAP_CLOCK_H
14#define __ARCH_ARM_OMAP_CLOCK_H 14#define __ARCH_ARM_OMAP_CLOCK_H
15 15
16#include <linux/list.h>
17
16struct module; 18struct module;
17struct clk; 19struct clk;
18struct clockdomain; 20struct clockdomain;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 04:51:22 -0500