diff options
author | Chris Dearman <chris@mips.com> | 2007-05-08 09:05:39 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-05-11 09:28:31 -0400 |
commit | d725cf3818b12a17d78b87a2de19e8eec17126ae (patch) | |
tree | 9d200020488b886201771bd6516c63ef43397baa | |
parent | ef300e42234eac066b193c871714203d999b481c (diff) |
[MIPS] MT: Reenable EIC support and add support for SOCit SC.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/Kconfig | 4 | ||||
-rw-r--r-- | arch/mips/kernel/irq-msc01.c | 10 | ||||
-rw-r--r-- | arch/mips/mips-boards/malta/malta_int.c | 21 | ||||
-rw-r--r-- | include/asm-mips/mips-boards/malta.h | 4 | ||||
-rw-r--r-- | include/asm-mips/msc01_ic.h | 5 |
5 files changed, 27 insertions, 17 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 16ecea3c0813..b684385c4e65 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
@@ -1557,6 +1557,7 @@ config MIPS_MT_SMP | |||
1557 | bool "Use 1 TC on each available VPE for SMP" | 1557 | bool "Use 1 TC on each available VPE for SMP" |
1558 | depends on SYS_SUPPORTS_MULTITHREADING | 1558 | depends on SYS_SUPPORTS_MULTITHREADING |
1559 | select CPU_MIPSR2_IRQ_VI | 1559 | select CPU_MIPSR2_IRQ_VI |
1560 | select CPU_MIPSR2_IRQ_EI | ||
1560 | select CPU_MIPSR2_SRS | 1561 | select CPU_MIPSR2_SRS |
1561 | select MIPS_MT | 1562 | select MIPS_MT |
1562 | select NR_CPUS_DEFAULT_2 | 1563 | select NR_CPUS_DEFAULT_2 |
@@ -1572,6 +1573,7 @@ config MIPS_MT_SMTC | |||
1572 | #depends on CPU_MIPS64_R2 # once there is hardware ... | 1573 | #depends on CPU_MIPS64_R2 # once there is hardware ... |
1573 | depends on SYS_SUPPORTS_MULTITHREADING | 1574 | depends on SYS_SUPPORTS_MULTITHREADING |
1574 | select CPU_MIPSR2_IRQ_VI | 1575 | select CPU_MIPSR2_IRQ_VI |
1576 | select CPU_MIPSR2_IRQ_EI | ||
1575 | select CPU_MIPSR2_SRS | 1577 | select CPU_MIPSR2_SRS |
1576 | select MIPS_MT | 1578 | select MIPS_MT |
1577 | select NR_CPUS_DEFAULT_8 | 1579 | select NR_CPUS_DEFAULT_8 |
@@ -1584,6 +1586,8 @@ config MIPS_MT_SMTC | |||
1584 | config MIPS_VPE_LOADER | 1586 | config MIPS_VPE_LOADER |
1585 | bool "VPE loader support." | 1587 | bool "VPE loader support." |
1586 | depends on SYS_SUPPORTS_MULTITHREADING | 1588 | depends on SYS_SUPPORTS_MULTITHREADING |
1589 | select CPU_MIPSR2_IRQ_VI | ||
1590 | select CPU_MIPSR2_IRQ_EI | ||
1587 | select MIPS_MT | 1591 | select MIPS_MT |
1588 | help | 1592 | help |
1589 | Includes a loader for loading an elf relocatable object | 1593 | Includes a loader for loading an elf relocatable object |
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 2967537221e2..410868b5ea5f 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
@@ -132,11 +132,11 @@ struct irq_chip msc_edgeirq_type = { | |||
132 | }; | 132 | }; |
133 | 133 | ||
134 | 134 | ||
135 | void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | 135 | void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq) |
136 | { | 136 | { |
137 | extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); | 137 | extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); |
138 | 138 | ||
139 | _icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000); | 139 | _icctrl_msc = (unsigned long) ioremap (icubase, 0x40000); |
140 | 140 | ||
141 | /* Reset interrupt controller - initialises all registers to 0 */ | 141 | /* Reset interrupt controller - initialises all registers to 0 */ |
142 | MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); | 142 | MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); |
@@ -148,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
148 | 148 | ||
149 | switch (imp->im_type) { | 149 | switch (imp->im_type) { |
150 | case MSC01_IRQ_EDGE: | 150 | case MSC01_IRQ_EDGE: |
151 | set_irq_chip(base+n, &msc_edgeirq_type); | 151 | set_irq_chip(irqbase+n, &msc_edgeirq_type); |
152 | if (cpu_has_veic) | 152 | if (cpu_has_veic) |
153 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); | 153 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
154 | else | 154 | else |
155 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | 155 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
156 | break; | 156 | break; |
157 | case MSC01_IRQ_LEVEL: | 157 | case MSC01_IRQ_LEVEL: |
158 | set_irq_chip(base+n, &msc_levelirq_type); | 158 | set_irq_chip(irqbase+n, &msc_levelirq_type); |
159 | if (cpu_has_veic) | 159 | if (cpu_has_veic) |
160 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); | 160 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
161 | else | 161 | else |
@@ -163,7 +163,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
163 | } | 163 | } |
164 | } | 164 | } |
165 | 165 | ||
166 | irq_base = base; | 166 | irq_base = irqbase; |
167 | 167 | ||
168 | MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ | 168 | MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ |
169 | 169 | ||
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index 83d76025d61d..1cd830e3d933 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c | |||
@@ -311,16 +311,21 @@ void __init arch_init_irq(void) | |||
311 | if (!cpu_has_veic) | 311 | if (!cpu_has_veic) |
312 | mips_cpu_irq_init(); | 312 | mips_cpu_irq_init(); |
313 | 313 | ||
314 | switch(mips_revision_corid) { | 314 | switch(mips_revision_sconid) { |
315 | case MIPS_REVISION_CORID_CORE_MSC: | 315 | case MIPS_REVISION_SCON_SOCIT: |
316 | case MIPS_REVISION_CORID_CORE_FPGA2: | 316 | case MIPS_REVISION_SCON_ROCIT: |
317 | case MIPS_REVISION_CORID_CORE_FPGA3: | 317 | if (cpu_has_veic) |
318 | case MIPS_REVISION_CORID_CORE_24K: | 318 | init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); |
319 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: | 319 | else |
320 | init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); | ||
321 | break; | ||
322 | |||
323 | case MIPS_REVISION_SCON_SOCITSC: | ||
324 | case MIPS_REVISION_SCON_SOCITSCP: | ||
320 | if (cpu_has_veic) | 325 | if (cpu_has_veic) |
321 | init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); | 326 | init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); |
322 | else | 327 | else |
323 | init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); | 328 | init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); |
324 | } | 329 | } |
325 | 330 | ||
326 | if (cpu_has_veic) { | 331 | if (cpu_has_veic) { |
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h index b0ba3c5a921e..eec91001bb65 100644 --- a/include/asm-mips/mips-boards/malta.h +++ b/include/asm-mips/mips-boards/malta.h | |||
@@ -25,6 +25,10 @@ | |||
25 | #include <asm/mips-boards/msc01_pci.h> | 25 | #include <asm/mips-boards/msc01_pci.h> |
26 | #include <asm/gt64120.h> | 26 | #include <asm/gt64120.h> |
27 | 27 | ||
28 | /* Mips interrupt controller found in SOCit variations */ | ||
29 | #define MIPS_MSC01_IC_REG_BASE 0x1bc40000 | ||
30 | #define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000 | ||
31 | |||
28 | /* | 32 | /* |
29 | * Malta I/O ports base address for the Galileo GT64120 and Algorithmics | 33 | * Malta I/O ports base address for the Galileo GT64120 and Algorithmics |
30 | * Bonito system controllers. | 34 | * Bonito system controllers. |
diff --git a/include/asm-mips/msc01_ic.h b/include/asm-mips/msc01_ic.h index aa7ad9a71762..7989b9ffc1d2 100644 --- a/include/asm-mips/msc01_ic.h +++ b/include/asm-mips/msc01_ic.h | |||
@@ -94,10 +94,7 @@ | |||
94 | /* | 94 | /* |
95 | * MIPS System controller interrupt register base. | 95 | * MIPS System controller interrupt register base. |
96 | * | 96 | * |
97 | * FIXME - are these macros specific to Malta and co or to the MSC? If the | ||
98 | * latter, they should be moved elsewhere. | ||
99 | */ | 97 | */ |
100 | #define MIPS_MSC01_IC_REG_BASE 0x1bc40000 | ||
101 | 98 | ||
102 | /***************************************************************************** | 99 | /***************************************************************************** |
103 | * Absolute register addresses | 100 | * Absolute register addresses |
@@ -144,7 +141,7 @@ typedef struct msc_irqmap { | |||
144 | #define MSC01_IRQ_LEVEL 0 | 141 | #define MSC01_IRQ_LEVEL 0 |
145 | #define MSC01_IRQ_EDGE 1 | 142 | #define MSC01_IRQ_EDGE 1 |
146 | 143 | ||
147 | extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq); | 144 | extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq); |
148 | extern void ll_msc_irq(void); | 145 | extern void ll_msc_irq(void); |
149 | 146 | ||
150 | #endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */ | 147 | #endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */ |