ARM: 6379/1: Assume new page cache pages have dirty D-cache

There are places in Linux where writes to newly allocated page cache
pages happen without a subsequent call to flush_dcache_page() (several
PIO drivers including USB HCD). This patch changes the meaning of
PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
mapped page in update_mmu_cache().

The patch also sets the PG_arch_1 bit in the DMA cache maintenance
function to avoid additional cache flushing in update_mmu_cache().

Tested-by: Rabin Vincent <rabin.vincent@stericsson.com>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

8 files changed, 17 insertions, 10 deletions

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24058d2..d3730f0f4b50 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -137,10 +137,10 @@
 #endif
 
 /*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
  */
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 
 /*
  *      MM Cache Management
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546ae72d4..9ad329ad7458 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -560,7 +560,7 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 #endif
 
 /*
- * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
  * back to the page.
  */
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 598c51ad5071..b8061519ce77 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
 {
         void *kto = kmap_atomic(to, KM_USER1);
 
-        if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+        if (!test_and_set_bit(PG_dcache_clean, &from->flags))
                 __flush_dcache_page(page_mapping(from), from);
 
         spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index f55fa1044f72..bdba6c65c901 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
         unsigned int offset = CACHE_COLOUR(vaddr);
         unsigned long kfrom, kto;
 
-        if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+        if (!test_and_set_bit(PG_dcache_clean, &from->flags))
                 __flush_dcache_page(page_mapping(from), from);
 
         /* FIXME: not highmem safe */
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 9920c0ae2096..649bbcd325bf 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
 {
         void *kto = kmap_atomic(to, KM_USER1);
 
-        if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+        if (!test_and_set_bit(PG_dcache_clean, &from->flags))
                 __flush_dcache_page(page_mapping(from), from);
 
         spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4bc43e535d3b..e4dd0646e859 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -523,6 +523,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
                 outer_inv_range(paddr, paddr + size);
 
         dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+
+        /*
+         * Mark the D-cache clean for this page to avoid extra flushing.
+         */
+        if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
+                set_bit(PG_dcache_clean, &page->flags);
 }
 EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9b906dec1ca1..58846cbd0e0b 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -141,7 +141,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
  * a page table, or changing an existing PTE.  Basically, there are two
  * things that we need to take care of:
  *
- *  1. If PG_dcache_dirty is set for the page, we need to ensure
+ *  1. If PG_dcache_clean is not set for the page, we need to ensure
  *     that any cache entries for the kernels virtual memory
  *     range are written back to the page.
  *  2. If we have multiple shared mappings of the same space in
@@ -169,7 +169,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 
         mapping = page_mapping(page);
 #ifndef CONFIG_SMP
-        if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
+        if (!test_and_set_bit(PG_dcache_clean, &page->flags))
                 __flush_dcache_page(mapping, page);
 #endif
         if (mapping) {
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 87dd5ffdfa2d..b4efce9b7985 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -248,7 +248,7 @@ void flush_dcache_page(struct page *page)
 
 #ifndef CONFIG_SMP
         if (mapping && !mapping_mapped(mapping))
-                set_bit(PG_dcache_dirty, &page->flags);
+                clear_bit(PG_dcache_clean, &page->flags);
         else
 #endif
         {
@@ -257,6 +257,7 @@ void flush_dcache_page(struct page *page)
                         __flush_dcache_aliases(mapping, page);
                 else if (mapping)
                         __flush_icache_all();
+                set_bit(PG_dcache_clean, &page->flags);
         }
 }
 EXPORT_SYMBOL(flush_dcache_page);