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authorEric Miao <ycmiao@ycmiao-hp520.(none)>2008-12-18 09:10:00 -0500
committerEric Miao <eric.miao@marvell.com>2008-12-29 04:59:17 -0500
commita0427509a76c61984fbba4e206b617c689f419ef (patch)
treee7b7f74b912ae35677767213c77308c3e9c4d64e
parent6e354846e807e037751fdc8faaee8ad492177113 (diff)
[ARM] pxafb: add palette format support for LCCR4_PAL_FOR_3
Add the palette format support for LCCR4_PAL_FOR_3, and fix the issue of LCCR4 being never assigned. Also remove the useless pxafb_set_truecolor(). Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Eric Miao <ycmiao@ycmiao-hp520.(none)>
-rw-r--r--arch/arm/mach-pxa/include/mach/regs-lcd.h1
-rw-r--r--drivers/video/pxafb.c21
2 files changed, 11 insertions, 11 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
index c15df557fa8a..5c522263e401 100644
--- a/arch/arm/mach-pxa/include/mach/regs-lcd.h
+++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h
@@ -48,6 +48,7 @@
48#define LCCR4_PAL_FOR_0 (0 << 15) 48#define LCCR4_PAL_FOR_0 (0 << 15)
49#define LCCR4_PAL_FOR_1 (1 << 15) 49#define LCCR4_PAL_FOR_1 (1 << 15)
50#define LCCR4_PAL_FOR_2 (2 << 15) 50#define LCCR4_PAL_FOR_2 (2 << 15)
51#define LCCR4_PAL_FOR_3 (3 << 15)
51#define LCCR4_PAL_FOR_MASK (3 << 15) 52#define LCCR4_PAL_FOR_MASK (3 << 15)
52 53
53#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */ 54#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index b43907d36d66..c57f909cb7a8 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -155,6 +155,12 @@ pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
155 val |= ((blue >> 8) & 0x000000fc); 155 val |= ((blue >> 8) & 0x000000fc);
156 ((u32 *)(fbi->palette_cpu))[regno] = val; 156 ((u32 *)(fbi->palette_cpu))[regno] = val;
157 break; 157 break;
158 case LCCR4_PAL_FOR_3:
159 val = ((red << 8) & 0x00ff0000);
160 val |= ((green >> 0) & 0x0000ff00);
161 val |= ((blue >> 8) & 0x000000ff);
162 ((u32 *)(fbi->palette_cpu))[regno] = val;
163 break;
158 } 164 }
159 165
160 return 0; 166 return 0;
@@ -416,11 +422,6 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
416 return 0; 422 return 0;
417} 423}
418 424
419static inline void pxafb_set_truecolor(u_int is_true_color)
420{
421 /* do your machine-specific setup if needed */
422}
423
424/* 425/*
425 * pxafb_set_par(): 426 * pxafb_set_par():
426 * Set the user defined part of the display for the specified console 427 * Set the user defined part of the display for the specified console
@@ -453,11 +454,6 @@ static int pxafb_set_par(struct fb_info *info)
453 454
454 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; 455 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
455 456
456 /*
457 * Set (any) board control register to handle new color depth
458 */
459 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
460
461 if (fbi->fb.var.bits_per_pixel >= 16) 457 if (fbi->fb.var.bits_per_pixel >= 16)
462 fb_dealloc_cmap(&fbi->fb.cmap); 458 fb_dealloc_cmap(&fbi->fb.cmap);
463 else 459 else
@@ -727,6 +723,7 @@ int pxafb_smart_flush(struct fb_info *info)
727 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 723 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
728 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 724 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
729 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 725 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
726 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
730 lcd_writel(fbi, FDADR0, fbi->fdadr[0]); 727 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
731 lcd_writel(fbi, FDADR6, fbi->fdadr[6]); 728 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
732 729
@@ -995,6 +992,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
995 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || 992 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
996 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || 993 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
997 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || 994 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
995 (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
998 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || 996 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
999 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])) 997 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1000 pxafb_schedule_work(fbi, C_REENABLE); 998 pxafb_schedule_work(fbi, C_REENABLE);
@@ -1041,6 +1039,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
1041 return; 1039 return;
1042 1040
1043 /* Sequence from 11.7.10 */ 1041 /* Sequence from 11.7.10 */
1042 lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1044 lcd_writel(fbi, LCCR3, fbi->reg_lccr3); 1043 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1045 lcd_writel(fbi, LCCR2, fbi->reg_lccr2); 1044 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1046 lcd_writel(fbi, LCCR1, fbi->reg_lccr1); 1045 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
@@ -1313,6 +1312,7 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1313 1312
1314 fbi->cmap_inverse = inf->cmap_inverse; 1313 fbi->cmap_inverse = inf->cmap_inverse;
1315 fbi->cmap_static = inf->cmap_static; 1314 fbi->cmap_static = inf->cmap_static;
1315 fbi->lccr4 = inf->lccr4;
1316 1316
1317 switch (lcd_conn & LCD_TYPE_MASK) { 1317 switch (lcd_conn & LCD_TYPE_MASK) {
1318 case LCD_TYPE_MONO_STN: 1318 case LCD_TYPE_MONO_STN:
@@ -1337,7 +1337,6 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1337 /* fall back to backward compatibility way */ 1337 /* fall back to backward compatibility way */
1338 fbi->lccr0 = inf->lccr0; 1338 fbi->lccr0 = inf->lccr0;
1339 fbi->lccr3 = inf->lccr3; 1339 fbi->lccr3 = inf->lccr3;
1340 fbi->lccr4 = inf->lccr4;
1341 goto decode_mode; 1340 goto decode_mode;
1342 } 1341 }
1343 1342