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authorAlan Cox <alan@lxorguk.ukuu.org.uk>2007-05-25 15:48:55 -0400
committerJeff Garzik <jeff@garzik.org>2007-05-25 17:29:59 -0400
commit960c8a10cbd47d1535996f40749b36f3d2c45f88 (patch)
tree5c010bb20aeee5755703514a665dce20ffe1ac9e
parentc343a8391496de83c66e771ead986aab0d6f777f (diff)
pata_hpt37x: Further improvements based on the IDE updates and vendor drivers
Better DPLL use and calibration Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r--drivers/ata/pata_hpt37x.c27
1 files changed, 11 insertions, 16 deletions
diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c
index a54c17433eef..6446735a46e0 100644
--- a/drivers/ata/pata_hpt37x.c
+++ b/drivers/ata/pata_hpt37x.c
@@ -26,7 +26,7 @@
26#include <linux/libata.h> 26#include <linux/libata.h>
27 27
28#define DRV_NAME "pata_hpt37x" 28#define DRV_NAME "pata_hpt37x"
29#define DRV_VERSION "0.6.5" 29#define DRV_VERSION "0.6.6"
30 30
31struct hpt_clock { 31struct hpt_clock {
32 u8 xfer_speed; 32 u8 xfer_speed;
@@ -931,15 +931,6 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
931 .udma_mask = 0x7f, 931 .udma_mask = 0x7f,
932 .port_ops = &hpt372_port_ops 932 .port_ops = &hpt372_port_ops
933 }; 933 };
934 /* HPT371, 372 and friends - UDMA100 at 50MHz clock */
935 static const struct ata_port_info info_hpt372_50 = {
936 .sht = &hpt37x_sht,
937 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
938 .pio_mask = 0x1f,
939 .mwdma_mask = 0x07,
940 .udma_mask = 0x3f,
941 .port_ops = &hpt372_port_ops
942 };
943 /* HPT374 - UDMA133 */ 934 /* HPT374 - UDMA133 */
944 static const struct ata_port_info info_hpt374 = { 935 static const struct ata_port_info info_hpt374 = {
945 .sht = &hpt37x_sht, 936 .sht = &hpt37x_sht,
@@ -1098,17 +1089,21 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1098 * use a 50MHz DPLL by choice 1089 * use a 50MHz DPLL by choice
1099 */ 1090 */
1100 unsigned int f_low, f_high; 1091 unsigned int f_low, f_high;
1101 int adjust; 1092 int dpll, adjust;
1102 1093
1103 clock_slot = 2; 1094 /* Compute DPLL */
1095 dpll = 2;
1104 if (port->udma_mask & 0xE0) 1096 if (port->udma_mask & 0xE0)
1105 clock_slot = 3; 1097 dpll = 3;
1106 1098
1107 f_low = (MHz[clock_slot] * chip_table->base) / 192; 1099 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
1108 f_high = f_low + 2; 1100 f_high = f_low + 2;
1101 if (clock_slot > 1)
1102 f_high += 2;
1109 1103
1110 /* Select the DPLL clock. */ 1104 /* Select the DPLL clock. */
1111 pci_write_config_byte(dev, 0x5b, 0x21); 1105 pci_write_config_byte(dev, 0x5b, 0x21);
1106 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
1112 1107
1113 for(adjust = 0; adjust < 8; adjust++) { 1108 for(adjust = 0; adjust < 8; adjust++) {
1114 if (hpt37x_calibrate_dpll(dev)) 1109 if (hpt37x_calibrate_dpll(dev))
@@ -1124,12 +1119,12 @@ static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1124 printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n"); 1119 printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n");
1125 return -ENODEV; 1120 return -ENODEV;
1126 } 1121 }
1127 if (clock_slot == 3) 1122 if (dpll == 3)
1128 private_data = (void *)hpt37x_timings_66; 1123 private_data = (void *)hpt37x_timings_66;
1129 else 1124 else
1130 private_data = (void *)hpt37x_timings_50; 1125 private_data = (void *)hpt37x_timings_50;
1131 1126
1132 printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]); 1127 printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[dpll]);
1133 } else { 1128 } else {
1134 private_data = (void *)chip_table->clocks[clock_slot]; 1129 private_data = (void *)chip_table->clocks[clock_slot];
1135 /* 1130 /*