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authorKrzysztof Halasa <khc@pm.waw.pl>2007-10-16 04:29:33 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-16 12:43:19 -0400
commitee5618f4937dcbff15e504663d81a7adb3d849bf (patch)
tree3fec7a2565f4f123ab2ccd0b3243e3bf49f16b6b
parent689c9568f54747c13f287ae53956281e7cd810fa (diff)
Intel FB: obvious changes and corrections
Intel FB: obvious changes and corrections Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: <sylvain.meyer@worldonline.fr> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-rw-r--r--drivers/video/intelfb/intelfb.h5
-rw-r--r--drivers/video/intelfb/intelfbhw.c14
-rw-r--r--drivers/video/intelfb/intelfbhw.h4
3 files changed, 13 insertions, 10 deletions
diff --git a/drivers/video/intelfb/intelfb.h b/drivers/video/intelfb/intelfb.h
index 7e9d62a83472..2fe3f7def530 100644
--- a/drivers/video/intelfb/intelfb.h
+++ b/drivers/video/intelfb/intelfb.h
@@ -355,7 +355,10 @@ struct intelfb_info {
355 struct intelfb_output_rec output[MAX_OUTPUTS]; 355 struct intelfb_output_rec output[MAX_OUTPUTS];
356}; 356};
357 357
358#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G)||(dinfo->chipset == INTEL_915GM)||((dinfo)->chipset == INTEL_945G)||(dinfo->chipset==INTEL_945GM)) 358#define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G) || \
359 ((dinfo)->chipset == INTEL_915GM) || \
360 ((dinfo)->chipset == INTEL_945G) || \
361 ((dinfo)->chipset==INTEL_945GM))
359 362
360#ifndef FBIO_WAITFORVSYNC 363#ifndef FBIO_WAITFORVSYNC
361#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32) 364#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
diff --git a/drivers/video/intelfb/intelfbhw.c b/drivers/video/intelfb/intelfbhw.c
index fe38df8e2b6f..270f6552603c 100644
--- a/drivers/video/intelfb/intelfbhw.c
+++ b/drivers/video/intelfb/intelfbhw.c
@@ -434,14 +434,14 @@ void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
434 unsigned red, unsigned green, unsigned blue, 434 unsigned red, unsigned green, unsigned blue,
435 unsigned transp) 435 unsigned transp)
436{ 436{
437 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
438 PALETTE_A : PALETTE_B;
439
437#if VERBOSE > 0 440#if VERBOSE > 0
438 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n", 441 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
439 regno, red, green, blue); 442 regno, red, green, blue);
440#endif 443#endif
441 444
442 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
443 PALETTE_A : PALETTE_B;
444
445 OUTREG(palette_reg + (regno << 2), 445 OUTREG(palette_reg + (regno << 2),
446 (red << PALETTE_8_RED_SHIFT) | 446 (red << PALETTE_8_RED_SHIFT) |
447 (green << PALETTE_8_GREEN_SHIFT) | 447 (green << PALETTE_8_GREEN_SHIFT) |
@@ -1305,8 +1305,8 @@ int intelfbhw_program_mode(struct intelfb_info *dinfo,
1305 1305
1306 count = 0; 1306 count = 0;
1307 do { 1307 do {
1308 tmp_val[count%3] = INREG(0x70000); 1308 tmp_val[count % 3] = INREG(PIPEA_DSL);
1309 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2])) 1309 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))
1310 break; 1310 break;
1311 count++; 1311 count++;
1312 udelay(1); 1312 udelay(1);
@@ -2004,7 +2004,6 @@ intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
2004 2004
2005void 2005void
2006intelfbhw_disable_irq(struct intelfb_info *dinfo) { 2006intelfbhw_disable_irq(struct intelfb_info *dinfo) {
2007 u16 tmp;
2008 2007
2009 if (test_and_clear_bit(0, &dinfo->irq_flags)) { 2008 if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2010 if (dinfo->vsync.pan_display) { 2009 if (dinfo->vsync.pan_display) {
@@ -2016,8 +2015,7 @@ intelfbhw_disable_irq(struct intelfb_info *dinfo) {
2016 OUTREG16(IMR, 0xffff); 2015 OUTREG16(IMR, 0xffff);
2017 OUTREG16(IER, 0x0); 2016 OUTREG16(IER, 0x0);
2018 2017
2019 tmp = INREG16(IIR); 2018 OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */
2020 OUTREG16(IIR, tmp);
2021 spin_unlock_irq(&dinfo->int_lock); 2019 spin_unlock_irq(&dinfo->int_lock);
2022 2020
2023 free_irq(dinfo->pdev->irq, dinfo); 2021 free_irq(dinfo->pdev->irq, dinfo);
diff --git a/drivers/video/intelfb/intelfbhw.h b/drivers/video/intelfb/intelfbhw.h
index 1a4df251b540..3cbfcef83361 100644
--- a/drivers/video/intelfb/intelfbhw.h
+++ b/drivers/video/intelfb/intelfbhw.h
@@ -93,7 +93,7 @@
93#define IIR 0x20A4 93#define IIR 0x20A4
94#define IMR 0x20A8 94#define IMR 0x20A8
95#define VSYNC_PIPE_A_INTERRUPT (1 << 7) 95#define VSYNC_PIPE_A_INTERRUPT (1 << 7)
96#define PIPE_A_EVENT_INTERRUPT (1 << 4) 96#define PIPE_A_EVENT_INTERRUPT (1 << 6)
97#define VSYNC_PIPE_B_INTERRUPT (1 << 5) 97#define VSYNC_PIPE_B_INTERRUPT (1 << 5)
98#define PIPE_B_EVENT_INTERRUPT (1 << 4) 98#define PIPE_B_EVENT_INTERRUPT (1 << 4)
99#define HOST_PORT_EVENT_INTERRUPT (1 << 3) 99#define HOST_PORT_EVENT_INTERRUPT (1 << 3)
@@ -276,6 +276,8 @@
276#define DVOB_SRCDIM 0x61144 276#define DVOB_SRCDIM 0x61144
277#define DVOC_SRCDIM 0x61164 277#define DVOC_SRCDIM 0x61164
278 278
279#define PIPEA_DSL 0x70000
280#define PIPEB_DSL 0x71000
279#define PIPEACONF 0x70008 281#define PIPEACONF 0x70008
280#define PIPEBCONF 0x71008 282#define PIPEBCONF 0x71008
281#define PIPECONF_ENABLE (1 << 31) 283#define PIPECONF_ENABLE (1 << 31)