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authorAlan Cox <alan@redhat.com>2008-10-17 14:08:31 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-10-28 00:35:59 -0400
commite7c0d217cdaa837d30bc265eddac4d176969fd68 (patch)
tree72f4ccbfc074c003ac2a8d80308b715cfb269f87
parent054e5f616b5becdc096b793407dc33fe379749ac (diff)
pata_ninja32: suspend/resume support
I had assumed that the standard recovery would be sufficient for this hardware but it isn't. Fix up the other registers on resume as needed. See bug #11735 Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
-rw-r--r--drivers/ata/pata_ninja32.c43
1 files changed, 34 insertions, 9 deletions
diff --git a/drivers/ata/pata_ninja32.c b/drivers/ata/pata_ninja32.c
index 5e76f96ec7e5..4e466eae8b46 100644
--- a/drivers/ata/pata_ninja32.c
+++ b/drivers/ata/pata_ninja32.c
@@ -44,7 +44,7 @@
44#include <linux/libata.h> 44#include <linux/libata.h>
45 45
46#define DRV_NAME "pata_ninja32" 46#define DRV_NAME "pata_ninja32"
47#define DRV_VERSION "0.0.1" 47#define DRV_VERSION "0.1.1"
48 48
49 49
50/** 50/**
@@ -88,6 +88,17 @@ static struct ata_port_operations ninja32_port_ops = {
88 .set_piomode = ninja32_set_piomode, 88 .set_piomode = ninja32_set_piomode,
89}; 89};
90 90
91static void ninja32_program(void __iomem *base)
92{
93 iowrite8(0x05, base + 0x01); /* Enable interrupt lines */
94 iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */
95 iowrite8(0x01, base + 0x03); /* Unknown */
96 iowrite8(0x20, base + 0x04); /* WAIT0 */
97 iowrite8(0x8f, base + 0x05); /* Unknown */
98 iowrite8(0xa4, base + 0x1c); /* Unknown */
99 iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */
100}
101
91static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id) 102static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
92{ 103{
93 struct ata_host *host; 104 struct ata_host *host;
@@ -133,18 +144,28 @@ static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
133 ap->ioaddr.bmdma_addr = base; 144 ap->ioaddr.bmdma_addr = base;
134 ata_sff_std_ports(&ap->ioaddr); 145 ata_sff_std_ports(&ap->ioaddr);
135 146
136 iowrite8(0x05, base + 0x01); /* Enable interrupt lines */ 147 ninja32_program(base);
137 iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */
138 iowrite8(0x01, base + 0x03); /* Unknown */
139 iowrite8(0x20, base + 0x04); /* WAIT0 */
140 iowrite8(0x8f, base + 0x05); /* Unknown */
141 iowrite8(0xa4, base + 0x1c); /* Unknown */
142 iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */
143 /* FIXME: Should we disable them at remove ? */ 148 /* FIXME: Should we disable them at remove ? */
144 return ata_host_activate(host, dev->irq, ata_sff_interrupt, 149 return ata_host_activate(host, dev->irq, ata_sff_interrupt,
145 IRQF_SHARED, &ninja32_sht); 150 IRQF_SHARED, &ninja32_sht);
146} 151}
147 152
153#ifdef CONFIG_PM
154
155static int ninja32_reinit_one(struct pci_dev *pdev)
156{
157 struct ata_host *host = dev_get_drvdata(&pdev->dev);
158 int rc;
159
160 rc = ata_pci_device_do_resume(pdev);
161 if (rc)
162 return rc;
163 ninja32_program(host->iomap[0]);
164 ata_host_resume(host);
165 return 0;
166}
167#endif
168
148static const struct pci_device_id ninja32[] = { 169static const struct pci_device_id ninja32[] = {
149 { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 170 { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 171 { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
@@ -155,7 +176,11 @@ static struct pci_driver ninja32_pci_driver = {
155 .name = DRV_NAME, 176 .name = DRV_NAME,
156 .id_table = ninja32, 177 .id_table = ninja32,
157 .probe = ninja32_init_one, 178 .probe = ninja32_init_one,
158 .remove = ata_pci_remove_one 179 .remove = ata_pci_remove_one,
180#ifdef CONFIG_PM
181 .suspend = ata_pci_device_suspend,
182 .resume = ninja32_reinit_one,
183#endif
159}; 184};
160 185
161static int __init ninja32_init(void) 186static int __init ninja32_init(void)