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authorRalf Baechle <ralf@linux-mips.org>2007-10-14 09:02:26 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-16 13:23:45 -0400
commitdd67b1556ebea118b40986cdb8e70874b5454442 (patch)
tree167320a78cb4afb05d841027d2860f7c38346470
parent65a6ec0d72a07f16719e9b7a96e1c4bae044b591 (diff)
[MIPS] IP32: Fix build by conversion to irq_cpu.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/Kconfig1
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c162
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c2
-rw-r--r--include/asm-mips/ip32/ip32_ints.h158
4 files changed, 163 insertions, 160 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f943736541cb..f921235239f9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -410,6 +410,7 @@ config SGI_IP32
410 select BOOT_ELF32 410 select BOOT_ELF32
411 select DMA_NONCOHERENT 411 select DMA_NONCOHERENT
412 select HW_HAS_PCI 412 select HW_HAS_PCI
413 select IRQ_CPU
413 select R5000_CPU_SCACHE 414 select R5000_CPU_SCACHE
414 select RM7000_CPU_SCACHE 415 select RM7000_CPU_SCACHE
415 select SYS_HAS_CPU_R5000 416 select SYS_HAS_CPU_R5000
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 7f4b793c3df3..7e8094f617bf 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -20,6 +20,7 @@
20#include <linux/random.h> 20#include <linux/random.h>
21#include <linux/sched.h> 21#include <linux/sched.h>
22 22
23#include <asm/irq_cpu.h>
23#include <asm/mipsregs.h> 24#include <asm/mipsregs.h>
24#include <asm/signal.h> 25#include <asm/signal.h>
25#include <asm/system.h> 26#include <asm/system.h>
@@ -46,7 +47,8 @@ static void inline flush_mace_bus(void)
46#define DBG(x...) 47#define DBG(x...)
47#endif 48#endif
48 49
49/* O2 irq map 50/*
51 * O2 irq map
50 * 52 *
51 * IP0 -> software (ignored) 53 * IP0 -> software (ignored)
52 * IP1 -> software (ignored) 54 * IP1 -> software (ignored)
@@ -55,60 +57,60 @@ static void inline flush_mace_bus(void)
55 * IP4 -> (irq2) X unknown 57 * IP4 -> (irq2) X unknown
56 * IP5 -> (irq3) X unknown 58 * IP5 -> (irq3) X unknown
57 * IP6 -> (irq4) X unknown 59 * IP6 -> (irq4) X unknown
58 * IP7 -> (irq5) 0 CPU count/compare timer (system timer) 60 * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
59 * 61 *
60 * crime: (C) 62 * crime: (C)
61 * 63 *
62 * CRIME_INT_STAT 31:0: 64 * CRIME_INT_STAT 31:0:
63 * 65 *
64 * 0 -> 1 Video in 1 66 * 0 -> 8 Video in 1
65 * 1 -> 2 Video in 2 67 * 1 -> 9 Video in 2
66 * 2 -> 3 Video out 68 * 2 -> 10 Video out
67 * 3 -> 4 Mace ethernet 69 * 3 -> 11 Mace ethernet
68 * 4 -> S SuperIO sub-interrupt 70 * 4 -> S SuperIO sub-interrupt
69 * 5 -> M Miscellaneous sub-interrupt 71 * 5 -> M Miscellaneous sub-interrupt
70 * 6 -> A Audio sub-interrupt 72 * 6 -> A Audio sub-interrupt
71 * 7 -> 8 PCI bridge errors 73 * 7 -> 15 PCI bridge errors
72 * 8 -> 9 PCI SCSI aic7xxx 0 74 * 8 -> 16 PCI SCSI aic7xxx 0
73 * 9 -> 10 PCI SCSI aic7xxx 1 75 * 9 -> 17 PCI SCSI aic7xxx 1
74 * 10 -> 11 PCI slot 0 76 * 10 -> 18 PCI slot 0
75 * 11 -> 12 unused (PCI slot 1) 77 * 11 -> 19 unused (PCI slot 1)
76 * 12 -> 13 unused (PCI slot 2) 78 * 12 -> 20 unused (PCI slot 2)
77 * 13 -> 14 unused (PCI shared 0) 79 * 13 -> 21 unused (PCI shared 0)
78 * 14 -> 15 unused (PCI shared 1) 80 * 14 -> 22 unused (PCI shared 1)
79 * 15 -> 16 unused (PCI shared 2) 81 * 15 -> 23 unused (PCI shared 2)
80 * 16 -> 17 GBE0 (E) 82 * 16 -> 24 GBE0 (E)
81 * 17 -> 18 GBE1 (E) 83 * 17 -> 25 GBE1 (E)
82 * 18 -> 19 GBE2 (E) 84 * 18 -> 26 GBE2 (E)
83 * 19 -> 20 GBE3 (E) 85 * 19 -> 27 GBE3 (E)
84 * 20 -> 21 CPU errors 86 * 20 -> 28 CPU errors
85 * 21 -> 22 Memory errors 87 * 21 -> 29 Memory errors
86 * 22 -> 23 RE empty edge (E) 88 * 22 -> 30 RE empty edge (E)
87 * 23 -> 24 RE full edge (E) 89 * 23 -> 31 RE full edge (E)
88 * 24 -> 25 RE idle edge (E) 90 * 24 -> 32 RE idle edge (E)
89 * 25 -> 26 RE empty level 91 * 25 -> 33 RE empty level
90 * 26 -> 27 RE full level 92 * 26 -> 34 RE full level
91 * 27 -> 28 RE idle level 93 * 27 -> 35 RE idle level
92 * 28 -> 29 unused (software 0) (E) 94 * 28 -> 36 unused (software 0) (E)
93 * 29 -> 30 unused (software 1) (E) 95 * 29 -> 37 unused (software 1) (E)
94 * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E) 96 * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
95 * 31 -> 32 VICE 97 * 31 -> 39 VICE
96 * 98 *
97 * S, M, A: Use the MACE ISA interrupt register 99 * S, M, A: Use the MACE ISA interrupt register
98 * MACE_ISA_INT_STAT 31:0 100 * MACE_ISA_INT_STAT 31:0
99 * 101 *
100 * 0-7 -> 33-40 Audio 102 * 0-7 -> 40-47 Audio
101 * 8 -> 41 RTC 103 * 8 -> 48 RTC
102 * 9 -> 42 Keyboard 104 * 9 -> 49 Keyboard
103 * 10 -> X Keyboard polled 105 * 10 -> X Keyboard polled
104 * 11 -> 44 Mouse 106 * 11 -> 51 Mouse
105 * 12 -> X Mouse polled 107 * 12 -> X Mouse polled
106 * 13-15 -> 46-48 Count/compare timers 108 * 13-15 -> 53-55 Count/compare timers
107 * 16-19 -> 49-52 Parallel (16 E) 109 * 16-19 -> 56-59 Parallel (16 E)
108 * 20-25 -> 53-58 Serial 1 (22 E) 110 * 20-25 -> 60-62 Serial 1 (22 E)
109 * 26-31 -> 59-64 Serial 2 (28 E) 111 * 26-31 -> 66-71 Serial 2 (28 E)
110 * 112 *
111 * Note that this means IRQs 5-7, 43, and 45 do not exist. This is a 113 * Note that this means IRQs 12-14, 50, and 52 do not exist. This is a
112 * different IRQ map than IRIX uses, but that's OK as Linux irq handling 114 * different IRQ map than IRIX uses, but that's OK as Linux irq handling
113 * is quite different anyway. 115 * is quite different anyway.
114 */ 116 */
@@ -131,36 +133,6 @@ struct irqaction cpuerr_irq = {
131}; 133};
132 134
133/* 135/*
134 * For interrupts wired from a single device to the CPU. Only the clock
135 * uses this it seems, which is IRQ 0 and IP7.
136 */
137
138static void enable_cpu_irq(unsigned int irq)
139{
140 set_c0_status(STATUSF_IP7);
141}
142
143static void disable_cpu_irq(unsigned int irq)
144{
145 clear_c0_status(STATUSF_IP7);
146}
147
148static void end_cpu_irq(unsigned int irq)
149{
150 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
151 enable_cpu_irq(irq);
152}
153
154static struct irq_chip ip32_cpu_interrupt = {
155 .name = "IP32 CPU",
156 .ack = disable_cpu_irq,
157 .mask = disable_cpu_irq,
158 .mask_ack = disable_cpu_irq,
159 .unmask = enable_cpu_irq,
160 .end = end_cpu_irq,
161};
162
163/*
164 * This is for pure CRIME interrupts - ie not MACE. The advantage? 136 * This is for pure CRIME interrupts - ie not MACE. The advantage?
165 * We get to split the register in half and do faster lookups. 137 * We get to split the register in half and do faster lookups.
166 */ 138 */
@@ -422,15 +394,23 @@ static void ip32_irq0(void)
422 uint64_t crime_int; 394 uint64_t crime_int;
423 int irq = 0; 395 int irq = 0;
424 396
397 /*
398 * Sanity check interrupt numbering enum.
399 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
400 * chained.
401 */
402 BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
403 BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
404
425 crime_int = crime->istat & crime_mask; 405 crime_int = crime->istat & crime_mask;
426 irq = __ffs(crime_int); 406 irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
427 crime_int = 1 << irq; 407 crime_int = 1 << irq;
428 408
429 if (crime_int & CRIME_MACEISA_INT_MASK) { 409 if (crime_int & CRIME_MACEISA_INT_MASK) {
430 unsigned long mace_int = mace->perif.ctrl.istat; 410 unsigned long mace_int = mace->perif.ctrl.istat;
431 irq = __ffs(mace_int & maceisa_mask) + 32; 411 irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
432 } 412 }
433 irq++; 413
434 DBG("*irq %u*\n", irq); 414 DBG("*irq %u*\n", irq);
435 do_IRQ(irq); 415 do_IRQ(irq);
436} 416}
@@ -457,7 +437,7 @@ static void ip32_irq4(void)
457 437
458static void ip32_irq5(void) 438static void ip32_irq5(void)
459{ 439{
460 do_IRQ(IP32_R4K_TIMER_IRQ); 440 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
461} 441}
462 442
463asmlinkage void plat_irq_dispatch(void) 443asmlinkage void plat_irq_dispatch(void)
@@ -490,21 +470,25 @@ void __init arch_init_irq(void)
490 mace->perif.ctrl.istat = 0; 470 mace->perif.ctrl.istat = 0;
491 mace->perif.ctrl.imask = 0; 471 mace->perif.ctrl.imask = 0;
492 472
493 for (irq = 0; irq <= IP32_IRQ_MAX; irq++) { 473 mips_cpu_irq_init();
494 struct irq_chip *controller; 474 for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) {
495 475 struct irq_chip *chip;
496 if (irq == IP32_R4K_TIMER_IRQ) 476
497 controller = &ip32_cpu_interrupt; 477 switch (irq) {
498 else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ) 478 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
499 controller = &ip32_mace_interrupt; 479 chip = &ip32_mace_interrupt;
500 else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ) 480 break;
501 controller = &ip32_macepci_interrupt; 481 case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ:
502 else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ) 482 chip = &ip32_macepci_interrupt;
503 controller = &ip32_crime_interrupt; 483 break;
504 else 484 case CRIME_GBE0_IRQ ... CRIME_VICE_IRQ:
505 controller = &ip32_maceisa_interrupt; 485 chip = &ip32_crime_interrupt;
506 486 break;
507 set_irq_chip(irq, controller); 487 default:
488 chip = &ip32_maceisa_interrupt;
489 }
490
491 set_irq_chip(irq, chip);
508 } 492 }
509 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 493 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
510 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 494 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index 4125a5ba119e..fc75bfcb0c0e 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -83,7 +83,7 @@ void __init plat_time_init(void)
83void __init plat_timer_setup(struct irqaction *irq) 83void __init plat_timer_setup(struct irqaction *irq)
84{ 84{
85 irq->handler = no_action; 85 irq->handler = no_action;
86 setup_irq(IP32_R4K_TIMER_IRQ, irq); 86 setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
87} 87}
88 88
89void __init plat_mem_setup(void) 89void __init plat_mem_setup(void)
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index c3c280e3d591..042f821899a8 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -9,86 +9,104 @@
9#ifndef __ASM_IP32_INTS_H 9#ifndef __ASM_IP32_INTS_H
10#define __ASM_IP32_INTS_H 10#define __ASM_IP32_INTS_H
11 11
12#include <asm/irq.h>
13
12/* 14/*
13 * This list reflects the assignment of interrupt numbers to 15 * This list reflects the assignment of interrupt numbers to
14 * interrupting events. Order is fairly irrelevant to handling 16 * interrupting events. Order is fairly irrelevant to handling
15 * priority. This differs from irix. 17 * priority. This differs from irix.
16 */ 18 */
17 19
18/* CPU */ 20enum ip32_irq_no {
19#define IP32_R4K_TIMER_IRQ 0 21 /*
22 * CPU interrupts are 0 ... 7
23 */
20 24
21/* MACE */ 25 /*
22#define MACE_VID_IN1_IRQ 1 26 * MACE
23#define MACE_VID_IN2_IRQ 2 27 */
24#define MACE_VID_OUT_IRQ 3 28 MACE_VID_IN1_IRQ = MIPS_CPU_IRQ_BASE + 8,
25#define MACE_ETHERNET_IRQ 4 29 MACE_VID_IN2_IRQ,
26/* SUPERIO, MISC, and AUDIO are MACEISA */ 30 MACE_VID_OUT_IRQ,
27#define MACE_PCI_BRIDGE_IRQ 8 31 MACE_ETHERNET_IRQ,
32 /* SUPERIO, MISC, and AUDIO are MACEISA */
33 __MACE_SUPERIO,
34 __MACE_MISC,
35 __MACE_AUDIO,
36 MACE_PCI_BRIDGE_IRQ,
28 37
29/* MACEPCI */ 38 /*
30#define MACEPCI_SCSI0_IRQ 9 39 * MACEPCI
31#define MACEPCI_SCSI1_IRQ 10 40 */
32#define MACEPCI_SLOT0_IRQ 11 41 MACEPCI_SCSI0_IRQ,
33#define MACEPCI_SLOT1_IRQ 12 42 MACEPCI_SCSI1_IRQ,
34#define MACEPCI_SLOT2_IRQ 13 43 MACEPCI_SLOT0_IRQ,
35#define MACEPCI_SHARED0_IRQ 14 44 MACEPCI_SLOT1_IRQ,
36#define MACEPCI_SHARED1_IRQ 15 45 MACEPCI_SLOT2_IRQ,
37#define MACEPCI_SHARED2_IRQ 16 46 MACEPCI_SHARED0_IRQ,
47 MACEPCI_SHARED1_IRQ,
48 MACEPCI_SHARED2_IRQ,
38 49
39/* CRIME */ 50 /*
40#define CRIME_GBE0_IRQ 17 51 * CRIME
41#define CRIME_GBE1_IRQ 18 52 */
42#define CRIME_GBE2_IRQ 19 53 CRIME_GBE0_IRQ,
43#define CRIME_GBE3_IRQ 20 54 CRIME_GBE1_IRQ,
44#define CRIME_CPUERR_IRQ 21 55 CRIME_GBE2_IRQ,
45#define CRIME_MEMERR_IRQ 22 56 CRIME_GBE3_IRQ,
46#define CRIME_RE_EMPTY_E_IRQ 23 57 CRIME_CPUERR_IRQ,
47#define CRIME_RE_FULL_E_IRQ 24 58 CRIME_MEMERR_IRQ,
48#define CRIME_RE_IDLE_E_IRQ 25 59 CRIME_RE_EMPTY_E_IRQ,
49#define CRIME_RE_EMPTY_L_IRQ 26 60 CRIME_RE_FULL_E_IRQ,
50#define CRIME_RE_FULL_L_IRQ 27 61 CRIME_RE_IDLE_E_IRQ,
51#define CRIME_RE_IDLE_L_IRQ 28 62 CRIME_RE_EMPTY_L_IRQ,
52#define CRIME_SOFT0_IRQ 29 63 CRIME_RE_FULL_L_IRQ,
53#define CRIME_SOFT1_IRQ 30 64 CRIME_RE_IDLE_L_IRQ,
54#define CRIME_SOFT2_IRQ 31 65 CRIME_SOFT0_IRQ,
55#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ 66 CRIME_SOFT1_IRQ,
56#define CRIME_VICE_IRQ 32 67 CRIME_SOFT2_IRQ,
68 CRIME_SYSCORERR_IRQ = CRIME_SOFT2_IRQ,
69 CRIME_VICE_IRQ,
57 70
58/* MACEISA */ 71 /*
59#define MACEISA_AUDIO_SW_IRQ 33 72 * MACEISA
60#define MACEISA_AUDIO_SC_IRQ 34 73 */
61#define MACEISA_AUDIO1_DMAT_IRQ 35 74 MACEISA_AUDIO_SW_IRQ,
62#define MACEISA_AUDIO1_OF_IRQ 36 75 MACEISA_AUDIO_SC_IRQ,
63#define MACEISA_AUDIO2_DMAT_IRQ 37 76 MACEISA_AUDIO1_DMAT_IRQ,
64#define MACEISA_AUDIO2_MERR_IRQ 38 77 MACEISA_AUDIO1_OF_IRQ,
65#define MACEISA_AUDIO3_DMAT_IRQ 39 78 MACEISA_AUDIO2_DMAT_IRQ,
66#define MACEISA_AUDIO3_MERR_IRQ 40 79 MACEISA_AUDIO2_MERR_IRQ,
67#define MACEISA_RTC_IRQ 41 80 MACEISA_AUDIO3_DMAT_IRQ,
68#define MACEISA_KEYB_IRQ 42 81 MACEISA_AUDIO3_MERR_IRQ,
69/* MACEISA_KEYB_POLL is not an IRQ */ 82 MACEISA_RTC_IRQ,
70#define MACEISA_MOUSE_IRQ 44 83 MACEISA_KEYB_IRQ,
71/* MACEISA_MOUSE_POLL is not an IRQ */ 84 /* MACEISA_KEYB_POLL is not an IRQ */
72#define MACEISA_TIMER0_IRQ 46 85 __MACEISA_KEYB_POLL,
73#define MACEISA_TIMER1_IRQ 47 86 MACEISA_MOUSE_IRQ,
74#define MACEISA_TIMER2_IRQ 48 87 /* MACEISA_MOUSE_POLL is not an IRQ */
75#define MACEISA_PARALLEL_IRQ 49 88 __MACEISA_MOUSE_POLL,
76#define MACEISA_PAR_CTXA_IRQ 50 89 MACEISA_TIMER0_IRQ,
77#define MACEISA_PAR_CTXB_IRQ 51 90 MACEISA_TIMER1_IRQ,
78#define MACEISA_PAR_MERR_IRQ 52 91 MACEISA_TIMER2_IRQ,
79#define MACEISA_SERIAL1_IRQ 53 92 MACEISA_PARALLEL_IRQ,
80#define MACEISA_SERIAL1_TDMAT_IRQ 54 93 MACEISA_PAR_CTXA_IRQ,
81#define MACEISA_SERIAL1_TDMAPR_IRQ 55 94 MACEISA_PAR_CTXB_IRQ,
82#define MACEISA_SERIAL1_TDMAME_IRQ 56 95 MACEISA_PAR_MERR_IRQ,
83#define MACEISA_SERIAL1_RDMAT_IRQ 57 96 MACEISA_SERIAL1_IRQ,
84#define MACEISA_SERIAL1_RDMAOR_IRQ 58 97 MACEISA_SERIAL1_TDMAT_IRQ,
85#define MACEISA_SERIAL2_IRQ 59 98 MACEISA_SERIAL1_TDMAPR_IRQ,
86#define MACEISA_SERIAL2_TDMAT_IRQ 60 99 MACEISA_SERIAL1_TDMAME_IRQ,
87#define MACEISA_SERIAL2_TDMAPR_IRQ 61 100 MACEISA_SERIAL1_RDMAT_IRQ,
88#define MACEISA_SERIAL2_TDMAME_IRQ 62 101 MACEISA_SERIAL1_RDMAOR_IRQ,
89#define MACEISA_SERIAL2_RDMAT_IRQ 63 102 MACEISA_SERIAL2_IRQ,
90#define MACEISA_SERIAL2_RDMAOR_IRQ 64 103 MACEISA_SERIAL2_TDMAT_IRQ,
104 MACEISA_SERIAL2_TDMAPR_IRQ,
105 MACEISA_SERIAL2_TDMAME_IRQ,
106 MACEISA_SERIAL2_RDMAT_IRQ,
107 MACEISA_SERIAL2_RDMAOR_IRQ,
91 108
92#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ 109 IP32_IRQ_MAX = MACEISA_SERIAL2_RDMAOR_IRQ
110};
93 111
94#endif /* __ASM_IP32_INTS_H */ 112#endif /* __ASM_IP32_INTS_H */