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authorRandolph Chung <tausq@debian.org>2006-12-12 08:51:54 -0500
committerKyle McMartin <kyle@athena.road.mcmartin.ca>2007-02-17 00:41:30 -0500
commitd6ce8626dbc7d277d29b62e31c24ce777c60546b (patch)
tree1078d6aa204de1bc5d64a9595c7c1599fcd6eb52
parent592ac93a607109e0643da6c23ae07ac749e973b1 (diff)
[PARISC] Clean up the cache and tlb headers
No changes in functionality. Signed-off-by: Randolph Chung <tausq@debian.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
-rw-r--r--arch/parisc/kernel/cache.c186
-rw-r--r--arch/parisc/kernel/traps.c5
-rw-r--r--include/asm-parisc/cache.h29
-rw-r--r--include/asm-parisc/cacheflush.h177
-rw-r--r--include/asm-parisc/tlbflush.h30
5 files changed, 221 insertions, 206 deletions
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 0be51e92a2fc..75582c5a3211 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -68,16 +68,6 @@ flush_cache_all_local(void)
68} 68}
69EXPORT_SYMBOL(flush_cache_all_local); 69EXPORT_SYMBOL(flush_cache_all_local);
70 70
71/* flushes EVERYTHING (tlb & cache) */
72
73void
74flush_all_caches(void)
75{
76 flush_cache_all();
77 flush_tlb_all();
78}
79EXPORT_SYMBOL(flush_all_caches);
80
81void 71void
82update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) 72update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
83{ 73{
@@ -270,6 +260,83 @@ void disable_sr_hashing(void)
270 panic("SpaceID hashing is still on!\n"); 260 panic("SpaceID hashing is still on!\n");
271} 261}
272 262
263/* Simple function to work out if we have an existing address translation
264 * for a user space vma. */
265static inline int translation_exists(struct vm_area_struct *vma,
266 unsigned long addr, unsigned long pfn)
267{
268 pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
269 pmd_t *pmd;
270 pte_t pte;
271
272 if(pgd_none(*pgd))
273 return 0;
274
275 pmd = pmd_offset(pgd, addr);
276 if(pmd_none(*pmd) || pmd_bad(*pmd))
277 return 0;
278
279 /* We cannot take the pte lock here: flush_cache_page is usually
280 * called with pte lock already held. Whereas flush_dcache_page
281 * takes flush_dcache_mmap_lock, which is lower in the hierarchy:
282 * the vma itself is secure, but the pte might come or go racily.
283 */
284 pte = *pte_offset_map(pmd, addr);
285 /* But pte_unmap() does nothing on this architecture */
286
287 /* Filter out coincidental file entries and swap entries */
288 if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT)))
289 return 0;
290
291 return pte_pfn(pte) == pfn;
292}
293
294/* Private function to flush a page from the cache of a non-current
295 * process. cr25 contains the Page Directory of the current user
296 * process; we're going to hijack both it and the user space %sr3 to
297 * temporarily make the non-current process current. We have to do
298 * this because cache flushing may cause a non-access tlb miss which
299 * the handlers have to fill in from the pgd of the non-current
300 * process. */
301static inline void
302flush_user_cache_page_non_current(struct vm_area_struct *vma,
303 unsigned long vmaddr)
304{
305 /* save the current process space and pgd */
306 unsigned long space = mfsp(3), pgd = mfctl(25);
307
308 /* we don't mind taking interrups since they may not
309 * do anything with user space, but we can't
310 * be preempted here */
311 preempt_disable();
312
313 /* make us current */
314 mtctl(__pa(vma->vm_mm->pgd), 25);
315 mtsp(vma->vm_mm->context, 3);
316
317 flush_user_dcache_page(vmaddr);
318 if(vma->vm_flags & VM_EXEC)
319 flush_user_icache_page(vmaddr);
320
321 /* put the old current process back */
322 mtsp(space, 3);
323 mtctl(pgd, 25);
324 preempt_enable();
325}
326
327
328static inline void
329__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
330{
331 if (likely(vma->vm_mm->context == mfsp(3))) {
332 flush_user_dcache_page(vmaddr);
333 if (vma->vm_flags & VM_EXEC)
334 flush_user_icache_page(vmaddr);
335 } else {
336 flush_user_cache_page_non_current(vma, vmaddr);
337 }
338}
339
273void flush_dcache_page(struct page *page) 340void flush_dcache_page(struct page *page)
274{ 341{
275 struct address_space *mapping = page_mapping(page); 342 struct address_space *mapping = page_mapping(page);
@@ -342,7 +409,7 @@ void clear_user_page_asm(void *page, unsigned long vaddr)
342#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */ 409#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
343int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD; 410int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
344 411
345void parisc_setup_cache_timing(void) 412void __init parisc_setup_cache_timing(void)
346{ 413{
347 unsigned long rangetime, alltime; 414 unsigned long rangetime, alltime;
348 unsigned long size; 415 unsigned long size;
@@ -366,6 +433,9 @@ void parisc_setup_cache_timing(void)
366 if (!parisc_cache_flush_threshold) 433 if (!parisc_cache_flush_threshold)
367 parisc_cache_flush_threshold = FLUSH_THRESHOLD; 434 parisc_cache_flush_threshold = FLUSH_THRESHOLD;
368 435
436 if (parisc_cache_flush_threshold > cache_info.dc_size)
437 parisc_cache_flush_threshold = cache_info.dc_size;
438
369 printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus()); 439 printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
370} 440}
371 441
@@ -410,3 +480,97 @@ void kunmap_parisc(void *addr)
410} 480}
411EXPORT_SYMBOL(kunmap_parisc); 481EXPORT_SYMBOL(kunmap_parisc);
412#endif 482#endif
483
484void __flush_tlb_range(unsigned long sid, unsigned long start,
485 unsigned long end)
486{
487 unsigned long npages;
488
489 npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
490 if (npages >= 512) /* 2MB of space: arbitrary, should be tuned */
491 flush_tlb_all();
492 else {
493 mtsp(sid, 1);
494 purge_tlb_start();
495 if (split_tlb) {
496 while (npages--) {
497 pdtlb(start);
498 pitlb(start);
499 start += PAGE_SIZE;
500 }
501 } else {
502 while (npages--) {
503 pdtlb(start);
504 start += PAGE_SIZE;
505 }
506 }
507 purge_tlb_end();
508 }
509}
510
511static void cacheflush_h_tmp_function(void *dummy)
512{
513 flush_cache_all_local();
514}
515
516void flush_cache_all(void)
517{
518 on_each_cpu(cacheflush_h_tmp_function, NULL, 1, 1);
519}
520
521void flush_cache_mm(struct mm_struct *mm)
522{
523#ifdef CONFIG_SMP
524 flush_cache_all();
525#else
526 flush_cache_all_local();
527#endif
528}
529
530void
531flush_user_dcache_range(unsigned long start, unsigned long end)
532{
533 if ((end - start) < parisc_cache_flush_threshold)
534 flush_user_dcache_range_asm(start,end);
535 else
536 flush_data_cache();
537}
538
539void
540flush_user_icache_range(unsigned long start, unsigned long end)
541{
542 if ((end - start) < parisc_cache_flush_threshold)
543 flush_user_icache_range_asm(start,end);
544 else
545 flush_instruction_cache();
546}
547
548
549void flush_cache_range(struct vm_area_struct *vma,
550 unsigned long start, unsigned long end)
551{
552 int sr3;
553
554 if (!vma->vm_mm->context) {
555 BUG();
556 return;
557 }
558
559 sr3 = mfsp(3);
560 if (vma->vm_mm->context == sr3) {
561 flush_user_dcache_range(start,end);
562 flush_user_icache_range(start,end);
563 } else {
564 flush_cache_all();
565 }
566}
567
568void
569flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
570{
571 BUG_ON(!vma->vm_mm->context);
572
573 if (likely(translation_exists(vma, vmaddr, pfn)))
574 __flush_cache_page(vma, vmaddr);
575
576}
diff --git a/arch/parisc/kernel/traps.c b/arch/parisc/kernel/traps.c
index 65cd6ca32fed..fa0811295acc 100644
--- a/arch/parisc/kernel/traps.c
+++ b/arch/parisc/kernel/traps.c
@@ -39,6 +39,8 @@
39#include <asm/pdc.h> 39#include <asm/pdc.h>
40#include <asm/pdc_chassis.h> 40#include <asm/pdc_chassis.h>
41#include <asm/unwind.h> 41#include <asm/unwind.h>
42#include <asm/tlbflush.h>
43#include <asm/cacheflush.h>
42 44
43#include "../math-emu/math-emu.h" /* for handle_fpe() */ 45#include "../math-emu/math-emu.h" /* for handle_fpe() */
44 46
@@ -554,7 +556,8 @@ void handle_interruption(int code, struct pt_regs *regs)
554 /* Low-priority machine check */ 556 /* Low-priority machine check */
555 pdc_chassis_send_status(PDC_CHASSIS_DIRECT_LPMC); 557 pdc_chassis_send_status(PDC_CHASSIS_DIRECT_LPMC);
556 558
557 flush_all_caches(); 559 flush_cache_all();
560 flush_tlb_all();
558 cpu_lpmc(5, regs); 561 cpu_lpmc(5, regs);
559 return; 562 return;
560 563
diff --git a/include/asm-parisc/cache.h b/include/asm-parisc/cache.h
index 7d22fa206fc4..32c2cca74345 100644
--- a/include/asm-parisc/cache.h
+++ b/include/asm-parisc/cache.h
@@ -30,31 +30,11 @@
30 30
31#define __read_mostly __attribute__((__section__(".data.read_mostly"))) 31#define __read_mostly __attribute__((__section__(".data.read_mostly")))
32 32
33extern void flush_data_cache_local(void *); /* flushes local data-cache only */ 33void parisc_cache_init(void); /* initializes cache-flushing */
34extern void flush_instruction_cache_local(void *); /* flushes local code-cache only */ 34void disable_sr_hashing_asm(int); /* low level support for above */
35#ifdef CONFIG_SMP 35void disable_sr_hashing(void); /* turns off space register hashing */
36extern void flush_data_cache(void); /* flushes data-cache only (all processors) */ 36void free_sid(unsigned long);
37extern void flush_instruction_cache(void); /* flushes i-cache only (all processors) */
38#else
39#define flush_data_cache() flush_data_cache_local(NULL)
40#define flush_instruction_cache() flush_instruction_cache_local(NULL)
41#endif
42
43extern void parisc_cache_init(void); /* initializes cache-flushing */
44extern void flush_all_caches(void); /* flush everything (tlb & cache) */
45extern int get_cache_info(char *);
46extern void flush_user_icache_range_asm(unsigned long, unsigned long);
47extern void flush_kernel_icache_range_asm(unsigned long, unsigned long);
48extern void flush_user_dcache_range_asm(unsigned long, unsigned long);
49extern void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
50extern void flush_kernel_dcache_page_asm(void *);
51extern void flush_kernel_icache_page(void *);
52extern void disable_sr_hashing(void); /* turns off space register hashing */
53extern void disable_sr_hashing_asm(int); /* low level support for above */
54extern void free_sid(unsigned long);
55unsigned long alloc_sid(void); 37unsigned long alloc_sid(void);
56extern void flush_user_dcache_page(unsigned long);
57extern void flush_user_icache_page(unsigned long);
58 38
59struct seq_file; 39struct seq_file;
60extern void show_cache_info(struct seq_file *m); 40extern void show_cache_info(struct seq_file *m);
@@ -63,6 +43,7 @@ extern int split_tlb;
63extern int dcache_stride; 43extern int dcache_stride;
64extern int icache_stride; 44extern int icache_stride;
65extern struct pdc_cache_info cache_info; 45extern struct pdc_cache_info cache_info;
46void parisc_setup_cache_timing(void);
66 47
67#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr)); 48#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
68#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr)); 49#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
diff --git a/include/asm-parisc/cacheflush.h b/include/asm-parisc/cacheflush.h
index a799dd8ef395..ed433da216db 100644
--- a/include/asm-parisc/cacheflush.h
+++ b/include/asm-parisc/cacheflush.h
@@ -2,60 +2,44 @@
2#define _PARISC_CACHEFLUSH_H 2#define _PARISC_CACHEFLUSH_H
3 3
4#include <linux/mm.h> 4#include <linux/mm.h>
5#include <asm/cache.h> /* for flush_user_dcache_range_asm() proto */
6 5
7/* The usual comment is "Caches aren't brain-dead on the <architecture>". 6/* The usual comment is "Caches aren't brain-dead on the <architecture>".
8 * Unfortunately, that doesn't apply to PA-RISC. */ 7 * Unfortunately, that doesn't apply to PA-RISC. */
9 8
10/* Cache flush operations */ 9/* Internal implementation */
11 10void flush_data_cache_local(void *); /* flushes local data-cache only */
11void flush_instruction_cache_local(void *); /* flushes local code-cache only */
12#ifdef CONFIG_SMP 12#ifdef CONFIG_SMP
13#define flush_cache_mm(mm) flush_cache_all() 13void flush_data_cache(void); /* flushes data-cache only (all processors) */
14void flush_instruction_cache(void); /* flushes i-cache only (all processors) */
14#else 15#else
15#define flush_cache_mm(mm) flush_cache_all_local() 16#define flush_data_cache() flush_data_cache_local(NULL)
17#define flush_instruction_cache() flush_instruction_cache_local(NULL)
16#endif 18#endif
17 19
18#define flush_cache_dup_mm(mm) flush_cache_mm(mm) 20#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
19 21
20#define flush_kernel_dcache_range(start,size) \ 22void flush_user_icache_range_asm(unsigned long, unsigned long);
21 flush_kernel_dcache_range_asm((start), (start)+(size)); 23void flush_kernel_icache_range_asm(unsigned long, unsigned long);
24void flush_user_dcache_range_asm(unsigned long, unsigned long);
25void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
26void flush_kernel_dcache_page_asm(void *);
27void flush_kernel_icache_page(void *);
28void flush_user_dcache_page(unsigned long);
29void flush_user_icache_page(unsigned long);
22 30
23extern void flush_cache_all_local(void); 31/* Cache flush operations */
24 32
25static inline void cacheflush_h_tmp_function(void *dummy) 33void flush_cache_all_local(void);
26{ 34void flush_cache_all(void);
27 flush_cache_all_local(); 35void flush_cache_mm(struct mm_struct *mm);
28}
29 36
30static inline void flush_cache_all(void) 37#define flush_kernel_dcache_range(start,size) \
31{ 38 flush_kernel_dcache_range_asm((start), (start)+(size));
32 on_each_cpu(cacheflush_h_tmp_function, NULL, 1, 1);
33}
34 39
35#define flush_cache_vmap(start, end) flush_cache_all() 40#define flush_cache_vmap(start, end) flush_cache_all()
36#define flush_cache_vunmap(start, end) flush_cache_all() 41#define flush_cache_vunmap(start, end) flush_cache_all()
37 42
38extern int parisc_cache_flush_threshold;
39void parisc_setup_cache_timing(void);
40
41static inline void
42flush_user_dcache_range(unsigned long start, unsigned long end)
43{
44 if ((end - start) < parisc_cache_flush_threshold)
45 flush_user_dcache_range_asm(start,end);
46 else
47 flush_data_cache();
48}
49
50static inline void
51flush_user_icache_range(unsigned long start, unsigned long end)
52{
53 if ((end - start) < parisc_cache_flush_threshold)
54 flush_user_icache_range_asm(start,end);
55 else
56 flush_instruction_cache();
57}
58
59extern void flush_dcache_page(struct page *page); 43extern void flush_dcache_page(struct page *page);
60 44
61#define flush_dcache_mmap_lock(mapping) \ 45#define flush_dcache_mmap_lock(mapping) \
@@ -63,9 +47,15 @@ extern void flush_dcache_page(struct page *page);
63#define flush_dcache_mmap_unlock(mapping) \ 47#define flush_dcache_mmap_unlock(mapping) \
64 write_unlock_irq(&(mapping)->tree_lock) 48 write_unlock_irq(&(mapping)->tree_lock)
65 49
66#define flush_icache_page(vma,page) do { flush_kernel_dcache_page(page); flush_kernel_icache_page(page_address(page)); } while (0) 50#define flush_icache_page(vma,page) do { \
51 flush_kernel_dcache_page(page); \
52 flush_kernel_icache_page(page_address(page)); \
53} while (0)
67 54
68#define flush_icache_range(s,e) do { flush_kernel_dcache_range_asm(s,e); flush_kernel_icache_range_asm(s,e); } while (0) 55#define flush_icache_range(s,e) do { \
56 flush_kernel_dcache_range_asm(s,e); \
57 flush_kernel_icache_range_asm(s,e); \
58} while (0)
69 59
70#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 60#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
71do { \ 61do { \
@@ -80,118 +70,17 @@ do { \
80 memcpy(dst, src, len); \ 70 memcpy(dst, src, len); \
81} while (0) 71} while (0)
82 72
83static inline void flush_cache_range(struct vm_area_struct *vma, 73void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn);
84 unsigned long start, unsigned long end) 74void flush_cache_range(struct vm_area_struct *vma,
85{ 75 unsigned long start, unsigned long end);
86 int sr3;
87
88 if (!vma->vm_mm->context) {
89 BUG();
90 return;
91 }
92
93 sr3 = mfsp(3);
94 if (vma->vm_mm->context == sr3) {
95 flush_user_dcache_range(start,end);
96 flush_user_icache_range(start,end);
97 } else {
98 flush_cache_all();
99 }
100}
101
102/* Simple function to work out if we have an existing address translation
103 * for a user space vma. */
104static inline int translation_exists(struct vm_area_struct *vma,
105 unsigned long addr, unsigned long pfn)
106{
107 pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
108 pmd_t *pmd;
109 pte_t pte;
110
111 if(pgd_none(*pgd))
112 return 0;
113
114 pmd = pmd_offset(pgd, addr);
115 if(pmd_none(*pmd) || pmd_bad(*pmd))
116 return 0;
117
118 /* We cannot take the pte lock here: flush_cache_page is usually
119 * called with pte lock already held. Whereas flush_dcache_page
120 * takes flush_dcache_mmap_lock, which is lower in the hierarchy:
121 * the vma itself is secure, but the pte might come or go racily.
122 */
123 pte = *pte_offset_map(pmd, addr);
124 /* But pte_unmap() does nothing on this architecture */
125
126 /* Filter out coincidental file entries and swap entries */
127 if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT)))
128 return 0;
129
130 return pte_pfn(pte) == pfn;
131}
132
133/* Private function to flush a page from the cache of a non-current
134 * process. cr25 contains the Page Directory of the current user
135 * process; we're going to hijack both it and the user space %sr3 to
136 * temporarily make the non-current process current. We have to do
137 * this because cache flushing may cause a non-access tlb miss which
138 * the handlers have to fill in from the pgd of the non-current
139 * process. */
140static inline void
141flush_user_cache_page_non_current(struct vm_area_struct *vma,
142 unsigned long vmaddr)
143{
144 /* save the current process space and pgd */
145 unsigned long space = mfsp(3), pgd = mfctl(25);
146
147 /* we don't mind taking interrups since they may not
148 * do anything with user space, but we can't
149 * be preempted here */
150 preempt_disable();
151
152 /* make us current */
153 mtctl(__pa(vma->vm_mm->pgd), 25);
154 mtsp(vma->vm_mm->context, 3);
155
156 flush_user_dcache_page(vmaddr);
157 if(vma->vm_flags & VM_EXEC)
158 flush_user_icache_page(vmaddr);
159
160 /* put the old current process back */
161 mtsp(space, 3);
162 mtctl(pgd, 25);
163 preempt_enable();
164}
165
166static inline void
167__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
168{
169 if (likely(vma->vm_mm->context == mfsp(3))) {
170 flush_user_dcache_page(vmaddr);
171 if (vma->vm_flags & VM_EXEC)
172 flush_user_icache_page(vmaddr);
173 } else {
174 flush_user_cache_page_non_current(vma, vmaddr);
175 }
176}
177
178static inline void
179flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
180{
181 BUG_ON(!vma->vm_mm->context);
182
183 if (likely(translation_exists(vma, vmaddr, pfn)))
184 __flush_cache_page(vma, vmaddr);
185
186}
187 76
77#define ARCH_HAS_FLUSH_ANON_PAGE
188static inline void 78static inline void
189flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr) 79flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
190{ 80{
191 if (PageAnon(page)) 81 if (PageAnon(page))
192 flush_user_dcache_page(vmaddr); 82 flush_user_dcache_page(vmaddr);
193} 83}
194#define ARCH_HAS_FLUSH_ANON_PAGE
195 84
196#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE 85#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
197void flush_kernel_dcache_page_addr(void *addr); 86void flush_kernel_dcache_page_addr(void *addr);
diff --git a/include/asm-parisc/tlbflush.h b/include/asm-parisc/tlbflush.h
index 67b3814a71dd..ae2d12008546 100644
--- a/include/asm-parisc/tlbflush.h
+++ b/include/asm-parisc/tlbflush.h
@@ -71,33 +71,11 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
71 purge_tlb_end(); 71 purge_tlb_end();
72} 72}
73 73
74static inline void flush_tlb_range(struct vm_area_struct *vma, 74void __flush_tlb_range(unsigned long sid,
75 unsigned long start, unsigned long end) 75 unsigned long start, unsigned long end);
76{
77 unsigned long npages;
78 76
79 npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 77#define flush_tlb_range(vma,start,end) __flush_tlb_range((vma)->vm_mm->context,start,end)
80 if (npages >= 512) /* 2MB of space: arbitrary, should be tuned */
81 flush_tlb_all();
82 else {
83 mtsp(vma->vm_mm->context,1);
84 purge_tlb_start();
85 if (split_tlb) {
86 while (npages--) {
87 pdtlb(start);
88 pitlb(start);
89 start += PAGE_SIZE;
90 }
91 } else {
92 while (npages--) {
93 pdtlb(start);
94 start += PAGE_SIZE;
95 }
96 }
97 purge_tlb_end();
98 }
99}
100 78
101#define flush_tlb_kernel_range(start, end) flush_tlb_all() 79#define flush_tlb_kernel_range(start, end) __flush_tlb_range(0,start,end)
102 80
103#endif 81#endif