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authorLinus Torvalds <torvalds@g5.osdl.org>2006-03-28 16:53:03 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-03-28 16:53:03 -0500
commitca9ba4471c1203bb6e759b76e83167fec54fe590 (patch)
tree8aeb359631742f77f635cb5ff785bea9132502f9
parentd4965b3e2ff94d0c7b7e6e7e9794b54950a2f4b9 (diff)
parentc4713074375c61f939310b04e92090afe29810dc (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 3388/1: ixp23xx: add core ixp23xx support [ARM] 3417/1: add support for logicpd pxa270 card engine [ARM] 3387/1: ixp23xx: add defconfig [ARM] 3377/2: add support for intel xsc3 core [ARM] Move ice-dcc code into misc.c [ARM] Fix decompressor serial IO to give CRLF not LFCR [ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX. [ARM] nommu: trivial patch for arch/arm/lib/Makefile [ARM] 3416/1: Update LART site URL [ARM] 3415/1: Akita: Add missing EXPORT_SYMBOL [ARM] 3414/1: ep93xx: reset ethernet controller before uncompressing
Diffstat
-rw-r--r--Documentation/arm/SA1100/Assabet2
-rw-r--r--Documentation/arm/SA1100/LART2
-rw-r--r--arch/arm/Kconfig11
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boot/compressed/Makefile4
-rw-r--r--arch/arm/boot/compressed/ice-dcc.S17
-rw-r--r--arch/arm/boot/compressed/misc.c41
-rw-r--r--arch/arm/configs/ixp23xx_defconfig1302
-rw-r--r--arch/arm/lib/Makefile2
-rw-r--r--arch/arm/mach-ixp23xx/Kconfig25
-rw-r--r--arch/arm/mach-ixp23xx/Makefile11
-rw-r--r--arch/arm/mach-ixp23xx/Makefile.boot2
-rw-r--r--arch/arm/mach-ixp23xx/core.c431
-rw-r--r--arch/arm/mach-ixp23xx/espresso.c69
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c325
-rw-r--r--arch/arm/mach-ixp23xx/pci.c275
-rw-r--r--arch/arm/mach-ixp23xx/roadrunner.c164
-rw-r--r--arch/arm/mach-pxa/Kconfig5
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/lpd270.c393
-rw-r--r--arch/arm/mach-pxa/spitz.c2
-rw-r--r--arch/arm/mach-sa1100/Kconfig2
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1100.c2
-rw-r--r--arch/arm/mm/Kconfig19
-rw-r--r--arch/arm/mm/Makefile2
-rw-r--r--arch/arm/mm/copypage-xsc3.S97
-rw-r--r--arch/arm/mm/mm-armv.c3
-rw-r--r--arch/arm/mm/proc-v6.S16
-rw-r--r--arch/arm/mm/proc-xsc3.S498
-rw-r--r--include/asm-arm/arch-aaec2000/uncompress.h23
-rw-r--r--include/asm-arm/arch-at91rm9200/uncompress.h23
-rw-r--r--include/asm-arm/arch-cl7500/uncompress.h18
-rw-r--r--include/asm-arm/arch-clps711x/uncompress.h21
-rw-r--r--include/asm-arm/arch-ebsa110/uncompress.h47
-rw-r--r--include/asm-arm/arch-ebsa285/uncompress.h16
-rw-r--r--include/asm-arm/arch-ep93xx/uncompress.h50
-rw-r--r--include/asm-arm/arch-h720x/uncompress.h24
-rw-r--r--include/asm-arm/arch-imx/uncompress.h21
-rw-r--r--include/asm-arm/arch-integrator/uncompress.h21
-rw-r--r--include/asm-arm/arch-iop3xx/uncompress.h16
-rw-r--r--include/asm-arm/arch-ixp2000/uncompress.h15
-rw-r--r--include/asm-arm/arch-ixp23xx/debug-macro.S23
-rw-r--r--include/asm-arm/arch-ixp23xx/dma.h3
-rw-r--r--include/asm-arm/arch-ixp23xx/entry-macro.S31
-rw-r--r--include/asm-arm/arch-ixp23xx/hardware.h37
-rw-r--r--include/asm-arm/arch-ixp23xx/io.h54
-rw-r--r--include/asm-arm/arch-ixp23xx/irqs.h223
-rw-r--r--include/asm-arm/arch-ixp23xx/ixdp2351.h89
-rw-r--r--include/asm-arm/arch-ixp23xx/ixp23xx.h306
-rw-r--r--include/asm-arm/arch-ixp23xx/memory.h46
-rw-r--r--include/asm-arm/arch-ixp23xx/platform.h31
-rw-r--r--include/asm-arm/arch-ixp23xx/system.h33
-rw-r--r--include/asm-arm/arch-ixp23xx/time.h3
-rw-r--r--include/asm-arm/arch-ixp23xx/timex.h7
-rw-r--r--include/asm-arm/arch-ixp23xx/uncompress.h45
-rw-r--r--include/asm-arm/arch-ixp23xx/vmalloc.h10
-rw-r--r--include/asm-arm/arch-ixp4xx/uncompress.h18
-rw-r--r--include/asm-arm/arch-l7200/uncompress.h15
-rw-r--r--include/asm-arm/arch-lh7a40x/uncompress.h11
-rw-r--r--include/asm-arm/arch-omap/uncompress.h20
-rw-r--r--include/asm-arm/arch-pxa/irqs.h6
-rw-r--r--include/asm-arm/arch-pxa/lpd270.h38
-rw-r--r--include/asm-arm/arch-pxa/uncompress.h13
-rw-r--r--include/asm-arm/arch-realview/uncompress.h20
-rw-r--r--include/asm-arm/arch-rpc/uncompress.h27
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h15
-rw-r--r--include/asm-arm/arch-sa1100/uncompress.h21
-rw-r--r--include/asm-arm/arch-shark/uncompress.h13
-rw-r--r--include/asm-arm/arch-versatile/uncompress.h20
-rw-r--r--include/asm-arm/cacheflush.h8
-rw-r--r--include/asm-arm/domain.h18
-rw-r--r--include/asm-arm/page.h9
-rw-r--r--include/asm-arm/proc-fns.h8
-rw-r--r--include/asm-arm/system.h19
74 files changed, 4937 insertions, 323 deletions
diff --git a/Documentation/arm/SA1100/Assabet b/Documentation/arm/SA1100/Assabet
index cbbe5587c78d..78bc1c1b04e5 100644
--- a/Documentation/arm/SA1100/Assabet
+++ b/Documentation/arm/SA1100/Assabet
@@ -26,7 +26,7 @@ Installing a bootloader
26 26
27A couple of bootloaders able to boot Linux on Assabet are available: 27A couple of bootloaders able to boot Linux on Assabet are available:
28 28
29BLOB (http://www.lart.tudelft.nl/lartware/blob/) 29BLOB (http://www.lartmaker.nl/lartware/blob/)
30 30
31 BLOB is a bootloader used within the LART project. Some contributed 31 BLOB is a bootloader used within the LART project. Some contributed
32 patches were merged into BLOB to add support for Assabet. 32 patches were merged into BLOB to add support for Assabet.
diff --git a/Documentation/arm/SA1100/LART b/Documentation/arm/SA1100/LART
index 2f73f513e16a..6d412b685598 100644
--- a/Documentation/arm/SA1100/LART
+++ b/Documentation/arm/SA1100/LART
@@ -11,4 +11,4 @@ is under development, with plenty of others in different stages of
11planning. 11planning.
12 12
13The hardware designs for this board have been released under an open license; 13The hardware designs for this board have been released under an open license;
14see the LART page at http://www.lart.tudelft.nl/ for more information. 14see the LART page at http://www.lartmaker.nl/ for more information.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9731b3f826ab..ba46d779ede7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -153,6 +153,12 @@ config ARCH_IXP2000
153 help 153 help
154 Support for Intel's IXP2400/2800 (XScale) family of processors. 154 Support for Intel's IXP2400/2800 (XScale) family of processors.
155 155
156config ARCH_IXP23XX
157 bool "IXP23XX-based"
158 select PCI
159 help
160 Support for Intel's IXP23xx (XScale) family of processors.
161
156config ARCH_L7200 162config ARCH_L7200
157 bool "LinkUp-L7200" 163 bool "LinkUp-L7200"
158 select FIQ 164 select FIQ
@@ -274,6 +280,8 @@ source "arch/arm/mach-ixp4xx/Kconfig"
274 280
275source "arch/arm/mach-ixp2000/Kconfig" 281source "arch/arm/mach-ixp2000/Kconfig"
276 282
283source "arch/arm/mach-ixp23xx/Kconfig"
284
277source "arch/arm/mach-pxa/Kconfig" 285source "arch/arm/mach-pxa/Kconfig"
278 286
279source "arch/arm/mach-sa1100/Kconfig" 287source "arch/arm/mach-sa1100/Kconfig"
@@ -792,7 +800,8 @@ source "drivers/acorn/block/Kconfig"
792 800
793if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \ 801if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \
794 || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \ 802 || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \
795 || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE 803 || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \
804 || ARCH_IXP23XX
796source "drivers/ide/Kconfig" 805source "drivers/ide/Kconfig"
797endif 806endif
798 807
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 99c0d323719a..ce3e804ea0f3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -57,6 +57,7 @@ tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi
57tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110 57tune-$(CONFIG_CPU_SA110) :=-mtune=strongarm110
58tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100 58tune-$(CONFIG_CPU_SA1100) :=-mtune=strongarm1100
59tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale 59tune-$(CONFIG_CPU_XSCALE) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
60tune-$(CONFIG_CPU_XSC3) :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
60tune-$(CONFIG_CPU_V6) :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm) 61tune-$(CONFIG_CPU_V6) :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
61 62
62ifeq ($(CONFIG_AEABI),y) 63ifeq ($(CONFIG_AEABI),y)
@@ -97,6 +98,7 @@ endif
97 machine-$(CONFIG_ARCH_IOP3XX) := iop3xx 98 machine-$(CONFIG_ARCH_IOP3XX) := iop3xx
98 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 99 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
99 machine-$(CONFIG_ARCH_IXP2000) := ixp2000 100 machine-$(CONFIG_ARCH_IXP2000) := ixp2000
101 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
100 machine-$(CONFIG_ARCH_OMAP1) := omap1 102 machine-$(CONFIG_ARCH_OMAP1) := omap1
101 machine-$(CONFIG_ARCH_OMAP2) := omap2 103 machine-$(CONFIG_ARCH_OMAP2) := omap2
102 incdir-$(CONFIG_ARCH_OMAP) := omap 104 incdir-$(CONFIG_ARCH_OMAP) := omap
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 35ffe0f4ece7..2adc1527e0eb 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -50,10 +50,6 @@ ifeq ($(CONFIG_ARCH_AT91RM9200),y)
50OBJS += head-at91rm9200.o 50OBJS += head-at91rm9200.o
51endif 51endif
52 52
53ifeq ($(CONFIG_DEBUG_ICEDCC),y)
54OBJS += ice-dcc.o
55endif
56
57ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) 53ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
58OBJS += big-endian.o 54OBJS += big-endian.o
59endif 55endif
diff --git a/arch/arm/boot/compressed/ice-dcc.S b/arch/arm/boot/compressed/ice-dcc.S
deleted file mode 100644
index 104377a199bb..000000000000
--- a/arch/arm/boot/compressed/ice-dcc.S
+++ /dev/null
@@ -1,17 +0,0 @@
1
2
3 .text
4
5 .global icedcc_putc
6
7icedcc_putc:
8 mov r2, #0x4000000
91:
10 subs r2, r2, #1
11 movlt pc, r14
12 mrc p14, 0, r1, c0, c0, 0
13 tst r1, #2
14 bne 1b
15
16 mcr p14, 0, r0, c1, c0, 0
17 mov pc, r14
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 5ab94584baee..0af3772efcb7 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -20,24 +20,45 @@ unsigned int __machine_arch_type;
20 20
21#include <linux/string.h> 21#include <linux/string.h>
22 22
23#include <asm/arch/uncompress.h>
24
25#ifdef STANDALONE_DEBUG 23#ifdef STANDALONE_DEBUG
26#define putstr printf 24#define putstr printf
27#endif 25#else
26
27static void putstr(const char *ptr);
28
29#include <linux/compiler.h>
30#include <asm/arch/uncompress.h>
28 31
29#ifdef CONFIG_DEBUG_ICEDCC 32#ifdef CONFIG_DEBUG_ICEDCC
30#define putstr icedcc_putstr 33static void icedcc_putc(int ch)
31#define putc icedcc_putc 34{
35 int status, i = 0x4000000;
32 36
33extern void icedcc_putc(int ch); 37 do {
38 if (--i < 0)
39 return;
34 40
35static void 41 asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (status));
36icedcc_putstr(const char *ptr) 42 } while (status & 2);
43
44 asm("mcr p15, 0, %0, c1, c0, 0" : : "r" (ch));
45}
46
47#define putc(ch) icedcc_putc(ch)
48#define flush() do { } while (0)
49#endif
50
51static void putstr(const char *ptr)
37{ 52{
38 for (; *ptr != '\0'; ptr++) { 53 char c;
39 icedcc_putc(*ptr); 54
55 while ((c = *ptr++) != '\0') {
56 if (c == '\n')
57 putc('\r');
58 putc(c);
40 } 59 }
60
61 flush();
41} 62}
42 63
43#endif 64#endif
diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig
new file mode 100644
index 000000000000..1a2751e9ab05
--- /dev/null
+++ b/arch/arm/configs/ixp23xx_defconfig
@@ -0,0 +1,1302 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.16
4# Tue Mar 21 03:27:20 2006
5#
6CONFIG_ARM=y
7CONFIG_MMU=y
8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9CONFIG_GENERIC_CALIBRATE_DELAY=y
10
11#
12# Code maturity level options
13#
14CONFIG_EXPERIMENTAL=y
15CONFIG_BROKEN_ON_SMP=y
16CONFIG_INIT_ENV_ARG_LIMIT=32
17
18#
19# General setup
20#
21CONFIG_LOCALVERSION=""
22CONFIG_LOCALVERSION_AUTO=y
23CONFIG_SWAP=y
24CONFIG_SYSVIPC=y
25# CONFIG_POSIX_MQUEUE is not set
26CONFIG_BSD_PROCESS_ACCT=y
27# CONFIG_BSD_PROCESS_ACCT_V3 is not set
28CONFIG_SYSCTL=y
29# CONFIG_AUDIT is not set
30# CONFIG_IKCONFIG is not set
31CONFIG_INITRAMFS_SOURCE=""
32CONFIG_UID16=y
33CONFIG_CC_OPTIMIZE_FOR_SIZE=y
34CONFIG_EMBEDDED=y
35CONFIG_KALLSYMS=y
36# CONFIG_KALLSYMS_ALL is not set
37# CONFIG_KALLSYMS_EXTRA_PASS is not set
38CONFIG_HOTPLUG=y
39CONFIG_PRINTK=y
40CONFIG_BUG=y
41CONFIG_ELF_CORE=y
42CONFIG_BASE_FULL=y
43CONFIG_FUTEX=y
44CONFIG_EPOLL=y
45CONFIG_SHMEM=y
46CONFIG_CC_ALIGN_FUNCTIONS=0
47CONFIG_CC_ALIGN_LABELS=0
48CONFIG_CC_ALIGN_LOOPS=0
49CONFIG_CC_ALIGN_JUMPS=0
50CONFIG_SLAB=y
51# CONFIG_TINY_SHMEM is not set
52CONFIG_BASE_SMALL=0
53# CONFIG_SLOB is not set
54CONFIG_OBSOLETE_INTERMODULE=y
55
56#
57# Loadable module support
58#
59CONFIG_MODULES=y
60CONFIG_MODULE_UNLOAD=y
61# CONFIG_MODULE_FORCE_UNLOAD is not set
62CONFIG_OBSOLETE_MODPARM=y
63# CONFIG_MODVERSIONS is not set
64# CONFIG_MODULE_SRCVERSION_ALL is not set
65CONFIG_KMOD=y
66
67#
68# Block layer
69#
70
71#
72# IO Schedulers
73#
74CONFIG_IOSCHED_NOOP=y
75CONFIG_IOSCHED_AS=y
76CONFIG_IOSCHED_DEADLINE=y
77CONFIG_IOSCHED_CFQ=y
78CONFIG_DEFAULT_AS=y
79# CONFIG_DEFAULT_DEADLINE is not set
80# CONFIG_DEFAULT_CFQ is not set
81# CONFIG_DEFAULT_NOOP is not set
82CONFIG_DEFAULT_IOSCHED="anticipatory"
83
84#
85# System Type
86#
87# CONFIG_ARCH_CLPS7500 is not set
88# CONFIG_ARCH_CLPS711X is not set
89# CONFIG_ARCH_CO285 is not set
90# CONFIG_ARCH_EBSA110 is not set
91# CONFIG_ARCH_EP93XX is not set
92# CONFIG_ARCH_FOOTBRIDGE is not set
93# CONFIG_ARCH_INTEGRATOR is not set
94# CONFIG_ARCH_IOP3XX is not set
95# CONFIG_ARCH_IXP4XX is not set
96# CONFIG_ARCH_IXP2000 is not set
97CONFIG_ARCH_IXP23XX=y
98# CONFIG_ARCH_L7200 is not set
99# CONFIG_ARCH_PXA is not set
100# CONFIG_ARCH_RPC is not set
101# CONFIG_ARCH_SA1100 is not set
102# CONFIG_ARCH_S3C2410 is not set
103# CONFIG_ARCH_SHARK is not set
104# CONFIG_ARCH_LH7A40X is not set
105# CONFIG_ARCH_OMAP is not set
106# CONFIG_ARCH_VERSATILE is not set
107# CONFIG_ARCH_REALVIEW is not set
108# CONFIG_ARCH_IMX is not set
109# CONFIG_ARCH_H720X is not set
110# CONFIG_ARCH_AAEC2000 is not set
111# CONFIG_ARCH_AT91RM9200 is not set
112CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
113
114#
115# Intel IXP23xx Implementation Options
116#
117
118#
119# IXP23xx Platforms
120#
121CONFIG_MACH_ESPRESSO=y
122CONFIG_MACH_IXDP2351=y
123CONFIG_MACH_ROADRUNNER=y
124
125#
126# Processor Type
127#
128CONFIG_CPU_32=y
129CONFIG_CPU_XSC3=y
130CONFIG_CPU_32v5=y
131CONFIG_CPU_ABRT_EV5T=y
132CONFIG_CPU_CACHE_VIVT=y
133CONFIG_CPU_TLB_V4WBI=y
134CONFIG_IO_36=y
135
136#
137# Processor Features
138#
139# CONFIG_ARM_THUMB is not set
140CONFIG_CPU_BIG_ENDIAN=y
141
142#
143# Bus support
144#
145CONFIG_PCI=y
146CONFIG_PCI_LEGACY_PROC=y
147# CONFIG_PCI_DEBUG is not set
148
149#
150# PCCARD (PCMCIA/CardBus) support
151#
152# CONFIG_PCCARD is not set
153
154#
155# Kernel Features
156#
157# CONFIG_PREEMPT is not set
158# CONFIG_NO_IDLE_HZ is not set
159CONFIG_HZ=100
160# CONFIG_AEABI is not set
161# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
162CONFIG_SELECT_MEMORY_MODEL=y
163CONFIG_FLATMEM_MANUAL=y
164# CONFIG_DISCONTIGMEM_MANUAL is not set
165# CONFIG_SPARSEMEM_MANUAL is not set
166CONFIG_FLATMEM=y
167CONFIG_FLAT_NODE_MEM_MAP=y
168# CONFIG_SPARSEMEM_STATIC is not set
169CONFIG_SPLIT_PTLOCK_CPUS=4096
170CONFIG_ALIGNMENT_TRAP=y
171
172#
173# Boot options
174#
175CONFIG_ZBOOT_ROM_TEXT=0x0
176CONFIG_ZBOOT_ROM_BSS=0x0
177CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp"
178# CONFIG_XIP_KERNEL is not set
179
180#
181# Floating point emulation
182#
183
184#
185# At least one emulation must be selected
186#
187CONFIG_FPE_NWFPE=y
188CONFIG_FPE_NWFPE_XP=y
189# CONFIG_FPE_FASTFPE is not set
190
191#
192# Userspace binary formats
193#
194CONFIG_BINFMT_ELF=y
195# CONFIG_BINFMT_AOUT is not set
196# CONFIG_BINFMT_MISC is not set
197# CONFIG_ARTHUR is not set
198
199#
200# Power management options
201#
202# CONFIG_PM is not set
203# CONFIG_APM is not set
204
205#
206# Networking
207#
208CONFIG_NET=y
209
210#
211# Networking options
212#
213# CONFIG_NETDEBUG is not set
214CONFIG_PACKET=y
215CONFIG_PACKET_MMAP=y
216CONFIG_UNIX=y
217# CONFIG_NET_KEY is not set
218CONFIG_INET=y
219# CONFIG_IP_MULTICAST is not set
220# CONFIG_IP_ADVANCED_ROUTER is not set
221CONFIG_IP_FIB_HASH=y
222CONFIG_IP_PNP=y
223CONFIG_IP_PNP_DHCP=y
224CONFIG_IP_PNP_BOOTP=y
225# CONFIG_IP_PNP_RARP is not set
226# CONFIG_NET_IPIP is not set
227# CONFIG_NET_IPGRE is not set
228# CONFIG_ARPD is not set
229CONFIG_SYN_COOKIES=y
230# CONFIG_INET_AH is not set
231# CONFIG_INET_ESP is not set
232# CONFIG_INET_IPCOMP is not set
233# CONFIG_INET_TUNNEL is not set
234CONFIG_INET_DIAG=y
235CONFIG_INET_TCP_DIAG=y
236# CONFIG_TCP_CONG_ADVANCED is not set
237CONFIG_TCP_CONG_BIC=y
238# CONFIG_IPV6 is not set
239# CONFIG_NETFILTER is not set
240
241#
242# DCCP Configuration (EXPERIMENTAL)
243#
244# CONFIG_IP_DCCP is not set
245
246#
247# SCTP Configuration (EXPERIMENTAL)
248#
249# CONFIG_IP_SCTP is not set
250
251#
252# TIPC Configuration (EXPERIMENTAL)
253#
254# CONFIG_TIPC is not set
255# CONFIG_ATM is not set
256# CONFIG_BRIDGE is not set
257# CONFIG_VLAN_8021Q is not set
258# CONFIG_DECNET is not set
259# CONFIG_LLC2 is not set
260# CONFIG_IPX is not set
261# CONFIG_ATALK is not set
262# CONFIG_X25 is not set
263# CONFIG_LAPB is not set
264# CONFIG_NET_DIVERT is not set
265# CONFIG_ECONET is not set
266# CONFIG_WAN_ROUTER is not set
267
268#
269# QoS and/or fair queueing
270#
271# CONFIG_NET_SCHED is not set
272
273#
274# Network testing
275#
276# CONFIG_NET_PKTGEN is not set
277# CONFIG_HAMRADIO is not set
278# CONFIG_IRDA is not set
279# CONFIG_BT is not set
280# CONFIG_IEEE80211 is not set
281
282#
283# Device Drivers
284#
285
286#
287# Generic Driver Options
288#
289CONFIG_STANDALONE=y
290# CONFIG_PREVENT_FIRMWARE_BUILD is not set
291# CONFIG_FW_LOADER is not set
292# CONFIG_DEBUG_DRIVER is not set
293
294#
295# Connector - unified userspace <-> kernelspace linker
296#
297# CONFIG_CONNECTOR is not set
298
299#
300# Memory Technology Devices (MTD)
301#
302CONFIG_MTD=y
303# CONFIG_MTD_DEBUG is not set
304# CONFIG_MTD_CONCAT is not set
305CONFIG_MTD_PARTITIONS=y
306CONFIG_MTD_REDBOOT_PARTS=y
307CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
308CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
309CONFIG_MTD_REDBOOT_PARTS_READONLY=y
310# CONFIG_MTD_CMDLINE_PARTS is not set
311# CONFIG_MTD_AFS_PARTS is not set
312
313#
314# User Modules And Translation Layers
315#
316CONFIG_MTD_CHAR=y
317CONFIG_MTD_BLOCK=y
318# CONFIG_FTL is not set
319# CONFIG_NFTL is not set
320# CONFIG_INFTL is not set
321# CONFIG_RFD_FTL is not set
322
323#
324# RAM/ROM/Flash chip drivers
325#
326CONFIG_MTD_CFI=y
327# CONFIG_MTD_JEDECPROBE is not set
328CONFIG_MTD_GEN_PROBE=y
329# CONFIG_MTD_CFI_ADV_OPTIONS is not set
330CONFIG_MTD_MAP_BANK_WIDTH_1=y
331CONFIG_MTD_MAP_BANK_WIDTH_2=y
332CONFIG_MTD_MAP_BANK_WIDTH_4=y
333# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
334# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
335# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
336CONFIG_MTD_CFI_I1=y
337CONFIG_MTD_CFI_I2=y
338# CONFIG_MTD_CFI_I4 is not set
339# CONFIG_MTD_CFI_I8 is not set
340CONFIG_MTD_CFI_INTELEXT=y
341# CONFIG_MTD_CFI_AMDSTD is not set
342# CONFIG_MTD_CFI_STAA is not set
343CONFIG_MTD_CFI_UTIL=y
344# CONFIG_MTD_RAM is not set
345# CONFIG_MTD_ROM is not set
346# CONFIG_MTD_ABSENT is not set
347# CONFIG_MTD_OBSOLETE_CHIPS is not set
348
349#
350# Mapping drivers for chip access
351#
352CONFIG_MTD_COMPLEX_MAPPINGS=y
353CONFIG_MTD_PHYSMAP=y
354CONFIG_MTD_PHYSMAP_START=0x0
355CONFIG_MTD_PHYSMAP_LEN=0x0
356CONFIG_MTD_PHYSMAP_BANKWIDTH=1
357# CONFIG_MTD_ARM_INTEGRATOR is not set
358# CONFIG_MTD_PCI is not set
359# CONFIG_MTD_PLATRAM is not set
360
361#
362# Self-contained MTD device drivers
363#
364# CONFIG_MTD_PMC551 is not set
365# CONFIG_MTD_SLRAM is not set
366# CONFIG_MTD_PHRAM is not set
367# CONFIG_MTD_MTDRAM is not set
368# CONFIG_MTD_BLKMTD is not set
369# CONFIG_MTD_BLOCK2MTD is not set
370
371#
372# Disk-On-Chip Device Drivers
373#
374# CONFIG_MTD_DOC2000 is not set
375# CONFIG_MTD_DOC2001 is not set
376# CONFIG_MTD_DOC2001PLUS is not set
377
378#
379# NAND Flash Device Drivers
380#
381# CONFIG_MTD_NAND is not set
382
383#
384# OneNAND Flash Device Drivers
385#
386# CONFIG_MTD_ONENAND is not set
387
388#
389# Parallel port support
390#
391# CONFIG_PARPORT is not set
392
393#
394# Plug and Play support
395#
396
397#
398# Block devices
399#
400# CONFIG_BLK_CPQ_DA is not set
401# CONFIG_BLK_CPQ_CISS_DA is not set
402# CONFIG_BLK_DEV_DAC960 is not set
403# CONFIG_BLK_DEV_UMEM is not set
404# CONFIG_BLK_DEV_COW_COMMON is not set
405CONFIG_BLK_DEV_LOOP=y
406# CONFIG_BLK_DEV_CRYPTOLOOP is not set
407# CONFIG_BLK_DEV_NBD is not set
408# CONFIG_BLK_DEV_SX8 is not set
409# CONFIG_BLK_DEV_UB is not set
410CONFIG_BLK_DEV_RAM=y
411CONFIG_BLK_DEV_RAM_COUNT=16
412CONFIG_BLK_DEV_RAM_SIZE=8192
413CONFIG_BLK_DEV_INITRD=y
414# CONFIG_CDROM_PKTCDVD is not set
415# CONFIG_ATA_OVER_ETH is not set
416
417#
418# ATA/ATAPI/MFM/RLL support
419#
420CONFIG_IDE=y
421CONFIG_BLK_DEV_IDE=y
422
423#
424# Please see Documentation/ide.txt for help/info on IDE drives
425#
426# CONFIG_BLK_DEV_IDE_SATA is not set
427CONFIG_BLK_DEV_IDEDISK=y
428# CONFIG_IDEDISK_MULTI_MODE is not set
429# CONFIG_BLK_DEV_IDECD is not set
430# CONFIG_BLK_DEV_IDETAPE is not set
431# CONFIG_BLK_DEV_IDEFLOPPY is not set
432# CONFIG_BLK_DEV_IDESCSI is not set
433# CONFIG_IDE_TASK_IOCTL is not set
434
435#
436# IDE chipset support/bugfixes
437#
438CONFIG_IDE_GENERIC=y
439CONFIG_BLK_DEV_IDEPCI=y
440# CONFIG_IDEPCI_SHARE_IRQ is not set
441# CONFIG_BLK_DEV_OFFBOARD is not set
442# CONFIG_BLK_DEV_GENERIC is not set
443# CONFIG_BLK_DEV_OPTI621 is not set
444# CONFIG_BLK_DEV_SL82C105 is not set
445CONFIG_BLK_DEV_IDEDMA_PCI=y
446# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
447# CONFIG_IDEDMA_PCI_AUTO is not set
448# CONFIG_BLK_DEV_AEC62XX is not set
449# CONFIG_BLK_DEV_ALI15X3 is not set
450# CONFIG_BLK_DEV_AMD74XX is not set
451# CONFIG_BLK_DEV_CMD64X is not set
452# CONFIG_BLK_DEV_TRIFLEX is not set
453# CONFIG_BLK_DEV_CY82C693 is not set
454# CONFIG_BLK_DEV_CS5520 is not set
455# CONFIG_BLK_DEV_CS5530 is not set
456# CONFIG_BLK_DEV_HPT34X is not set
457# CONFIG_BLK_DEV_HPT366 is not set
458# CONFIG_BLK_DEV_SC1200 is not set
459# CONFIG_BLK_DEV_PIIX is not set
460# CONFIG_BLK_DEV_IT821X is not set
461# CONFIG_BLK_DEV_NS87415 is not set
462# CONFIG_BLK_DEV_PDC202XX_OLD is not set
463# CONFIG_BLK_DEV_PDC202XX_NEW is not set
464# CONFIG_BLK_DEV_SVWKS is not set
465CONFIG_BLK_DEV_SIIMAGE=y
466# CONFIG_BLK_DEV_SLC90E66 is not set
467# CONFIG_BLK_DEV_TRM290 is not set
468# CONFIG_BLK_DEV_VIA82CXXX is not set
469# CONFIG_IDE_ARM is not set
470CONFIG_BLK_DEV_IDEDMA=y
471# CONFIG_IDEDMA_IVB is not set
472# CONFIG_IDEDMA_AUTO is not set
473# CONFIG_BLK_DEV_HD is not set
474
475#
476# SCSI device support
477#
478# CONFIG_RAID_ATTRS is not set
479CONFIG_SCSI=y
480CONFIG_SCSI_PROC_FS=y
481
482#
483# SCSI support type (disk, tape, CD-ROM)
484#
485CONFIG_BLK_DEV_SD=y
486# CONFIG_CHR_DEV_ST is not set
487# CONFIG_CHR_DEV_OSST is not set
488# CONFIG_BLK_DEV_SR is not set
489# CONFIG_CHR_DEV_SG is not set
490# CONFIG_CHR_DEV_SCH is not set
491
492#
493# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
494#
495# CONFIG_SCSI_MULTI_LUN is not set
496# CONFIG_SCSI_CONSTANTS is not set
497# CONFIG_SCSI_LOGGING is not set
498
499#
500# SCSI Transport Attributes
501#
502# CONFIG_SCSI_SPI_ATTRS is not set
503# CONFIG_SCSI_FC_ATTRS is not set
504# CONFIG_SCSI_ISCSI_ATTRS is not set
505# CONFIG_SCSI_SAS_ATTRS is not set
506
507#
508# SCSI low-level drivers
509#
510# CONFIG_ISCSI_TCP is not set
511# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
512# CONFIG_SCSI_3W_9XXX is not set
513# CONFIG_SCSI_ACARD is not set
514# CONFIG_SCSI_AACRAID is not set
515# CONFIG_SCSI_AIC7XXX is not set
516# CONFIG_SCSI_AIC7XXX_OLD is not set
517# CONFIG_SCSI_AIC79XX is not set
518# CONFIG_SCSI_DPT_I2O is not set
519# CONFIG_MEGARAID_NEWGEN is not set
520# CONFIG_MEGARAID_LEGACY is not set
521# CONFIG_MEGARAID_SAS is not set
522# CONFIG_SCSI_SATA is not set
523# CONFIG_SCSI_DMX3191D is not set
524# CONFIG_SCSI_FUTURE_DOMAIN is not set
525# CONFIG_SCSI_IPS is not set
526# CONFIG_SCSI_INITIO is not set
527# CONFIG_SCSI_INIA100 is not set
528# CONFIG_SCSI_SYM53C8XX_2 is not set
529# CONFIG_SCSI_IPR is not set
530# CONFIG_SCSI_QLOGIC_FC is not set
531# CONFIG_SCSI_QLOGIC_1280 is not set
532# CONFIG_SCSI_QLA_FC is not set
533# CONFIG_SCSI_LPFC is not set
534# CONFIG_SCSI_DC395x is not set
535# CONFIG_SCSI_DC390T is not set
536# CONFIG_SCSI_NSP32 is not set
537# CONFIG_SCSI_DEBUG is not set
538
539#
540# Multi-device support (RAID and LVM)
541#
542# CONFIG_MD is not set
543
544#
545# Fusion MPT device support
546#
547# CONFIG_FUSION is not set
548# CONFIG_FUSION_SPI is not set
549# CONFIG_FUSION_FC is not set
550# CONFIG_FUSION_SAS is not set
551
552#
553# IEEE 1394 (FireWire) support
554#
555# CONFIG_IEEE1394 is not set
556
557#
558# I2O device support
559#
560# CONFIG_I2O is not set
561
562#
563# Network device support
564#
565CONFIG_NETDEVICES=y
566CONFIG_DUMMY=y
567# CONFIG_BONDING is not set
568# CONFIG_EQUALIZER is not set
569# CONFIG_TUN is not set
570
571#
572# ARCnet devices
573#
574# CONFIG_ARCNET is not set
575
576#
577# PHY device support
578#
579# CONFIG_PHYLIB is not set
580
581#
582# Ethernet (10 or 100Mbit)
583#
584CONFIG_NET_ETHERNET=y
585CONFIG_MII=y
586# CONFIG_HAPPYMEAL is not set
587# CONFIG_SUNGEM is not set
588# CONFIG_CASSINI is not set
589# CONFIG_NET_VENDOR_3COM is not set
590# CONFIG_SMC91X is not set
591# CONFIG_DM9000 is not set
592
593#
594# Tulip family network device support
595#
596# CONFIG_NET_TULIP is not set
597# CONFIG_HP100 is not set
598CONFIG_NET_PCI=y
599# CONFIG_PCNET32 is not set
600# CONFIG_AMD8111_ETH is not set
601# CONFIG_ADAPTEC_STARFIRE is not set
602# CONFIG_B44 is not set
603# CONFIG_FORCEDETH is not set
604# CONFIG_CS89x0 is not set
605# CONFIG_DGRS is not set
606# CONFIG_EEPRO100 is not set
607CONFIG_E100=y
608# CONFIG_FEALNX is not set
609# CONFIG_NATSEMI is not set
610# CONFIG_NE2K_PCI is not set
611# CONFIG_8139CP is not set
612# CONFIG_8139TOO is not set
613# CONFIG_SIS900 is not set
614# CONFIG_EPIC100 is not set
615# CONFIG_SUNDANCE is not set
616# CONFIG_TLAN is not set
617# CONFIG_VIA_RHINE is not set
618
619#
620# Ethernet (1000 Mbit)
621#
622# CONFIG_ACENIC is not set
623# CONFIG_DL2K is not set
624CONFIG_E1000=y
625CONFIG_E1000_NAPI=y
626# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
627# CONFIG_NS83820 is not set
628# CONFIG_HAMACHI is not set
629# CONFIG_YELLOWFIN is not set
630# CONFIG_R8169 is not set
631# CONFIG_SIS190 is not set
632# CONFIG_SKGE is not set
633# CONFIG_SKY2 is not set
634# CONFIG_SK98LIN is not set
635# CONFIG_VIA_VELOCITY is not set
636# CONFIG_TIGON3 is not set
637# CONFIG_BNX2 is not set
638
639#
640# Ethernet (10000 Mbit)
641#
642# CONFIG_CHELSIO_T1 is not set
643# CONFIG_IXGB is not set
644# CONFIG_S2IO is not set
645
646#
647# Token Ring devices
648#
649# CONFIG_TR is not set
650
651#
652# Wireless LAN (non-hamradio)
653#
654# CONFIG_NET_RADIO is not set
655
656#
657# Wan interfaces
658#
659CONFIG_WAN=y
660# CONFIG_DSCC4 is not set
661# CONFIG_LANMEDIA is not set
662# CONFIG_SYNCLINK_SYNCPPP is not set
663CONFIG_HDLC=y
664CONFIG_HDLC_RAW=y
665# CONFIG_HDLC_RAW_ETH is not set
666CONFIG_HDLC_CISCO=y
667CONFIG_HDLC_FR=y
668CONFIG_HDLC_PPP=y
669
670#
671# X.25/LAPB support is disabled
672#
673# CONFIG_PCI200SYN is not set
674# CONFIG_WANXL is not set
675# CONFIG_PC300 is not set
676# CONFIG_FARSYNC is not set
677CONFIG_DLCI=y
678CONFIG_DLCI_COUNT=24
679CONFIG_DLCI_MAX=8
680# CONFIG_FDDI is not set
681# CONFIG_HIPPI is not set
682# CONFIG_PPP is not set
683# CONFIG_SLIP is not set
684# CONFIG_NET_FC is not set
685# CONFIG_SHAPER is not set
686# CONFIG_NETCONSOLE is not set
687# CONFIG_NETPOLL is not set
688# CONFIG_NET_POLL_CONTROLLER is not set
689
690#
691# ISDN subsystem
692#
693# CONFIG_ISDN is not set
694
695#
696# Input device support
697#
698CONFIG_INPUT=y
699
700#
701# Userland interfaces
702#
703CONFIG_INPUT_MOUSEDEV=y
704CONFIG_INPUT_MOUSEDEV_PSAUX=y
705CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
706CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
707# CONFIG_INPUT_JOYDEV is not set
708# CONFIG_INPUT_TSDEV is not set
709# CONFIG_INPUT_EVDEV is not set
710# CONFIG_INPUT_EVBUG is not set
711
712#
713# Input Device Drivers
714#
715# CONFIG_INPUT_KEYBOARD is not set
716# CONFIG_INPUT_MOUSE is not set
717# CONFIG_INPUT_JOYSTICK is not set
718# CONFIG_INPUT_TOUCHSCREEN is not set
719# CONFIG_INPUT_MISC is not set
720
721#
722# Hardware I/O ports
723#
724# CONFIG_SERIO is not set
725# CONFIG_GAMEPORT is not set
726
727#
728# Character devices
729#
730# CONFIG_VT is not set
731# CONFIG_SERIAL_NONSTANDARD is not set
732
733#
734# Serial drivers
735#
736CONFIG_SERIAL_8250=y
737CONFIG_SERIAL_8250_CONSOLE=y
738CONFIG_SERIAL_8250_NR_UARTS=4
739CONFIG_SERIAL_8250_RUNTIME_UARTS=4
740# CONFIG_SERIAL_8250_EXTENDED is not set
741
742#
743# Non-8250 serial port support
744#
745CONFIG_SERIAL_CORE=y
746CONFIG_SERIAL_CORE_CONSOLE=y
747# CONFIG_SERIAL_JSM is not set
748CONFIG_UNIX98_PTYS=y
749CONFIG_LEGACY_PTYS=y
750CONFIG_LEGACY_PTY_COUNT=256
751
752#
753# IPMI
754#
755# CONFIG_IPMI_HANDLER is not set
756
757#
758# Watchdog Cards
759#
760CONFIG_WATCHDOG=y
761# CONFIG_WATCHDOG_NOWAYOUT is not set
762
763#
764# Watchdog Device Drivers
765#
766# CONFIG_SOFT_WATCHDOG is not set
767
768#
769# PCI-based Watchdog Cards
770#
771# CONFIG_PCIPCWATCHDOG is not set
772# CONFIG_WDTPCI is not set
773
774#
775# USB-based Watchdog Cards
776#
777# CONFIG_USBPCWATCHDOG is not set
778# CONFIG_NVRAM is not set
779# CONFIG_RTC is not set
780# CONFIG_DTLK is not set
781# CONFIG_R3964 is not set
782# CONFIG_APPLICOM is not set
783
784#
785# Ftape, the floppy tape device driver
786#
787# CONFIG_DRM is not set
788# CONFIG_RAW_DRIVER is not set
789
790#
791# TPM devices
792#
793# CONFIG_TCG_TPM is not set
794# CONFIG_TELCLOCK is not set
795
796#
797# I2C support
798#
799CONFIG_I2C=y
800CONFIG_I2C_CHARDEV=y
801
802#
803# I2C Algorithms
804#
805CONFIG_I2C_ALGOBIT=y
806# CONFIG_I2C_ALGOPCF is not set
807# CONFIG_I2C_ALGOPCA is not set
808
809#
810# I2C Hardware Bus support
811#
812# CONFIG_I2C_ALI1535 is not set
813# CONFIG_I2C_ALI1563 is not set
814# CONFIG_I2C_ALI15X3 is not set
815# CONFIG_I2C_AMD756 is not set
816# CONFIG_I2C_AMD8111 is not set
817# CONFIG_I2C_I801 is not set
818# CONFIG_I2C_I810 is not set
819# CONFIG_I2C_PIIX4 is not set
820# CONFIG_I2C_NFORCE2 is not set
821# CONFIG_I2C_PARPORT_LIGHT is not set
822# CONFIG_I2C_PROSAVAGE is not set
823# CONFIG_I2C_SAVAGE4 is not set
824# CONFIG_SCx200_ACB is not set
825# CONFIG_I2C_SIS5595 is not set
826# CONFIG_I2C_SIS630 is not set
827# CONFIG_I2C_SIS96X is not set
828# CONFIG_I2C_STUB is not set
829# CONFIG_I2C_VIA is not set
830# CONFIG_I2C_VIAPRO is not set
831# CONFIG_I2C_VOODOO3 is not set
832# CONFIG_I2C_PCA_ISA is not set
833
834#
835# Miscellaneous I2C Chip support
836#
837# CONFIG_SENSORS_DS1337 is not set
838# CONFIG_SENSORS_DS1374 is not set
839CONFIG_SENSORS_EEPROM=y
840# CONFIG_SENSORS_PCF8574 is not set
841# CONFIG_SENSORS_PCA9539 is not set
842# CONFIG_SENSORS_PCF8591 is not set
843# CONFIG_SENSORS_RTC8564 is not set
844# CONFIG_SENSORS_MAX6875 is not set
845# CONFIG_RTC_X1205_I2C is not set
846# CONFIG_I2C_DEBUG_CORE is not set
847# CONFIG_I2C_DEBUG_ALGO is not set
848# CONFIG_I2C_DEBUG_BUS is not set
849# CONFIG_I2C_DEBUG_CHIP is not set
850
851#
852# SPI support
853#
854# CONFIG_SPI is not set
855# CONFIG_SPI_MASTER is not set
856
857#
858# Dallas's 1-wire bus
859#
860# CONFIG_W1 is not set
861
862#
863# Hardware Monitoring support
864#
865CONFIG_HWMON=y
866# CONFIG_HWMON_VID is not set
867# CONFIG_SENSORS_ADM1021 is not set
868# CONFIG_SENSORS_ADM1025 is not set
869# CONFIG_SENSORS_ADM1026 is not set
870# CONFIG_SENSORS_ADM1031 is not set
871# CONFIG_SENSORS_ADM9240 is not set
872# CONFIG_SENSORS_ASB100 is not set
873# CONFIG_SENSORS_ATXP1 is not set
874# CONFIG_SENSORS_DS1621 is not set
875# CONFIG_SENSORS_F71805F is not set
876# CONFIG_SENSORS_FSCHER is not set
877# CONFIG_SENSORS_FSCPOS is not set
878# CONFIG_SENSORS_GL518SM is not set
879# CONFIG_SENSORS_GL520SM is not set
880# CONFIG_SENSORS_IT87 is not set
881# CONFIG_SENSORS_LM63 is not set
882# CONFIG_SENSORS_LM75 is not set
883# CONFIG_SENSORS_LM77 is not set
884# CONFIG_SENSORS_LM78 is not set
885# CONFIG_SENSORS_LM80 is not set
886# CONFIG_SENSORS_LM83 is not set
887# CONFIG_SENSORS_LM85 is not set
888# CONFIG_SENSORS_LM87 is not set
889# CONFIG_SENSORS_LM90 is not set
890# CONFIG_SENSORS_LM92 is not set
891# CONFIG_SENSORS_MAX1619 is not set
892# CONFIG_SENSORS_PC87360 is not set
893# CONFIG_SENSORS_SIS5595 is not set
894# CONFIG_SENSORS_SMSC47M1 is not set
895# CONFIG_SENSORS_SMSC47B397 is not set
896# CONFIG_SENSORS_VIA686A is not set
897# CONFIG_SENSORS_VT8231 is not set
898# CONFIG_SENSORS_W83781D is not set
899# CONFIG_SENSORS_W83792D is not set
900# CONFIG_SENSORS_W83L785TS is not set
901# CONFIG_SENSORS_W83627HF is not set
902# CONFIG_SENSORS_W83627EHF is not set
903# CONFIG_HWMON_DEBUG_CHIP is not set
904
905#
906# Misc devices
907#
908
909#
910# Multimedia Capabilities Port drivers
911#
912
913#
914# Multimedia devices
915#
916# CONFIG_VIDEO_DEV is not set
917
918#
919# Digital Video Broadcasting Devices
920#
921# CONFIG_DVB is not set
922
923#
924# Graphics support
925#
926# CONFIG_FB is not set
927
928#
929# Sound
930#
931# CONFIG_SOUND is not set
932
933#
934# USB support
935#
936CONFIG_USB_ARCH_HAS_HCD=y
937CONFIG_USB_ARCH_HAS_OHCI=y
938CONFIG_USB=y
939# CONFIG_USB_DEBUG is not set
940
941#
942# Miscellaneous USB options
943#
944# CONFIG_USB_DEVICEFS is not set
945# CONFIG_USB_BANDWIDTH is not set
946# CONFIG_USB_DYNAMIC_MINORS is not set
947# CONFIG_USB_OTG is not set
948
949#
950# USB Host Controller Drivers
951#
952CONFIG_USB_EHCI_HCD=y
953# CONFIG_USB_EHCI_SPLIT_ISO is not set
954# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
955# CONFIG_USB_ISP116X_HCD is not set
956CONFIG_USB_OHCI_HCD=y
957# CONFIG_USB_OHCI_BIG_ENDIAN is not set
958CONFIG_USB_OHCI_LITTLE_ENDIAN=y
959CONFIG_USB_UHCI_HCD=y
960# CONFIG_USB_SL811_HCD is not set
961
962#
963# USB Device Class drivers
964#
965# CONFIG_USB_ACM is not set
966# CONFIG_USB_PRINTER is not set
967
968#
969# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
970#
971
972#
973# may also be needed; see USB_STORAGE Help for more information
974#
975CONFIG_USB_STORAGE=y
976# CONFIG_USB_STORAGE_DEBUG is not set
977# CONFIG_USB_STORAGE_DATAFAB is not set
978# CONFIG_USB_STORAGE_FREECOM is not set
979# CONFIG_USB_STORAGE_ISD200 is not set
980# CONFIG_USB_STORAGE_DPCM is not set
981# CONFIG_USB_STORAGE_USBAT is not set
982# CONFIG_USB_STORAGE_SDDR09 is not set
983# CONFIG_USB_STORAGE_SDDR55 is not set
984# CONFIG_USB_STORAGE_JUMPSHOT is not set
985# CONFIG_USB_STORAGE_ALAUDA is not set
986# CONFIG_USB_LIBUSUAL is not set
987
988#
989# USB Input Devices
990#
991# CONFIG_USB_HID is not set
992
993#
994# USB HID Boot Protocol drivers
995#
996# CONFIG_USB_KBD is not set
997# CONFIG_USB_MOUSE is not set
998# CONFIG_USB_AIPTEK is not set
999# CONFIG_USB_WACOM is not set
1000# CONFIG_USB_ACECAD is not set
1001# CONFIG_USB_KBTAB is not set
1002# CONFIG_USB_POWERMATE is not set
1003# CONFIG_USB_MTOUCH is not set
1004# CONFIG_USB_ITMTOUCH is not set
1005# CONFIG_USB_EGALAX is not set
1006# CONFIG_USB_YEALINK is not set
1007# CONFIG_USB_XPAD is not set
1008# CONFIG_USB_ATI_REMOTE is not set
1009# CONFIG_USB_ATI_REMOTE2 is not set
1010# CONFIG_USB_KEYSPAN_REMOTE is not set
1011# CONFIG_USB_APPLETOUCH is not set
1012
1013#
1014# USB Imaging devices
1015#
1016# CONFIG_USB_MDC800 is not set
1017# CONFIG_USB_MICROTEK is not set
1018
1019#
1020# USB Multimedia devices
1021#
1022# CONFIG_USB_DABUSB is not set
1023
1024#
1025# Video4Linux support is needed for USB Multimedia device support
1026#
1027
1028#
1029# USB Network Adapters
1030#
1031# CONFIG_USB_CATC is not set
1032# CONFIG_USB_KAWETH is not set
1033# CONFIG_USB_PEGASUS is not set
1034# CONFIG_USB_RTL8150 is not set
1035# CONFIG_USB_USBNET is not set
1036CONFIG_USB_MON=y
1037
1038#
1039# USB port drivers
1040#
1041
1042#
1043# USB Serial Converter support
1044#
1045# CONFIG_USB_SERIAL is not set
1046
1047#
1048# USB Miscellaneous drivers
1049#
1050# CONFIG_USB_EMI62 is not set
1051# CONFIG_USB_EMI26 is not set
1052# CONFIG_USB_AUERSWALD is not set
1053# CONFIG_USB_RIO500 is not set
1054# CONFIG_USB_LEGOTOWER is not set
1055# CONFIG_USB_LCD is not set
1056# CONFIG_USB_LED is not set
1057# CONFIG_USB_CYTHERM is not set
1058# CONFIG_USB_PHIDGETKIT is not set
1059# CONFIG_USB_PHIDGETSERVO is not set
1060# CONFIG_USB_IDMOUSE is not set
1061# CONFIG_USB_SISUSBVGA is not set
1062# CONFIG_USB_LD is not set
1063
1064#
1065# USB DSL modem support
1066#
1067
1068#
1069# USB Gadget Support
1070#
1071# CONFIG_USB_GADGET is not set
1072
1073#
1074# MMC/SD Card support
1075#
1076# CONFIG_MMC is not set
1077
1078#
1079# File systems
1080#
1081CONFIG_EXT2_FS=y
1082CONFIG_EXT2_FS_XATTR=y
1083CONFIG_EXT2_FS_POSIX_ACL=y
1084# CONFIG_EXT2_FS_SECURITY is not set
1085# CONFIG_EXT2_FS_XIP is not set
1086CONFIG_EXT3_FS=y
1087CONFIG_EXT3_FS_XATTR=y
1088CONFIG_EXT3_FS_POSIX_ACL=y
1089# CONFIG_EXT3_FS_SECURITY is not set
1090CONFIG_JBD=y
1091# CONFIG_JBD_DEBUG is not set
1092CONFIG_FS_MBCACHE=y
1093# CONFIG_REISERFS_FS is not set
1094# CONFIG_JFS_FS is not set
1095CONFIG_FS_POSIX_ACL=y
1096# CONFIG_XFS_FS is not set
1097# CONFIG_OCFS2_FS is not set
1098# CONFIG_MINIX_FS is not set
1099# CONFIG_ROMFS_FS is not set
1100CONFIG_INOTIFY=y
1101# CONFIG_QUOTA is not set
1102CONFIG_DNOTIFY=y
1103# CONFIG_AUTOFS_FS is not set
1104# CONFIG_AUTOFS4_FS is not set
1105# CONFIG_FUSE_FS is not set
1106
1107#
1108# CD-ROM/DVD Filesystems
1109#
1110# CONFIG_ISO9660_FS is not set
1111# CONFIG_UDF_FS is not set
1112
1113#
1114# DOS/FAT/NT Filesystems
1115#
1116CONFIG_FAT_FS=y
1117CONFIG_MSDOS_FS=y
1118# CONFIG_VFAT_FS is not set
1119CONFIG_FAT_DEFAULT_CODEPAGE=437
1120# CONFIG_NTFS_FS is not set
1121
1122#
1123# Pseudo filesystems
1124#
1125CONFIG_PROC_FS=y
1126CONFIG_SYSFS=y
1127CONFIG_TMPFS=y
1128# CONFIG_HUGETLB_PAGE is not set
1129CONFIG_RAMFS=y
1130# CONFIG_RELAYFS_FS is not set
1131# CONFIG_CONFIGFS_FS is not set
1132
1133#
1134# Miscellaneous filesystems
1135#
1136# CONFIG_ADFS_FS is not set
1137# CONFIG_AFFS_FS is not set
1138# CONFIG_HFS_FS is not set
1139# CONFIG_HFSPLUS_FS is not set
1140# CONFIG_BEFS_FS is not set
1141# CONFIG_BFS_FS is not set
1142# CONFIG_EFS_FS is not set
1143# CONFIG_JFFS_FS is not set
1144CONFIG_JFFS2_FS=y
1145CONFIG_JFFS2_FS_DEBUG=0
1146CONFIG_JFFS2_FS_WRITEBUFFER=y
1147# CONFIG_JFFS2_SUMMARY is not set
1148# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1149CONFIG_JFFS2_ZLIB=y
1150CONFIG_JFFS2_RTIME=y
1151# CONFIG_JFFS2_RUBIN is not set
1152# CONFIG_CRAMFS is not set
1153# CONFIG_VXFS_FS is not set
1154# CONFIG_HPFS_FS is not set
1155# CONFIG_QNX4FS_FS is not set
1156# CONFIG_SYSV_FS is not set
1157# CONFIG_UFS_FS is not set
1158
1159#
1160# Network File Systems
1161#
1162CONFIG_NFS_FS=y
1163CONFIG_NFS_V3=y
1164# CONFIG_NFS_V3_ACL is not set
1165# CONFIG_NFS_V4 is not set
1166# CONFIG_NFS_DIRECTIO is not set
1167# CONFIG_NFSD is not set
1168CONFIG_ROOT_NFS=y
1169CONFIG_LOCKD=y
1170CONFIG_LOCKD_V4=y
1171CONFIG_NFS_COMMON=y
1172CONFIG_SUNRPC=y
1173# CONFIG_RPCSEC_GSS_KRB5 is not set
1174# CONFIG_RPCSEC_GSS_SPKM3 is not set
1175# CONFIG_SMB_FS is not set
1176# CONFIG_CIFS is not set
1177# CONFIG_NCP_FS is not set
1178# CONFIG_CODA_FS is not set
1179# CONFIG_AFS_FS is not set
1180# CONFIG_9P_FS is not set
1181
1182#
1183# Partition Types
1184#
1185CONFIG_PARTITION_ADVANCED=y
1186# CONFIG_ACORN_PARTITION is not set
1187# CONFIG_OSF_PARTITION is not set
1188# CONFIG_AMIGA_PARTITION is not set
1189# CONFIG_ATARI_PARTITION is not set
1190# CONFIG_MAC_PARTITION is not set
1191CONFIG_MSDOS_PARTITION=y
1192# CONFIG_BSD_DISKLABEL is not set
1193# CONFIG_MINIX_SUBPARTITION is not set
1194# CONFIG_SOLARIS_X86_PARTITION is not set
1195# CONFIG_UNIXWARE_DISKLABEL is not set
1196# CONFIG_LDM_PARTITION is not set
1197# CONFIG_SGI_PARTITION is not set
1198# CONFIG_ULTRIX_PARTITION is not set
1199# CONFIG_SUN_PARTITION is not set
1200# CONFIG_KARMA_PARTITION is not set
1201# CONFIG_EFI_PARTITION is not set
1202
1203#
1204# Native Language Support
1205#
1206CONFIG_NLS=y
1207CONFIG_NLS_DEFAULT="iso8859-1"
1208CONFIG_NLS_CODEPAGE_437=y
1209# CONFIG_NLS_CODEPAGE_737 is not set
1210# CONFIG_NLS_CODEPAGE_775 is not set
1211# CONFIG_NLS_CODEPAGE_850 is not set
1212# CONFIG_NLS_CODEPAGE_852 is not set
1213# CONFIG_NLS_CODEPAGE_855 is not set
1214# CONFIG_NLS_CODEPAGE_857 is not set
1215# CONFIG_NLS_CODEPAGE_860 is not set
1216# CONFIG_NLS_CODEPAGE_861 is not set
1217# CONFIG_NLS_CODEPAGE_862 is not set
1218# CONFIG_NLS_CODEPAGE_863 is not set
1219# CONFIG_NLS_CODEPAGE_864 is not set
1220# CONFIG_NLS_CODEPAGE_865 is not set
1221# CONFIG_NLS_CODEPAGE_866 is not set
1222# CONFIG_NLS_CODEPAGE_869 is not set
1223# CONFIG_NLS_CODEPAGE_936 is not set
1224# CONFIG_NLS_CODEPAGE_950 is not set
1225# CONFIG_NLS_CODEPAGE_932 is not set
1226# CONFIG_NLS_CODEPAGE_949 is not set
1227# CONFIG_NLS_CODEPAGE_874 is not set
1228# CONFIG_NLS_ISO8859_8 is not set
1229# CONFIG_NLS_CODEPAGE_1250 is not set
1230# CONFIG_NLS_CODEPAGE_1251 is not set
1231# CONFIG_NLS_ASCII is not set
1232# CONFIG_NLS_ISO8859_1 is not set
1233# CONFIG_NLS_ISO8859_2 is not set
1234# CONFIG_NLS_ISO8859_3 is not set
1235# CONFIG_NLS_ISO8859_4 is not set
1236# CONFIG_NLS_ISO8859_5 is not set
1237# CONFIG_NLS_ISO8859_6 is not set
1238# CONFIG_NLS_ISO8859_7 is not set
1239# CONFIG_NLS_ISO8859_9 is not set
1240# CONFIG_NLS_ISO8859_13 is not set
1241# CONFIG_NLS_ISO8859_14 is not set
1242# CONFIG_NLS_ISO8859_15 is not set
1243# CONFIG_NLS_KOI8_R is not set
1244# CONFIG_NLS_KOI8_U is not set
1245# CONFIG_NLS_UTF8 is not set
1246
1247#
1248# Profiling support
1249#
1250# CONFIG_PROFILING is not set
1251
1252#
1253# Kernel hacking
1254#
1255# CONFIG_PRINTK_TIME is not set
1256CONFIG_MAGIC_SYSRQ=y
1257CONFIG_DEBUG_KERNEL=y
1258CONFIG_LOG_BUF_SHIFT=14
1259CONFIG_DETECT_SOFTLOCKUP=y
1260# CONFIG_SCHEDSTATS is not set
1261# CONFIG_DEBUG_SLAB is not set
1262CONFIG_DEBUG_MUTEXES=y
1263# CONFIG_DEBUG_SPINLOCK is not set
1264# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1265# CONFIG_DEBUG_KOBJECT is not set
1266CONFIG_DEBUG_BUGVERBOSE=y
1267# CONFIG_DEBUG_INFO is not set
1268# CONFIG_DEBUG_FS is not set
1269# CONFIG_DEBUG_VM is not set
1270CONFIG_FRAME_POINTER=y
1271CONFIG_FORCED_INLINING=y
1272# CONFIG_RCU_TORTURE_TEST is not set
1273CONFIG_DEBUG_USER=y
1274# CONFIG_DEBUG_WAITQ is not set
1275CONFIG_DEBUG_ERRORS=y
1276CONFIG_DEBUG_LL=y
1277# CONFIG_DEBUG_ICEDCC is not set
1278
1279#
1280# Security options
1281#
1282# CONFIG_KEYS is not set
1283# CONFIG_SECURITY is not set
1284
1285#
1286# Cryptographic options
1287#
1288# CONFIG_CRYPTO is not set
1289
1290#
1291# Hardware crypto devices
1292#
1293
1294#
1295# Library routines
1296#
1297# CONFIG_CRC_CCITT is not set
1298# CONFIG_CRC16 is not set
1299CONFIG_CRC32=y
1300# CONFIG_LIBCRC32C is not set
1301CONFIG_ZLIB_INFLATE=y
1302CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 391f3ab3ff32..7b726b627ea5 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -18,7 +18,7 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
18 18
19# the code in uaccess.S is not preemption safe and 19# the code in uaccess.S is not preemption safe and
20# probably faster on ARMv3 only 20# probably faster on ARMv3 only
21ifeq ($CONFIG_PREEMPT,y) 21ifeq ($(CONFIG_PREEMPT),y)
22 lib-y += copy_from_user.o copy_to_user.o 22 lib-y += copy_from_user.o copy_to_user.o
23else 23else
24ifneq ($(CONFIG_CPU_32v3),y) 24ifneq ($(CONFIG_CPU_32v3),y)
diff --git a/arch/arm/mach-ixp23xx/Kconfig b/arch/arm/mach-ixp23xx/Kconfig
new file mode 100644
index 000000000000..982670ec3866
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Kconfig
@@ -0,0 +1,25 @@
1if ARCH_IXP23XX
2
3config ARCH_SUPPORTS_BIG_ENDIAN
4 bool
5 default y
6
7menu "Intel IXP23xx Implementation Options"
8
9comment "IXP23xx Platforms"
10
11config MACH_ESPRESSO
12 bool "Support IP Fabrics Double Espresso platform"
13 help
14
15config MACH_IXDP2351
16 bool "Support Intel IXDP2351 platform"
17 help
18
19config MACH_ROADRUNNER
20 bool "Support ADI RoadRunner platform"
21 help
22
23endmenu
24
25endif
diff --git a/arch/arm/mach-ixp23xx/Makefile b/arch/arm/mach-ixp23xx/Makefile
new file mode 100644
index 000000000000..288b371b6d03
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the linux kernel.
3#
4obj-y := core.o pci.o
5obj-m :=
6obj-n :=
7obj- :=
8
9obj-$(CONFIG_MACH_ESPRESSO) += espresso.o
10obj-$(CONFIG_MACH_IXDP2351) += ixdp2351.o
11obj-$(CONFIG_MACH_ROADRUNNER) += roadrunner.o
diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot
new file mode 100644
index 000000000000..d5561ad15bad
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Makefile.boot
@@ -0,0 +1,2 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
new file mode 100644
index 000000000000..092ee12ced42
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -0,0 +1,431 @@
1/*
2 * arch/arm/mach-ixp23xx/core.c
3 *
4 * Core routines for IXP23xx chips
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/config.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/sched.h>
22#include <linux/interrupt.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/serial.h>
27#include <linux/serial_8250.h>
28#include <linux/serial_core.h>
29#include <linux/device.h>
30#include <linux/mm.h>
31#include <linux/time.h>
32#include <linux/timex.h>
33
34#include <asm/types.h>
35#include <asm/setup.h>
36#include <asm/memory.h>
37#include <asm/hardware.h>
38#include <asm/mach-types.h>
39#include <asm/irq.h>
40#include <asm/system.h>
41#include <asm/tlbflush.h>
42#include <asm/pgtable.h>
43
44#include <asm/mach/map.h>
45#include <asm/mach/time.h>
46#include <asm/mach/irq.h>
47#include <asm/mach/arch.h>
48
49
50/*************************************************************************
51 * Chip specific mappings shared by all IXP23xx systems
52 *************************************************************************/
53static struct map_desc ixp23xx_io_desc[] __initdata = {
54 { /* XSI-CPP CSRs */
55 .virtual = IXP23XX_XSI2CPP_CSR_VIRT,
56 .pfn = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
57 .length = IXP23XX_XSI2CPP_CSR_SIZE,
58 .type = MT_DEVICE,
59 }, { /* Expansion Bus Config */
60 .virtual = IXP23XX_EXP_CFG_VIRT,
61 .pfn = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
62 .length = IXP23XX_EXP_CFG_SIZE,
63 .type = MT_DEVICE,
64 }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
65 .virtual = IXP23XX_PERIPHERAL_VIRT,
66 .pfn = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
67 .length = IXP23XX_PERIPHERAL_SIZE,
68 .type = MT_DEVICE,
69 }, { /* CAP CSRs */
70 .virtual = IXP23XX_CAP_CSR_VIRT,
71 .pfn = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
72 .length = IXP23XX_CAP_CSR_SIZE,
73 .type = MT_DEVICE,
74 }, { /* MSF CSRs */
75 .virtual = IXP23XX_MSF_CSR_VIRT,
76 .pfn = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
77 .length = IXP23XX_MSF_CSR_SIZE,
78 .type = MT_DEVICE,
79 }, { /* PCI I/O Space */
80 .virtual = IXP23XX_PCI_IO_VIRT,
81 .pfn = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
82 .length = IXP23XX_PCI_IO_SIZE,
83 .type = MT_DEVICE,
84 }, { /* PCI Config Space */
85 .virtual = IXP23XX_PCI_CFG_VIRT,
86 .pfn = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
87 .length = IXP23XX_PCI_CFG_SIZE,
88 .type = MT_DEVICE,
89 }, { /* PCI local CFG CSRs */
90 .virtual = IXP23XX_PCI_CREG_VIRT,
91 .pfn = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
92 .length = IXP23XX_PCI_CREG_SIZE,
93 .type = MT_DEVICE,
94 }, { /* PCI MEM Space */
95 .virtual = IXP23XX_PCI_MEM_VIRT,
96 .pfn = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
97 .length = IXP23XX_PCI_MEM_SIZE,
98 .type = MT_DEVICE,
99 }
100};
101
102void __init ixp23xx_map_io(void)
103{
104 iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
105}
106
107
108/***************************************************************************
109 * IXP23xx Interrupt Handling
110 ***************************************************************************/
111enum ixp23xx_irq_type {
112 IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
113};
114
115static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
116
117static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
118{
119 int line = irq - IRQ_IXP23XX_GPIO6 + 6;
120 u32 int_style;
121 enum ixp23xx_irq_type irq_type;
122 volatile u32 *int_reg;
123
124 /*
125 * Only GPIOs 6-15 are wired to interrupts on IXP23xx
126 */
127 if (line < 6 || line > 15)
128 return -EINVAL;
129
130 switch (type) {
131 case IRQT_BOTHEDGE:
132 int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
133 irq_type = IXP23XX_IRQ_EDGE;
134 break;
135 case IRQT_RISING:
136 int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
137 irq_type = IXP23XX_IRQ_EDGE;
138 break;
139 case IRQT_FALLING:
140 int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
141 irq_type = IXP23XX_IRQ_EDGE;
142 break;
143 case IRQT_HIGH:
144 int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
145 irq_type = IXP23XX_IRQ_LEVEL;
146 break;
147 case IRQT_LOW:
148 int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
149 irq_type = IXP23XX_IRQ_LEVEL;
150 break;
151 default:
152 return -EINVAL;
153 }
154
155 ixp23xx_config_irq(irq, irq_type);
156
157 if (line >= 8) { /* pins 8-15 */
158 line -= 8;
159 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
160 } else { /* pins 0-7 */
161 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
162 }
163
164 /*
165 * Clear pending interrupts
166 */
167 *IXP23XX_GPIO_GPISR = (1 << line);
168
169 /* Clear the style for the appropriate pin */
170 *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
171 (line * IXP23XX_GPIO_STYLE_SIZE));
172
173 /* Set the new style */
174 *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
175
176 return 0;
177}
178
179static void ixp23xx_irq_mask(unsigned int irq)
180{
181 volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
182
183 *intr_reg &= ~(1 << (irq % 32));
184}
185
186static void ixp23xx_irq_ack(unsigned int irq)
187{
188 int line = irq - IRQ_IXP23XX_GPIO6 + 6;
189
190 if ((line < 6) || (line > 15))
191 return;
192
193 *IXP23XX_GPIO_GPISR = (1 << line);
194}
195
196/*
197 * Level triggered interrupts on GPIO lines can only be cleared when the
198 * interrupt condition disappears.
199 */
200static void ixp23xx_irq_level_unmask(unsigned int irq)
201{
202 volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
203
204 ixp23xx_irq_ack(irq);
205
206 *intr_reg |= (1 << (irq % 32));
207}
208
209static void ixp23xx_irq_edge_unmask(unsigned int irq)
210{
211 volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
212
213 *intr_reg |= (1 << (irq % 32));
214}
215
216static struct irqchip ixp23xx_irq_level_chip = {
217 .ack = ixp23xx_irq_mask,
218 .mask = ixp23xx_irq_mask,
219 .unmask = ixp23xx_irq_level_unmask,
220 .set_type = ixp23xx_irq_set_type
221};
222
223static struct irqchip ixp23xx_irq_edge_chip = {
224 .ack = ixp23xx_irq_ack,
225 .mask = ixp23xx_irq_mask,
226 .unmask = ixp23xx_irq_edge_unmask,
227 .set_type = ixp23xx_irq_set_type
228};
229
230static void ixp23xx_pci_irq_mask(unsigned int irq)
231{
232 *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
233}
234
235static void ixp23xx_pci_irq_unmask(unsigned int irq)
236{
237 *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
238}
239
240/*
241 * TODO: Should this just be done at ASM level?
242 */
243static void pci_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
244{
245 u32 pci_interrupt;
246 unsigned int irqno;
247 struct irqdesc *int_desc;
248
249 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
250
251 desc->chip->ack(irq);
252
253 /* See which PCI_INTA, or PCI_INTB interrupted */
254 if (pci_interrupt & (1 << 26)) {
255 irqno = IRQ_IXP23XX_INTB;
256 } else if (pci_interrupt & (1 << 27)) {
257 irqno = IRQ_IXP23XX_INTA;
258 } else {
259 BUG();
260 }
261
262 int_desc = irq_desc + irqno;
263 int_desc->handle(irqno, int_desc, regs);
264
265 desc->chip->unmask(irq);
266}
267
268static struct irqchip ixp23xx_pci_irq_chip = {
269 .ack = ixp23xx_pci_irq_mask,
270 .mask = ixp23xx_pci_irq_mask,
271 .unmask = ixp23xx_pci_irq_unmask
272};
273
274static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
275{
276 switch (type) {
277 case IXP23XX_IRQ_LEVEL:
278 set_irq_chip(irq, &ixp23xx_irq_level_chip);
279 set_irq_handler(irq, do_level_IRQ);
280 break;
281 case IXP23XX_IRQ_EDGE:
282 set_irq_chip(irq, &ixp23xx_irq_edge_chip);
283 set_irq_handler(irq, do_edge_IRQ);
284 break;
285 }
286 set_irq_flags(irq, IRQF_VALID);
287}
288
289void __init ixp23xx_init_irq(void)
290{
291 int irq;
292
293 /* Route everything to IRQ */
294 *IXP23XX_INTR_SEL1 = 0x0;
295 *IXP23XX_INTR_SEL2 = 0x0;
296 *IXP23XX_INTR_SEL3 = 0x0;
297 *IXP23XX_INTR_SEL4 = 0x0;
298
299 /* Mask all sources */
300 *IXP23XX_INTR_EN1 = 0x0;
301 *IXP23XX_INTR_EN2 = 0x0;
302 *IXP23XX_INTR_EN3 = 0x0;
303 *IXP23XX_INTR_EN4 = 0x0;
304
305 /*
306 * Configure all IRQs for level-sensitive operation
307 */
308 for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
309 ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
310 }
311
312 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
313 set_irq_chip(irq, &ixp23xx_pci_irq_chip);
314 set_irq_handler(irq, do_level_IRQ);
315 set_irq_flags(irq, IRQF_VALID);
316 }
317
318 set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
319}
320
321
322/*************************************************************************
323 * Timer-tick functions for IXP23xx
324 *************************************************************************/
325#define CLOCK_TICKS_PER_USEC CLOCK_TICK_RATE / (USEC_PER_SEC)
326
327static unsigned long next_jiffy_time;
328
329static unsigned long
330ixp23xx_gettimeoffset(void)
331{
332 unsigned long elapsed;
333
334 elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
335
336 return elapsed / CLOCK_TICKS_PER_USEC;
337}
338
339static irqreturn_t
340ixp23xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
341{
342 /* Clear Pending Interrupt by writing '1' to it */
343 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
344 while ((*IXP23XX_TIMER_CONT - next_jiffy_time) > LATCH) {
345 timer_tick(regs);
346 next_jiffy_time += LATCH;
347 }
348
349 return IRQ_HANDLED;
350}
351
352static struct irqaction ixp23xx_timer_irq = {
353 .name = "IXP23xx Timer Tick",
354 .handler = ixp23xx_timer_interrupt,
355 .flags = SA_INTERRUPT | SA_TIMER,
356};
357
358void __init ixp23xx_init_timer(void)
359{
360 /* Clear Pending Interrupt by writing '1' to it */
361 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
362
363 /* Setup the Timer counter value */
364 *IXP23XX_TIMER1_RELOAD =
365 (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
366
367 *IXP23XX_TIMER_CONT = 0;
368 next_jiffy_time = LATCH;
369
370 /* Connect the interrupt handler and enable the interrupt */
371 setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
372}
373
374struct sys_timer ixp23xx_timer = {
375 .init = ixp23xx_init_timer,
376 .offset = ixp23xx_gettimeoffset,
377};
378
379
380/*************************************************************************
381 * IXP23xx Platform Initializaion
382 *************************************************************************/
383static struct resource ixp23xx_uart_resources[] = {
384 {
385 .start = IXP23XX_UART1_PHYS,
386 .end = IXP23XX_UART1_PHYS + 0x0fff,
387 .flags = IORESOURCE_MEM
388 }, {
389 .start = IXP23XX_UART2_PHYS,
390 .end = IXP23XX_UART2_PHYS + 0x0fff,
391 .flags = IORESOURCE_MEM
392 }
393};
394
395static struct plat_serial8250_port ixp23xx_uart_data[] = {
396 {
397 .mapbase = IXP23XX_UART1_PHYS,
398 .membase = (char *)(IXP23XX_UART1_VIRT + 3),
399 .irq = IRQ_IXP23XX_UART1,
400 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
401 .iotype = UPIO_MEM,
402 .regshift = 2,
403 .uartclk = IXP23XX_UART_XTAL,
404 }, {
405 .mapbase = IXP23XX_UART2_PHYS,
406 .membase = (char *)(IXP23XX_UART2_VIRT + 3),
407 .irq = IRQ_IXP23XX_UART2,
408 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
409 .iotype = UPIO_MEM,
410 .regshift = 2,
411 .uartclk = IXP23XX_UART_XTAL,
412 },
413 { },
414};
415
416static struct platform_device ixp23xx_uart = {
417 .name = "serial8250",
418 .id = 0,
419 .dev.platform_data = ixp23xx_uart_data,
420 .num_resources = 2,
421 .resource = ixp23xx_uart_resources,
422};
423
424static struct platform_device *ixp23xx_devices[] __initdata = {
425 &ixp23xx_uart,
426};
427
428void __init ixp23xx_sys_init(void)
429{
430 platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
431}
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
new file mode 100644
index 000000000000..2327c9790416
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -0,0 +1,69 @@
1/*
2 * arch/arm/mach-ixp23xx/espresso.c
3 *
4 * Double Espresso-specific routines
5 *
6 * Author: Lennert Buytenhek <buytenh@wantstofly.org>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/config.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/spinlock.h>
17#include <linux/sched.h>
18#include <linux/interrupt.h>
19#include <linux/serial.h>
20#include <linux/tty.h>
21#include <linux/bitops.h>
22#include <linux/ioport.h>
23#include <linux/serial.h>
24#include <linux/serial_8250.h>
25#include <linux/serial_core.h>
26#include <linux/device.h>
27#include <linux/mm.h>
28#include <linux/pci.h>
29#include <linux/mtd/physmap.h>
30
31#include <asm/types.h>
32#include <asm/setup.h>
33#include <asm/memory.h>
34#include <asm/hardware.h>
35#include <asm/mach-types.h>
36#include <asm/irq.h>
37#include <asm/system.h>
38#include <asm/tlbflush.h>
39#include <asm/pgtable.h>
40
41#include <asm/mach/map.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/arch.h>
44#include <asm/mach/irq.h>
45#include <asm/mach/pci.h>
46
47static void __init espresso_init(void)
48{
49 physmap_configure(0x90000000, 0x02000000, 2, NULL);
50
51 /*
52 * Mark flash as writeable.
53 */
54 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
55 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
56
57 ixp23xx_sys_init();
58}
59
60MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
61 /* Maintainer: Lennert Buytenhek */
62 .phys_io = IXP23XX_PERIPHERAL_PHYS,
63 .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
64 .map_io = ixp23xx_map_io,
65 .init_irq = ixp23xx_init_irq,
66 .timer = &ixp23xx_timer,
67 .boot_params = 0x00000100,
68 .init_machine = espresso_init,
69MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
new file mode 100644
index 000000000000..00146c35daac
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -0,0 +1,325 @@
1/*
2 * arch/arm/mach-ixp23xx/ixdp2351.c
3 *
4 * IXDP2351 board-specific routines
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/config.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/sched.h>
22#include <linux/interrupt.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/ioport.h>
27#include <linux/serial.h>
28#include <linux/serial_8250.h>
29#include <linux/serial_core.h>
30#include <linux/device.h>
31#include <linux/mm.h>
32#include <linux/pci.h>
33#include <linux/mtd/physmap.h>
34
35#include <asm/types.h>
36#include <asm/setup.h>
37#include <asm/memory.h>
38#include <asm/hardware.h>
39#include <asm/mach-types.h>
40#include <asm/irq.h>
41#include <asm/system.h>
42#include <asm/tlbflush.h>
43#include <asm/pgtable.h>
44
45#include <asm/mach/map.h>
46#include <asm/mach/irq.h>
47#include <asm/mach/arch.h>
48#include <asm/mach/irq.h>
49#include <asm/mach/pci.h>
50
51/*
52 * IXDP2351 Interrupt Handling
53 */
54static void ixdp2351_inta_mask(unsigned int irq)
55{
56 *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq);
57}
58
59static void ixdp2351_inta_unmask(unsigned int irq)
60{
61 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
62}
63
64static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
65{
66 u16 ex_interrupt =
67 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
68 int i;
69
70 desc->chip->mask(irq);
71
72 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
73 if (ex_interrupt & (1 << i)) {
74 struct irqdesc *cpld_desc;
75 int cpld_irq =
76 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
77 cpld_desc = irq_desc + cpld_irq;
78 cpld_desc->handle(cpld_irq, cpld_desc, regs);
79 }
80 }
81
82 desc->chip->unmask(irq);
83}
84
85static struct irqchip ixdp2351_inta_chip = {
86 .ack = ixdp2351_inta_mask,
87 .mask = ixdp2351_inta_mask,
88 .unmask = ixdp2351_inta_unmask
89};
90
91static void ixdp2351_intb_mask(unsigned int irq)
92{
93 *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq);
94}
95
96static void ixdp2351_intb_unmask(unsigned int irq)
97{
98 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
99}
100
101static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
102{
103 u16 ex_interrupt =
104 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
105 int i;
106
107 desc->chip->ack(irq);
108
109 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
110 if (ex_interrupt & (1 << i)) {
111 struct irqdesc *cpld_desc;
112 int cpld_irq =
113 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
114 cpld_desc = irq_desc + cpld_irq;
115 cpld_desc->handle(cpld_irq, cpld_desc, regs);
116 }
117 }
118
119 desc->chip->unmask(irq);
120}
121
122static struct irqchip ixdp2351_intb_chip = {
123 .ack = ixdp2351_intb_mask,
124 .mask = ixdp2351_intb_mask,
125 .unmask = ixdp2351_intb_unmask
126};
127
128void ixdp2351_init_irq(void)
129{
130 int irq;
131
132 /* Mask all interrupts from CPLD, disable simulation */
133 *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
134 *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
135 *IXDP2351_CPLD_INTA_SIM_REG = 0;
136 *IXDP2351_CPLD_INTB_SIM_REG = 0;
137
138 ixp23xx_init_irq();
139
140 for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
141 irq <
142 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
143 irq++) {
144 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
145 set_irq_flags(irq, IRQF_VALID);
146 set_irq_handler(irq, do_level_IRQ);
147 set_irq_chip(irq, &ixdp2351_inta_chip);
148 }
149 }
150
151 for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
152 irq <
153 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
154 irq++) {
155 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
156 set_irq_flags(irq, IRQF_VALID);
157 set_irq_handler(irq, do_level_IRQ);
158 set_irq_chip(irq, &ixdp2351_intb_chip);
159 }
160 }
161
162 set_irq_chained_handler(IRQ_IXP23XX_INTA, &ixdp2351_inta_handler);
163 set_irq_chained_handler(IRQ_IXP23XX_INTB, &ixdp2351_intb_handler);
164}
165
166/*
167 * IXDP2351 PCI
168 */
169
170/*
171 * This board does not do normal PCI IRQ routing, or any
172 * sort of swizzling, so we just need to check where on the
173 * bus the device is and figure out what CPLD pin it is
174 * being routed to.
175 */
176#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
177
178static int __init ixdp2351_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
179{
180 u8 bus = dev->bus->number;
181 u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
182 struct pci_bus *tmp_bus = dev->bus;
183
184 /* Primary bus, no interrupts here */
185 if (!bus)
186 return -1;
187
188 /* Lookup first leaf in bus tree */
189 while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
190 tmp_bus = tmp_bus->parent;
191
192 /* Select between known bridges */
193 switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
194 /* Device is located after first bridge */
195 case 0x0008:
196 if (tmp_bus == dev->bus) {
197 /* Device is located directy after first bridge */
198 switch (devpin) {
199 /* Onboard 82546 */
200 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
201 return IRQ_IXDP2351_INTA_82546;
202 case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
203 return IRQ_IXDP2351_INTB_82546;
204 /* PMC SLOT */
205 case DEVPIN(0, 1): /* PMCP INTA# */
206 case DEVPIN(2, 4): /* PMCS INTD# */
207 return IRQ_IXDP2351_SPCI_PMC_INTA;
208 case DEVPIN(0, 2): /* PMCP INTB# */
209 case DEVPIN(2, 1): /* PMCS INTA# */
210 return IRQ_IXDP2351_SPCI_PMC_INTB;
211 case DEVPIN(0, 3): /* PMCP INTC# */
212 case DEVPIN(2, 2): /* PMCS INTB# */
213 return IRQ_IXDP2351_SPCI_PMC_INTC;
214 case DEVPIN(0, 4): /* PMCP INTD# */
215 case DEVPIN(2, 3): /* PMCS INTC# */
216 return IRQ_IXDP2351_SPCI_PMC_INTD;
217 }
218 } else {
219 /* Device is located indirectly after first bridge */
220 /* Not supported now */
221 return -1;
222 }
223 break;
224 case 0x0010:
225 if (tmp_bus == dev->bus) {
226 /* Device is located directy after second bridge */
227 /* Secondary bus of second bridge */
228 switch (devpin) {
229 case DEVPIN(0, 1): /* DB#0 */
230 case DEVPIN(0, 2):
231 case DEVPIN(0, 3):
232 case DEVPIN(0, 4):
233 return IRQ_IXDP2351_SPCI_DB_0;
234 case DEVPIN(1, 1): /* DB#1 */
235 case DEVPIN(1, 2):
236 case DEVPIN(1, 3):
237 case DEVPIN(1, 4):
238 return IRQ_IXDP2351_SPCI_DB_1;
239 case DEVPIN(2, 1): /* FIC1 */
240 case DEVPIN(2, 2):
241 case DEVPIN(2, 3):
242 case DEVPIN(2, 4):
243 case DEVPIN(3, 1): /* FIC2 */
244 case DEVPIN(3, 2):
245 case DEVPIN(3, 3):
246 case DEVPIN(3, 4):
247 return IRQ_IXDP2351_SPCI_FIC;
248 }
249 } else {
250 /* Device is located indirectly after second bridge */
251 /* Not supported now */
252 return -1;
253 }
254 break;
255 }
256
257 return -1;
258}
259
260struct hw_pci ixdp2351_pci __initdata = {
261 .nr_controllers = 1,
262 .preinit = ixp23xx_pci_preinit,
263 .setup = ixp23xx_pci_setup,
264 .scan = ixp23xx_pci_scan_bus,
265 .map_irq = ixdp2351_map_irq,
266};
267
268int __init ixdp2351_pci_init(void)
269{
270 if (machine_is_ixdp2351())
271 pci_common_init(&ixdp2351_pci);
272
273 return 0;
274}
275
276subsys_initcall(ixdp2351_pci_init);
277
278/*
279 * IXDP2351 Static Mapped I/O
280 */
281static struct map_desc ixdp2351_io_desc[] __initdata = {
282 {
283 .virtual = IXDP2351_NP_VIRT_BASE,
284 .pfn = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
285 .length = IXDP2351_NP_PHYS_SIZE,
286 .type = MT_DEVICE
287 }, {
288 .virtual = IXDP2351_BB_BASE_VIRT,
289 .pfn = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
290 .length = IXDP2351_BB_SIZE,
291 .type = MT_DEVICE
292 }
293};
294
295static void __init ixdp2351_map_io(void)
296{
297 ixp23xx_map_io();
298 iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
299}
300
301static void __init ixdp2351_init(void)
302{
303 physmap_configure(0x90000000, 0x04000000, 1, NULL);
304
305 /*
306 * Mark flash as writeable
307 */
308 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
309 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
310 IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
311 IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
312
313 ixp23xx_sys_init();
314}
315
316MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
317 /* Maintainer: MontaVista Software, Inc. */
318 .phys_io = IXP23XX_PERIPHERAL_PHYS,
319 .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
320 .map_io = ixdp2351_map_io,
321 .init_irq = ixdp2351_init_irq,
322 .timer = &ixp23xx_timer,
323 .boot_params = 0x00000100,
324 .init_machine = ixdp2351_init,
325MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
new file mode 100644
index 000000000000..5330ad78c1bb
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -0,0 +1,275 @@
1/*
2 * arch/arm/mach-ixp23xx/pci.c
3 *
4 * PCI routines for IXP23XX based systems
5 *
6 * Copyright (c) 2005 MontaVista Software, Inc.
7 *
8 * based on original code:
9 *
10 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
11 * Copyright 2002-2005 Intel Corp.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/config.h>
20#include <linux/sched.h>
21#include <linux/kernel.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/mm.h>
25#include <linux/init.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/delay.h>
29
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/sizes.h>
33#include <asm/system.h>
34#include <asm/mach/pci.h>
35#include <asm/mach-types.h>
36#include <asm/hardware.h>
37
38extern int (*external_fault) (unsigned long, struct pt_regs *);
39
40static int pci_master_aborts = 0;
41
42#ifdef DEBUG
43#define DBG(x...) printk(x)
44#else
45#define DBG(x...)
46#endif
47
48int clear_master_aborts(void);
49
50static u32
51*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
52{
53 u32 *paddress;
54
55 /*
56 * Must be dword aligned
57 */
58 where &= ~3;
59
60 /*
61 * For top bus, generate type 0, else type 1
62 */
63 if (!bus_nr) {
64 if (PCI_SLOT(devfn) >= 8)
65 return 0;
66
67 paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
68 | (1 << (PCI_SLOT(devfn) + 16))
69 | (PCI_FUNC(devfn) << 8) | where);
70 } else {
71 paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
72 | (bus_nr << 16)
73 | (PCI_SLOT(devfn) << 11)
74 | (PCI_FUNC(devfn) << 8) | where);
75 }
76
77 return paddress;
78}
79
80/*
81 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
82 * 0 and 3 are not valid indexes...
83 */
84static u32 bytemask[] = {
85 /*0*/ 0,
86 /*1*/ 0xff,
87 /*2*/ 0xffff,
88 /*3*/ 0,
89 /*4*/ 0xffffffff,
90};
91
92static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
93 int where, int size, u32 *value)
94{
95 u32 n;
96 u32 *addr;
97
98 n = where % 4;
99
100 DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
101 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
102
103 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
104 if (!addr)
105 return PCIBIOS_DEVICE_NOT_FOUND;
106
107 pci_master_aborts = 0;
108 *value = (*addr >> (8*n)) & bytemask[size];
109 if (pci_master_aborts) {
110 pci_master_aborts = 0;
111 *value = 0xffffffff;
112 return PCIBIOS_DEVICE_NOT_FOUND;
113 }
114
115 return PCIBIOS_SUCCESSFUL;
116}
117
118/*
119 * We don't do error checking on the address for writes.
120 * It's assumed that the user checked for the device existing first
121 * by doing a read first.
122 */
123static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
124 int where, int size, u32 value)
125{
126 u32 mask;
127 u32 *addr;
128 u32 temp;
129
130 mask = ~(bytemask[size] << ((where % 0x4) * 8));
131 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
132 if (!addr)
133 return PCIBIOS_DEVICE_NOT_FOUND;
134 temp = (u32) (value) << ((where % 0x4) * 8);
135 *addr = (*addr & mask) | temp;
136
137 clear_master_aborts();
138
139 return PCIBIOS_SUCCESSFUL;
140}
141
142struct pci_ops ixp23xx_pci_ops = {
143 .read = ixp23xx_pci_read_config,
144 .write = ixp23xx_pci_write_config,
145};
146
147struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
148{
149 return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
150}
151
152int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
153{
154 volatile unsigned long temp;
155 unsigned long flags;
156
157 pci_master_aborts = 1;
158
159 local_irq_save(flags);
160 temp = *IXP23XX_PCI_CONTROL;
161
162 /*
163 * master abort and cmd tgt err
164 */
165 if (temp & ((1 << 8) | (1 << 5)))
166 *IXP23XX_PCI_CONTROL = temp;
167
168 temp = *IXP23XX_PCI_CMDSTAT;
169
170 if (temp & (1 << 29))
171 *IXP23XX_PCI_CMDSTAT = temp;
172 local_irq_restore(flags);
173
174 /*
175 * If it was an imprecise abort, then we need to correct the
176 * return address to be _after_ the instruction.
177 */
178 if (fsr & (1 << 10))
179 regs->ARM_pc += 4;
180
181 return 0;
182}
183
184int clear_master_aborts(void)
185{
186 volatile u32 temp;
187
188 temp = *IXP23XX_PCI_CONTROL;
189
190 /*
191 * master abort and cmd tgt err
192 */
193 if (temp & ((1 << 8) | (1 << 5)))
194 *IXP23XX_PCI_CONTROL = temp;
195
196 temp = *IXP23XX_PCI_CMDSTAT;
197
198 if (temp & (1 << 29))
199 *IXP23XX_PCI_CMDSTAT = temp;
200
201 return 0;
202}
203
204void __init ixp23xx_pci_preinit(void)
205{
206#ifdef __ARMEB__
207 *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
208#endif
209 /*
210 * ADDR_31 needs to be clear for PCI memory access to CPP memory
211 */
212 *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
213 *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
214
215 /*
216 * Select correct memory for PCI inbound transactions
217 */
218 if (ixp23xx_cpp_boot()) {
219 *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
220 } else {
221 *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
222 }
223
224 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
225 "PCI config cycle to non-existent device");
226
227 *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
228}
229
230/*
231 * Prevent PCI layer from seeing the inbound host-bridge resources
232 */
233static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
234{
235 int i;
236
237 dev->class &= 0xff;
238 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
239 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
240 dev->resource[i].start = 0;
241 dev->resource[i].end = 0;
242 dev->resource[i].flags = 0;
243 }
244}
245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
246
247/*
248 * IXP2300 systems often have large resource requirements, so we just
249 * use our own resource space.
250 */
251static struct resource ixp23xx_pci_mem_space = {
252 .start = IXP23XX_PCI_MEM_START,
253 .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
254 .flags = IORESOURCE_MEM,
255 .name = "PCI Mem Space"
256};
257
258static struct resource ixp23xx_pci_io_space = {
259 .start = 0x00000100,
260 .end = 0x01ffffff,
261 .flags = IORESOURCE_IO,
262 .name = "PCI I/O Space"
263};
264
265int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
266{
267 if (nr >= 1)
268 return 0;
269
270 sys->resource[0] = &ixp23xx_pci_io_space;
271 sys->resource[1] = &ixp23xx_pci_mem_space;
272 sys->resource[2] = NULL;
273
274 return 1;
275}
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
new file mode 100644
index 000000000000..43c14e740794
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -0,0 +1,164 @@
1/*
2 * arch/arm/mach-ixp23xx/roadrunner.c
3 *
4 * RoadRunner board-specific routines
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2005 (c) ADI Engineering Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/config.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/sched.h>
22#include <linux/interrupt.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/ioport.h>
27#include <linux/serial.h>
28#include <linux/serial_8250.h>
29#include <linux/serial_core.h>
30#include <linux/device.h>
31#include <linux/mm.h>
32#include <linux/pci.h>
33#include <linux/mtd/physmap.h>
34
35#include <asm/types.h>
36#include <asm/setup.h>
37#include <asm/memory.h>
38#include <asm/hardware.h>
39#include <asm/mach-types.h>
40#include <asm/irq.h>
41#include <asm/system.h>
42#include <asm/tlbflush.h>
43#include <asm/pgtable.h>
44
45#include <asm/mach/map.h>
46#include <asm/mach/irq.h>
47#include <asm/mach/arch.h>
48#include <asm/mach/irq.h>
49#include <asm/mach/pci.h>
50
51/*
52 * Interrupt mapping
53 */
54#define INTA IRQ_ROADRUNNER_PCI_INTA
55#define INTB IRQ_ROADRUNNER_PCI_INTB
56#define INTC IRQ_ROADRUNNER_PCI_INTC
57#define INTD IRQ_ROADRUNNER_PCI_INTD
58
59#define INTC_PIN IXP23XX_GPIO_PIN_11
60#define INTD_PIN IXP23XX_GPIO_PIN_12
61
62static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
63{
64 static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA};
65 static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD};
66 static int usb_irq[] = {INTB, INTC, INTD, -1};
67 static int mini_pci_1_irq[] = {INTB, INTC, -1, -1};
68 static int mini_pci_2_irq[] = {INTC, INTD, -1, -1};
69
70 switch(dev->bus->number) {
71 case 0:
72 switch(dev->devfn) {
73 case 0x0: // PCI-PCI bridge
74 break;
75 case 0x8: // PCI Card Slot
76 return pci_card_slot_irq[pin - 1];
77 case 0x10: // PMC Slot
78 return pmc_card_slot_irq[pin - 1];
79 case 0x18: // PMC Slot Secondary Agent
80 break;
81 case 0x20: // IXP Processor
82 break;
83 default:
84 return NO_IRQ;
85 }
86 break;
87
88 case 1:
89 switch(dev->devfn) {
90 case 0x0: // IDE Controller
91 return (pin == 1) ? INTC : -1;
92 case 0x8: // USB fun 0
93 case 0x9: // USB fun 1
94 case 0xa: // USB fun 2
95 return usb_irq[pin - 1];
96 case 0x10: // Mini PCI 1
97 return mini_pci_1_irq[pin-1];
98 case 0x18: // Mini PCI 2
99 return mini_pci_2_irq[pin-1];
100 case 0x20: // MEM slot
101 return (pin == 1) ? INTA : -1;
102 default:
103 return NO_IRQ;
104 }
105 break;
106
107 default:
108 return NO_IRQ;
109 }
110
111 return NO_IRQ;
112}
113
114static void roadrunner_pci_preinit(void)
115{
116 set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQT_LOW);
117 set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQT_LOW);
118
119 ixp23xx_pci_preinit();
120}
121
122static struct hw_pci roadrunner_pci __initdata = {
123 .nr_controllers = 1,
124 .preinit = roadrunner_pci_preinit,
125 .setup = ixp23xx_pci_setup,
126 .scan = ixp23xx_pci_scan_bus,
127 .map_irq = roadrunner_map_irq,
128};
129
130static int __init roadrunner_pci_init(void)
131{
132 if (machine_is_roadrunner())
133 pci_common_init(&roadrunner_pci);
134
135 return 0;
136};
137
138subsys_initcall(roadrunner_pci_init);
139
140static void __init roadrunner_init(void)
141{
142 physmap_configure(0x90000000, 0x04000000, 2, NULL);
143
144 /*
145 * Mark flash as writeable
146 */
147 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
148 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
149 IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
150 IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
151
152 ixp23xx_sys_init();
153}
154
155MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
156 /* Maintainer: Deepak Saxena */
157 .phys_io = IXP23XX_PERIPHERAL_PHYS,
158 .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
159 .map_io = ixp23xx_map_io,
160 .init_irq = ixp23xx_init_irq,
161 .timer = &ixp23xx_timer,
162 .boot_params = 0x00000100,
163 .init_machine = roadrunner_init,
164MACHINE_END
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index c1d77f5b3823..0104fd142e70 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -10,6 +10,11 @@ config ARCH_LUBBOCK
10 select PXA25x 10 select PXA25x
11 select SA1111 11 select SA1111
12 12
13config MACH_LOGICPD_PXA270
14 bool "LogicPD PXA270 Card Engine Development Platform"
15 select PXA27x
16 select IWMMXT
17
13config MACH_MAINSTONE 18config MACH_MAINSTONE
14 bool "Intel HCDDBBVA0 Development Platform" 19 bool "Intel HCDDBBVA0 Development Platform"
15 select PXA27x 20 select PXA27x
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 382644401a4d..4e8a983e2b83 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PXA27x) += pxa27x.o
9 9
10# Specific board support 10# Specific board support
11obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o 11obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
12obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
12obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o 13obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
13obj-$(CONFIG_ARCH_PXA_IDP) += idp.o 14obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
14obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o 15obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
new file mode 100644
index 000000000000..ec0f43a102c7
--- /dev/null
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -0,0 +1,393 @@
1/*
2 * linux/arch/arm/mach-pxa/lpd270.c
3 *
4 * Support for the LogicPD PXA270 Card Engine.
5 * Derived from the mainstone code, which carries these notices:
6 *
7 * Author: Nicolas Pitre
8 * Created: Nov 05, 2002
9 * Copyright: MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/sysdev.h>
19#include <linux/interrupt.h>
20#include <linux/sched.h>
21#include <linux/bitops.h>
22#include <linux/fb.h>
23#include <linux/ioport.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26
27#include <asm/types.h>
28#include <asm/setup.h>
29#include <asm/memory.h>
30#include <asm/mach-types.h>
31#include <asm/hardware.h>
32#include <asm/irq.h>
33#include <asm/sizes.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/irq.h>
38#include <asm/mach/flash.h>
39
40#include <asm/arch/pxa-regs.h>
41#include <asm/arch/lpd270.h>
42#include <asm/arch/audio.h>
43#include <asm/arch/pxafb.h>
44#include <asm/arch/mmc.h>
45#include <asm/arch/irda.h>
46#include <asm/arch/ohci.h>
47
48#include "generic.h"
49
50
51static unsigned int lpd270_irq_enabled;
52
53static void lpd270_mask_irq(unsigned int irq)
54{
55 int lpd270_irq = irq - LPD270_IRQ(0);
56
57 __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
58
59 lpd270_irq_enabled &= ~(1 << lpd270_irq);
60 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
61}
62
63static void lpd270_unmask_irq(unsigned int irq)
64{
65 int lpd270_irq = irq - LPD270_IRQ(0);
66
67 lpd270_irq_enabled |= 1 << lpd270_irq;
68 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
69}
70
71static struct irqchip lpd270_irq_chip = {
72 .ack = lpd270_mask_irq,
73 .mask = lpd270_mask_irq,
74 .unmask = lpd270_unmask_irq,
75};
76
77static void lpd270_irq_handler(unsigned int irq, struct irqdesc *desc,
78 struct pt_regs *regs)
79{
80 unsigned long pending;
81
82 pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
83 do {
84 GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
85 if (likely(pending)) {
86 irq = LPD270_IRQ(0) + __ffs(pending);
87 desc = irq_desc + irq;
88 desc_handle_irq(irq, desc, regs);
89
90 pending = __raw_readw(LPD270_INT_STATUS) &
91 lpd270_irq_enabled;
92 }
93 } while (pending);
94}
95
96static void __init lpd270_init_irq(void)
97{
98 int irq;
99
100 pxa_init_irq();
101
102 __raw_writew(0, LPD270_INT_MASK);
103 __raw_writew(0, LPD270_INT_STATUS);
104
105 /* setup extra LogicPD PXA270 irqs */
106 for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
107 set_irq_chip(irq, &lpd270_irq_chip);
108 set_irq_handler(irq, do_level_IRQ);
109 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
110 }
111 set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
112 set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
113}
114
115
116#ifdef CONFIG_PM
117static int lpd270_irq_resume(struct sys_device *dev)
118{
119 __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
120 return 0;
121}
122
123static struct sysdev_class lpd270_irq_sysclass = {
124 set_kset_name("cpld_irq"),
125 .resume = lpd270_irq_resume,
126};
127
128static struct sys_device lpd270_irq_device = {
129 .cls = &lpd270_irq_sysclass,
130};
131
132static int __init lpd270_irq_device_init(void)
133{
134 int ret = sysdev_class_register(&lpd270_irq_sysclass);
135 if (ret == 0)
136 ret = sysdev_register(&lpd270_irq_device);
137 return ret;
138}
139
140device_initcall(lpd270_irq_device_init);
141#endif
142
143
144static struct resource smc91x_resources[] = {
145 [0] = {
146 .start = LPD270_ETH_PHYS,
147 .end = (LPD270_ETH_PHYS + 0xfffff),
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = LPD270_ETHERNET_IRQ,
152 .end = LPD270_ETHERNET_IRQ,
153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct platform_device smc91x_device = {
158 .name = "smc91x",
159 .id = 0,
160 .num_resources = ARRAY_SIZE(smc91x_resources),
161 .resource = smc91x_resources,
162};
163
164static struct platform_device lpd270_audio_device = {
165 .name = "pxa2xx-ac97",
166 .id = -1,
167};
168
169static struct resource lpd270_flash_resources[] = {
170 [0] = {
171 .start = PXA_CS0_PHYS,
172 .end = PXA_CS0_PHYS + SZ_64M - 1,
173 .flags = IORESOURCE_MEM,
174 },
175 [1] = {
176 .start = PXA_CS1_PHYS,
177 .end = PXA_CS1_PHYS + SZ_64M - 1,
178 .flags = IORESOURCE_MEM,
179 },
180};
181
182static struct mtd_partition lpd270_flash0_partitions[] = {
183 {
184 .name = "Bootloader",
185 .size = 0x00040000,
186 .offset = 0,
187 .mask_flags = MTD_WRITEABLE /* force read-only */
188 }, {
189 .name = "Kernel",
190 .size = 0x00400000,
191 .offset = 0x00040000,
192 }, {
193 .name = "Filesystem",
194 .size = MTDPART_SIZ_FULL,
195 .offset = 0x00440000
196 },
197};
198
199static struct flash_platform_data lpd270_flash_data[2] = {
200 {
201 .name = "processor-flash",
202 .map_name = "cfi_probe",
203 .parts = lpd270_flash0_partitions,
204 .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
205 }, {
206 .name = "mainboard-flash",
207 .map_name = "cfi_probe",
208 .parts = NULL,
209 .nr_parts = 0,
210 }
211};
212
213static struct platform_device lpd270_flash_device[2] = {
214 {
215 .name = "pxa2xx-flash",
216 .id = 0,
217 .dev = {
218 .platform_data = &lpd270_flash_data[0],
219 },
220 .resource = &lpd270_flash_resources[0],
221 .num_resources = 1,
222 }, {
223 .name = "pxa2xx-flash",
224 .id = 1,
225 .dev = {
226 .platform_data = &lpd270_flash_data[1],
227 },
228 .resource = &lpd270_flash_resources[1],
229 .num_resources = 1,
230 },
231};
232
233static void lpd270_backlight_power(int on)
234{
235 if (on) {
236 pxa_gpio_mode(GPIO16_PWM0_MD);
237 pxa_set_cken(CKEN0_PWM0, 1);
238 PWM_CTRL0 = 0;
239 PWM_PWDUTY0 = 0x3ff;
240 PWM_PERVAL0 = 0x3ff;
241 } else {
242 PWM_CTRL0 = 0;
243 PWM_PWDUTY0 = 0x0;
244 PWM_PERVAL0 = 0x3FF;
245 pxa_set_cken(CKEN0_PWM0, 0);
246 }
247}
248
249/* 5.7" TFT QVGA (LoLo display number 1) */
250static struct pxafb_mach_info sharp_lq057q3dc02 __initdata = {
251 .pixclock = 100000,
252 .xres = 240,
253 .yres = 320,
254 .bpp = 16,
255 .hsync_len = 64,
256 .left_margin = 0x27,
257 .right_margin = 0x09,
258 .vsync_len = 0x04,
259 .upper_margin = 0x08,
260 .lower_margin = 0x14,
261 .sync = 0,
262 .lccr0 = 0x07800080,
263 .lccr3 = 0x04400007,
264 .pxafb_backlight_power = lpd270_backlight_power,
265};
266
267/* 6.4" TFT VGA (LoLo display number 5) */
268static struct pxafb_mach_info sharp_lq64d343 __initdata = {
269 .pixclock = 20000,
270 .xres = 640,
271 .yres = 480,
272 .bpp = 16,
273 .hsync_len = 49,
274 .left_margin = 0x89,
275 .right_margin = 0x19,
276 .vsync_len = 18,
277 .upper_margin = 0x22,
278 .lower_margin = 0,
279 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
280 .lccr0 = 0x07800080,
281 .lccr3 = 0x04400001,
282 .pxafb_backlight_power = lpd270_backlight_power,
283};
284
285/* 3.5" TFT QVGA (LoLo display number 8) */
286static struct pxafb_mach_info sharp_lq035q7db02_20 __initdata = {
287 .pixclock = 100000,
288 .xres = 240,
289 .yres = 320,
290 .bpp = 16,
291 .hsync_len = 0x34,
292 .left_margin = 0x09,
293 .right_margin = 0x09,
294 .vsync_len = 0x08,
295 .upper_margin = 0x05,
296 .lower_margin = 0x14,
297 .sync = 0,
298 .lccr0 = 0x07800080,
299 .lccr3 = 0x04400007,
300 .pxafb_backlight_power = lpd270_backlight_power,
301};
302
303static struct platform_device *platform_devices[] __initdata = {
304 &smc91x_device,
305 &lpd270_audio_device,
306 &lpd270_flash_device[0],
307 &lpd270_flash_device[1],
308};
309
310static int lpd270_ohci_init(struct device *dev)
311{
312 /* setup Port1 GPIO pin. */
313 pxa_gpio_mode(88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
314 pxa_gpio_mode(89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
315
316 /* Set the Power Control Polarity Low and Power Sense
317 Polarity Low to active low. */
318 UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
319 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
320
321 return 0;
322}
323
324static struct pxaohci_platform_data lpd270_ohci_platform_data = {
325 .port_mode = PMM_PERPORT_MODE,
326 .init = lpd270_ohci_init,
327};
328
329static void __init lpd270_init(void)
330{
331 lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
332 lpd270_flash_data[1].width = 4;
333
334 /*
335 * System bus arbiter setting:
336 * - Core_Park
337 * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
338 */
339 ARB_CNTRL = ARB_CORE_PARK | 0x234;
340
341 /*
342 * On LogicPD PXA270, we route AC97_SYSCLK via GPIO45.
343 */
344 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
345
346 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
347
348 // set_pxa_fb_info(&sharp_lq057q3dc02);
349 set_pxa_fb_info(&sharp_lq64d343);
350 // set_pxa_fb_info(&sharp_lq035q7db02_20);
351
352 pxa_set_ohci_info(&lpd270_ohci_platform_data);
353}
354
355
356static struct map_desc lpd270_io_desc[] __initdata = {
357 {
358 .virtual = LPD270_CPLD_VIRT,
359 .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
360 .length = LPD270_CPLD_SIZE,
361 .type = MT_DEVICE,
362 },
363};
364
365static void __init lpd270_map_io(void)
366{
367 pxa_map_io();
368 iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
369
370 /* initialize sleep mode regs (wake-up sources, etc) */
371 PGSR0 = 0x00008800;
372 PGSR1 = 0x00000002;
373 PGSR2 = 0x0001FC00;
374 PGSR3 = 0x00001F81;
375 PWER = 0xC0000002;
376 PRER = 0x00000002;
377 PFER = 0x00000002;
378
379 /* for use I SRAM as framebuffer. */
380 PSLR |= 0x00000F04;
381 PCFR = 0x00000066;
382}
383
384MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
385 /* Maintainer: Peter Barada */
386 .phys_io = 0x40000000,
387 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
388 .boot_params = 0xa0000100,
389 .map_io = lpd270_map_io,
390 .init_irq = lpd270_init_irq,
391 .timer = &pxa_timer,
392 .init_machine = lpd270_init,
393MACHINE_END
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 30ec317bbb97..0dbb079ecd25 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -467,6 +467,8 @@ struct platform_device akitaioexp_device = {
467 .id = -1, 467 .id = -1,
468}; 468};
469 469
470EXPORT_SYMBOL_GPL(akitaioexp_device);
471
470static void __init akita_init(void) 472static void __init akita_init(void)
471{ 473{
472 spitz_ficp_platform_data.transceiver_mode = akita_irda_transceiver_mode; 474 spitz_ficp_platform_data.transceiver_mode = akita_irda_transceiver_mode;
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 6923316b3d0d..cd67ab1b217b 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -111,7 +111,7 @@ config SA1100_LART
111 bool "LART" 111 bool "LART"
112 help 112 help
113 Say Y here if you are using the Linux Advanced Radio Terminal 113 Say Y here if you are using the Linux Advanced Radio Terminal
114 (also known as the LART). See <http://www.lart.tudelft.nl/> for 114 (also known as the LART). See <http://www.lartmaker.nl/> for
115 information on the LART. 115 information on the LART.
116 116
117config SA1100_PLEB 117config SA1100_PLEB
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index 6435b2e48ffa..d68630b74d78 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -11,7 +11,7 @@
11 * linux-2.4.5-rmk1 11 * linux-2.4.5-rmk1
12 * 12 *
13 * This software has been developed while working on the LART 13 * This software has been developed while working on the LART
14 * computing board (http://www.lart.tudelft.nl/), which is 14 * computing board (http://www.lartmaker.nl/), which is
15 * sponsored by the Mobile Multi-media Communications 15 * sponsored by the Mobile Multi-media Communications
16 * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications 16 * (http://www.mmc.tudelft.nl/) and Ubiquitous Communications
17 * (http://www.ubicom.tudelft.nl/) projects. 17 * (http://www.ubicom.tudelft.nl/) projects.
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e680c5fd93b5..c55b739e10ba 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -239,6 +239,17 @@ config CPU_XSCALE
239 select CPU_CACHE_VIVT 239 select CPU_CACHE_VIVT
240 select CPU_TLB_V4WBI 240 select CPU_TLB_V4WBI
241 241
242# XScale Core Version 3
243config CPU_XSC3
244 bool
245 depends on ARCH_IXP23XX
246 default y
247 select CPU_32v5
248 select CPU_ABRT_EV5T
249 select CPU_CACHE_VIVT
250 select CPU_TLB_V4WBI
251 select IO_36
252
242# ARMv6 253# ARMv6
243config CPU_V6 254config CPU_V6
244 bool "Support ARM V6 processor" 255 bool "Support ARM V6 processor"
@@ -361,11 +372,17 @@ config CPU_TLB_V4WBI
361config CPU_TLB_V6 372config CPU_TLB_V6
362 bool 373 bool
363 374
375#
376# CPU supports 36-bit I/O
377#
378config IO_36
379 bool
380
364comment "Processor Features" 381comment "Processor Features"
365 382
366config ARM_THUMB 383config ARM_THUMB
367 bool "Support Thumb user binaries" 384 bool "Support Thumb user binaries"
368 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_V6 385 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
369 default y 386 default y
370 help 387 help
371 Say Y if you want to include kernel support for running user space 388 Say Y if you want to include kernel support for running user space
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index ffe73ba2bf17..07a538505784 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o
30obj-$(CONFIG_CPU_COPY_V6) += copypage-v6.o mmu.o 30obj-$(CONFIG_CPU_COPY_V6) += copypage-v6.o mmu.o
31obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o 31obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o
32obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o 32obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o
33obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
33 34
34obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o 35obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o
35obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o 36obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
@@ -51,4 +52,5 @@ obj-$(CONFIG_CPU_ARM1026) += proc-arm1026.o
51obj-$(CONFIG_CPU_SA110) += proc-sa110.o 52obj-$(CONFIG_CPU_SA110) += proc-sa110.o
52obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o 53obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o
53obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o 54obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o
55obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o
54obj-$(CONFIG_CPU_V6) += proc-v6.o 56obj-$(CONFIG_CPU_V6) += proc-v6.o
diff --git a/arch/arm/mm/copypage-xsc3.S b/arch/arm/mm/copypage-xsc3.S
new file mode 100644
index 000000000000..9a2cb4332b4c
--- /dev/null
+++ b/arch/arm/mm/copypage-xsc3.S
@@ -0,0 +1,97 @@
1/*
2 * linux/arch/arm/lib/copypage-xsc3.S
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Adapted for 3rd gen XScale core, no more mini-dcache
11 * Author: Matt Gilbert (matthew.m.gilbert@intel.com)
12 */
13
14#include <linux/linkage.h>
15#include <linux/init.h>
16#include <asm/asm-offsets.h>
17
18/*
19 * General note:
20 * We don't really want write-allocate cache behaviour for these functions
21 * since that will just eat through 8K of the cache.
22 */
23
24 .text
25 .align 5
26/*
27 * XSC3 optimised copy_user_page
28 * r0 = destination
29 * r1 = source
30 * r2 = virtual user address of ultimate destination page
31 *
32 * The source page may have some clean entries in the cache already, but we
33 * can safely ignore them - break_cow() will flush them out of the cache
34 * if we eventually end up using our copied page.
35 *
36 */
37ENTRY(xsc3_mc_copy_user_page)
38 stmfd sp!, {r4, r5, lr}
39 mov lr, #PAGE_SZ/64-1
40
41 pld [r1, #0]
42 pld [r1, #32]
431: pld [r1, #64]
44 pld [r1, #96]
45
462: ldrd r2, [r1], #8
47 mov ip, r0
48 ldrd r4, [r1], #8
49 mcr p15, 0, ip, c7, c6, 1 @ invalidate
50 strd r2, [r0], #8
51 ldrd r2, [r1], #8
52 strd r4, [r0], #8
53 ldrd r4, [r1], #8
54 strd r2, [r0], #8
55 strd r4, [r0], #8
56 ldrd r2, [r1], #8
57 mov ip, r0
58 ldrd r4, [r1], #8
59 mcr p15, 0, ip, c7, c6, 1 @ invalidate
60 strd r2, [r0], #8
61 ldrd r2, [r1], #8
62 subs lr, lr, #1
63 strd r4, [r0], #8
64 ldrd r4, [r1], #8
65 strd r2, [r0], #8
66 strd r4, [r0], #8
67 bgt 1b
68 beq 2b
69
70 ldmfd sp!, {r4, r5, pc}
71
72 .align 5
73/*
74 * XScale optimised clear_user_page
75 * r0 = destination
76 * r1 = virtual user address of ultimate destination page
77 */
78ENTRY(xsc3_mc_clear_user_page)
79 mov r1, #PAGE_SZ/32
80 mov r2, #0
81 mov r3, #0
821: mcr p15, 0, r0, c7, c6, 1 @ invalidate line
83 strd r2, [r0], #8
84 strd r2, [r0], #8
85 strd r2, [r0], #8
86 strd r2, [r0], #8
87 subs r1, r1, #1
88 bne 1b
89 mov pc, lr
90
91 __INITDATA
92
93 .type xsc3_mc_user_fns, #object
94ENTRY(xsc3_mc_user_fns)
95 .long xsc3_mc_clear_user_page
96 .long xsc3_mc_copy_user_page
97 .size xsc3_mc_user_fns, . - xsc3_mc_user_fns
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index ef8d30a185a9..5e5d05bcad50 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -557,7 +557,8 @@ void __init create_mapping(struct map_desc *md)
557 * supersections are only allocated for domain 0 regardless 557 * supersections are only allocated for domain 0 regardless
558 * of the actual domain assignments in use. 558 * of the actual domain assignments in use.
559 */ 559 */
560 if (cpu_architecture() >= CPU_ARCH_ARMv6 && domain == 0) { 560 if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
561 && domain == 0) {
561 /* 562 /*
562 * Align to supersection boundary if !high pages. 563 * Align to supersection boundary if !high pages.
563 * High pages have already been checked for proper 564 * High pages have already been checked for proper
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 9a7e7c096aa9..ee6f15298735 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -21,6 +21,14 @@
21 21
22#define D_CACHE_LINE_SIZE 32 22#define D_CACHE_LINE_SIZE 32
23 23
24#define TTB_C (1 << 0)
25#define TTB_S (1 << 1)
26#define TTB_IMP (1 << 2)
27#define TTB_RGN_NC (0 << 3)
28#define TTB_RGN_WBWA (1 << 3)
29#define TTB_RGN_WT (2 << 3)
30#define TTB_RGN_WB (3 << 3)
31
24 .macro cpsie, flags 32 .macro cpsie, flags
25 .ifc \flags, f 33 .ifc \flags, f
26 .long 0xf1080040 34 .long 0xf1080040
@@ -115,7 +123,7 @@ ENTRY(cpu_v6_switch_mm)
115 mov r2, #0 123 mov r2, #0
116 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 124 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
117#ifdef CONFIG_SMP 125#ifdef CONFIG_SMP
118 orr r0, r0, #2 @ set shared pgtable 126 orr r0, r0, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
119#endif 127#endif
120 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 128 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
121 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 129 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
@@ -161,8 +169,8 @@ ENTRY(cpu_v6_set_pte)
161 tst r1, #L_PTE_YOUNG 169 tst r1, #L_PTE_YOUNG
162 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK 170 biceq r2, r2, #PTE_EXT_APX | PTE_EXT_AP_MASK
163 171
164@ tst r1, #L_PTE_EXEC 172 tst r1, #L_PTE_EXEC
165@ orreq r2, r2, #PTE_EXT_XN 173 orreq r2, r2, #PTE_EXT_XN
166 174
167 tst r1, #L_PTE_PRESENT 175 tst r1, #L_PTE_PRESENT
168 moveq r2, #0 176 moveq r2, #0
@@ -221,7 +229,7 @@ __v6_setup:
221 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 229 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
222 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 230 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
223#ifdef CONFIG_SMP 231#ifdef CONFIG_SMP
224 orr r4, r4, #2 @ set shared pgtable 232 orr r4, r4, #TTB_RGN_WBWA|TTB_S @ mark PTWs shared, outer cacheable
225#endif 233#endif
226 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 234 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
227#ifdef CONFIG_VFP 235#ifdef CONFIG_VFP
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
new file mode 100644
index 000000000000..f90513e9af0c
--- /dev/null
+++ b/arch/arm/mm/proc-xsc3.S
@@ -0,0 +1,498 @@
1/*
2 * linux/arch/arm/mm/proc-xsc3.S
3 *
4 * Original Author: Matthew Gilbert
5 * Current Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright 2004 (C) Intel Corp.
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is an
15 * extension to Intel's original XScale core that adds the following
16 * features:
17 *
18 * - ARMv6 Supersections
19 * - Low Locality Reference pages (replaces mini-cache)
20 * - 36-bit addressing
21 * - L2 cache
22 * - Cache-coherency if chipset supports it
23 *
24 * Based on orignal XScale code by Nicolas Pitre
25 */
26
27#include <linux/linkage.h>
28#include <linux/init.h>
29#include <asm/assembler.h>
30#include <asm/procinfo.h>
31#include <asm/hardware.h>
32#include <asm/pgtable.h>
33#include <asm/page.h>
34#include <asm/ptrace.h>
35#include "proc-macros.S"
36
37/*
38 * This is the maximum size of an area which will be flushed. If the
39 * area is larger than this, then we flush the whole cache.
40 */
41#define MAX_AREA_SIZE 32768
42
43/*
44 * The cache line size of the I and D cache.
45 */
46#define CACHELINESIZE 32
47
48/*
49 * The size of the data cache.
50 */
51#define CACHESIZE 32768
52
53/*
54 * Run with L2 enabled.
55 */
56#define L2_CACHE_ENABLE 1
57
58/*
59 * Enable the Branch Target Buffer (can cause crashes, see erratum #42.)
60 */
61#define BTB_ENABLE 0
62
63/*
64 * This macro is used to wait for a CP15 write and is needed
65 * when we have to ensure that the last operation to the co-pro
66 * was completed before continuing with operation.
67 */
68 .macro cpwait_ret, lr, rd
69 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
70 sub pc, \lr, \rd, LSR #32 @ wait for completion and
71 @ flush instruction pipeline
72 .endm
73
74/*
75 * This macro cleans & invalidates the entire xsc3 dcache by set & way.
76 */
77
78 .macro clean_d_cache rd, rs
79 mov \rd, #0x1f00
80 orr \rd, \rd, #0x00e0
811: mcr p15, 0, \rd, c7, c14, 2 @ clean/inv set/way
82 adds \rd, \rd, #0x40000000
83 bcc 1b
84 subs \rd, \rd, #0x20
85 bpl 1b
86 .endm
87
88 .text
89
90/*
91 * cpu_xsc3_proc_init()
92 *
93 * Nothing too exciting at the moment
94 */
95ENTRY(cpu_xsc3_proc_init)
96 mov pc, lr
97
98/*
99 * cpu_xsc3_proc_fin()
100 */
101ENTRY(cpu_xsc3_proc_fin)
102 str lr, [sp, #-4]!
103 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
104 msr cpsr_c, r0
105 bl xsc3_flush_kern_cache_all @ clean caches
106 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
107 bic r0, r0, #0x1800 @ ...IZ...........
108 bic r0, r0, #0x0006 @ .............CA.
109 mcr p15, 0, r0, c1, c0, 0 @ disable caches
110 ldr pc, [sp], #4
111
112/*
113 * cpu_xsc3_reset(loc)
114 *
115 * Perform a soft reset of the system. Put the CPU into the
116 * same state as it would be if it had been reset, and branch
117 * to what would be the reset vector.
118 *
119 * loc: location to jump to for soft reset
120 */
121 .align 5
122ENTRY(cpu_xsc3_reset)
123 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
124 msr cpsr_c, r1 @ reset CPSR
125 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
126 bic r1, r1, #0x0086 @ ........B....CA.
127 bic r1, r1, #0x3900 @ ..VIZ..S........
128 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
129 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
130 bic r1, r1, #0x0001 @ ...............M
131 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
132 @ CAUTION: MMU turned off from this point. We count on the pipeline
133 @ already containing those two last instructions to survive.
134 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
135 mov pc, r0
136
137/*
138 * cpu_xsc3_do_idle()
139 *
140 * Cause the processor to idle
141 *
142 * For now we do nothing but go to idle mode for every case
143 *
144 * XScale supports clock switching, but using idle mode support
145 * allows external hardware to react to system state changes.
146
147 MMG: Come back to this one.
148 */
149 .align 5
150
151ENTRY(cpu_xsc3_do_idle)
152 mov r0, #1
153 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
154 mov pc, lr
155
156/* ================================= CACHE ================================ */
157
158/*
159 * flush_user_cache_all()
160 *
161 * Invalidate all cache entries in a particular address
162 * space.
163 */
164ENTRY(xsc3_flush_user_cache_all)
165 /* FALLTHROUGH */
166
167/*
168 * flush_kern_cache_all()
169 *
170 * Clean and invalidate the entire cache.
171 */
172ENTRY(xsc3_flush_kern_cache_all)
173 mov r2, #VM_EXEC
174 mov ip, #0
175__flush_whole_cache:
176 clean_d_cache r0, r1
177 tst r2, #VM_EXEC
178 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
179 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
180 mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
181 mov pc, lr
182
183/*
184 * flush_user_cache_range(start, end, vm_flags)
185 *
186 * Invalidate a range of cache entries in the specified
187 * address space.
188 *
189 * - start - start address (may not be aligned)
190 * - end - end address (exclusive, may not be aligned)
191 * - vma - vma_area_struct describing address space
192 */
193 .align 5
194ENTRY(xsc3_flush_user_cache_range)
195 mov ip, #0
196 sub r3, r1, r0 @ calculate total size
197 cmp r3, #MAX_AREA_SIZE
198 bhs __flush_whole_cache
199
2001: tst r2, #VM_EXEC
201 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
202 mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate D cache line
203 add r0, r0, #CACHELINESIZE
204 cmp r0, r1
205 blo 1b
206 tst r2, #VM_EXEC
207 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
208 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
209 mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
210 mov pc, lr
211
212/*
213 * coherent_kern_range(start, end)
214 *
215 * Ensure coherency between the Icache and the Dcache in the
216 * region described by start. If you have non-snooping
217 * Harvard caches, you need to implement this function.
218 *
219 * - start - virtual start address
220 * - end - virtual end address
221 *
222 * Note: single I-cache line invalidation isn't used here since
223 * it also trashes the mini I-cache used by JTAG debuggers.
224 */
225ENTRY(xsc3_coherent_kern_range)
226/* FALLTHROUGH */
227ENTRY(xsc3_coherent_user_range)
228 bic r0, r0, #CACHELINESIZE - 1
2291: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
230 add r0, r0, #CACHELINESIZE
231 cmp r0, r1
232 blo 1b
233 mov r0, #0
234 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
235 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
236 mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
237 mov pc, lr
238
239/*
240 * flush_kern_dcache_page(void *page)
241 *
242 * Ensure no D cache aliasing occurs, either with itself or
243 * the I cache
244 *
245 * - addr - page aligned address
246 */
247ENTRY(xsc3_flush_kern_dcache_page)
248 add r1, r0, #PAGE_SZ
2491: mcr p15, 0, r0, c7, c14, 1 @ Clean/Invalidate D Cache line
250 add r0, r0, #CACHELINESIZE
251 cmp r0, r1
252 blo 1b
253 mov r0, #0
254 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
255 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
256 mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
257 mov pc, lr
258
259/*
260 * dma_inv_range(start, end)
261 *
262 * Invalidate (discard) the specified virtual address range.
263 * May not write back any entries. If 'start' or 'end'
264 * are not cache line aligned, those lines must be written
265 * back.
266 *
267 * - start - virtual start address
268 * - end - virtual end address
269 */
270ENTRY(xsc3_dma_inv_range)
271 tst r0, #CACHELINESIZE - 1
272 bic r0, r0, #CACHELINESIZE - 1
273 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D entry
274 mcrne p15, 1, r0, c7, c11, 1 @ clean L2 D entry
275 tst r1, #CACHELINESIZE - 1
276 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D entry
277 mcrne p15, 1, r1, c7, c11, 1 @ clean L2 D entry
2781: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D entry
279 mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
280 add r0, r0, #CACHELINESIZE
281 cmp r0, r1
282 blo 1b
283 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
284 mov pc, lr
285
286/*
287 * dma_clean_range(start, end)
288 *
289 * Clean the specified virtual address range.
290 *
291 * - start - virtual start address
292 * - end - virtual end address
293 */
294ENTRY(xsc3_dma_clean_range)
295 bic r0, r0, #CACHELINESIZE - 1
2961: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D entry
297 mcr p15, 1, r0, c7, c11, 1 @ clean L2 D entry
298 add r0, r0, #CACHELINESIZE
299 cmp r0, r1
300 blo 1b
301 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
302 mov pc, lr
303
304/*
305 * dma_flush_range(start, end)
306 *
307 * Clean and invalidate the specified virtual address range.
308 *
309 * - start - virtual start address
310 * - end - virtual end address
311 */
312ENTRY(xsc3_dma_flush_range)
313 bic r0, r0, #CACHELINESIZE - 1
3141: mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate L1 D cache line
315 mcr p15, 1, r0, c7, c11, 1 @ Clean L2 D cache line
316 mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
317 add r0, r0, #CACHELINESIZE
318 cmp r0, r1
319 blo 1b
320 mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
321 mov pc, lr
322
323ENTRY(xsc3_cache_fns)
324 .long xsc3_flush_kern_cache_all
325 .long xsc3_flush_user_cache_all
326 .long xsc3_flush_user_cache_range
327 .long xsc3_coherent_kern_range
328 .long xsc3_coherent_user_range
329 .long xsc3_flush_kern_dcache_page
330 .long xsc3_dma_inv_range
331 .long xsc3_dma_clean_range
332 .long xsc3_dma_flush_range
333
334ENTRY(cpu_xsc3_dcache_clean_area)
3351: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
336 add r0, r0, #CACHELINESIZE
337 subs r1, r1, #CACHELINESIZE
338 bhi 1b
339 mov pc, lr
340
341/* =============================== PageTable ============================== */
342
343/*
344 * cpu_xsc3_switch_mm(pgd)
345 *
346 * Set the translation base pointer to be as described by pgd.
347 *
348 * pgd: new page tables
349 */
350 .align 5
351ENTRY(cpu_xsc3_switch_mm)
352 clean_d_cache r1, r2
353 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
354 mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
355 mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
356#ifdef L2_CACHE_ENABLE
357 orr r0, r0, #0x18 @ cache the page table in L2
358#endif
359 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
360 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
361 cpwait_ret lr, ip
362
363/*
364 * cpu_xsc3_set_pte(ptep, pte)
365 *
366 * Set a PTE and flush it out
367 *
368 */
369 .align 5
370ENTRY(cpu_xsc3_set_pte)
371 str r1, [r0], #-2048 @ linux version
372
373 bic r2, r1, #0xff0
374 orr r2, r2, #PTE_TYPE_EXT @ extended page
375
376 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
377
378 tst r3, #L_PTE_USER @ User?
379 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
380
381 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
382 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
383 @ combined with user -> user r/w
384
385#if L2_CACHE_ENABLE
386 @ If its cacheable it needs to be in L2 also.
387 eor ip, r1, #L_PTE_CACHEABLE
388 tst ip, #L_PTE_CACHEABLE
389 orreq r2, r2, #PTE_EXT_TEX(0x5)
390#endif
391
392 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
393 movne r2, #0 @ no -> fault
394
395 str r2, [r0] @ hardware version
396 mov ip, #0
397 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line mcr
398 mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
399 mov pc, lr
400
401 .ltorg
402
403 .align
404
405 __INIT
406
407 .type __xsc3_setup, #function
408__xsc3_setup:
409 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
410 msr cpsr_c, r0
411 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
412 mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
413 mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
414 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
415#if L2_CACHE_ENABLE
416 orr r4, r4, #0x18 @ cache the page table in L2
417#endif
418 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
419 mov r0, #1 @ Allow access to CP0 and CP13
420 orr r0, r0, #1 << 13 @ Its undefined whether this
421 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
422 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
423 and r0, r0, #2 @ preserve bit P bit setting
424#if L2_CACHE_ENABLE
425 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
426#endif
427 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
428 mrc p15, 0, r0, c1, c0, 0 @ get control register
429 bic r0, r0, #0x0200 @ .... ..R. .... ....
430 bic r0, r0, #0x0002 @ .... .... .... ..A.
431 orr r0, r0, #0x0005 @ .... .... .... .C.M
432#if BTB_ENABLE
433 orr r0, r0, #0x3900 @ ..VI Z..S .... ....
434#else
435 orr r0, r0, #0x3100 @ ..VI ...S .... ....
436#endif
437#if L2_CACHE_ENABLE
438 orr r0, r0, #0x4000000 @ L2 enable
439#endif
440 mov pc, lr
441
442 .size __xsc3_setup, . - __xsc3_setup
443
444 __INITDATA
445
446/*
447 * Purpose : Function pointers used to access above functions - all calls
448 * come through these
449 */
450
451 .type xsc3_processor_functions, #object
452ENTRY(xsc3_processor_functions)
453 .word v5t_early_abort
454 .word cpu_xsc3_proc_init
455 .word cpu_xsc3_proc_fin
456 .word cpu_xsc3_reset
457 .word cpu_xsc3_do_idle
458 .word cpu_xsc3_dcache_clean_area
459 .word cpu_xsc3_switch_mm
460 .word cpu_xsc3_set_pte
461 .size xsc3_processor_functions, . - xsc3_processor_functions
462
463 .section ".rodata"
464
465 .type cpu_arch_name, #object
466cpu_arch_name:
467 .asciz "armv5te"
468 .size cpu_arch_name, . - cpu_arch_name
469
470 .type cpu_elf_name, #object
471cpu_elf_name:
472 .asciz "v5"
473 .size cpu_elf_name, . - cpu_elf_name
474
475 .type cpu_xsc3_name, #object
476cpu_xsc3_name:
477 .asciz "XScale-Core3"
478 .size cpu_xsc3_name, . - cpu_xsc3_name
479
480 .align
481
482 .section ".proc.info.init", #alloc, #execinstr
483
484 .type __xsc3_proc_info,#object
485__xsc3_proc_info:
486 .long 0x69056000
487 .long 0xffffe000
488 .long 0x00000c0e
489 b __xsc3_setup
490 .long cpu_arch_name
491 .long cpu_elf_name
492 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
493 .long cpu_xsc3_name
494 .long xsc3_processor_functions
495 .long v4wbi_tlb_fns
496 .long xsc3_mc_user_fns
497 .long xsc3_cache_fns
498 .size __xsc3_proc_info, . - __xsc3_proc_info
diff --git a/include/asm-arm/arch-aaec2000/uncompress.h b/include/asm-arm/arch-aaec2000/uncompress.h
index fff0c94b75c4..300f4bf3bc74 100644
--- a/include/asm-arm/arch-aaec2000/uncompress.h
+++ b/include/asm-arm/arch-aaec2000/uncompress.h
@@ -15,7 +15,7 @@
15 15
16#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) 16#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
17 17
18static void putstr( const char *s ) 18static void putc(int c)
19{ 19{
20 unsigned long serial_port; 20 unsigned long serial_port;
21 do { 21 do {
@@ -28,17 +28,16 @@ static void putstr( const char *s )
28 return; 28 return;
29 } while (0); 29 } while (0);
30 30
31 for (; *s; s++) { 31 /* wait for space in the UART's transmitter */
32 /* wait for space in the UART's transmitter */ 32 while ((UART(UART_SR) & UART_SR_TxFF))
33 while ((UART(UART_SR) & UART_SR_TxFF)); 33 barrier();
34 /* send the character out. */ 34
35 UART(UART_DR) = *s; 35 /* send the character out. */
36 /* if a LF, also do CR... */ 36 UART(UART_DR) = c;
37 if (*s == 10) { 37}
38 while ((UART(UART_SR) & UART_SR_TxFF)); 38
39 UART(UART_DR) = 13; 39static inline void flush(void)
40 } 40{
41 }
42} 41}
43 42
44#define arch_decomp_setup() 43#define arch_decomp_setup()
diff --git a/include/asm-arm/arch-at91rm9200/uncompress.h b/include/asm-arm/arch-at91rm9200/uncompress.h
index b30dd5520713..7b38497c24b5 100644
--- a/include/asm-arm/arch-at91rm9200/uncompress.h
+++ b/include/asm-arm/arch-at91rm9200/uncompress.h
@@ -31,21 +31,22 @@
31 * 31 *
32 * This does not append a newline 32 * This does not append a newline
33 */ 33 */
34static void putstr(const char *s) 34static void putc(int c)
35{
36 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
37
38 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY))
39 barrier();
40 __raw_writel(c, sys + AT91_DBGU_THR);
41}
42
43static inline void flush(void)
35{ 44{
36 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */ 45 void __iomem *sys = (void __iomem *) AT91_BASE_SYS; /* physical address */
37 46
38 while (*s) {
39 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
40 __raw_writel(*s, sys + AT91_DBGU_THR);
41 if (*s == '\n') {
42 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY)) { barrier(); }
43 __raw_writel('\r', sys + AT91_DBGU_THR);
44 }
45 s++;
46 }
47 /* wait for transmission to complete */ 47 /* wait for transmission to complete */
48 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY)) { barrier(); } 48 while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY))
49 barrier();
49} 50}
50 51
51#define arch_decomp_setup() 52#define arch_decomp_setup()
diff --git a/include/asm-arm/arch-cl7500/uncompress.h b/include/asm-arm/arch-cl7500/uncompress.h
index 68601b3e3b95..c437e0c88c3f 100644
--- a/include/asm-arm/arch-cl7500/uncompress.h
+++ b/include/asm-arm/arch-cl7500/uncompress.h
@@ -3,27 +3,19 @@
3 * 3 *
4 * Copyright (C) 1999, 2000 Nexus Electronics Ltd. 4 * Copyright (C) 1999, 2000 Nexus Electronics Ltd.
5 */ 5 */
6
7#define BASE 0x03010000 6#define BASE 0x03010000
8#define SERBASE (BASE + (0x2f8 << 2)) 7#define SERBASE (BASE + (0x2f8 << 2))
9 8
10static __inline__ void putc(char c) 9static inline void putc(char c)
11{ 10{
12 while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20)); 11 while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20))
12 barrier();
13
13 *((volatile unsigned int *)(SERBASE)) = c; 14 *((volatile unsigned int *)(SERBASE)) = c;
14} 15}
15 16
16/* 17static inline void flush(void)
17 * This does not append a newline
18 */
19static void putstr(const char *s)
20{ 18{
21 while (*s) {
22 putc(*s);
23 if (*s == '\n')
24 putc('\r');
25 s++;
26 }
27} 19}
28 20
29static __inline__ void arch_decomp_setup(void) 21static __inline__ void arch_decomp_setup(void)
diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h
index 9fc4bcfa1681..07157b7e4b20 100644
--- a/include/asm-arm/arch-clps711x/uncompress.h
+++ b/include/asm-arm/arch-clps711x/uncompress.h
@@ -25,7 +25,6 @@
25#undef CLPS7111_BASE 25#undef CLPS7111_BASE
26#define CLPS7111_BASE CLPS7111_PHYS_BASE 26#define CLPS7111_BASE CLPS7111_PHYS_BASE
27 27
28#define barrier() __asm__ __volatile__("": : :"memory")
29#define __raw_readl(p) (*(unsigned long *)(p)) 28#define __raw_readl(p) (*(unsigned long *)(p))
30#define __raw_writel(v,p) (*(unsigned long *)(p) = (v)) 29#define __raw_writel(v,p) (*(unsigned long *)(p) = (v))
31 30
@@ -40,21 +39,15 @@
40/* 39/*
41 * This does not append a newline 40 * This does not append a newline
42 */ 41 */
43static void putstr(const char *s) 42static inline void putc(int c)
44{ 43{
45 char c; 44 while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
46 45 barrier();
47 while ((c = *s++) != '\0') { 46 clps_writel(c, UARTDRx);
48 while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) 47}
49 barrier();
50 clps_writel(c, UARTDRx);
51 48
52 if (c == '\n') { 49static inline void flush(void)
53 while (clps_readl(SYSFLGx) & SYSFLG_UTXFF) 50{
54 barrier();
55 clps_writel('\r', UARTDRx);
56 }
57 }
58 while (clps_readl(SYSFLGx) & SYSFLG_UBUSY) 51 while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
59 barrier(); 52 barrier();
60} 53}
diff --git a/include/asm-arm/arch-ebsa110/uncompress.h b/include/asm-arm/arch-ebsa110/uncompress.h
index eee95581a923..66b19c7fd908 100644
--- a/include/asm-arm/arch-ebsa110/uncompress.h
+++ b/include/asm-arm/arch-ebsa110/uncompress.h
@@ -8,33 +8,34 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11#include <linux/serial_reg.h>
12
13#define SERIAL_BASE ((unsigned char *)0xfe000be0)
14
11/* 15/*
12 * This does not append a newline 16 * This does not append a newline
13 */ 17 */
14static void putstr(const char *s) 18static inline void putc(int c)
19{
20 unsigned char v, *base = SERIAL_BASE;
21
22 do {
23 v = base[UART_LSR << 2];
24 barrier();
25 } while (!(v & UART_LSR_THRE));
26
27 base[UART_TX << 2] = c;
28}
29
30static inline void flush(void)
15{ 31{
16 unsigned long tmp1, tmp2; 32 unsigned char v, *base = SERIAL_BASE;
17 __asm__ __volatile__( 33
18 "ldrb %0, [%2], #1\n" 34 do {
19" teq %0, #0\n" 35 v = base[UART_LSR << 2];
20" beq 3f\n" 36 barrier();
21"1: strb %0, [%3]\n" 37 } while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) !=
22"2: ldrb %1, [%3, #0x14]\n" 38 (UART_LSR_TEMT|UART_LSR_THRE));
23" and %1, %1, #0x60\n"
24" teq %1, #0x60\n"
25" bne 2b\n"
26" teq %0, #'\n'\n"
27" moveq %0, #'\r'\n"
28" beq 1b\n"
29" ldrb %0, [%2], #1\n"
30" teq %0, #0\n"
31" bne 1b\n"
32"3: ldrb %1, [%3, #0x14]\n"
33" and %1, %1, #0x60\n"
34" teq %1, #0x60\n"
35" bne 3b"
36 : "=&r" (tmp1), "=&r" (tmp2)
37 : "r" (s), "r" (0xf0000be0) : "cc");
38} 39}
39 40
40/* 41/*
diff --git a/include/asm-arm/arch-ebsa285/uncompress.h b/include/asm-arm/arch-ebsa285/uncompress.h
index c2fd84e2d90e..86142c882b3a 100644
--- a/include/asm-arm/arch-ebsa285/uncompress.h
+++ b/include/asm-arm/arch-ebsa285/uncompress.h
@@ -15,10 +15,11 @@
15#define DC21285_BASE ((volatile unsigned int *)0x42000160) 15#define DC21285_BASE ((volatile unsigned int *)0x42000160)
16#define SER0_BASE ((volatile unsigned char *)0x7c0003f8) 16#define SER0_BASE ((volatile unsigned char *)0x7c0003f8)
17 17
18static __inline__ void putc(char c) 18static inline void putc(char c)
19{ 19{
20 if (machine_is_netwinder()) { 20 if (machine_is_netwinder()) {
21 while ((SER0_BASE[5] & 0x60) != 0x60); 21 while ((SER0_BASE[5] & 0x60) != 0x60)
22 barrier();
22 SER0_BASE[0] = c; 23 SER0_BASE[0] = c;
23 } else { 24 } else {
24 while (DC21285_BASE[6] & 8); 25 while (DC21285_BASE[6] & 8);
@@ -26,17 +27,8 @@ static __inline__ void putc(char c)
26 } 27 }
27} 28}
28 29
29/* 30static inline void flush(void)
30 * This does not append a newline
31 */
32static void putstr(const char *s)
33{ 31{
34 while (*s) {
35 putc(*s);
36 if (*s == '\n')
37 putc('\r');
38 s++;
39 }
40} 32}
41 33
42/* 34/*
diff --git a/include/asm-arm/arch-ep93xx/uncompress.h b/include/asm-arm/arch-ep93xx/uncompress.h
index 4410d217077e..c15274c85d5d 100644
--- a/include/asm-arm/arch-ep93xx/uncompress.h
+++ b/include/asm-arm/arch-ep93xx/uncompress.h
@@ -16,17 +16,27 @@ static unsigned char __raw_readb(unsigned int ptr)
16 return *((volatile unsigned char *)ptr); 16 return *((volatile unsigned char *)ptr);
17} 17}
18 18
19static unsigned int __raw_readl(unsigned int ptr)
20{
21 return *((volatile unsigned int *)ptr);
22}
23
19static void __raw_writeb(unsigned char value, unsigned int ptr) 24static void __raw_writeb(unsigned char value, unsigned int ptr)
20{ 25{
21 *((volatile unsigned char *)ptr) = value; 26 *((volatile unsigned char *)ptr) = value;
22} 27}
23 28
29static void __raw_writel(unsigned int value, unsigned int ptr)
30{
31 *((volatile unsigned int *)ptr) = value;
32}
33
24 34
25#define PHYS_UART1_DATA 0x808c0000 35#define PHYS_UART1_DATA 0x808c0000
26#define PHYS_UART1_FLAG 0x808c0018 36#define PHYS_UART1_FLAG 0x808c0018
27#define UART1_FLAG_TXFF 0x20 37#define UART1_FLAG_TXFF 0x20
28 38
29static __inline__ void putc(char c) 39static inline void putc(int c)
30{ 40{
31 int i; 41 int i;
32 42
@@ -39,15 +49,37 @@ static __inline__ void putc(char c)
39 __raw_writeb(c, PHYS_UART1_DATA); 49 __raw_writeb(c, PHYS_UART1_DATA);
40} 50}
41 51
42static void putstr(const char *s) 52static inline void flush(void)
43{ 53{
44 while (*s) {
45 putc(*s);
46 if (*s == '\n')
47 putc('\r');
48 s++;
49 }
50} 54}
51 55
52#define arch_decomp_setup() 56
57/*
58 * Some bootloaders don't turn off DMA from the ethernet MAC before
59 * jumping to linux, which means that we might end up with bits of RX
60 * status and packet data scribbled over the uncompressed kernel image.
61 * Work around this by resetting the ethernet MAC before we uncompress.
62 */
63#define PHYS_ETH_SELF_CTL 0x80010020
64#define ETH_SELF_CTL_RESET 0x00000001
65
66static void ethernet_reset(void)
67{
68 unsigned int v;
69
70 /* Reset the ethernet MAC. */
71 v = __raw_readl(PHYS_ETH_SELF_CTL);
72 __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL);
73
74 /* Wait for reset to finish. */
75 while (__raw_readl(PHYS_ETH_SELF_CTL) & ETH_SELF_CTL_RESET)
76 ;
77}
78
79
80static void arch_decomp_setup(void)
81{
82 ethernet_reset();
83}
84
53#define arch_decomp_wdog() 85#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-h720x/uncompress.h b/include/asm-arm/arch-h720x/uncompress.h
index 9535764bcc71..18c69e0f3585 100644
--- a/include/asm-arm/arch-h720x/uncompress.h
+++ b/include/asm-arm/arch-h720x/uncompress.h
@@ -12,22 +12,20 @@
12#define LSR 0x14 12#define LSR 0x14
13#define TEMPTY 0x40 13#define TEMPTY 0x40
14 14
15static void putstr(const char *s) 15static inline void putc(int c)
16{ 16{
17 char c;
18 volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000); 17 volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
19 18
20 while ( (c = *s++) != '\0') { 19 /* wait until transmit buffer is empty */
21 /* wait until transmit buffer is empty */ 20 while((p[LSR] & TEMPTY) == 0x0)
22 while((p[LSR] & TEMPTY) == 0x0); 21 barrier();
23 /* write next character */ 22
24 *p = c; 23 /* write next character */
25 24 *p = c;
26 if(c == '\n') { 25}
27 while((p[LSR] & TEMPTY) == 0x0); 26
28 *p = '\r'; 27static inline void flush(void)
29 } 28{
30 }
31} 29}
32 30
33/* 31/*
diff --git a/include/asm-arm/arch-imx/uncompress.h b/include/asm-arm/arch-imx/uncompress.h
index 096077f2750b..da333f69136f 100644
--- a/include/asm-arm/arch-imx/uncompress.h
+++ b/include/asm-arm/arch-imx/uncompress.h
@@ -39,8 +39,7 @@
39 * 39 *
40 * This does not append a newline 40 * This does not append a newline
41 */ 41 */
42static void 42static void putc(int c)
43putstr(const char *s)
44{ 43{
45 unsigned long serial_port; 44 unsigned long serial_port;
46 45
@@ -54,20 +53,14 @@ putstr(const char *s)
54 return; 53 return;
55 } while(0); 54 } while(0);
56 55
57 while (*s) { 56 while (!(UART(USR2) & USR2_TXFE))
58 while ( !(UART(USR2) & USR2_TXFE) ) 57 barrier();
59 barrier();
60 58
61 UART(TXR) = *s; 59 UART(TXR) = c;
62 60}
63 if (*s == '\n') {
64 while ( !(UART(USR2) & USR2_TXFE) )
65 barrier();
66 61
67 UART(TXR) = '\r'; 62static inline void flush(void)
68 } 63{
69 s++;
70 }
71} 64}
72 65
73/* 66/*
diff --git a/include/asm-arm/arch-integrator/uncompress.h b/include/asm-arm/arch-integrator/uncompress.h
index 3957402741d3..f61825c4d901 100644
--- a/include/asm-arm/arch-integrator/uncompress.h
+++ b/include/asm-arm/arch-integrator/uncompress.h
@@ -28,21 +28,18 @@
28/* 28/*
29 * This does not append a newline 29 * This does not append a newline
30 */ 30 */
31static void putstr(const char *s) 31static void putc(int c)
32{ 32{
33 while (*s) { 33 while (AMBA_UART_FR & (1 << 5))
34 while (AMBA_UART_FR & (1 << 5)); 34 barrier();
35 35
36 AMBA_UART_DR = *s; 36 AMBA_UART_DR = c;
37 37}
38 if (*s == '\n') {
39 while (AMBA_UART_FR & (1 << 5));
40 38
41 AMBA_UART_DR = '\r'; 39static inline void flush(void)
42 } 40{
43 s++; 41 while (AMBA_UART_FR & (1 << 3))
44 } 42 barrier();
45 while (AMBA_UART_FR & (1 << 3));
46} 43}
47 44
48/* 45/*
diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h
index 82b88762c3cc..c98eb6254b1f 100644
--- a/include/asm-arm/arch-iop3xx/uncompress.h
+++ b/include/asm-arm/arch-iop3xx/uncompress.h
@@ -19,23 +19,15 @@ static volatile UTYPE uart_base;
19 19
20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) 20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
21 21
22static __inline__ void putc(char c) 22static inline void putc(char c)
23{ 23{
24 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE); 24 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
25 barrier();
25 *uart_base = c; 26 *uart_base = c;
26} 27}
27 28
28/* 29static inline void flush(void)
29 * This does not append a newline
30 */
31static void putstr(const char *s)
32{ 30{
33 while (*s) {
34 putc(*s);
35 if (*s == '\n')
36 putc('\r');
37 s++;
38 }
39} 31}
40 32
41static __inline__ void __arch_decomp_setup(unsigned long arch_id) 33static __inline__ void __arch_decomp_setup(unsigned long arch_id)
diff --git a/include/asm-arm/arch-ixp2000/uncompress.h b/include/asm-arm/arch-ixp2000/uncompress.h
index 3d3d5b2ed6e9..f66b408f363e 100644
--- a/include/asm-arm/arch-ixp2000/uncompress.h
+++ b/include/asm-arm/arch-ixp2000/uncompress.h
@@ -29,23 +29,18 @@
29#define UARTSR PHYS(0x14) /* Status reg */ 29#define UARTSR PHYS(0x14) /* Status reg */
30 30
31 31
32static __inline__ void putc(char c) 32static inline void putc(int c)
33{ 33{
34 int j = 0x1000; 34 int j = 0x1000;
35 35
36 while (--j && !(*UARTSR & UART_LSR_THRE)); 36 while (--j && !(*UARTSR & UART_LSR_THRE))
37 barrier();
38
37 *UARTDR = c; 39 *UARTDR = c;
38} 40}
39 41
40static void putstr(const char *s) 42static inline void flush(void)
41{ 43{
42 while (*s)
43 {
44 putc(*s);
45 if (*s == '\n')
46 putc('\r');
47 s++;
48 }
49} 44}
50 45
51#define arch_decomp_setup() 46#define arch_decomp_setup()
diff --git a/include/asm-arm/arch-ixp23xx/debug-macro.S b/include/asm-arm/arch-ixp23xx/debug-macro.S
new file mode 100644
index 000000000000..eb99fd69fd24
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/debug-macro.S
@@ -0,0 +1,23 @@
1/*
2 * include/asm-arm/arch-ixp23xx/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <asm/arch/ixp23xx.h>
14
15 .macro addruart,rx
16 mrc p15, 0, \rx, c1, c0
17 tst \rx, #1 @ mmu enabled?
18 ldreq \rx, =IXP23XX_PERIPHERAL_PHYS @ physical
19 ldrne \rx, =IXP23XX_PERIPHERAL_VIRT @ virtual
20 .endm
21
22#define UART_SHIFT 2
23#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ixp23xx/dma.h b/include/asm-arm/arch-ixp23xx/dma.h
new file mode 100644
index 000000000000..2f4335e3b836
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/dma.h
@@ -0,0 +1,3 @@
1/*
2 * include/asm-arm/arch-ixp23xx/dma.h
3 */
diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S
new file mode 100644
index 000000000000..0ef4e6016ac4
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/entry-macro.S
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-ixp23xx/entry-macro.S
3 */
4
5 .macro disable_fiq
6 .endm
7
8 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
9 ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
10 ldr \irqnr, [\irqnr] @ get interrupt number
11 cmp \irqnr, #0x0 @ suprious interrupt ?
12 movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits
13 subne \irqnr, \irqnr, #1 @ convert to 0 based
14
15#if 0
16 cmp \irqnr, #IRQ_IXP23XX_PCI_INT_RPH
17 bne 1001f
18 mov \irqnr, #IRQ_IXP23XX_INTA
19
20 ldr \irqnr, =0xf5000030
21
22 mov \tmp, #(1<<26)
23 tst \irqnr, \tmp
24 movne \irqnr, #IRQ_IXP23XX_INTB
25
26 mov \tmp, #(1<<27)
27 tst \irqnr, \tmp
28 movne \irqnr, #IRQ_IXP23XX_INTA
291001:
30#endif
31 .endm
diff --git a/include/asm-arm/arch-ixp23xx/hardware.h b/include/asm-arm/arch-ixp23xx/hardware.h
new file mode 100644
index 000000000000..c0010d21a684
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/hardware.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-ixp23xx/hardware.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 * Copyricht (C) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Hardware definitions for IXP23XX based systems
12 */
13
14#ifndef __ASM_ARCH_HARDWARE_H
15#define __ASM_ARCH_HARDWARE_H
16
17/* PCI IO info */
18#define PCIO_BASE IXP23XX_PCI_IO_VIRT
19#define PCIBIOS_MIN_IO 0x00000000
20#define PCIBIOS_MIN_MEM 0xe0000000
21
22#include "ixp23xx.h"
23
24#define pcibios_assign_all_busses() 0
25
26/*
27 * Platform helper functions
28 */
29#include "platform.h"
30
31/*
32 * Platform-specific headers
33 */
34#include "ixdp2351.h"
35
36
37#endif
diff --git a/include/asm-arm/arch-ixp23xx/io.h b/include/asm-arm/arch-ixp23xx/io.h
new file mode 100644
index 000000000000..18415a81ac74
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/io.h
@@ -0,0 +1,54 @@
1/*
2 * include/asm-arm/arch-ixp23xx/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2003-2005 Intel Corp.
8 * Copyright (C) 2005 MontaVista Software, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IO_H
16#define __ASM_ARCH_IO_H
17
18#define IO_SPACE_LIMIT 0xffffffff
19
20#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
21#define __mem_pci(a) (a)
22
23#include <linux/kernel.h> /* For BUG */
24
25static inline void __iomem *
26ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned long flags)
27{
28 if (addr >= IXP23XX_PCI_MEM_START &&
29 addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
30 if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
31 return NULL;
32
33 return (void __iomem *)
34 ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
35 }
36
37 return __ioremap(addr, size, flags);
38}
39
40static inline void
41ixp23xx_iounmap(void __iomem *addr)
42{
43 if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
44 (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
45 return;
46
47 __iounmap(addr);
48}
49
50#define __arch_ioremap(a,s,f) ixp23xx_ioremap(a,s,f)
51#define __arch_iounmap(a) ixp23xx_iounmap(a)
52
53
54#endif
diff --git a/include/asm-arm/arch-ixp23xx/irqs.h b/include/asm-arm/arch-ixp23xx/irqs.h
new file mode 100644
index 000000000000..e69639585721
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/irqs.h
@@ -0,0 +1,223 @@
1/*
2 * include/asm-arm/arch-ixp23xx/irqs.h
3 *
4 * IRQ definitions for IXP23XX based systems
5 *
6 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 *
8 * Copyright (C) 2003-2004 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IRQS_H
16#define __ASM_ARCH_IRQS_H
17
18#define NR_IXP23XX_IRQS IRQ_IXP23XX_INTB+1
19#define IRQ_IXP23XX_EXTIRQS NR_IXP23XX_IRQS
20
21
22#define IRQ_IXP23XX_DBG0 0 /* Debug/Execution/MBox */
23#define IRQ_IXP23XX_DBG1 1 /* Debug/Execution/MBox */
24#define IRQ_IXP23XX_NPE_TRG 2 /* npe_trigger */
25#define IRQ_IXP23XX_TIMER1 3 /* Timer[0] */
26#define IRQ_IXP23XX_TIMER2 4 /* Timer[1] */
27#define IRQ_IXP23XX_TIMESTAMP 5 /* Timer[2], Time-stamp */
28#define IRQ_IXP23XX_WDOG 6 /* Time[3], Watchdog Timer */
29#define IRQ_IXP23XX_PCI_DBELL 7 /* PCI Doorbell */
30#define IRQ_IXP23XX_PCI_DMA1 8 /* PCI DMA Channel 1 */
31#define IRQ_IXP23XX_PCI_DMA2 9 /* PCI DMA Channel 2 */
32#define IRQ_IXP23XX_PCI_DMA3 10 /* PCI DMA Channel 3 */
33#define IRQ_IXP23XX_PCI_INT_RPH 11 /* pcxg_pci_int_rph */
34#define IRQ_IXP23XX_CPP_PMU 12 /* xpxg_pm_int_rpl */
35#define IRQ_IXP23XX_SWINT0 13 /* S/W Interrupt0 */
36#define IRQ_IXP23XX_SWINT1 14 /* S/W Interrupt1 */
37#define IRQ_IXP23XX_UART2 15 /* UART1 Interrupt */
38#define IRQ_IXP23XX_UART1 16 /* UART0 Interrupt */
39#define IRQ_IXP23XX_XSI_PMU_ROLLOVER 17 /* AHB Performance M. Unit counter rollover */
40#define IRQ_IXP23XX_XSI_AHB_PM0 18 /* intr_pm_o */
41#define IRQ_IXP23XX_XSI_AHB_ECE0 19 /* intr_ece_o */
42#define IRQ_IXP23XX_XSI_AHB_GASKET 20 /* gas_intr_o */
43#define IRQ_IXP23XX_XSI_CPP 21 /* xsi2cpp_int */
44#define IRQ_IXP23XX_CPP_XSI 22 /* cpp2xsi_int */
45#define IRQ_IXP23XX_ME_ATTN0 23 /* ME_ATTN */
46#define IRQ_IXP23XX_ME_ATTN1 24 /* ME_ATTN */
47#define IRQ_IXP23XX_ME_ATTN2 25 /* ME_ATTN */
48#define IRQ_IXP23XX_ME_ATTN3 26 /* ME_ATTN */
49#define IRQ_IXP23XX_PCI_ERR_RPH 27 /* PCXG_PCI_ERR_RPH */
50#define IRQ_IXP23XX_D0XG_ECC_CORR 28 /* D0XG_DRAM_ECC_CORR */
51#define IRQ_IXP23XX_D0XG_ECC_UNCORR 29 /* D0XG_DRAM_ECC_UNCORR */
52#define IRQ_IXP23XX_SRAM_ERR1 30 /* SRAM1_ERR */
53#define IRQ_IXP23XX_SRAM_ERR0 31 /* SRAM0_ERR */
54#define IRQ_IXP23XX_MEDIA_ERR 32 /* MEDIA_ERR */
55#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ 33 /* STH_DRAM0_ECC_MAJ */
56#define IRQ_IXP23XX_GPIO6 34 /* GPIO0 interrupts */
57#define IRQ_IXP23XX_GPIO7 35 /* GPIO1 interrupts */
58#define IRQ_IXP23XX_GPIO8 36 /* GPIO2 interrupts */
59#define IRQ_IXP23XX_GPIO9 37 /* GPIO3 interrupts */
60#define IRQ_IXP23XX_GPIO10 38 /* GPIO4 interrupts */
61#define IRQ_IXP23XX_GPIO11 39 /* GPIO5 interrupts */
62#define IRQ_IXP23XX_GPIO12 40 /* GPIO6 interrupts */
63#define IRQ_IXP23XX_GPIO13 41 /* GPIO7 interrupts */
64#define IRQ_IXP23XX_GPIO14 42 /* GPIO8 interrupts */
65#define IRQ_IXP23XX_GPIO15 43 /* GPIO9 interrupts */
66#define IRQ_IXP23XX_SHAC_RING0 44 /* SHAC Ring Full */
67#define IRQ_IXP23XX_SHAC_RING1 45 /* SHAC Ring Full */
68#define IRQ_IXP23XX_SHAC_RING2 46 /* SHAC Ring Full */
69#define IRQ_IXP23XX_SHAC_RING3 47 /* SHAC Ring Full */
70#define IRQ_IXP23XX_SHAC_RING4 48 /* SHAC Ring Full */
71#define IRQ_IXP23XX_SHAC_RING5 49 /* SHAC Ring Full */
72#define IRQ_IXP23XX_SHAC_RING6 50 /* SHAC RING Full */
73#define IRQ_IXP23XX_SHAC_RING7 51 /* SHAC Ring Full */
74#define IRQ_IXP23XX_SHAC_RING8 52 /* SHAC Ring Full */
75#define IRQ_IXP23XX_SHAC_RING9 53 /* SHAC Ring Full */
76#define IRQ_IXP23XX_SHAC_RING10 54 /* SHAC Ring Full */
77#define IRQ_IXP23XX_SHAC_RING11 55 /* SHAC Ring Full */
78#define IRQ_IXP23XX_ME_THREAD_A0_ME0 56 /* ME_THREAD_A */
79#define IRQ_IXP23XX_ME_THREAD_A1_ME0 57 /* ME_THREAD_A */
80#define IRQ_IXP23XX_ME_THREAD_A2_ME0 58 /* ME_THREAD_A */
81#define IRQ_IXP23XX_ME_THREAD_A3_ME0 59 /* ME_THREAD_A */
82#define IRQ_IXP23XX_ME_THREAD_A4_ME0 60 /* ME_THREAD_A */
83#define IRQ_IXP23XX_ME_THREAD_A5_ME0 61 /* ME_THREAD_A */
84#define IRQ_IXP23XX_ME_THREAD_A6_ME0 62 /* ME_THREAD_A */
85#define IRQ_IXP23XX_ME_THREAD_A7_ME0 63 /* ME_THREAD_A */
86#define IRQ_IXP23XX_ME_THREAD_A8_ME1 64 /* ME_THREAD_A */
87#define IRQ_IXP23XX_ME_THREAD_A9_ME1 65 /* ME_THREAD_A */
88#define IRQ_IXP23XX_ME_THREAD_A10_ME1 66 /* ME_THREAD_A */
89#define IRQ_IXP23XX_ME_THREAD_A11_ME1 67 /* ME_THREAD_A */
90#define IRQ_IXP23XX_ME_THREAD_A12_ME1 68 /* ME_THREAD_A */
91#define IRQ_IXP23XX_ME_THREAD_A13_ME1 69 /* ME_THREAD_A */
92#define IRQ_IXP23XX_ME_THREAD_A14_ME1 70 /* ME_THREAD_A */
93#define IRQ_IXP23XX_ME_THREAD_A15_ME1 71 /* ME_THREAD_A */
94#define IRQ_IXP23XX_ME_THREAD_A16_ME2 72 /* ME_THREAD_A */
95#define IRQ_IXP23XX_ME_THREAD_A17_ME2 73 /* ME_THREAD_A */
96#define IRQ_IXP23XX_ME_THREAD_A18_ME2 74 /* ME_THREAD_A */
97#define IRQ_IXP23XX_ME_THREAD_A19_ME2 75 /* ME_THREAD_A */
98#define IRQ_IXP23XX_ME_THREAD_A20_ME2 76 /* ME_THREAD_A */
99#define IRQ_IXP23XX_ME_THREAD_A21_ME2 77 /* ME_THREAD_A */
100#define IRQ_IXP23XX_ME_THREAD_A22_ME2 78 /* ME_THREAD_A */
101#define IRQ_IXP23XX_ME_THREAD_A23_ME2 79 /* ME_THREAD_A */
102#define IRQ_IXP23XX_ME_THREAD_A24_ME3 80 /* ME_THREAD_A */
103#define IRQ_IXP23XX_ME_THREAD_A25_ME3 81 /* ME_THREAD_A */
104#define IRQ_IXP23XX_ME_THREAD_A26_ME3 82 /* ME_THREAD_A */
105#define IRQ_IXP23XX_ME_THREAD_A27_ME3 83 /* ME_THREAD_A */
106#define IRQ_IXP23XX_ME_THREAD_A28_ME3 84 /* ME_THREAD_A */
107#define IRQ_IXP23XX_ME_THREAD_A29_ME3 85 /* ME_THREAD_A */
108#define IRQ_IXP23XX_ME_THREAD_A30_ME3 86 /* ME_THREAD_A */
109#define IRQ_IXP23XX_ME_THREAD_A31_ME3 87 /* ME_THREAD_A */
110#define IRQ_IXP23XX_ME_THREAD_B0_ME0 88 /* ME_THREAD_B */
111#define IRQ_IXP23XX_ME_THREAD_B1_ME0 89 /* ME_THREAD_B */
112#define IRQ_IXP23XX_ME_THREAD_B2_ME0 90 /* ME_THREAD_B */
113#define IRQ_IXP23XX_ME_THREAD_B3_ME0 91 /* ME_THREAD_B */
114#define IRQ_IXP23XX_ME_THREAD_B4_ME0 92 /* ME_THREAD_B */
115#define IRQ_IXP23XX_ME_THREAD_B5_ME0 93 /* ME_THREAD_B */
116#define IRQ_IXP23XX_ME_THREAD_B6_ME0 94 /* ME_THREAD_B */
117#define IRQ_IXP23XX_ME_THREAD_B7_ME0 95 /* ME_THREAD_B */
118#define IRQ_IXP23XX_ME_THREAD_B8_ME1 96 /* ME_THREAD_B */
119#define IRQ_IXP23XX_ME_THREAD_B9_ME1 97 /* ME_THREAD_B */
120#define IRQ_IXP23XX_ME_THREAD_B10_ME1 98 /* ME_THREAD_B */
121#define IRQ_IXP23XX_ME_THREAD_B11_ME1 99 /* ME_THREAD_B */
122#define IRQ_IXP23XX_ME_THREAD_B12_ME1 100 /* ME_THREAD_B */
123#define IRQ_IXP23XX_ME_THREAD_B13_ME1 101 /* ME_THREAD_B */
124#define IRQ_IXP23XX_ME_THREAD_B14_ME1 102 /* ME_THREAD_B */
125#define IRQ_IXP23XX_ME_THREAD_B15_ME1 103 /* ME_THREAD_B */
126#define IRQ_IXP23XX_ME_THREAD_B16_ME2 104 /* ME_THREAD_B */
127#define IRQ_IXP23XX_ME_THREAD_B17_ME2 105 /* ME_THREAD_B */
128#define IRQ_IXP23XX_ME_THREAD_B18_ME2 106 /* ME_THREAD_B */
129#define IRQ_IXP23XX_ME_THREAD_B19_ME2 107 /* ME_THREAD_B */
130#define IRQ_IXP23XX_ME_THREAD_B20_ME2 108 /* ME_THREAD_B */
131#define IRQ_IXP23XX_ME_THREAD_B21_ME2 109 /* ME_THREAD_B */
132#define IRQ_IXP23XX_ME_THREAD_B22_ME2 110 /* ME_THREAD_B */
133#define IRQ_IXP23XX_ME_THREAD_B23_ME2 111 /* ME_THREAD_B */
134#define IRQ_IXP23XX_ME_THREAD_B24_ME3 112 /* ME_THREAD_B */
135#define IRQ_IXP23XX_ME_THREAD_B25_ME3 113 /* ME_THREAD_B */
136#define IRQ_IXP23XX_ME_THREAD_B26_ME3 114 /* ME_THREAD_B */
137#define IRQ_IXP23XX_ME_THREAD_B27_ME3 115 /* ME_THREAD_B */
138#define IRQ_IXP23XX_ME_THREAD_B28_ME3 116 /* ME_THREAD_B */
139#define IRQ_IXP23XX_ME_THREAD_B29_ME3 117 /* ME_THREAD_B */
140#define IRQ_IXP23XX_ME_THREAD_B30_ME3 118 /* ME_THREAD_B */
141#define IRQ_IXP23XX_ME_THREAD_B31_ME3 119 /* ME_THREAD_B */
142
143#define NUM_IXP23XX_RAW_IRQS 120
144
145#define IRQ_IXP23XX_INTA 120 /* Indirect pcxg_pci_int_rph */
146#define IRQ_IXP23XX_INTB 121 /* Indirect pcxg_pci_int_rph */
147
148#define NR_IXP23XX_IRQ (IRQ_IXP23XX_INTB + 1)
149
150/*
151 * We default to 32 per-board IRQs. Increase this number if you need
152 * more, but keep it realistic.
153 */
154#define NR_IXP23XX_MACH_IRQS 32
155
156#define NR_IRQS NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS
157
158#define IXP23XX_MACH_IRQ(irq) (NR_IXP23XX_IRQ + (irq))
159
160
161/*
162 * IXDP2351-specific interrupts
163 */
164
165/*
166 * External PCI interrupts signaled through INTB
167 *
168 */
169#define IXDP2351_INTB_IRQ_BASE 0
170#define IRQ_IXDP2351_INTA_82546 IXP23XX_MACH_IRQ(0)
171#define IRQ_IXDP2351_INTB_82546 IXP23XX_MACH_IRQ(1)
172#define IRQ_IXDP2351_SPCI_DB_0 IXP23XX_MACH_IRQ(2)
173#define IRQ_IXDP2351_SPCI_DB_1 IXP23XX_MACH_IRQ(3)
174#define IRQ_IXDP2351_SPCI_PMC_INTA IXP23XX_MACH_IRQ(4)
175#define IRQ_IXDP2351_SPCI_PMC_INTB IXP23XX_MACH_IRQ(5)
176#define IRQ_IXDP2351_SPCI_PMC_INTC IXP23XX_MACH_IRQ(6)
177#define IRQ_IXDP2351_SPCI_PMC_INTD IXP23XX_MACH_IRQ(7)
178#define IRQ_IXDP2351_SPCI_FIC IXP23XX_MACH_IRQ(8)
179
180#define IXDP2351_INTB_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(0))
181#define IXDP2351_INTB_IRQ_MASK(irq) (1 << IXDP2351_INTB_IRQ_BIT(irq))
182#define IXDP2351_INTB_IRQ_VALID 0x01FF
183#define IXDP2351_INTB_IRQ_NUM 16
184
185/*
186 * Other external interrupts signaled through INTA
187 */
188#define IXDP2351_INTA_IRQ_BASE 16
189#define IRQ_IXDP2351_IPMI_FROM IXP23XX_MACH_IRQ(16)
190#define IRQ_IXDP2351_125US IXP23XX_MACH_IRQ(17)
191#define IRQ_IXDP2351_DB_0_ADD IXP23XX_MACH_IRQ(18)
192#define IRQ_IXDP2351_DB_1_ADD IXP23XX_MACH_IRQ(19)
193#define IRQ_IXDP2351_DEBUG1 IXP23XX_MACH_IRQ(20)
194#define IRQ_IXDP2351_ADD_UART IXP23XX_MACH_IRQ(21)
195#define IRQ_IXDP2351_FIC_ADD IXP23XX_MACH_IRQ(24)
196#define IRQ_IXDP2351_CS8900 IXP23XX_MACH_IRQ(25)
197#define IRQ_IXDP2351_BBSRAM IXP23XX_MACH_IRQ(26)
198#define IRQ_IXDP2351_CONFIG_MEDIA IXP23XX_MACH_IRQ(27)
199#define IRQ_IXDP2351_CLOCK_REF IXP23XX_MACH_IRQ(28)
200#define IRQ_IXDP2351_A10_NP IXP23XX_MACH_IRQ(29)
201#define IRQ_IXDP2351_A11_NP IXP23XX_MACH_IRQ(30)
202#define IRQ_IXDP2351_DEBUG_NP IXP23XX_MACH_IRQ(31)
203
204#define IXDP2351_INTA_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(16))
205#define IXDP2351_INTA_IRQ_MASK(irq) (1 << IXDP2351_INTA_IRQ_BIT(irq))
206#define IXDP2351_INTA_IRQ_VALID 0xFF3F
207#define IXDP2351_INTA_IRQ_NUM 16
208
209
210/*
211 * ADI RoadRunner IRQs
212 */
213#define IRQ_ROADRUNNER_PCI_INTA IRQ_IXP23XX_INTA
214#define IRQ_ROADRUNNER_PCI_INTB IRQ_IXP23XX_INTB
215#define IRQ_ROADRUNNER_PCI_INTC IRQ_IXP23XX_GPIO11
216#define IRQ_ROADRUNNER_PCI_INTD IRQ_IXP23XX_GPIO12
217
218/*
219 * Put new board definitions here
220 */
221
222
223#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixdp2351.h b/include/asm-arm/arch-ixp23xx/ixdp2351.h
new file mode 100644
index 000000000000..4a24f8f15655
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/ixdp2351.h
@@ -0,0 +1,89 @@
1/*
2 * include/asm-arm/arch-ixp23xx/ixdp2351.h
3 *
4 * Register and other defines for IXDP2351
5 *
6 * Copyright (c) 2002-2004 Intel Corp.
7 * Copytight (c) 2005 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#ifndef __ASM_ARCH_IXDP2351_H
16#define __ASM_ARCH_IXDP2351_H
17
18/*
19 * NP module memory map
20 */
21#define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE)
22#define IXDP2351_NP_PHYS_SIZE 0x00100000
23#define IXDP2351_NP_VIRT_BASE 0xeff00000
24
25#define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE)
26#define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16)
27
28#define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)
29
30#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))
31
32#define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00)
33#define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02)
34#define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04)
35
36/*
37 * Base board module memory map
38 */
39
40#define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE)
41#define IXDP2351_BB_SIZE 0x01000000
42#define IXDP2351_BB_BASE_VIRT (0xee000000)
43
44#define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset)
45
46#define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0)
47#define IXDP2351_NVRAM_SIZE (0x20000)
48
49#define IXDP2351_VIRT_MB_IXF1104_BASE IXDP3251_BB_AREA_BASE(0x00020000)
50#define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0)
51#define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000)
52#define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000)
53#define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000)
54#define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000)
55
56/*
57 * On board CPLD registers
58 */
59#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))
60
61#define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00)
62#define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04)
63
64#define IXDP2351_CPLD_RESET1_MAGIC 0x55AA
65#define IXDP2351_CPLD_RESET1_ENABLE 0x8000
66
67#define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08)
68#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10)
69#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14)
70#define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18)
71#define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C)
72#define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */
73#define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */
74#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */
75#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */
76#define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28)
77#define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C)
78 /* Interrupt bits are defined in irqs.h */
79#define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30)
80#define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34)
81
82/* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */
83/* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */
84/* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */
85/* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */
86/* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */
87
88
89#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixp23xx.h b/include/asm-arm/arch-ixp23xx/ixp23xx.h
new file mode 100644
index 000000000000..e49e1ca61b1a
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/ixp23xx.h
@@ -0,0 +1,306 @@
1/*
2 * include/asm-arm/arch-ixp23xx/ixp23xx.h
3 *
4 * Register definitions for IXP23XX
5 *
6 * Copyright (C) 2003-2005 Intel Corporation.
7 * Copyright (C) 2005 MontaVista Software, Inc.
8 *
9 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_IXP23XX_H
17#define __ASM_ARCH_IXP23XX_H
18
19/*
20 * IXP2300 linux memory map:
21 *
22 * virt phys size
23 * fffd0000 a0000000 64K XSI2CPP_CSR
24 * fffc0000 c4000000 4K EXP_CFG
25 * fff00000 c8000000 64K PERIPHERAL
26 * fe000000 1c0000000 16M CAP_CSR
27 * fd000000 1c8000000 16M MSF_CSR
28 * fb000000 16M ---
29 * fa000000 1d8000000 32M PCI_IO
30 * f8000000 1da000000 32M PCI_CFG
31 * f6000000 1de000000 32M PCI_CREG
32 * f4000000 32M ---
33 * f0000000 1e0000000 64M PCI_MEM
34 * e[c-f]000000 per-platform mappings
35 */
36
37
38/****************************************************************************
39 * Static mappings.
40 ****************************************************************************/
41#define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000
42#define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000
43#define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000
44
45#define IXP23XX_EXP_CFG_PHYS 0xc4000000
46#define IXP23XX_EXP_CFG_VIRT 0xfffc0000
47#define IXP23XX_EXP_CFG_SIZE 0x00001000
48
49#define IXP23XX_PERIPHERAL_PHYS 0xc8000000
50#define IXP23XX_PERIPHERAL_VIRT 0xfff00000
51#define IXP23XX_PERIPHERAL_SIZE 0x00010000
52
53#define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL
54#define IXP23XX_CAP_CSR_VIRT 0xfe000000
55#define IXP23XX_CAP_CSR_SIZE 0x01000000
56
57#define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL
58#define IXP23XX_MSF_CSR_VIRT 0xfd000000
59#define IXP23XX_MSF_CSR_SIZE 0x01000000
60
61#define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL
62#define IXP23XX_PCI_IO_VIRT 0xfa000000
63#define IXP23XX_PCI_IO_SIZE 0x02000000
64
65#define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL
66#define IXP23XX_PCI_CFG_VIRT 0xf8000000
67#define IXP23XX_PCI_CFG_SIZE 0x02000000
68#define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT
69#define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000)
70
71#define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL
72#define IXP23XX_PCI_CREG_VIRT 0xf6000000
73#define IXP23XX_PCI_CREG_SIZE 0x02000000
74#define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000)
75
76#define IXP23XX_PCI_MEM_START 0xe0000000
77#define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL
78#define IXP23XX_PCI_MEM_VIRT 0xf0000000
79#define IXP23XX_PCI_MEM_SIZE 0x04000000
80
81
82/****************************************************************************
83 * XSI2CPP CSRs.
84 ****************************************************************************/
85#define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x)))
86#define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8)
87#define IXP23XX_CPP2XSI_ADDR_31 (1 << 19)
88#define IXP23XX_CPP2XSI_PSH_OFF (1 << 20)
89#define IXP23XX_CPP2XSI_COH_OFF (1 << 21)
90
91
92/****************************************************************************
93 * Expansion Bus Config.
94 ****************************************************************************/
95#define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x)))
96#define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00)
97#define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04)
98#define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08)
99#define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c)
100#define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10)
101#define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14)
102#define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18)
103#define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c)
104#define IXP23XX_FLASH_WRITABLE (0x2)
105#define IXP23XX_FLASH_BUS8 (0x1)
106
107#define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20)
108#define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24)
109#define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31)
110#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22)
111#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21)
112#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19)
113#define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18)
114#define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16)
115#define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14)
116#define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13)
117#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12)
118#define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5)
119#define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4)
120#define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3)
121#define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2)
122#define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1)
123#define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0)
124
125#define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28)
126#define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30)
127
128#define IXP23XX_EXP_BUS_PHYS 0x90000000
129#define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000
130
131#define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000)
132#define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000)
133#define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000)
134#define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000)
135#define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000)
136#define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000)
137#define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000)
138#define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000)
139
140
141/****************************************************************************
142 * Peripherals.
143 ****************************************************************************/
144#define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000)
145#define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000)
146#define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000)
147#define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000)
148#define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000)
149#define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000)
150#define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000)
151#define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000)
152#define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000)
153#define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000)
154#define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000)
155#define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000)
156#define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000)
157#define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000)
158
159#define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000)
160#define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000)
161#define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000)
162#define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000)
163#define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000)
164#define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000)
165#define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000)
166#define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000)
167#define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000)
168#define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000)
169#define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000)
170#define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000)
171#define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000)
172#define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000)
173
174
175/****************************************************************************
176 * Interrupt controller.
177 ****************************************************************************/
178#define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x)))
179#define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00)
180#define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04)
181#define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08)
182#define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c)
183#define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10)
184#define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14)
185#define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18)
186#define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c)
187#define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20)
188#define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24)
189#define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28)
190#define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c)
191#define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30)
192#define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34)
193#define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38)
194#define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c)
195#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54
196
197
198/****************************************************************************
199 * GPIO.
200 ****************************************************************************/
201#define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x)))
202#define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00)
203#define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04)
204#define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08)
205#define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c)
206#define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10)
207#define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14)
208#define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18)
209#define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c)
210
211#define IXP23XX_GPIO_STYLE_MASK 0x7
212#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0
213#define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1
214#define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2
215#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3
216#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4
217
218#define IXP23XX_GPIO_STYLE_SIZE 3
219
220
221/****************************************************************************
222 * Timer.
223 ****************************************************************************/
224#define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x)))
225#define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00)
226#define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04)
227#define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08)
228#define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c)
229#define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10)
230#define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14)
231#define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18)
232#define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c)
233#define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e
234#define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20)
235#define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24)
236#define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28)
237
238#define IXP23XX_TIMER_ENABLE (1 << 0)
239#define IXP23XX_TIMER_ONE_SHOT (1 << 1)
240/* Low order bits of reload value ignored */
241#define IXP23XX_TIMER_RELOAD_MASK (0x3)
242#define IXP23XX_TIMER_DISABLED (0x0)
243#define IXP23XX_TIMER1_INT_PEND (1 << 0)
244#define IXP23XX_TIMER2_INT_PEND (1 << 1)
245#define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2)
246#define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3)
247#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4)
248
249
250/****************************************************************************
251 * CAP CSRs.
252 ****************************************************************************/
253#define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
254#define IXP23XX_PROD_IDG IXP23XX_GLOBAL_REG(0x00)
255#define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04)
256#define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08)
257#define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c)
258#define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10)
259#define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18)
260
261#define IXP23XX_ENABLE_WATCHDOG (1 << 24)
262#define IXP23XX_SHPC_INIT_COMP (1 << 21)
263#define IXP23XX_RST_ALL (1 << 16)
264#define IXP23XX_RESET_PCI (1 << 2)
265#define IXP23XX_PCI_UNIT_RESET (1 << 1)
266#define IXP23XX_XSCALE_RESET (1 << 0)
267
268
269/****************************************************************************
270 * PCI CSRs.
271 ****************************************************************************/
272#define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x)))
273#define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04)
274#define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14)
275#define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18)
276
277
278#define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x)))
279#define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030)
280#define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034)
281#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc)
282#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100)
283#define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c)
284#define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140)
285#define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148)
286#define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c)
287#define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150)
288#define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150)
289#define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154)
290#define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158)
291#define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c)
292#define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160)
293
294
295#ifndef __ASSEMBLY__
296/*
297 * Is system memory on the XSI or CPP bus?
298 */
299static inline unsigned ixp23xx_cpp_boot(void)
300{
301 return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES);
302}
303#endif
304
305
306#endif
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h
new file mode 100644
index 000000000000..bebcf0aa0d72
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/memory.h
@@ -0,0 +1,46 @@
1/*
2 * include/asm-arm/arch-ixp23xx/memory.h
3 *
4 * Copyright (c) 2003-2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H
14
15#include <asm/hardware.h>
16
17/*
18 * Physical DRAM offset.
19 */
20#define PHYS_OFFSET (0x00000000)
21
22
23/*
24 * Virtual view <-> DMA view memory address translations
25 * virt_to_bus: Used to translate the virtual address to an
26 * address suitable to be passed to set_dma_addr
27 * bus_to_virt: Used to convert an address for DMA operations
28 * to an address that the kernel can use.
29 */
30#ifndef __ASSEMBLY__
31
32#define __virt_to_bus(v) \
33 ({ unsigned int ret; \
34 ret = ((__virt_to_phys(v) - 0x00000000) + \
35 (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)); \
36 ret; })
37
38#define __bus_to_virt(b) \
39 ({ unsigned int data; \
40 data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \
41 __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
42
43#endif
44
45
46#endif
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h
new file mode 100644
index 000000000000..f85b4685a491
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/platform.h
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-ixp23xx/platform.h
3 *
4 * Various bits of code used by platform-level code.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASSEMBLY__
16
17struct pci_sys_data;
18
19void ixp23xx_map_io(void);
20void ixp23xx_init_irq(void);
21void ixp23xx_sys_init(void);
22int ixp23xx_pci_setup(int, struct pci_sys_data *);
23void ixp23xx_pci_preinit(void);
24struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
25
26extern struct sys_timer ixp23xx_timer;
27
28#define IXP23XX_UART_XTAL 14745600
29
30
31#endif
diff --git a/include/asm-arm/arch-ixp23xx/system.h b/include/asm-arm/arch-ixp23xx/system.h
new file mode 100644
index 000000000000..925e6b0c338b
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/system.h
@@ -0,0 +1,33 @@
1/*
2 * include/asm-arm/arch-ixp23xx/system.h
3 *
4 * Copyright (C) 2003 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <asm/hardware.h>
12#include <asm/mach-types.h>
13
14static inline void arch_idle(void)
15{
16#if 0
17 if (!hlt_counter)
18 cpu_do_idle();
19#endif
20}
21
22static inline void arch_reset(char mode)
23{
24 /* First try machine specific support */
25 if (machine_is_ixdp2351()) {
26 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
27 (void) *IXDP2351_CPLD_RESET1_REG;
28 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
29 }
30
31 /* Use on-chip reset capability */
32 *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
33}
diff --git a/include/asm-arm/arch-ixp23xx/time.h b/include/asm-arm/arch-ixp23xx/time.h
new file mode 100644
index 000000000000..f6828fdd2883
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/time.h
@@ -0,0 +1,3 @@
1/*
2 * include/asm-arm/arch-ixp23xx/time.h
3 */
diff --git a/include/asm-arm/arch-ixp23xx/timex.h b/include/asm-arm/arch-ixp23xx/timex.h
new file mode 100644
index 000000000000..516f72fe6082
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/timex.h
@@ -0,0 +1,7 @@
1/*
2 * include/asm-arm/arch-ixp23xx/timex.h
3 *
4 * XScale architecture timex specifications
5 */
6
7#define CLOCK_TICK_RATE 75000000
diff --git a/include/asm-arm/arch-ixp23xx/uncompress.h b/include/asm-arm/arch-ixp23xx/uncompress.h
new file mode 100644
index 000000000000..62623fa9b2f7
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/uncompress.h
@@ -0,0 +1,45 @@
1/*
2 * include/asm-arm/arch-ixp23xx/uncompress.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_UNCOMPRESS_H
12#define __ASM_ARCH_UNCOMPRESS_H
13
14#include <asm/hardware.h>
15#include <linux/serial_reg.h>
16
17#define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS)
18
19static __inline__ void putc(char c)
20{
21 int j;
22
23 for (j = 0; j < 0x1000; j++) {
24 if (UART_BASE[UART_LSR] & UART_LSR_THRE)
25 break;
26 }
27
28 UART_BASE[UART_TX] = c;
29}
30
31static void putstr(const char *s)
32{
33 while (*s) {
34 putc(*s);
35 if (*s == '\n')
36 putc('\r');
37 s++;
38 }
39}
40
41#define arch_decomp_setup()
42#define arch_decomp_wdog()
43
44
45#endif
diff --git a/include/asm-arm/arch-ixp23xx/vmalloc.h b/include/asm-arm/arch-ixp23xx/vmalloc.h
new file mode 100644
index 000000000000..9f2566658541
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/vmalloc.h
@@ -0,0 +1,10 @@
1/*
2 * include/asm-arm/arch-ixp23xx/vmalloc.h
3 *
4 * Copyright (c) 2005 MontaVista Software, Inc.
5 *
6 * NPU mappings end at 0xf0000000 and we allocate 64MB for board
7 * specific static I/O.
8 */
9
10#define VMALLOC_END (0xec000000)
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
index 960c35810a22..09ae6c91be60 100644
--- a/include/asm-arm/arch-ixp4xx/uncompress.h
+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
@@ -21,26 +21,18 @@
21 21
22static volatile u32* uart_base; 22static volatile u32* uart_base;
23 23
24static __inline__ void putc(char c) 24static inline void putc(int c)
25{ 25{
26 /* Check THRE and TEMT bits before we transmit the character. 26 /* Check THRE and TEMT bits before we transmit the character.
27 */ 27 */
28 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE); 28 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
29 barrier();
30
29 *uart_base = c; 31 *uart_base = c;
30} 32}
31 33
32/* 34static void flush(void)
33 * This does not append a newline
34 */
35static void putstr(const char *s)
36{ 35{
37 while (*s)
38 {
39 putc(*s);
40 if (*s == '\n')
41 putc('\r');
42 s++;
43 }
44} 36}
45 37
46static __inline__ void __arch_decomp_setup(unsigned long arch_id) 38static __inline__ void __arch_decomp_setup(unsigned long arch_id)
diff --git a/include/asm-arm/arch-l7200/uncompress.h b/include/asm-arm/arch-l7200/uncompress.h
index 1caa2b560f53..9fcd40aee3e3 100644
--- a/include/asm-arm/arch-l7200/uncompress.h
+++ b/include/asm-arm/arch-l7200/uncompress.h
@@ -16,22 +16,17 @@
16#define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v)) 16#define __raw_writeb(v,p) (*(volatile unsigned char *)(p) = (v))
17#define __raw_readb(p) (*(volatile unsigned char *)(p)) 17#define __raw_readb(p) (*(volatile unsigned char *)(p))
18 18
19static __inline__ void putc(char c) 19static inline void putc(int c)
20{ 20{
21 while(__raw_readb(IO_UART + 0x18) & 0x20 || 21 while(__raw_readb(IO_UART + 0x18) & 0x20 ||
22 __raw_readb(IO_UART + 0x18) & 0x08); 22 __raw_readb(IO_UART + 0x18) & 0x08)
23 barrier();
24
23 __raw_writeb(c, IO_UART + 0x00); 25 __raw_writeb(c, IO_UART + 0x00);
24} 26}
25 27
26static void putstr(const char *s) 28static inline void flush(void)
27{ 29{
28 while (*s) {
29 if (*s == 10) { /* If a LF, add CR */
30 putc(10);
31 putc(13);
32 }
33 putc(*(s++));
34 }
35} 30}
36 31
37static __inline__ void arch_decomp_setup(void) 32static __inline__ void arch_decomp_setup(void)
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
index ec8ab67122f3..f8053346f608 100644
--- a/include/asm-arm/arch-lh7a40x/uncompress.h
+++ b/include/asm-arm/arch-lh7a40x/uncompress.h
@@ -22,20 +22,15 @@
22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) 22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
23#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA)) 23#define UART_DATA (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA))
24 24
25static __inline__ void putc (char ch) 25static inline void putc(int ch)
26{ 26{
27 while (UART_STATUS & nTxRdy) 27 while (UART_STATUS & nTxRdy)
28 ; 28 barrier();
29 UART_DATA = ch; 29 UART_DATA = ch;
30} 30}
31 31
32static void putstr (const char* sz) 32static inline void flush(void)
33{ 33{
34 for (; *sz; ++sz) {
35 putc (*sz);
36 if (*sz == '\n')
37 putc ('\r');
38 }
39} 34}
40 35
41 /* NULL functions; we don't presently need them */ 36 /* NULL functions; we don't presently need them */
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
index c718264affbd..ca2c8bec82e7 100644
--- a/include/asm-arm/arch-omap/uncompress.h
+++ b/include/asm-arm/arch-omap/uncompress.h
@@ -30,8 +30,7 @@ unsigned int system_rev;
30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0) 30#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK 31#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
32 32
33static void 33static void putc(int c)
34putstr(const char *s)
35{ 34{
36 volatile u8 * uart = 0; 35 volatile u8 * uart = 0;
37 int shift = 2; 36 int shift = 2;
@@ -69,16 +68,13 @@ putstr(const char *s)
69 /* 68 /*
70 * Now, xmit each character 69 * Now, xmit each character
71 */ 70 */
72 while (*s) { 71 while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
73 while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) 72 barrier();
74 barrier(); 73 uart[UART_TX << shift] = c;
75 uart[UART_TX << shift] = *s; 74}
76 if (*s++ == '\n') { 75
77 while (!(uart[UART_LSR << shift] & UART_LSR_THRE)) 76static inline void flush(void)
78 barrier(); 77{
79 uart[UART_TX << shift] = '\r';
80 }
81 }
82} 78}
83 79
84/* 80/*
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index 05c4b7027592..67af238a8f8e 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -176,6 +176,7 @@
176#elif defined(CONFIG_SHARP_LOCOMO) 176#elif defined(CONFIG_SHARP_LOCOMO)
177#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) 177#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1)
178#elif defined(CONFIG_ARCH_LUBBOCK) || \ 178#elif defined(CONFIG_ARCH_LUBBOCK) || \
179 defined(CONFIG_MACH_LOGICPD_PXA270) || \
179 defined(CONFIG_MACH_MAINSTONE) 180 defined(CONFIG_MACH_MAINSTONE)
180#define NR_IRQS (IRQ_BOARD_END) 181#define NR_IRQS (IRQ_BOARD_END)
181#else 182#else
@@ -196,6 +197,11 @@
196#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ 197#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
197#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) 198#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
198 199
200#define LPD270_IRQ(x) (IRQ_BOARD_START + (x))
201#define LPD270_USBC_IRQ LPD270_IRQ(2)
202#define LPD270_ETHERNET_IRQ LPD270_IRQ(3)
203#define LPD270_AC97_IRQ LPD270_IRQ(4)
204
199#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) 205#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x))
200#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) 206#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
201#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) 207#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
diff --git a/include/asm-arm/arch-pxa/lpd270.h b/include/asm-arm/arch-pxa/lpd270.h
new file mode 100644
index 000000000000..501d240ac120
--- /dev/null
+++ b/include/asm-arm/arch-pxa/lpd270.h
@@ -0,0 +1,38 @@
1/*
2 * include/asm-arm/arch-pxa/lpd270.h
3 *
4 * Author: Lennert Buytenhek
5 * Created: Feb 10, 2006
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_LPD270_H
13#define __ASM_ARCH_LPD270_H
14
15#define LPD270_CPLD_PHYS PXA_CS2_PHYS
16#define LPD270_CPLD_VIRT 0xf0000000
17#define LPD270_CPLD_SIZE 0x00100000
18
19#define LPD270_ETH_PHYS (PXA_CS2_PHYS + 0x01000000)
20
21/* CPLD registers */
22#define LPD270_CPLD_REG(x) ((unsigned long)(LPD270_CPLD_VIRT + (x)))
23#define LPD270_CONTROL LPD270_CPLD_REG(0x00)
24#define LPD270_PERIPHERAL0 LPD270_CPLD_REG(0x04)
25#define LPD270_PERIPHERAL1 LPD270_CPLD_REG(0x08)
26#define LPD270_CPLD_REVISION LPD270_CPLD_REG(0x14)
27#define LPD270_EEPROM_SPI_ITF LPD270_CPLD_REG(0x20)
28#define LPD270_MODE_PINS LPD270_CPLD_REG(0x24)
29#define LPD270_EGPIO LPD270_CPLD_REG(0x30)
30#define LPD270_INT_MASK LPD270_CPLD_REG(0x40)
31#define LPD270_INT_STATUS LPD270_CPLD_REG(0x50)
32
33#define LPD270_INT_AC97 (1 << 4) /* AC'97 CODEC IRQ */
34#define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */
35#define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */
36
37
38#endif
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
index fe38090444e0..178aa2e073ac 100644
--- a/include/asm-arm/arch-pxa/uncompress.h
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -17,23 +17,18 @@
17#define UART FFUART 17#define UART FFUART
18 18
19 19
20static __inline__ void putc(char c) 20static inline void putc(char c)
21{ 21{
22 while (!(UART[5] & 0x20)); 22 while (!(UART[5] & 0x20))
23 barrier();
23 UART[0] = c; 24 UART[0] = c;
24} 25}
25 26
26/* 27/*
27 * This does not append a newline 28 * This does not append a newline
28 */ 29 */
29static void putstr(const char *s) 30static inline void flush(void)
30{ 31{
31 while (*s) {
32 putc(*s);
33 if (*s == '\n')
34 putc('\r');
35 s++;
36 }
37} 32}
38 33
39/* 34/*
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
index b5e4d360665b..f05631d76743 100644
--- a/include/asm-arm/arch-realview/uncompress.h
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -27,22 +27,16 @@
27/* 27/*
28 * This does not append a newline 28 * This does not append a newline
29 */ 29 */
30static void putstr(const char *s) 30static inline void putc(int c)
31{ 31{
32 while (*s) { 32 while (AMBA_UART_FR & (1 << 5))
33 while (AMBA_UART_FR & (1 << 5)) 33 barrier();
34 barrier();
35
36 AMBA_UART_DR = *s;
37 34
38 if (*s == '\n') { 35 AMBA_UART_DR = c;
39 while (AMBA_UART_FR & (1 << 5)) 36}
40 barrier();
41 37
42 AMBA_UART_DR = '\r'; 38static inline void flush(void)
43 } 39{
44 s++;
45 }
46 while (AMBA_UART_FR & (1 << 3)) 40 while (AMBA_UART_FR & (1 << 3))
47 barrier(); 41 barrier();
48} 42}
diff --git a/include/asm-arm/arch-rpc/uncompress.h b/include/asm-arm/arch-rpc/uncompress.h
index 43035fec64d2..06231ede54e5 100644
--- a/include/asm-arm/arch-rpc/uncompress.h
+++ b/include/asm-arm/arch-rpc/uncompress.h
@@ -67,31 +67,28 @@ extern __attribute__((pure)) struct param_struct *params(void);
67/* 67/*
68 * This does not append a newline 68 * This does not append a newline
69 */ 69 */
70static void putstr(const char *s) 70static void putc(int c)
71{ 71{
72 extern void ll_write_char(char *, char c, char white); 72 extern void ll_write_char(char *, char c, char white);
73 int x,y; 73 int x,y;
74 unsigned char c;
75 char *ptr; 74 char *ptr;
76 75
77 x = params->video_x; 76 x = params->video_x;
78 y = params->video_y; 77 y = params->video_y;
79 78
80 while ( ( c = *(unsigned char *)s++ ) != '\0' ) { 79 if (c == '\n') {
81 if ( c == '\n' ) { 80 if (++y >= video_num_lines)
81 y--;
82 } else if (c == '\r') {
83 x = 0;
84 } else {
85 ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h);
86 ll_write_char(ptr, c, white);
87 if (++x >= video_num_columns) {
82 x = 0; 88 x = 0;
83 if ( ++y >= video_num_lines ) { 89 if ( ++y >= video_num_lines ) {
84 y--; 90 y--;
85 } 91 }
86 } else {
87 ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h);
88 ll_write_char(ptr, c, white);
89 if ( ++x >= video_num_columns ) {
90 x = 0;
91 if ( ++y >= video_num_lines ) {
92 y--;
93 }
94 }
95 } 92 }
96 } 93 }
97 94
@@ -99,6 +96,10 @@ static void putstr(const char *s)
99 params->video_y = y; 96 params->video_y = y;
100} 97}
101 98
99static inline void flush(void)
100{
101}
102
102static void error(char *x); 103static void error(char *x);
103 104
104/* 105/*
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index 4367ec054b51..a6f6a0e44afa 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -67,8 +67,7 @@ uart_rd(unsigned int reg)
67 * waiting for tx to happen... 67 * waiting for tx to happen...
68*/ 68*/
69 69
70static void 70static void putc(int ch)
71putc(char ch)
72{ 71{
73 int cpuid = S3C2410_GSTATUS1_2410; 72 int cpuid = S3C2410_GSTATUS1_2410;
74 73
@@ -77,9 +76,6 @@ putc(char ch)
77 cpuid &= S3C2410_GSTATUS1_IDMASK; 76 cpuid &= S3C2410_GSTATUS1_IDMASK;
78#endif 77#endif
79 78
80 if (ch == '\n')
81 putc('\r'); /* expand newline to \r\n */
82
83 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) { 79 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
84 int level; 80 int level;
85 81
@@ -101,19 +97,16 @@ putc(char ch)
101 } else { 97 } else {
102 /* not using fifos */ 98 /* not using fifos */
103 99
104 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE); 100 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
101 barrier();
105 } 102 }
106 103
107 /* write byte to transmission register */ 104 /* write byte to transmission register */
108 uart_wr(S3C2410_UTXH, ch); 105 uart_wr(S3C2410_UTXH, ch);
109} 106}
110 107
111static void 108static inline void flush(void)
112putstr(const char *ptr)
113{ 109{
114 for (; *ptr != '\0'; ptr++) {
115 putc(*ptr);
116 }
117} 110}
118 111
119#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) 112#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
diff --git a/include/asm-arm/arch-sa1100/uncompress.h b/include/asm-arm/arch-sa1100/uncompress.h
index 43453501ee66..2601a77a6dda 100644
--- a/include/asm-arm/arch-sa1100/uncompress.h
+++ b/include/asm-arm/arch-sa1100/uncompress.h
@@ -17,7 +17,7 @@
17 17
18#define UART(x) (*(volatile unsigned long *)(serial_port + (x))) 18#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
19 19
20static void putstr( const char *s ) 20static void putc(int c)
21{ 21{
22 unsigned long serial_port; 22 unsigned long serial_port;
23 23
@@ -31,19 +31,16 @@ static void putstr( const char *s )
31 return; 31 return;
32 } while (0); 32 } while (0);
33 33
34 for (; *s; s++) { 34 /* wait for space in the UART's transmitter */
35 /* wait for space in the UART's transmitter */ 35 while (!(UART(UTSR1) & UTSR1_TNF))
36 while (!(UART(UTSR1) & UTSR1_TNF)); 36 barrier();
37 37
38 /* send the character out. */ 38 /* send the character out. */
39 UART(UTDR) = *s; 39 UART(UTDR) = c;
40}
40 41
41 /* if a LF, also do CR... */ 42static inline void flush(void)
42 if (*s == 10) { 43{
43 while (!(UART(UTSR1) & UTSR1_TNF));
44 UART(UTDR) = 13;
45 }
46 }
47} 44}
48 45
49/* 46/*
diff --git a/include/asm-arm/arch-shark/uncompress.h b/include/asm-arm/arch-shark/uncompress.h
index 910a8e0a0ca5..7eca6534f1bb 100644
--- a/include/asm-arm/arch-shark/uncompress.h
+++ b/include/asm-arm/arch-shark/uncompress.h
@@ -9,7 +9,7 @@
9 9
10#define SERIAL_BASE ((volatile unsigned char *)0x400003f8) 10#define SERIAL_BASE ((volatile unsigned char *)0x400003f8)
11 11
12static __inline__ void putc(char c) 12static inline void putc(int c)
13{ 13{
14 int t; 14 int t;
15 15
@@ -18,17 +18,8 @@ static __inline__ void putc(char c)
18 while (t--); 18 while (t--);
19} 19}
20 20
21/* 21static inline void flush(void)
22 * This does not append a newline
23 */
24static void putstr(const char *s)
25{ 22{
26 while (*s) {
27 putc(*s);
28 if (*s == '\n')
29 putc('\r');
30 s++;
31 }
32} 23}
33 24
34#ifdef DEBUG 25#ifdef DEBUG
diff --git a/include/asm-arm/arch-versatile/uncompress.h b/include/asm-arm/arch-versatile/uncompress.h
index 2f57499c7b92..7215133d0514 100644
--- a/include/asm-arm/arch-versatile/uncompress.h
+++ b/include/asm-arm/arch-versatile/uncompress.h
@@ -25,22 +25,16 @@
25/* 25/*
26 * This does not append a newline 26 * This does not append a newline
27 */ 27 */
28static void putstr(const char *s) 28static inline void putc(int c)
29{ 29{
30 while (*s) { 30 while (AMBA_UART_FR & (1 << 5))
31 while (AMBA_UART_FR & (1 << 5)) 31 barrier();
32 barrier();
33
34 AMBA_UART_DR = *s;
35 32
36 if (*s == '\n') { 33 AMBA_UART_DR = c;
37 while (AMBA_UART_FR & (1 << 5)) 34}
38 barrier();
39 35
40 AMBA_UART_DR = '\r'; 36static inline void flush(void)
41 } 37{
42 s++;
43 }
44 while (AMBA_UART_FR & (1 << 3)) 38 while (AMBA_UART_FR & (1 << 3))
45 barrier(); 39 barrier();
46} 40}
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 09e19a783a51..746be56b1b70 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -71,6 +71,14 @@
71# endif 71# endif
72#endif 72#endif
73 73
74#if defined(CONFIG_CPU_XSC3)
75# ifdef _CACHE
76# define MULTI_CACHE 1
77# else
78# define _CACHE xsc3
79# endif
80#endif
81
74#if defined(CONFIG_CPU_V6) 82#if defined(CONFIG_CPU_V6)
75//# ifdef _CACHE 83//# ifdef _CACHE
76# define MULTI_CACHE 1 84# define MULTI_CACHE 1
diff --git a/include/asm-arm/domain.h b/include/asm-arm/domain.h
index da1d960387d9..f8ea2de4848e 100644
--- a/include/asm-arm/domain.h
+++ b/include/asm-arm/domain.h
@@ -16,11 +16,29 @@
16 * DOMAIN_IO - domain 2 includes all IO only 16 * DOMAIN_IO - domain 2 includes all IO only
17 * DOMAIN_USER - domain 1 includes all user memory only 17 * DOMAIN_USER - domain 1 includes all user memory only
18 * DOMAIN_KERNEL - domain 0 includes all kernel memory only 18 * DOMAIN_KERNEL - domain 0 includes all kernel memory only
19 *
20 * The domain numbering depends on whether we support 36 physical
21 * address for I/O or not. Addresses above the 32 bit boundary can
22 * only be mapped using supersections and supersections can only
23 * be set for domain 0. We could just default to DOMAIN_IO as zero,
24 * but there may be systems with supersection support and no 36-bit
25 * addressing. In such cases, we want to map system memory with
26 * supersections to reduce TLB misses and footprint.
27 *
28 * 36-bit addressing and supersections are only available on
29 * CPUs based on ARMv6+ or the Intel XSC3 core.
19 */ 30 */
31#ifndef CONFIG_IO_36
20#define DOMAIN_KERNEL 0 32#define DOMAIN_KERNEL 0
21#define DOMAIN_TABLE 0 33#define DOMAIN_TABLE 0
22#define DOMAIN_USER 1 34#define DOMAIN_USER 1
23#define DOMAIN_IO 2 35#define DOMAIN_IO 2
36#else
37#define DOMAIN_KERNEL 2
38#define DOMAIN_TABLE 2
39#define DOMAIN_USER 1
40#define DOMAIN_IO 0
41#endif
24 42
25/* 43/*
26 * Domain types 44 * Domain types
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 416320d95419..a404d2bf0c68 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -40,6 +40,7 @@
40 * v4wb - ARMv4 with writeback cache, without minicache 40 * v4wb - ARMv4 with writeback cache, without minicache
41 * v4_mc - ARMv4 with minicache 41 * v4_mc - ARMv4 with minicache
42 * xscale - Xscale 42 * xscale - Xscale
43 * xsc3 - XScalev3
43 */ 44 */
44#undef _USER 45#undef _USER
45#undef MULTI_USER 46#undef MULTI_USER
@@ -84,6 +85,14 @@
84# endif 85# endif
85#endif 86#endif
86 87
88#ifdef CONFIG_CPU_XSC3
89# ifdef _USER
90# define MULTI_USER 1
91# else
92# define _USER xsc3_mc
93# endif
94#endif
95
87#ifdef CONFIG_CPU_COPY_V6 96#ifdef CONFIG_CPU_COPY_V6
88# define MULTI_USER 1 97# define MULTI_USER 1
89#endif 98#endif
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 7bef2bf6be51..106045edb862 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -138,6 +138,14 @@
138# define CPU_NAME cpu_xscale 138# define CPU_NAME cpu_xscale
139# endif 139# endif
140# endif 140# endif
141# ifdef CONFIG_CPU_XSC3
142# ifdef CPU_NAME
143# undef MULTI_CPU
144# define MULTI_CPU
145# else
146# define CPU_NAME cpu_xsc3
147# endif
148# endif
141# ifdef CONFIG_CPU_V6 149# ifdef CONFIG_CPU_V6
142# ifdef CPU_NAME 150# ifdef CPU_NAME
143# undef MULTI_CPU 151# undef MULTI_CPU
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index ec91d1ff032a..95b3abf4851b 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -108,6 +108,25 @@ extern void __show_regs(struct pt_regs *);
108extern int cpu_architecture(void); 108extern int cpu_architecture(void);
109extern void cpu_init(void); 109extern void cpu_init(void);
110 110
111/*
112 * Intel's XScale3 core supports some v6 features (supersections, L2)
113 * but advertises itself as v5 as it does not support the v6 ISA. For
114 * this reason, we need a way to explicitly test for this type of CPU.
115 */
116#ifndef CONFIG_CPU_XSC3
117#define cpu_is_xsc3() 0
118#else
119static inline int cpu_is_xsc3(void)
120{
121 extern unsigned int processor_id;
122
123 if ((processor_id & 0xffffe000) == 0x69056000)
124 return 1;
125
126 return 0;
127}
128#endif
129
111#define set_cr(x) \ 130#define set_cr(x) \
112 __asm__ __volatile__( \ 131 __asm__ __volatile__( \
113 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ 132 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-26 13:37:35 -0400