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authorHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>2009-06-15 04:25:27 -0400
committerH. Peter Anvin <hpa@zytor.com>2009-06-16 19:56:08 -0400
commita65c88dd2c83b569dbd13778da689861bdf977f2 (patch)
tree61c1e44b539b722909256969bd4d4dfb1c5143b5
parente8ce2c5ee826b3787202493effcd08d4b1e1e639 (diff)
x86, mce: unify smp_thermal_interrupt
Put common functions into therm_throt.c, modify Makefile. unexpected_thermal_interrupt intel_thermal_interrupt smp_thermal_interrupt intel_set_thermal_handler Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--arch/x86/kernel/cpu/mcheck/Makefile7
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_intel_64.c38
-rw-r--r--arch/x86/kernel/cpu/mcheck/p4.c45
-rw-r--r--arch/x86/kernel/cpu/mcheck/therm_throt.c40
4 files changed, 43 insertions, 87 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/Makefile b/arch/x86/kernel/cpu/mcheck/Makefile
index 45004faf67ea..53df57d11c50 100644
--- a/arch/x86/kernel/cpu/mcheck/Makefile
+++ b/arch/x86/kernel/cpu/mcheck/Makefile
@@ -1,11 +1,12 @@
1obj-y = mce.o therm_throt.o 1obj-y = mce.o
2 2
3obj-$(CONFIG_X86_NEW_MCE) += mce-severity.o 3obj-$(CONFIG_X86_NEW_MCE) += mce-severity.o
4obj-$(CONFIG_X86_OLD_MCE) += k7.o p4.o p6.o 4obj-$(CONFIG_X86_OLD_MCE) += k7.o p4.o p6.o
5obj-$(CONFIG_X86_ANCIENT_MCE) += winchip.o p5.o 5obj-$(CONFIG_X86_ANCIENT_MCE) += winchip.o p5.o
6obj-$(CONFIG_X86_MCE_P4THERMAL) += mce_intel.o 6obj-$(CONFIG_X86_MCE_INTEL) += mce_intel_64.o
7obj-$(CONFIG_X86_MCE_INTEL) += mce_intel_64.o mce_intel.o
8obj-$(CONFIG_X86_MCE_AMD) += mce_amd_64.o 7obj-$(CONFIG_X86_MCE_AMD) += mce_amd_64.o
9obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o 8obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o
10obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o 9obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o
11obj-$(CONFIG_X86_MCE_INJECT) += mce-inject.o 10obj-$(CONFIG_X86_MCE_INJECT) += mce-inject.o
11
12obj-$(CONFIG_X86_THERMAL_VECTOR) += therm_throt.o mce_intel.o
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
index 922e3a482f6f..3b7a0572e2fe 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
@@ -9,48 +9,10 @@
9#include <linux/interrupt.h> 9#include <linux/interrupt.h>
10#include <linux/percpu.h> 10#include <linux/percpu.h>
11#include <asm/processor.h> 11#include <asm/processor.h>
12#include <asm/apic.h>
13#include <asm/msr.h> 12#include <asm/msr.h>
14#include <asm/mce.h> 13#include <asm/mce.h>
15#include <asm/hw_irq.h>
16#include <asm/idle.h>
17#include <asm/therm_throt.h> 14#include <asm/therm_throt.h>
18 15
19static void unexpected_thermal_interrupt(void)
20{
21 printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
22 smp_processor_id());
23 add_taint(TAINT_MACHINE_CHECK);
24}
25
26/* P4/Xeon Thermal transition interrupt handler: */
27static void intel_thermal_interrupt(void)
28{
29 __u64 msr_val;
30
31 rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
32 if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))
33 mce_log_therm_throt_event(msr_val);
34}
35
36/* Thermal interrupt handler for this CPU setup: */
37static void (*vendor_thermal_interrupt)(void) = unexpected_thermal_interrupt;
38
39asmlinkage void smp_thermal_interrupt(void)
40{
41 exit_idle();
42 irq_enter();
43 inc_irq_stat(irq_thermal_count);
44 intel_thermal_interrupt();
45 irq_exit();
46 ack_APIC_irq();
47}
48
49void intel_set_thermal_handler(void)
50{
51 vendor_thermal_interrupt = intel_thermal_interrupt;
52}
53
54/* 16/*
55 * Support for Intel Correct Machine Check Interrupts. This allows 17 * Support for Intel Correct Machine Check Interrupts. This allows
56 * the CPU to raise an interrupt when a corrected machine check happened. 18 * the CPU to raise an interrupt when a corrected machine check happened.
diff --git a/arch/x86/kernel/cpu/mcheck/p4.c b/arch/x86/kernel/cpu/mcheck/p4.c
index 75313f5b624e..76c5f0305f9f 100644
--- a/arch/x86/kernel/cpu/mcheck/p4.c
+++ b/arch/x86/kernel/cpu/mcheck/p4.c
@@ -1,8 +1,6 @@
1/* 1/*
2 * P4 specific Machine Check Exception Reporting 2 * P4 specific Machine Check Exception Reporting
3 */ 3 */
4
5#include <linux/interrupt.h>
6#include <linux/kernel.h> 4#include <linux/kernel.h>
7#include <linux/types.h> 5#include <linux/types.h>
8#include <linux/init.h> 6#include <linux/init.h>
@@ -10,9 +8,6 @@
10 8
11#include <asm/therm_throt.h> 9#include <asm/therm_throt.h>
12#include <asm/processor.h> 10#include <asm/processor.h>
13#include <asm/system.h>
14#include <asm/apic.h>
15#include <asm/idle.h>
16#include <asm/mce.h> 11#include <asm/mce.h>
17#include <asm/msr.h> 12#include <asm/msr.h>
18 13
@@ -33,46 +28,6 @@ struct intel_mce_extended_msrs {
33 28
34static int mce_num_extended_msrs; 29static int mce_num_extended_msrs;
35 30
36
37#ifdef CONFIG_X86_MCE_P4THERMAL
38
39static void unexpected_thermal_interrupt(void)
40{
41 printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
42 smp_processor_id());
43 add_taint(TAINT_MACHINE_CHECK);
44}
45
46/* P4/Xeon Thermal transition interrupt handler: */
47static void intel_thermal_interrupt(void)
48{
49 __u64 msr_val;
50
51 rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
52 if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))
53 mce_log_therm_throt_event(msr_val);
54}
55
56/* Thermal interrupt handler for this CPU setup: */
57static void (*vendor_thermal_interrupt)(void) = unexpected_thermal_interrupt;
58
59void smp_thermal_interrupt(struct pt_regs *regs)
60{
61 exit_idle();
62 irq_enter();
63 inc_irq_stat(irq_thermal_count);
64 vendor_thermal_interrupt();
65 irq_exit();
66 ack_APIC_irq();
67}
68
69void intel_set_thermal_handler(void)
70{
71 vendor_thermal_interrupt = intel_thermal_interrupt;
72}
73
74#endif /* CONFIG_X86_MCE_P4THERMAL */
75
76/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */ 31/* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
77static void intel_get_extended_msrs(struct intel_mce_extended_msrs *r) 32static void intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
78{ 33{
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index 7b1ae2e20ba5..b3792b196856 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -13,6 +13,7 @@
13 * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. 13 * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
14 * Inspired by Ross Biro's and Al Borchers' counter code. 14 * Inspired by Ross Biro's and Al Borchers' counter code.
15 */ 15 */
16#include <linux/interrupt.h>
16#include <linux/notifier.h> 17#include <linux/notifier.h>
17#include <linux/jiffies.h> 18#include <linux/jiffies.h>
18#include <linux/percpu.h> 19#include <linux/percpu.h>
@@ -20,6 +21,8 @@
20#include <linux/cpu.h> 21#include <linux/cpu.h>
21 22
22#include <asm/therm_throt.h> 23#include <asm/therm_throt.h>
24#include <asm/idle.h>
25#include <asm/mce.h>
23 26
24/* How long to wait between reporting thermal events */ 27/* How long to wait between reporting thermal events */
25#define CHECK_INTERVAL (300 * HZ) 28#define CHECK_INTERVAL (300 * HZ)
@@ -186,6 +189,41 @@ static __init int thermal_throttle_init_device(void)
186 189
187 return 0; 190 return 0;
188} 191}
189
190device_initcall(thermal_throttle_init_device); 192device_initcall(thermal_throttle_init_device);
193
191#endif /* CONFIG_SYSFS */ 194#endif /* CONFIG_SYSFS */
195
196/* Thermal transition interrupt handler */
197void intel_thermal_interrupt(void)
198{
199 __u64 msr_val;
200
201 rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
202 if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))
203 mce_log_therm_throt_event(msr_val);
204}
205
206static void unexpected_thermal_interrupt(void)
207{
208 printk(KERN_ERR "CPU%d: Unexpected LVT TMR interrupt!\n",
209 smp_processor_id());
210 add_taint(TAINT_MACHINE_CHECK);
211}
212
213static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
214
215asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
216{
217 exit_idle();
218 irq_enter();
219 inc_irq_stat(irq_thermal_count);
220 smp_thermal_vector();
221 irq_exit();
222 /* Ack only at the end to avoid potential reentry */
223 ack_APIC_irq();
224}
225
226void intel_set_thermal_handler(void)
227{
228 smp_thermal_vector = intel_thermal_interrupt;
229}