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authorMatt Carlson <mcarlson@broadcom.com>2010-02-17 10:17:03 -0500
committerDavid S. Miller <davem@davemloft.net>2010-02-17 20:27:39 -0500
commit79eb6904361fe4e54e589919a9b62c5e036c42c3 (patch)
tree5341c14a99cad6ab3442290828d759e22b45b2f5
parent24daf2b0a4005f3a4e757752fcfed9da276cf202 (diff)
tg3: Rename tg3 phy ID preprocessor definitions
The phylib presents the phy ID in a different format than the one tg3 has traditionally used. To highlight the distinction, this patch prepends the tg3 native phy ID format with TG3. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/tg3.c122
-rw-r--r--drivers/net/tg3.h91
2 files changed, 106 insertions, 107 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b545ea7e0ad6..965efa92b020 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1995,7 +1995,7 @@ out:
1995 } 1995 }
1996 /* Set Extended packet length bit (bit 14) on all chips that */ 1996 /* Set Extended packet length bit (bit 14) on all chips that */
1997 /* support jumbo frames */ 1997 /* support jumbo frames */
1998 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 1998 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1999 /* Cannot do read-modify-write on 5401 */ 1999 /* Cannot do read-modify-write on 5401 */
2000 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); 2000 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2001 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { 2001 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
@@ -2147,7 +2147,7 @@ static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2147{ 2147{
2148 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) 2148 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2149 return 1; 2149 return 1;
2150 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) { 2150 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2151 if (speed != SPEED_10) 2151 if (speed != SPEED_10)
2152 return 1; 2152 return 1;
2153 } else if (speed == SPEED_10) 2153 } else if (speed == SPEED_10)
@@ -3077,7 +3077,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3077 if (force_reset) 3077 if (force_reset)
3078 tg3_phy_reset(tp); 3078 tg3_phy_reset(tp);
3079 3079
3080 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 3080 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3081 tg3_readphy(tp, MII_BMSR, &bmsr); 3081 tg3_readphy(tp, MII_BMSR, &bmsr);
3082 if (tg3_readphy(tp, MII_BMSR, &bmsr) || 3082 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3083 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) 3083 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
@@ -3098,7 +3098,8 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3098 } 3098 }
3099 } 3099 }
3100 3100
3101 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 && 3101 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3102 TG3_PHY_REV_BCM5401_B0 &&
3102 !(bmsr & BMSR_LSTATUS) && 3103 !(bmsr & BMSR_LSTATUS) &&
3103 tp->link_config.active_speed == SPEED_1000) { 3104 tp->link_config.active_speed == SPEED_1000) {
3104 err = tg3_phy_reset(tp); 3105 err = tg3_phy_reset(tp);
@@ -3253,7 +3254,7 @@ relink:
3253 /* ??? Without this setting Netgear GA302T PHY does not 3254 /* ??? Without this setting Netgear GA302T PHY does not
3254 * ??? send/receive packets... 3255 * ??? send/receive packets...
3255 */ 3256 */
3256 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 && 3257 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3257 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { 3258 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3258 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; 3259 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3259 tw32_f(MAC_MI_MODE, tp->mi_mode); 3260 tw32_f(MAC_MI_MODE, tp->mi_mode);
@@ -3968,7 +3969,7 @@ static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3968 tw32_f(MAC_MODE, tp->mac_mode); 3969 tw32_f(MAC_MODE, tp->mac_mode);
3969 udelay(40); 3970 udelay(40);
3970 3971
3971 if (tp->phy_id == PHY_ID_BCM8002) 3972 if (tp->phy_id == TG3_PHY_ID_BCM8002)
3972 tg3_init_bcm8002(tp); 3973 tg3_init_bcm8002(tp);
3973 3974
3974 /* Enable link change event even when serdes polling. */ 3975 /* Enable link change event even when serdes polling. */
@@ -10854,9 +10855,10 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10854 tw32_f(MAC_RX_MODE, tp->rx_mode); 10855 tw32_f(MAC_RX_MODE, tp->rx_mode);
10855 } 10856 }
10856 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { 10857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10857 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) 10858 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10859 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10858 mac_mode &= ~MAC_MODE_LINK_POLARITY; 10860 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10859 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) 10861 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10860 mac_mode |= MAC_MODE_LINK_POLARITY; 10862 mac_mode |= MAC_MODE_LINK_POLARITY;
10861 tg3_writephy(tp, MII_TG3_EXT_CTRL, 10863 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10862 MII_TG3_EXT_CTRL_LNK3_LED_MODE); 10864 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
@@ -12115,61 +12117,61 @@ struct subsys_tbl_ent {
12115static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { 12117static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12116 /* Broadcom boards. */ 12118 /* Broadcom boards. */
12117 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12119 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12118 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, PHY_ID_BCM5401 }, 12120 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12119 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12121 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12120 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, PHY_ID_BCM5701 }, 12122 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12121 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12123 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12122 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, PHY_ID_BCM8002 }, 12124 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12123 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12125 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12124 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, 12126 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12125 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12127 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12126 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, PHY_ID_BCM5701 }, 12128 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12127 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12129 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12128 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, PHY_ID_BCM5701 }, 12130 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12129 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12131 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12130 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, 12132 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12131 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12133 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12132 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, PHY_ID_BCM5701 }, 12134 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12133 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12135 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12134 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, PHY_ID_BCM5701 }, 12136 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12135 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12137 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12136 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, PHY_ID_BCM5703 }, 12138 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12137 { TG3PCI_SUBVENDOR_ID_BROADCOM, 12139 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12138 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, PHY_ID_BCM5703 }, 12140 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12139 12141
12140 /* 3com boards. */ 12142 /* 3com boards. */
12141 { TG3PCI_SUBVENDOR_ID_3COM, 12143 { TG3PCI_SUBVENDOR_ID_3COM,
12142 TG3PCI_SUBDEVICE_ID_3COM_3C996T, PHY_ID_BCM5401 }, 12144 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12143 { TG3PCI_SUBVENDOR_ID_3COM, 12145 { TG3PCI_SUBVENDOR_ID_3COM,
12144 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, PHY_ID_BCM5701 }, 12146 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12145 { TG3PCI_SUBVENDOR_ID_3COM, 12147 { TG3PCI_SUBVENDOR_ID_3COM,
12146 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, 12148 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12147 { TG3PCI_SUBVENDOR_ID_3COM, 12149 { TG3PCI_SUBVENDOR_ID_3COM,
12148 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, PHY_ID_BCM5701 }, 12150 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12149 { TG3PCI_SUBVENDOR_ID_3COM, 12151 { TG3PCI_SUBVENDOR_ID_3COM,
12150 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, PHY_ID_BCM5701 }, 12152 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12151 12153
12152 /* DELL boards. */ 12154 /* DELL boards. */
12153 { TG3PCI_SUBVENDOR_ID_DELL, 12155 { TG3PCI_SUBVENDOR_ID_DELL,
12154 TG3PCI_SUBDEVICE_ID_DELL_VIPER, PHY_ID_BCM5401 }, 12156 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12155 { TG3PCI_SUBVENDOR_ID_DELL, 12157 { TG3PCI_SUBVENDOR_ID_DELL,
12156 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, PHY_ID_BCM5401 }, 12158 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12157 { TG3PCI_SUBVENDOR_ID_DELL, 12159 { TG3PCI_SUBVENDOR_ID_DELL,
12158 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, PHY_ID_BCM5411 }, 12160 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12159 { TG3PCI_SUBVENDOR_ID_DELL, 12161 { TG3PCI_SUBVENDOR_ID_DELL,
12160 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, PHY_ID_BCM5411 }, 12162 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12161 12163
12162 /* Compaq boards. */ 12164 /* Compaq boards. */
12163 { TG3PCI_SUBVENDOR_ID_COMPAQ, 12165 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12164 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, PHY_ID_BCM5701 }, 12166 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12165 { TG3PCI_SUBVENDOR_ID_COMPAQ, 12167 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12166 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, PHY_ID_BCM5701 }, 12168 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12167 { TG3PCI_SUBVENDOR_ID_COMPAQ, 12169 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12168 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, 12170 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12169 { TG3PCI_SUBVENDOR_ID_COMPAQ, 12171 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12170 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, PHY_ID_BCM5701 }, 12172 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12171 { TG3PCI_SUBVENDOR_ID_COMPAQ, 12173 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12172 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, PHY_ID_BCM5701 }, 12174 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12173 12175
12174 /* IBM boards. */ 12176 /* IBM boards. */
12175 { TG3PCI_SUBVENDOR_ID_IBM, 12177 { TG3PCI_SUBVENDOR_ID_IBM,
@@ -12217,7 +12219,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12217 val = tr32(MEMARB_MODE); 12219 val = tr32(MEMARB_MODE);
12218 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); 12220 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12219 12221
12220 tp->phy_id = PHY_ID_INVALID; 12222 tp->phy_id = TG3_PHY_ID_INVALID;
12221 tp->led_ctrl = LED_CTRL_MODE_PHY_1; 12223 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12222 12224
12223 /* Assume an onboard device and WOL capable by default. */ 12225 /* Assume an onboard device and WOL capable by default. */
@@ -12468,7 +12470,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
12468 err = 0; 12470 err = 0;
12469 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || 12471 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12470 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { 12472 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12471 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID; 12473 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12472 } else { 12474 } else {
12473 /* Now read the physical PHY_ID from the chip and verify 12475 /* Now read the physical PHY_ID from the chip and verify
12474 * that it is sane. If it doesn't look good, we fall back 12476 * that it is sane. If it doesn't look good, we fall back
@@ -12482,17 +12484,17 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
12482 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; 12484 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12483 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; 12485 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12484 12486
12485 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK; 12487 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12486 } 12488 }
12487 12489
12488 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) { 12490 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12489 tp->phy_id = hw_phy_id; 12491 tp->phy_id = hw_phy_id;
12490 if (hw_phy_id_masked == PHY_ID_BCM8002) 12492 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12491 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; 12493 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12492 else 12494 else
12493 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES; 12495 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12494 } else { 12496 } else {
12495 if (tp->phy_id != PHY_ID_INVALID) { 12497 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12496 /* Do nothing, phy ID already set up in 12498 /* Do nothing, phy ID already set up in
12497 * tg3_get_eeprom_hw_cfg(). 12499 * tg3_get_eeprom_hw_cfg().
12498 */ 12500 */
@@ -12508,7 +12510,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
12508 12510
12509 tp->phy_id = p->phy_id; 12511 tp->phy_id = p->phy_id;
12510 if (!tp->phy_id || 12512 if (!tp->phy_id ||
12511 tp->phy_id == PHY_ID_BCM8002) 12513 tp->phy_id == TG3_PHY_ID_BCM8002)
12512 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; 12514 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12513 } 12515 }
12514 } 12516 }
@@ -12560,13 +12562,11 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
12560 } 12562 }
12561 12563
12562skip_phy_reset: 12564skip_phy_reset:
12563 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 12565 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12564 err = tg3_init_5401phy_dsp(tp); 12566 err = tg3_init_5401phy_dsp(tp);
12565 if (err) 12567 if (err)
12566 return err; 12568 return err;
12567 }
12568 12569
12569 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12570 err = tg3_init_5401phy_dsp(tp); 12570 err = tg3_init_5401phy_dsp(tp);
12571 } 12571 }
12572 12572
@@ -14317,28 +14317,28 @@ static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14317 14317
14318static char * __devinit tg3_phy_string(struct tg3 *tp) 14318static char * __devinit tg3_phy_string(struct tg3 *tp)
14319{ 14319{
14320 switch (tp->phy_id & PHY_ID_MASK) { 14320 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14321 case PHY_ID_BCM5400: return "5400"; 14321 case TG3_PHY_ID_BCM5400: return "5400";
14322 case PHY_ID_BCM5401: return "5401"; 14322 case TG3_PHY_ID_BCM5401: return "5401";
14323 case PHY_ID_BCM5411: return "5411"; 14323 case TG3_PHY_ID_BCM5411: return "5411";
14324 case PHY_ID_BCM5701: return "5701"; 14324 case TG3_PHY_ID_BCM5701: return "5701";
14325 case PHY_ID_BCM5703: return "5703"; 14325 case TG3_PHY_ID_BCM5703: return "5703";
14326 case PHY_ID_BCM5704: return "5704"; 14326 case TG3_PHY_ID_BCM5704: return "5704";
14327 case PHY_ID_BCM5705: return "5705"; 14327 case TG3_PHY_ID_BCM5705: return "5705";
14328 case PHY_ID_BCM5750: return "5750"; 14328 case TG3_PHY_ID_BCM5750: return "5750";
14329 case PHY_ID_BCM5752: return "5752"; 14329 case TG3_PHY_ID_BCM5752: return "5752";
14330 case PHY_ID_BCM5714: return "5714"; 14330 case TG3_PHY_ID_BCM5714: return "5714";
14331 case PHY_ID_BCM5780: return "5780"; 14331 case TG3_PHY_ID_BCM5780: return "5780";
14332 case PHY_ID_BCM5755: return "5755"; 14332 case TG3_PHY_ID_BCM5755: return "5755";
14333 case PHY_ID_BCM5787: return "5787"; 14333 case TG3_PHY_ID_BCM5787: return "5787";
14334 case PHY_ID_BCM5784: return "5784"; 14334 case TG3_PHY_ID_BCM5784: return "5784";
14335 case PHY_ID_BCM5756: return "5722/5756"; 14335 case TG3_PHY_ID_BCM5756: return "5722/5756";
14336 case PHY_ID_BCM5906: return "5906"; 14336 case TG3_PHY_ID_BCM5906: return "5906";
14337 case PHY_ID_BCM5761: return "5761"; 14337 case TG3_PHY_ID_BCM5761: return "5761";
14338 case PHY_ID_BCM5718C: return "5718C"; 14338 case TG3_PHY_ID_BCM5718C: return "5718C";
14339 case PHY_ID_BCM5718S: return "5718S"; 14339 case TG3_PHY_ID_BCM5718S: return "5718S";
14340 case PHY_ID_BCM57765: return "57765"; 14340 case TG3_PHY_ID_BCM57765: return "57765";
14341 case PHY_ID_BCM8002: return "8002/serdes"; 14341 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14342 case 0: return "serdes"; 14342 case 0: return "serdes";
14343 default: return "unknown"; 14343 default: return "unknown";
14344 } 14344 }
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 12ce22644ac8..800dec463e98 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2921,45 +2921,59 @@ struct tg3 {
2921 2921
2922 /* PHY info */ 2922 /* PHY info */
2923 u32 phy_id; 2923 u32 phy_id;
2924#define PHY_ID_MASK 0xfffffff0 2924#define TG3_PHY_ID_MASK 0xfffffff0
2925#define PHY_ID_BCM5400 0x60008040 2925#define TG3_PHY_ID_BCM5400 0x60008040
2926#define PHY_ID_BCM5401 0x60008050 2926#define TG3_PHY_ID_BCM5401 0x60008050
2927#define PHY_ID_BCM5411 0x60008070 2927#define TG3_PHY_ID_BCM5411 0x60008070
2928#define PHY_ID_BCM5701 0x60008110 2928#define TG3_PHY_ID_BCM5701 0x60008110
2929#define PHY_ID_BCM5703 0x60008160 2929#define TG3_PHY_ID_BCM5703 0x60008160
2930#define PHY_ID_BCM5704 0x60008190 2930#define TG3_PHY_ID_BCM5704 0x60008190
2931#define PHY_ID_BCM5705 0x600081a0 2931#define TG3_PHY_ID_BCM5705 0x600081a0
2932#define PHY_ID_BCM5750 0x60008180 2932#define TG3_PHY_ID_BCM5750 0x60008180
2933#define PHY_ID_BCM5752 0x60008100 2933#define TG3_PHY_ID_BCM5752 0x60008100
2934#define PHY_ID_BCM5714 0x60008340 2934#define TG3_PHY_ID_BCM5714 0x60008340
2935#define PHY_ID_BCM5780 0x60008350 2935#define TG3_PHY_ID_BCM5780 0x60008350
2936#define PHY_ID_BCM5755 0xbc050cc0 2936#define TG3_PHY_ID_BCM5755 0xbc050cc0
2937#define PHY_ID_BCM5787 0xbc050ce0 2937#define TG3_PHY_ID_BCM5787 0xbc050ce0
2938#define PHY_ID_BCM5756 0xbc050ed0 2938#define TG3_PHY_ID_BCM5756 0xbc050ed0
2939#define PHY_ID_BCM5784 0xbc050fa0 2939#define TG3_PHY_ID_BCM5784 0xbc050fa0
2940#define PHY_ID_BCM5761 0xbc050fd0 2940#define TG3_PHY_ID_BCM5761 0xbc050fd0
2941#define PHY_ID_BCM5718C 0x5c0d8a00 2941#define TG3_PHY_ID_BCM5718C 0x5c0d8a00
2942#define PHY_ID_BCM5718S 0xbc050ff0 2942#define TG3_PHY_ID_BCM5718S 0xbc050ff0
2943#define PHY_ID_BCM57765 0x5c0d8a40 2943#define TG3_PHY_ID_BCM57765 0x5c0d8a40
2944#define PHY_ID_BCM5906 0xdc00ac40 2944#define TG3_PHY_ID_BCM5906 0xdc00ac40
2945#define PHY_ID_BCM8002 0x60010140 2945#define TG3_PHY_ID_BCM8002 0x60010140
2946#define PHY_ID_INVALID 0xffffffff 2946#define TG3_PHY_ID_BCM50610 0x0143bd60
2947#define PHY_ID_REV_MASK 0x0000000f 2947#define TG3_PHY_ID_BCM50610M 0x0143bd70
2948#define PHY_REV_BCM5401_B0 0x1 2948#define TG3_PHY_ID_BCMAC131 0x0143bc70
2949#define PHY_REV_BCM5401_B2 0x3
2950#define PHY_REV_BCM5401_C0 0x6
2951#define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2952#define TG3_PHY_ID_BCM50610 0x143bd60
2953#define TG3_PHY_ID_BCM50610M 0x143bd70
2954#define TG3_PHY_ID_BCMAC131 0x143bc70
2955#define TG3_PHY_ID_RTL8211C 0x001cc910 2949#define TG3_PHY_ID_RTL8211C 0x001cc910
2956#define TG3_PHY_ID_RTL8201E 0x00008200 2950#define TG3_PHY_ID_RTL8201E 0x00008200
2957#define TG3_PHY_ID_BCM57780 0x03625d90 2951#define TG3_PHY_ID_BCM57780 0x03625d90
2952#define TG3_PHY_ID_INVALID 0xffffffff
2953
2954#define TG3_PHY_ID_REV_MASK 0x0000000f
2955#define TG3_PHY_REV_BCM5401_B0 0x1
2956
2958#define TG3_PHY_OUI_MASK 0xfffffc00 2957#define TG3_PHY_OUI_MASK 0xfffffc00
2959#define TG3_PHY_OUI_1 0x00206000 2958#define TG3_PHY_OUI_1 0x00206000
2960#define TG3_PHY_OUI_2 0x0143bc00 2959#define TG3_PHY_OUI_2 0x0143bc00
2961#define TG3_PHY_OUI_3 0x03625c00 2960#define TG3_PHY_OUI_3 0x03625c00
2962 2961
2962 /* This macro assumes the passed PHY ID is
2963 * already masked with TG3_PHY_ID_MASK.
2964 */
2965#define TG3_KNOWN_PHY_ID(X) \
2966 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
2967 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
2968 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
2969 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
2970 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
2971 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
2972 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
2973 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
2974 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
2975 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002)
2976
2963 u32 led_ctrl; 2977 u32 led_ctrl;
2964 u32 phy_otp; 2978 u32 phy_otp;
2965 2979
@@ -2971,21 +2985,6 @@ struct tg3 {
2971 u32 pci_clock_ctrl; 2985 u32 pci_clock_ctrl;
2972 struct pci_dev *pdev_peer; 2986 struct pci_dev *pdev_peer;
2973 2987
2974 /* This macro assumes the passed PHY ID is already masked
2975 * with PHY_ID_MASK.
2976 */
2977#define KNOWN_PHY_ID(X) \
2978 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2979 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2980 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2981 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2982 (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
2983 (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
2984 (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
2985 (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
2986 (X) == PHY_ID_BCM5718C || (X) == PHY_ID_BCM5718S || \
2987 (X) == PHY_ID_BCM57765 || (X) == PHY_ID_BCM8002)
2988
2989 struct tg3_hw_stats *hw_stats; 2988 struct tg3_hw_stats *hw_stats;
2990 dma_addr_t stats_mapping; 2989 dma_addr_t stats_mapping;
2991 struct work_struct reset_task; 2990 struct work_struct reset_task;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 23:16:25 -0400