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authorDan Williams <dan.j.williams@intel.com>2007-02-13 11:13:04 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-17 10:04:53 -0500
commit4434c5c7fd61c6713de882a2272b66f32fe7cac3 (patch)
treef20c9c4eba18dd915f07185cee5ededf33e28c02
parentf80dff9da07d81da16e3b842118d47b9febf9c01 (diff)
[ARM] 4186/1: iop: remove cp6_enable/disable routines
This functionality is replaced by cp6_trap Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-iop13xx/irq.c19
-rw-r--r--arch/arm/mach-iop13xx/time.c10
-rw-r--r--arch/arm/mach-iop32x/irq.c4
-rw-r--r--arch/arm/mach-iop33x/irq.c12
-rw-r--r--arch/arm/plat-iop/time.c4
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h26
-rw-r--r--include/asm-arm/arch-iop13xx/irqs.h17
-rw-r--r--include/asm-arm/arch-iop13xx/system.h2
-rw-r--r--include/asm-arm/hardware/iop3xx.h27
9 files changed, 0 insertions, 121 deletions
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index 162b93214965..b2eb0b961031 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -161,65 +161,49 @@ static void write_intsize(u32 val)
161static void 161static void
162iop13xx_irq_mask0 (unsigned int irq) 162iop13xx_irq_mask0 (unsigned int irq)
163{ 163{
164 u32 cp_flags = iop13xx_cp6_save();
165 write_intctl_0(read_intctl_0() & ~(1 << (irq - 0))); 164 write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
166 iop13xx_cp6_restore(cp_flags);
167} 165}
168 166
169static void 167static void
170iop13xx_irq_mask1 (unsigned int irq) 168iop13xx_irq_mask1 (unsigned int irq)
171{ 169{
172 u32 cp_flags = iop13xx_cp6_save();
173 write_intctl_1(read_intctl_1() & ~(1 << (irq - 32))); 170 write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
174 iop13xx_cp6_restore(cp_flags);
175} 171}
176 172
177static void 173static void
178iop13xx_irq_mask2 (unsigned int irq) 174iop13xx_irq_mask2 (unsigned int irq)
179{ 175{
180 u32 cp_flags = iop13xx_cp6_save();
181 write_intctl_2(read_intctl_2() & ~(1 << (irq - 64))); 176 write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
182 iop13xx_cp6_restore(cp_flags);
183} 177}
184 178
185static void 179static void
186iop13xx_irq_mask3 (unsigned int irq) 180iop13xx_irq_mask3 (unsigned int irq)
187{ 181{
188 u32 cp_flags = iop13xx_cp6_save();
189 write_intctl_3(read_intctl_3() & ~(1 << (irq - 96))); 182 write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
190 iop13xx_cp6_restore(cp_flags);
191} 183}
192 184
193static void 185static void
194iop13xx_irq_unmask0(unsigned int irq) 186iop13xx_irq_unmask0(unsigned int irq)
195{ 187{
196 u32 cp_flags = iop13xx_cp6_save();
197 write_intctl_0(read_intctl_0() | (1 << (irq - 0))); 188 write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
198 iop13xx_cp6_restore(cp_flags);
199} 189}
200 190
201static void 191static void
202iop13xx_irq_unmask1(unsigned int irq) 192iop13xx_irq_unmask1(unsigned int irq)
203{ 193{
204 u32 cp_flags = iop13xx_cp6_save();
205 write_intctl_1(read_intctl_1() | (1 << (irq - 32))); 194 write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
206 iop13xx_cp6_restore(cp_flags);
207} 195}
208 196
209static void 197static void
210iop13xx_irq_unmask2(unsigned int irq) 198iop13xx_irq_unmask2(unsigned int irq)
211{ 199{
212 u32 cp_flags = iop13xx_cp6_save();
213 write_intctl_2(read_intctl_2() | (1 << (irq - 64))); 200 write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
214 iop13xx_cp6_restore(cp_flags);
215} 201}
216 202
217static void 203static void
218iop13xx_irq_unmask3(unsigned int irq) 204iop13xx_irq_unmask3(unsigned int irq)
219{ 205{
220 u32 cp_flags = iop13xx_cp6_save();
221 write_intctl_3(read_intctl_3() | (1 << (irq - 96))); 206 write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
222 iop13xx_cp6_restore(cp_flags);
223} 207}
224 208
225static struct irq_chip iop13xx_irqchip1 = { 209static struct irq_chip iop13xx_irqchip1 = {
@@ -256,7 +240,6 @@ void __init iop13xx_init_irq(void)
256{ 240{
257 unsigned int i; 241 unsigned int i;
258 242
259 u32 cp_flags = iop13xx_cp6_save();
260 iop_init_cp6_handler(); 243 iop_init_cp6_handler();
261 244
262 /* disable all interrupts */ 245 /* disable all interrupts */
@@ -288,6 +271,4 @@ void __init iop13xx_init_irq(void)
288 set_irq_handler(i, handle_level_irq); 271 set_irq_handler(i, handle_level_irq);
289 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 272 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
290 } 273 }
291
292 iop13xx_cp6_restore(cp_flags);
293} 274}
diff --git a/arch/arm/mach-iop13xx/time.c b/arch/arm/mach-iop13xx/time.c
index 8b21365f653f..fc9d9d9a8429 100644
--- a/arch/arm/mach-iop13xx/time.c
+++ b/arch/arm/mach-iop13xx/time.c
@@ -38,11 +38,8 @@ static inline u32 read_tcr1(void)
38unsigned long iop13xx_gettimeoffset(void) 38unsigned long iop13xx_gettimeoffset(void)
39{ 39{
40 unsigned long offset; 40 unsigned long offset;
41 u32 cp_flags;
42 41
43 cp_flags = iop13xx_cp6_save();
44 offset = next_jiffy_time - read_tcr1(); 42 offset = next_jiffy_time - read_tcr1();
45 iop13xx_cp6_restore(cp_flags);
46 43
47 return offset / ticks_per_usec; 44 return offset / ticks_per_usec;
48} 45}
@@ -50,8 +47,6 @@ unsigned long iop13xx_gettimeoffset(void)
50static irqreturn_t 47static irqreturn_t
51iop13xx_timer_interrupt(int irq, void *dev_id) 48iop13xx_timer_interrupt(int irq, void *dev_id)
52{ 49{
53 u32 cp_flags = iop13xx_cp6_save();
54
55 write_seqlock(&xtime_lock); 50 write_seqlock(&xtime_lock);
56 51
57 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1)); 52 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
@@ -64,8 +59,6 @@ iop13xx_timer_interrupt(int irq, void *dev_id)
64 59
65 write_sequnlock(&xtime_lock); 60 write_sequnlock(&xtime_lock);
66 61
67 iop13xx_cp6_restore(cp_flags);
68
69 return IRQ_HANDLED; 62 return IRQ_HANDLED;
70} 63}
71 64
@@ -78,7 +71,6 @@ static struct irqaction iop13xx_timer_irq = {
78void __init iop13xx_init_time(unsigned long tick_rate) 71void __init iop13xx_init_time(unsigned long tick_rate)
79{ 72{
80 u32 timer_ctl; 73 u32 timer_ctl;
81 u32 cp_flags;
82 74
83 ticks_per_jiffy = (tick_rate + HZ/2) / HZ; 75 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
84 ticks_per_usec = tick_rate / 1000000; 76 ticks_per_usec = tick_rate / 1000000;
@@ -91,12 +83,10 @@ void __init iop13xx_init_time(unsigned long tick_rate)
91 * We use timer 0 for our timer interrupt, and timer 1 as 83 * We use timer 0 for our timer interrupt, and timer 1 as
92 * monotonic counter for tracking missed jiffies. 84 * monotonic counter for tracking missed jiffies.
93 */ 85 */
94 cp_flags = iop13xx_cp6_save();
95 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1)); 86 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
96 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl)); 87 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
97 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff)); 88 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
98 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl)); 89 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
99 iop13xx_cp6_restore(cp_flags);
100 90
101 setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq); 91 setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
102} 92}
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 8b0ac5590ae4..82598dc18d80 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -23,16 +23,12 @@ static u32 iop32x_mask;
23 23
24static inline void intctl_write(u32 val) 24static inline void intctl_write(u32 val)
25{ 25{
26 iop3xx_cp6_enable();
27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); 26 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
28 iop3xx_cp6_disable();
29} 27}
30 28
31static inline void intstr_write(u32 val) 29static inline void intstr_write(u32 val)
32{ 30{
33 iop3xx_cp6_enable();
34 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); 31 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
35 iop3xx_cp6_disable();
36} 32}
37 33
38static void 34static void
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index effbe6b782d0..c65ea78a2427 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -24,44 +24,32 @@ static u32 iop33x_mask1;
24 24
25static inline void intctl0_write(u32 val) 25static inline void intctl0_write(u32 val)
26{ 26{
27 iop3xx_cp6_enable();
28 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); 27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
29 iop3xx_cp6_disable();
30} 28}
31 29
32static inline void intctl1_write(u32 val) 30static inline void intctl1_write(u32 val)
33{ 31{
34 iop3xx_cp6_enable();
35 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); 32 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
36 iop3xx_cp6_disable();
37} 33}
38 34
39static inline void intstr0_write(u32 val) 35static inline void intstr0_write(u32 val)
40{ 36{
41 iop3xx_cp6_enable();
42 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); 37 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
43 iop3xx_cp6_disable();
44} 38}
45 39
46static inline void intstr1_write(u32 val) 40static inline void intstr1_write(u32 val)
47{ 41{
48 iop3xx_cp6_enable();
49 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); 42 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
50 iop3xx_cp6_disable();
51} 43}
52 44
53static inline void intbase_write(u32 val) 45static inline void intbase_write(u32 val)
54{ 46{
55 iop3xx_cp6_enable();
56 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); 47 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
57 iop3xx_cp6_disable();
58} 48}
59 49
60static inline void intsize_write(u32 val) 50static inline void intsize_write(u32 val)
61{ 51{
62 iop3xx_cp6_enable();
63 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); 52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
64 iop3xx_cp6_disable();
65} 53}
66 54
67static void 55static void
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index f530abdaa7a1..0d53b813cbb4 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -51,9 +51,7 @@ iop3xx_timer_interrupt(int irq, void *dev_id)
51{ 51{
52 write_seqlock(&xtime_lock); 52 write_seqlock(&xtime_lock);
53 53
54 iop3xx_cp6_enable();
55 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1)); 54 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
56 iop3xx_cp6_disable();
57 55
58 while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1) 56 while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
59 >= ticks_per_jiffy) { 57 >= ticks_per_jiffy) {
@@ -87,12 +85,10 @@ void __init iop3xx_init_time(unsigned long tick_rate)
87 * We use timer 0 for our timer interrupt, and timer 1 as 85 * We use timer 0 for our timer interrupt, and timer 1 as
88 * monotonic counter for tracking missed jiffies. 86 * monotonic counter for tracking missed jiffies.
89 */ 87 */
90 iop3xx_cp6_enable();
91 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1)); 88 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
92 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl)); 89 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
93 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff)); 90 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
94 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl)); 91 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
95 iop3xx_cp6_disable();
96 92
97 setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq); 93 setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
98} 94}
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index a88522a0ff8e..e7430593d6fb 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -12,32 +12,6 @@ void iop13xx_init_irq(void);
12void iop13xx_init_time(unsigned long tickrate); 12void iop13xx_init_time(unsigned long tickrate);
13unsigned long iop13xx_gettimeoffset(void); 13unsigned long iop13xx_gettimeoffset(void);
14 14
15/* handle cp6 access
16 * to do: handle access in entry-armv5.S and unify with
17 * the iop3xx implementation
18 * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
19 * when interrupts are enabled
20 */
21static inline unsigned long iop13xx_cp6_save(void)
22{
23 u32 temp, cp_flags;
24
25 asm volatile (
26 "mrc p15, 0, %1, c15, c1, 0\n\t"
27 "orr %0, %1, #(1 << 6)\n\t"
28 "mcr p15, 0, %0, c15, c1, 0\n\t"
29 : "=r" (temp), "=r"(cp_flags));
30
31 return cp_flags;
32}
33
34static inline void iop13xx_cp6_restore(unsigned long cp_flags)
35{
36 asm volatile (
37 "mcr p15, 0, %0, c15, c1, 0\n\t"
38 : : "r" (cp_flags) );
39}
40
41/* CPUID CP6 R0 Page 0 */ 15/* CPUID CP6 R0 Page 0 */
42static inline int iop13xx_cpu_id(void) 16static inline int iop13xx_cpu_id(void)
43{ 17{
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h
index 442e35a40359..5c6fac2a4004 100644
--- a/include/asm-arm/arch-iop13xx/irqs.h
+++ b/include/asm-arm/arch-iop13xx/irqs.h
@@ -3,8 +3,6 @@
3 3
4#ifndef __ASSEMBLER__ 4#ifndef __ASSEMBLER__
5#include <linux/types.h> 5#include <linux/types.h>
6#include <asm/system.h> /* local_irq_save */
7#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
8 6
9/* INTPND0 CP6 R0 Page 3 7/* INTPND0 CP6 R0 Page 3
10 */ 8 */
@@ -41,21 +39,6 @@ static inline u32 read_intpnd_3(void)
41 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); 39 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
42 return val; 40 return val;
43} 41}
44
45static inline void
46iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
47{
48 local_irq_save(*irq_flags);
49 *cp_flags = iop13xx_cp6_save();
50}
51
52static inline void
53iop13xx_cp6_irq_restore(unsigned long *cp_flags,
54 unsigned long *irq_flags)
55{
56 iop13xx_cp6_restore(*cp_flags);
57 local_irq_restore(*irq_flags);
58}
59#endif 42#endif
60 43
61#define INTBASE 0 44#define INTBASE 0
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
index ee3a62530af2..127827058e1f 100644
--- a/include/asm-arm/arch-iop13xx/system.h
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -48,12 +48,10 @@ static inline void arch_reset(char mode)
48 /* 48 /*
49 * Reset the internal bus (warning both cores are reset) 49 * Reset the internal bus (warning both cores are reset)
50 */ 50 */
51 u32 cp_flags = iop13xx_cp6_save();
52 write_wdtcr(IOP13XX_WDTCR_EN_ARM); 51 write_wdtcr(IOP13XX_WDTCR_EN_ARM);
53 write_wdtcr(IOP13XX_WDTCR_EN); 52 write_wdtcr(IOP13XX_WDTCR_EN);
54 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); 53 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
55 write_wdtcr(0x1000); 54 write_wdtcr(0x1000);
56 iop13xx_cp6_restore(cp_flags);
57 55
58 for(;;); 56 for(;;);
59} 57}
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index c91b546e20ef..47fcbf6f52d3 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -283,33 +283,6 @@ void iop_init_cp6_handler(void);
283extern struct platform_device iop3xx_i2c0_device; 283extern struct platform_device iop3xx_i2c0_device;
284extern struct platform_device iop3xx_i2c1_device; 284extern struct platform_device iop3xx_i2c1_device;
285 285
286extern inline void iop3xx_cp6_enable(void)
287{
288 u32 temp;
289
290 asm volatile (
291 "mrc p15, 0, %0, c15, c1, 0\n\t"
292 "orr %0, %0, #(1 << 6)\n\t"
293 "mcr p15, 0, %0, c15, c1, 0\n\t"
294 "mrc p15, 0, %0, c15, c1, 0\n\t"
295 "mov %0, %0\n\t"
296 "sub pc, pc, #4\n\t"
297 : "=r" (temp) );
298}
299
300extern inline void iop3xx_cp6_disable(void)
301{
302 u32 temp;
303
304 asm volatile (
305 "mrc p15, 0, %0, c15, c1, 0\n\t"
306 "bic %0, %0, #(1 << 6)\n\t"
307 "mcr p15, 0, %0, c15, c1, 0\n\t"
308 "mrc p15, 0, %0, c15, c1, 0\n\t"
309 "mov %0, %0\n\t"
310 "sub pc, pc, #4\n\t"
311 : "=r" (temp) );
312}
313#endif 286#endif
314 287
315 288