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authorRuss Anderson <rja@sgi.com>2006-10-25 15:18:27 -0400
committerTony Luck <tony.luck@intel.com>2006-12-07 14:02:38 -0500
commit323cbb09917024cab522bc7ce5c343659cbe8818 (patch)
treef8edcf9abe1236894fa66bf809daddf001a70c4e
parentc69577711a8fd232e6b309c3e99f9a8f96f63082 (diff)
[IA64] Add dp bit to cache and bus check structs
Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's Manual" (January 2006) adds a dp bit to the cache_check and bus_check fields (pages 2:401-2:404). This patch gets the structs back in sync with the spec. Signed-off-by: Russ Anderson (rja@sgi.com) Signed-off-by: Tony Luck <tony.luck@intel.com>
-rw-r--r--include/asm-ia64/pal.h8
1 files changed, 5 insertions, 3 deletions
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 4283ddcc25fb..b6d4f6f0c3c8 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -487,10 +487,12 @@ typedef struct pal_cache_check_info_s {
487 * error occurred 487 * error occurred
488 */ 488 */
489 wiv : 1, /* Way field valid */ 489 wiv : 1, /* Way field valid */
490 reserved2 : 10, 490 reserved2 : 1,
491 dp : 1, /* Data poisoned on MBE */
492 reserved3 : 8,
491 493
492 index : 20, /* Cache line index */ 494 index : 20, /* Cache line index */
493 reserved3 : 2, 495 reserved4 : 2,
494 496
495 is : 1, /* instruction set (1 == ia32) */ 497 is : 1, /* instruction set (1 == ia32) */
496 iv : 1, /* instruction set field valid */ 498 iv : 1, /* instruction set field valid */
@@ -557,7 +559,7 @@ typedef struct pal_bus_check_info_s {
557 type : 8, /* Bus xaction type*/ 559 type : 8, /* Bus xaction type*/
558 sev : 5, /* Bus error severity*/ 560 sev : 5, /* Bus error severity*/
559 hier : 2, /* Bus hierarchy level */ 561 hier : 2, /* Bus hierarchy level */
560 reserved1 : 1, 562 dp : 1, /* Data poisoned on MBE */
561 bsi : 8, /* Bus error status 563 bsi : 8, /* Bus error status
562 * info 564 * info
563 */ 565 */