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authorStephen Hemminger <shemminger@osdl.org>2005-07-22 19:26:07 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-07-31 00:40:53 -0400
commit2c66851460c9438823e39b76887376d1511fb67c (patch)
tree5a1028f8abb4ef03772f9f09c7e77cc7c110ca2b
parent382317138b3ade02c9c319531ab0619e95dbc672 (diff)
[PATCH] skge: whitespace fixes
Minor whitespace cleanups. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
-rw-r--r--drivers/net/skge.c6
-rw-r--r--drivers/net/skge.h20
2 files changed, 13 insertions, 13 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 0857be8f99f2..6b04b89cbb4f 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -248,7 +248,7 @@ static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
248 } else { 248 } else {
249 u32 setting; 249 u32 setting;
250 250
251 switch(ecmd->speed) { 251 switch (ecmd->speed) {
252 case SPEED_1000: 252 case SPEED_1000:
253 if (ecmd->duplex == DUPLEX_FULL) 253 if (ecmd->duplex == DUPLEX_FULL)
254 setting = SUPPORTED_1000baseT_Full; 254 setting = SUPPORTED_1000baseT_Full;
@@ -1026,7 +1026,7 @@ static void bcom_check_link(struct skge_hw *hw, int port)
1026 } 1026 }
1027 1027
1028 /* Check Duplex mismatch */ 1028 /* Check Duplex mismatch */
1029 switch(aux & PHY_B_AS_AN_RES_MSK) { 1029 switch (aux & PHY_B_AS_AN_RES_MSK) {
1030 case PHY_B_RES_1000FD: 1030 case PHY_B_RES_1000FD:
1031 skge->duplex = DUPLEX_FULL; 1031 skge->duplex = DUPLEX_FULL;
1032 break; 1032 break;
@@ -1097,7 +1097,7 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo)
1097 r |= XM_MMU_NO_PRE; 1097 r |= XM_MMU_NO_PRE;
1098 xm_write16(hw, port, XM_MMU_CMD,r); 1098 xm_write16(hw, port, XM_MMU_CMD,r);
1099 1099
1100 switch(id1) { 1100 switch (id1) {
1101 case PHY_BCOM_ID1_C0: 1101 case PHY_BCOM_ID1_C0:
1102 /* 1102 /*
1103 * Workaround BCOM Errata for the C0 type. 1103 * Workaround BCOM Errata for the C0 type.
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index fced3d2bc072..2086809f4b03 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -1509,7 +1509,7 @@ enum {
1509 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ 1509 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1510}; 1510};
1511 1511
1512#define PHY_M_LED_PULS_DUR(x) ( ((x)<<12) & PHY_M_LEDC_PULS_MSK) 1512#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1513 1513
1514enum { 1514enum {
1515 PULS_NO_STR = 0,/* no pulse stretching */ 1515 PULS_NO_STR = 0,/* no pulse stretching */
@@ -1522,7 +1522,7 @@ enum {
1522 PULS_1300MS = 7,/* 1.3 s to 2.7 s */ 1522 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1523}; 1523};
1524 1524
1525#define PHY_M_LED_BLINK_RT(x) ( ((x)<<8) & PHY_M_LEDC_BL_R_MSK) 1525#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1526 1526
1527enum { 1527enum {
1528 BLINK_42MS = 0,/* 42 ms */ 1528 BLINK_42MS = 0,/* 42 ms */
@@ -1602,9 +1602,9 @@ enum {
1602 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ 1602 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1603}; 1603};
1604 1604
1605#define PHY_M_FELP_LED2_CTRL(x) ( ((x)<<8) & PHY_M_FELP_LED2_MSK) 1605#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1606#define PHY_M_FELP_LED1_CTRL(x) ( ((x)<<4) & PHY_M_FELP_LED1_MSK) 1606#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1607#define PHY_M_FELP_LED0_CTRL(x) ( ((x)<<0) & PHY_M_FELP_LED0_MSK) 1607#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1608 1608
1609enum { 1609enum {
1610 LED_PAR_CTRL_COLX = 0x00, 1610 LED_PAR_CTRL_COLX = 0x00,
@@ -1640,7 +1640,7 @@ enum {
1640 PHY_M_MAC_MD_COPPER = 5,/* Copper only */ 1640 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1641 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ 1641 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1642}; 1642};
1643#define PHY_M_MAC_MODE_SEL(x) ( ((x)<<7) & PHY_M_MAC_MD_MSK) 1643#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1644 1644
1645/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1645/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1646enum { 1646enum {
@@ -1650,10 +1650,10 @@ enum {
1650 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1650 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1651}; 1651};
1652 1652
1653#define PHY_M_LEDC_LOS_CTRL(x) ( ((x)<<12) & PHY_M_LEDC_LOS_MSK) 1653#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1654#define PHY_M_LEDC_INIT_CTRL(x) ( ((x)<<8) & PHY_M_LEDC_INIT_MSK) 1654#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1655#define PHY_M_LEDC_STA1_CTRL(x) ( ((x)<<4) & PHY_M_LEDC_STA1_MSK) 1655#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1656#define PHY_M_LEDC_STA0_CTRL(x) ( ((x)<<0) & PHY_M_LEDC_STA0_MSK) 1656#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1657 1657
1658/* GMAC registers */ 1658/* GMAC registers */
1659/* Port Registers */ 1659/* Port Registers */