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authorJesse Barnes <jbarnes@virtuousgeek.org>2009-07-16 16:01:02 -0400
committerEric Anholt <eric@anholt.net>2009-07-16 16:02:40 -0400
commit2a2430f4542467502d39660bfd66b0004fd8d6a9 (patch)
tree8ff5a492835af7460bc0dd713e7b84b6dacdcd86
parent390c4dd448b1a5f04ea497c20f5ff664f8eeed01 (diff)
drm/i915: correct self-refresh calculation in "everything off" case
If no planes are enabled, the self-refresh calculation may end up doing a divide by zero. This patch should prevent that by making sure at least one of the CRTCs had a valid hdisplay value. Reported-by: Eric Anholt <eric@anholt.net> Tested-by: Eric Anholt <eric@anholt.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
-rw-r--r--drivers/gpu/drm/i915/intel_display.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 890f7108e723..a58bfadabd6f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1906,7 +1906,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
1906 cwm = 2; 1906 cwm = 2;
1907 1907
1908 /* Calc sr entries for one plane configs */ 1908 /* Calc sr entries for one plane configs */
1909 if (!planea_clock || !planeb_clock) { 1909 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
1910 /* self-refresh has much higher latency */ 1910 /* self-refresh has much higher latency */
1911 const static int sr_latency_ns = 6000; 1911 const static int sr_latency_ns = 6000;
1912 1912
@@ -1921,6 +1921,8 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
1921 srwm = total_size - sr_entries; 1921 srwm = total_size - sr_entries;
1922 if (srwm < 0) 1922 if (srwm < 0)
1923 srwm = 1; 1923 srwm = 1;
1924 if (IS_I9XX(dev))
1925 I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
1924 } 1926 }
1925 1927
1926 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1928 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
@@ -1935,8 +1937,6 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
1935 1937
1936 I915_WRITE(FW_BLC, fwater_lo); 1938 I915_WRITE(FW_BLC, fwater_lo);
1937 I915_WRITE(FW_BLC2, fwater_hi); 1939 I915_WRITE(FW_BLC2, fwater_hi);
1938 if (IS_I9XX(dev))
1939 I915_WRITE(FW_BLC_SELF, (srwm & 0x3f));
1940} 1940}
1941 1941
1942static void i830_update_wm(struct drm_device *dev, int planea_clock, 1942static void i830_update_wm(struct drm_device *dev, int planea_clock,