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authorZhenyu Wang <zhenyu.z.wang@intel.com>2008-06-19 00:17:58 -0400
committerDave Airlie <airlied@redhat.com>2008-06-19 00:17:58 -0400
commit25ce77abf8be3a96b3673e46722a9bd05f149584 (patch)
tree812ce16f60917030f5b71c9126c8e7e0dfa4862a
parent598d14482380312939a3e3a4ae0657eb6b50a532 (diff)
[AGP] intel_agp: Add support for Intel 4 series chipsets
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/char/agp/intel-agp.c83
1 files changed, 73 insertions, 10 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index e73f8f013283..b52988df2979 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -34,6 +34,12 @@
34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
35#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40 35#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
36#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42 36#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
37#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
38#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
39#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
40#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
41#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
42#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
37 43
38/* cover 915 and 945 variants */ 44/* cover 915 and 945 variants */
39#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 45#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -55,6 +61,10 @@
55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ 61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) 62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
57 63
64#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
65 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
67
58extern int agp_memory_reserved; 68extern int agp_memory_reserved;
59 69
60 70
@@ -80,8 +90,13 @@ extern int agp_memory_reserved;
80#define I915_PTEADDR 0x1C 90#define I915_PTEADDR 0x1C
81#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 91#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
82#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 92#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
83#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) 93#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
84#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) 94#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
95#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
96#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
97#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
98#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
99
85#define I915_IFPADDR 0x60 100#define I915_IFPADDR 0x60
86 101
87/* Intel 965G registers */ 102/* Intel 965G registers */
@@ -506,6 +521,10 @@ static void intel_i830_init_gtt_entries(void)
506 size = 512; 521 size = 512;
507 } 522 }
508 size += 4; 523 size += 4;
524 } else if (IS_G4X) {
525 /* On 4 series hardware, GTT stolen is separate from graphics
526 * stolen, ignore it in stolen gtt entries counting */
527 size = 0;
509 } else { 528 } else {
510 /* On previous hardware, the GTT size was just what was 529 /* On previous hardware, the GTT size was just what was
511 * required to map the aperture. 530 * required to map the aperture.
@@ -554,30 +573,54 @@ static void intel_i830_init_gtt_entries(void)
554 break; 573 break;
555 case I915_GMCH_GMS_STOLEN_48M: 574 case I915_GMCH_GMS_STOLEN_48M:
556 /* Check it's really I915G */ 575 /* Check it's really I915G */
557 if (IS_I915 || IS_I965 || IS_G33) 576 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
558 gtt_entries = MB(48) - KB(size); 577 gtt_entries = MB(48) - KB(size);
559 else 578 else
560 gtt_entries = 0; 579 gtt_entries = 0;
561 break; 580 break;
562 case I915_GMCH_GMS_STOLEN_64M: 581 case I915_GMCH_GMS_STOLEN_64M:
563 /* Check it's really I915G */ 582 /* Check it's really I915G */
564 if (IS_I915 || IS_I965 || IS_G33) 583 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
565 gtt_entries = MB(64) - KB(size); 584 gtt_entries = MB(64) - KB(size);
566 else 585 else
567 gtt_entries = 0; 586 gtt_entries = 0;
568 break; 587 break;
569 case G33_GMCH_GMS_STOLEN_128M: 588 case G33_GMCH_GMS_STOLEN_128M:
570 if (IS_G33 || IS_I965) 589 if (IS_G33 || IS_I965 || IS_G4X)
571 gtt_entries = MB(128) - KB(size); 590 gtt_entries = MB(128) - KB(size);
572 else 591 else
573 gtt_entries = 0; 592 gtt_entries = 0;
574 break; 593 break;
575 case G33_GMCH_GMS_STOLEN_256M: 594 case G33_GMCH_GMS_STOLEN_256M:
576 if (IS_G33 || IS_I965) 595 if (IS_G33 || IS_I965 || IS_G4X)
577 gtt_entries = MB(256) - KB(size); 596 gtt_entries = MB(256) - KB(size);
578 else 597 else
579 gtt_entries = 0; 598 gtt_entries = 0;
580 break; 599 break;
600 case INTEL_GMCH_GMS_STOLEN_96M:
601 if (IS_I965 || IS_G4X)
602 gtt_entries = MB(96) - KB(size);
603 else
604 gtt_entries = 0;
605 break;
606 case INTEL_GMCH_GMS_STOLEN_160M:
607 if (IS_I965 || IS_G4X)
608 gtt_entries = MB(160) - KB(size);
609 else
610 gtt_entries = 0;
611 break;
612 case INTEL_GMCH_GMS_STOLEN_224M:
613 if (IS_I965 || IS_G4X)
614 gtt_entries = MB(224) - KB(size);
615 else
616 gtt_entries = 0;
617 break;
618 case INTEL_GMCH_GMS_STOLEN_352M:
619 if (IS_I965 || IS_G4X)
620 gtt_entries = MB(352) - KB(size);
621 else
622 gtt_entries = 0;
623 break;
581 default: 624 default:
582 gtt_entries = 0; 625 gtt_entries = 0;
583 break; 626 break;
@@ -1136,6 +1179,20 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1136 return addr | bridge->driver->masks[type].mask; 1179 return addr | bridge->driver->masks[type].mask;
1137} 1180}
1138 1181
1182static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1183{
1184 switch (agp_bridge->dev->device) {
1185 case PCI_DEVICE_ID_INTEL_IGD_HB:
1186 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1187 case PCI_DEVICE_ID_INTEL_Q45_HB:
1188 case PCI_DEVICE_ID_INTEL_G45_HB:
1189 *gtt_offset = *gtt_size = MB(2);
1190 break;
1191 default:
1192 *gtt_offset = *gtt_size = KB(512);
1193 }
1194}
1195
1139/* The intel i965 automatically initializes the agp aperture during POST. 1196/* The intel i965 automatically initializes the agp aperture during POST.
1140 * Use the memory already set aside for in the GTT. 1197 * Use the memory already set aside for in the GTT.
1141 */ 1198 */
@@ -1156,10 +1213,7 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1156 1213
1157 temp &= 0xfff00000; 1214 temp &= 0xfff00000;
1158 1215
1159 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB) 1216 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1160 gtt_offset = gtt_size = MB(2);
1161 else
1162 gtt_offset = gtt_size = KB(512);
1163 1217
1164 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); 1218 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1165 1219
@@ -2065,6 +2119,12 @@ static const struct intel_driver_description {
2065 NULL, &intel_g33_driver }, 2119 NULL, &intel_g33_driver },
2066 { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0, 2120 { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2067 "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, 2121 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2122 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2123 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2124 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2125 "Q45/Q43", NULL, &intel_i965_driver },
2126 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2127 "G45/G43", NULL, &intel_i965_driver },
2068 { 0, 0, 0, NULL, NULL, NULL } 2128 { 0, 0, 0, NULL, NULL, NULL }
2069}; 2129};
2070 2130
@@ -2256,6 +2316,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
2256 ID(PCI_DEVICE_ID_INTEL_Q35_HB), 2316 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2257 ID(PCI_DEVICE_ID_INTEL_Q33_HB), 2317 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2258 ID(PCI_DEVICE_ID_INTEL_IGD_HB), 2318 ID(PCI_DEVICE_ID_INTEL_IGD_HB),
2319 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2320 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2321 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2259 { } 2322 { }
2260}; 2323};
2261 2324