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authorjoe@perches.com <joe@perches.com>2007-12-17 14:30:15 -0500
committerPaul Mackerras <paulus@samba.org>2007-12-20 00:17:49 -0500
commitf3d711aa02791ca5efa33112994063c9aeaf39ee (patch)
treee395d391543df75ab5146a83d704f1e563a39781
parentc90e10962516c36edf5d9ea756cf11c7853084c5 (diff)
[POWERPC] include/asm-ppc/: Spelling fixes
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--include/asm-ppc/8xx_immap.h2
-rw-r--r--include/asm-ppc/commproc.h2
-rw-r--r--include/asm-ppc/reg_booke.h2
3 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h
index 1311cefdfd30..4b0e15206006 100644
--- a/include/asm-ppc/8xx_immap.h
+++ b/include/asm-ppc/8xx_immap.h
@@ -123,7 +123,7 @@ typedef struct mem_ctlr {
123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ 123#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ 124#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
125#define OR_BI 0x00000100 /* Burst inhibit */ 125#define OR_BI 0x00000100 /* Burst inhibit */
126#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */ 126#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */
127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ 127#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ 128#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ 129#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/commproc.h
index 397248705e0e..462abb185f07 100644
--- a/include/asm-ppc/commproc.h
+++ b/include/asm-ppc/commproc.h
@@ -681,7 +681,7 @@ typedef struct risc_timer_pram {
681#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 681#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
682#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 682#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
683#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 683#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
684#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 684#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */
685#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 685#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
686#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 686#define CICR_IEN ((uint)0x00000080) /* Int. enable */
687#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 687#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 82948ed2744a..4cad45a055dd 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -283,7 +283,7 @@
283#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ 283#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
284#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ 284#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
285#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ 285#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
286#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ 286#define ESR_PPR 0x04000000 /* Program Exception - Privileged */
287#define ESR_PTR 0x02000000 /* Program Exception - Trap */ 287#define ESR_PTR 0x02000000 /* Program Exception - Trap */
288#define ESR_FP 0x01000000 /* Floating Point Operation */ 288#define ESR_FP 0x01000000 /* Floating Point Operation */
289#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ 289#define ESR_DST 0x00800000 /* Storage Exception - Data miss */