diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2009-09-22 10:48:37 -0400 |
---|---|---|
committer | Borislav Petkov <borislav.petkov@amd.com> | 2009-10-07 10:51:15 -0400 |
commit | 66216a7a15e75d517dddd0ac6514924b15071e4c (patch) | |
tree | 69247ab8326bbe69f4b6e875e2add0f884d386cc | |
parent | 9d858bb10a9907bbbaffbb4a80a31718d548868c (diff) |
amd64_edac: fix DRAM base and limit extraction
On Fam10h and above, F1x[1, 0][7C:40] are DRAM Base/Limit registers
which specify the destination node of a DRAM address. Those address
boundaries are being extracted into ->dram_base[] and ->dram_limit[].
Correct the extraction masks to match the respective address bits.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
-rw-r--r-- | drivers/edac/amd64_edac.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 85c308b1fed7..4f4ac82382f7 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c | |||
@@ -1368,8 +1368,8 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |||
1368 | 1368 | ||
1369 | pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; | 1369 | pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; |
1370 | 1370 | ||
1371 | pvt->dram_base[dram] = (((((u64) high_base & 0x000000FF) << 32) | | 1371 | pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) | |
1372 | ((u64) low_base & 0xFFFF0000))) << 8; | 1372 | (((u64)low_base & 0xFFFF0000) << 24); |
1373 | 1373 | ||
1374 | low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); | 1374 | low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); |
1375 | high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); | 1375 | high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); |
@@ -1390,9 +1390,9 @@ static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram) | |||
1390 | * Extract address values and form a LIMIT address. Limit is the HIGHEST | 1390 | * Extract address values and form a LIMIT address. Limit is the HIGHEST |
1391 | * memory location of the region, so low 24 bits need to be all ones. | 1391 | * memory location of the region, so low 24 bits need to be all ones. |
1392 | */ | 1392 | */ |
1393 | low_limit |= 0x0000FFFF; | 1393 | pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) | |
1394 | pvt->dram_limit[dram] = | 1394 | (((u64) low_limit & 0xFFFF0000) << 24) | |
1395 | ((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF); | 1395 | 0x00FFFFFF; |
1396 | } | 1396 | } |
1397 | 1397 | ||
1398 | static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) | 1398 | static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) |