diff options
author | Paul Mackerras <paulus@samba.org> | 2005-10-27 08:44:39 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2005-10-27 08:44:39 -0400 |
commit | 6316222ea050d469c3155881d9dee2c7671d9fef (patch) | |
tree | 2a075cbdab11e10efc868a31e378dffae90f06da | |
parent | 80579e1f4a6b5f5dec92faa6c3e0645961c99091 (diff) |
powerpc: Introduce toreal/fromreal assembly macros
On 32-bit platforms, these convert from kernel virtual addresses
to real (physical addresses), like tophys/tovirt but they use
the same register for the source and destination. On 64-bit
platforms, they do nothing because the hardware ignores the top
two bits of the address in real mode.
These new macros are used in fpu.S now.
Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r-- | arch/powerpc/kernel/fpu.S | 8 | ||||
-rw-r--r-- | include/asm-powerpc/ppc_asm.h | 29 |
2 files changed, 19 insertions, 18 deletions
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index 51fd78da25b7..4d6001fa1cf2 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S | |||
@@ -40,17 +40,17 @@ _GLOBAL(load_up_fpu) | |||
40 | */ | 40 | */ |
41 | #ifndef CONFIG_SMP | 41 | #ifndef CONFIG_SMP |
42 | LOADBASE(r3, last_task_used_math) | 42 | LOADBASE(r3, last_task_used_math) |
43 | tophys(r3,r3) | 43 | toreal(r3) |
44 | LDL r4,OFF(last_task_used_math)(r3) | 44 | LDL r4,OFF(last_task_used_math)(r3) |
45 | CMPI 0,r4,0 | 45 | CMPI 0,r4,0 |
46 | beq 1f | 46 | beq 1f |
47 | tophys(r4,r4) | 47 | toreal(r4) |
48 | addi r4,r4,THREAD /* want last_task_used_math->thread */ | 48 | addi r4,r4,THREAD /* want last_task_used_math->thread */ |
49 | SAVE_32FPRS(0, r4) | 49 | SAVE_32FPRS(0, r4) |
50 | mffs fr0 | 50 | mffs fr0 |
51 | stfd fr0,THREAD_FPSCR(r4) | 51 | stfd fr0,THREAD_FPSCR(r4) |
52 | LDL r5,PT_REGS(r4) | 52 | LDL r5,PT_REGS(r4) |
53 | tophys(r5,r5) | 53 | toreal(r5) |
54 | LDL r4,_MSR-STACK_FRAME_OVERHEAD(r5) | 54 | LDL r4,_MSR-STACK_FRAME_OVERHEAD(r5) |
55 | li r10,MSR_FP|MSR_FE0|MSR_FE1 | 55 | li r10,MSR_FP|MSR_FE0|MSR_FE1 |
56 | andc r4,r4,r10 /* disable FP for previous task */ | 56 | andc r4,r4,r10 /* disable FP for previous task */ |
@@ -76,7 +76,7 @@ _GLOBAL(load_up_fpu) | |||
76 | REST_32FPRS(0, r5) | 76 | REST_32FPRS(0, r5) |
77 | #ifndef CONFIG_SMP | 77 | #ifndef CONFIG_SMP |
78 | subi r4,r5,THREAD | 78 | subi r4,r5,THREAD |
79 | tovirt(r4,r4) | 79 | fromreal(r4) |
80 | STL r4,OFF(last_task_used_math)(r3) | 80 | STL r4,OFF(last_task_used_math)(r3) |
81 | #endif /* CONFIG_SMP */ | 81 | #endif /* CONFIG_SMP */ |
82 | /* restore registers and return */ | 82 | /* restore registers and return */ |
diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h index f8ad5df6ebef..470d7400ac59 100644 --- a/include/asm-powerpc/ppc_asm.h +++ b/include/asm-powerpc/ppc_asm.h | |||
@@ -154,7 +154,7 @@ n: | |||
154 | * loads the address of 'name' into 'rn' | 154 | * loads the address of 'name' into 'rn' |
155 | * | 155 | * |
156 | * LOADBASE( rn, name ) | 156 | * LOADBASE( rn, name ) |
157 | * loads the address (less the low 16 bits) of 'name' into 'rn' | 157 | * loads the address (possibly without the low 16 bits) of 'name' into 'rn' |
158 | * suitable for base+disp addressing | 158 | * suitable for base+disp addressing |
159 | */ | 159 | */ |
160 | #ifdef __powerpc64__ | 160 | #ifdef __powerpc64__ |
@@ -166,10 +166,7 @@ n: | |||
166 | ori rn,rn,name##@l | 166 | ori rn,rn,name##@l |
167 | 167 | ||
168 | #define LOADBASE(rn,name) \ | 168 | #define LOADBASE(rn,name) \ |
169 | .section .toc,"aw"; \ | 169 | ld rn,name@got(r2) |
170 | 1: .tc name[TC],name; \ | ||
171 | .previous; \ | ||
172 | ld rn,1b@toc(r2) | ||
173 | 170 | ||
174 | #define OFF(name) 0 | 171 | #define OFF(name) 0 |
175 | 172 | ||
@@ -278,6 +275,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) | |||
278 | 275 | ||
279 | 276 | ||
280 | #if defined(CONFIG_BOOKE) | 277 | #if defined(CONFIG_BOOKE) |
278 | #define toreal(rd) | ||
279 | #define fromreal(rd) | ||
280 | |||
281 | #define tophys(rd,rs) \ | 281 | #define tophys(rd,rs) \ |
282 | addis rd,rs,0 | 282 | addis rd,rs,0 |
283 | 283 | ||
@@ -285,23 +285,24 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) | |||
285 | addis rd,rs,0 | 285 | addis rd,rs,0 |
286 | 286 | ||
287 | #elif defined(CONFIG_PPC64) | 287 | #elif defined(CONFIG_PPC64) |
288 | /* PPPBBB - DRENG If KERNELBASE is always 0xC0..., | 288 | #define toreal(rd) /* we can access c000... in real mode */ |
289 | * Then we can easily do this with one asm insn. -Peter | 289 | #define fromreal(rd) |
290 | */ | 290 | |
291 | #define tophys(rd,rs) \ | 291 | #define tophys(rd,rs) \ |
292 | lis rd,((KERNELBASE>>48)&0xFFFF); \ | 292 | clrldi rd,rs,2 |
293 | rldicr rd,rd,32,31; \ | ||
294 | sub rd,rs,rd | ||
295 | 293 | ||
296 | #define tovirt(rd,rs) \ | 294 | #define tovirt(rd,rs) \ |
297 | lis rd,((KERNELBASE>>48)&0xFFFF); \ | 295 | rotldi rd,rs,16; \ |
298 | rldicr rd,rd,32,31; \ | 296 | ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ |
299 | add rd,rs,rd | 297 | rotldi rd,rd,48 |
300 | #else | 298 | #else |
301 | /* | 299 | /* |
302 | * On APUS (Amiga PowerPC cpu upgrade board), we don't know the | 300 | * On APUS (Amiga PowerPC cpu upgrade board), we don't know the |
303 | * physical base address of RAM at compile time. | 301 | * physical base address of RAM at compile time. |
304 | */ | 302 | */ |
303 | #define toreal(rd) tophys(rd,rd) | ||
304 | #define fromreal(rd) tovirt(rd,rd) | ||
305 | |||
305 | #define tophys(rd,rs) \ | 306 | #define tophys(rd,rs) \ |
306 | 0: addis rd,rs,-KERNELBASE@h; \ | 307 | 0: addis rd,rs,-KERNELBASE@h; \ |
307 | .section ".vtop_fixup","aw"; \ | 308 | .section ".vtop_fixup","aw"; \ |