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authorMichael Chan <mchan@broadcom.com>2010-12-23 02:43:04 -0500
committerDavid S. Miller <davem@davemloft.net>2010-12-23 14:44:34 -0500
commite1928c86c4829703b800c81cc9edc939b5634e6f (patch)
treebea86c1f19868963b95c0cdc45f22f5e6e5d789c
parente21ba414eed8a233eadb79bb6b158ac7ceb35025 (diff)
cnic: Add FCoE support on 57712
- Connection ID (cid) management - Slow-path command and response support - Update version to 2.2.11. Reviewed-by: Bhanu Prakash Gollapudi <bprakash@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/cnic.c466
-rw-r--r--drivers/net/cnic.h16
-rw-r--r--drivers/net/cnic_defs.h2095
-rw-r--r--drivers/net/cnic_if.h22
4 files changed, 2585 insertions, 14 deletions
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 6ce739859ac3..4a9c628ab2a6 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -850,6 +850,7 @@ static void cnic_free_resc(struct cnic_dev *dev)
850 kfree(cp->ctx_tbl); 850 kfree(cp->ctx_tbl);
851 cp->ctx_tbl = NULL; 851 cp->ctx_tbl = NULL;
852 852
853 cnic_free_id_tbl(&cp->fcoe_cid_tbl);
853 cnic_free_id_tbl(&cp->cid_tbl); 854 cnic_free_id_tbl(&cp->cid_tbl);
854} 855}
855 856
@@ -1137,12 +1138,22 @@ static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1137 1138
1138 cp->iro_arr = ethdev->iro_arr; 1139 cp->iro_arr = ethdev->iro_arr;
1139 1140
1140 cp->max_cid_space = MAX_ISCSI_TBL_SZ; 1141 cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
1141 cp->iscsi_start_cid = start_cid; 1142 cp->iscsi_start_cid = start_cid;
1143 cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
1144
1145 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
1146 cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
1147 cp->fcoe_init_cid = ethdev->fcoe_init_cid;
1148 if (!cp->fcoe_init_cid)
1149 cp->fcoe_init_cid = 0x10;
1150 }
1151
1142 if (start_cid < BNX2X_ISCSI_START_CID) { 1152 if (start_cid < BNX2X_ISCSI_START_CID) {
1143 u32 delta = BNX2X_ISCSI_START_CID - start_cid; 1153 u32 delta = BNX2X_ISCSI_START_CID - start_cid;
1144 1154
1145 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID; 1155 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
1156 cp->fcoe_start_cid += delta;
1146 cp->max_cid_space += delta; 1157 cp->max_cid_space += delta;
1147 } 1158 }
1148 1159
@@ -1161,6 +1172,9 @@ static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1161 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI; 1172 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1162 } 1173 }
1163 1174
1175 for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
1176 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
1177
1164 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) / 1178 pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
1165 PAGE_SIZE; 1179 PAGE_SIZE;
1166 1180
@@ -1454,8 +1468,11 @@ static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1454 cnic_free_dma(dev, &iscsi->hq_info); 1468 cnic_free_dma(dev, &iscsi->hq_info);
1455 cnic_free_dma(dev, &iscsi->r2tq_info); 1469 cnic_free_dma(dev, &iscsi->r2tq_info);
1456 cnic_free_dma(dev, &iscsi->task_array_info); 1470 cnic_free_dma(dev, &iscsi->task_array_info);
1471 cnic_free_id(&cp->cid_tbl, ctx->cid);
1472 } else {
1473 cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
1457 } 1474 }
1458 cnic_free_id(&cp->cid_tbl, ctx->cid); 1475
1459 ctx->cid = 0; 1476 ctx->cid = 0;
1460} 1477}
1461 1478
@@ -1467,6 +1484,16 @@ static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1467 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid]; 1484 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1468 struct cnic_iscsi *iscsi = ctx->proto.iscsi; 1485 struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1469 1486
1487 if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
1488 cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
1489 if (cid == -1) {
1490 ret = -ENOMEM;
1491 goto error;
1492 }
1493 ctx->cid = cid;
1494 return 0;
1495 }
1496
1470 cid = cnic_alloc_new_id(&cp->cid_tbl); 1497 cid = cnic_alloc_new_id(&cp->cid_tbl);
1471 if (cid == -1) { 1498 if (cid == -1) {
1472 ret = -ENOMEM; 1499 ret = -ENOMEM;
@@ -2107,8 +2134,307 @@ static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2107 return 0; 2134 return 0;
2108} 2135}
2109 2136
2110static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[], 2137static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
2111 u32 num_wqes) 2138{
2139 struct fcoe_kwqe_stat *req;
2140 struct fcoe_stat_ramrod_params *fcoe_stat;
2141 union l5cm_specific_data l5_data;
2142 struct cnic_local *cp = dev->cnic_priv;
2143 int ret;
2144 u32 cid;
2145
2146 req = (struct fcoe_kwqe_stat *) kwqe;
2147 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2148
2149 fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2150 if (!fcoe_stat)
2151 return -ENOMEM;
2152
2153 memset(fcoe_stat, 0, sizeof(*fcoe_stat));
2154 memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
2155
2156 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
2157 FCOE_CONNECTION_TYPE, &l5_data);
2158 return ret;
2159}
2160
2161static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
2162 u32 num, int *work)
2163{
2164 int ret;
2165 struct cnic_local *cp = dev->cnic_priv;
2166 u32 cid;
2167 struct fcoe_init_ramrod_params *fcoe_init;
2168 struct fcoe_kwqe_init1 *req1;
2169 struct fcoe_kwqe_init2 *req2;
2170 struct fcoe_kwqe_init3 *req3;
2171 union l5cm_specific_data l5_data;
2172
2173 if (num < 3) {
2174 *work = num;
2175 return -EINVAL;
2176 }
2177 req1 = (struct fcoe_kwqe_init1 *) wqes[0];
2178 req2 = (struct fcoe_kwqe_init2 *) wqes[1];
2179 req3 = (struct fcoe_kwqe_init3 *) wqes[2];
2180 if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
2181 *work = 1;
2182 return -EINVAL;
2183 }
2184 if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
2185 *work = 2;
2186 return -EINVAL;
2187 }
2188
2189 if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
2190 netdev_err(dev->netdev, "fcoe_init size too big\n");
2191 return -ENOMEM;
2192 }
2193 fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2194 if (!fcoe_init)
2195 return -ENOMEM;
2196
2197 memset(fcoe_init, 0, sizeof(*fcoe_init));
2198 memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
2199 memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
2200 memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
2201 fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
2202 fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
2203 fcoe_init->eq_next_page_addr.lo =
2204 cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
2205 fcoe_init->eq_next_page_addr.hi =
2206 (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
2207
2208 fcoe_init->sb_num = cp->status_blk_num;
2209 fcoe_init->eq_prod = MAX_KCQ_IDX;
2210 fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
2211 cp->kcq2.sw_prod_idx = 0;
2212
2213 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2214 printk(KERN_ERR "bdbg: submitting INIT RAMROD \n");
2215 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
2216 FCOE_CONNECTION_TYPE, &l5_data);
2217 *work = 3;
2218 return ret;
2219}
2220
2221static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
2222 u32 num, int *work)
2223{
2224 int ret = 0;
2225 u32 cid = -1, l5_cid;
2226 struct cnic_local *cp = dev->cnic_priv;
2227 struct fcoe_kwqe_conn_offload1 *req1;
2228 struct fcoe_kwqe_conn_offload2 *req2;
2229 struct fcoe_kwqe_conn_offload3 *req3;
2230 struct fcoe_kwqe_conn_offload4 *req4;
2231 struct fcoe_conn_offload_ramrod_params *fcoe_offload;
2232 struct cnic_context *ctx;
2233 struct fcoe_context *fctx;
2234 struct regpair ctx_addr;
2235 union l5cm_specific_data l5_data;
2236 struct fcoe_kcqe kcqe;
2237 struct kcqe *cqes[1];
2238
2239 if (num < 4) {
2240 *work = num;
2241 return -EINVAL;
2242 }
2243 req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
2244 req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
2245 req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
2246 req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
2247
2248 *work = 4;
2249
2250 l5_cid = req1->fcoe_conn_id;
2251 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2252 goto err_reply;
2253
2254 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2255
2256 ctx = &cp->ctx_tbl[l5_cid];
2257 if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2258 goto err_reply;
2259
2260 ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
2261 if (ret) {
2262 ret = 0;
2263 goto err_reply;
2264 }
2265 cid = ctx->cid;
2266
2267 fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
2268 if (fctx) {
2269 u32 hw_cid = BNX2X_HW_CID(cp, cid);
2270 u32 val;
2271
2272 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
2273 FCOE_CONNECTION_TYPE);
2274 fctx->xstorm_ag_context.cdu_reserved = val;
2275 val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
2276 FCOE_CONNECTION_TYPE);
2277 fctx->ustorm_ag_context.cdu_usage = val;
2278 }
2279 if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
2280 netdev_err(dev->netdev, "fcoe_offload size too big\n");
2281 goto err_reply;
2282 }
2283 fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2284 if (!fcoe_offload)
2285 goto err_reply;
2286
2287 memset(fcoe_offload, 0, sizeof(*fcoe_offload));
2288 memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
2289 memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
2290 memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
2291 memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
2292
2293 cid = BNX2X_HW_CID(cp, cid);
2294 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
2295 FCOE_CONNECTION_TYPE, &l5_data);
2296 if (!ret)
2297 set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2298
2299 return ret;
2300
2301err_reply:
2302 if (cid != -1)
2303 cnic_free_bnx2x_conn_resc(dev, l5_cid);
2304
2305 memset(&kcqe, 0, sizeof(kcqe));
2306 kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
2307 kcqe.fcoe_conn_id = req1->fcoe_conn_id;
2308 kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
2309
2310 cqes[0] = (struct kcqe *) &kcqe;
2311 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2312 return ret;
2313}
2314
2315static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
2316{
2317 struct fcoe_kwqe_conn_enable_disable *req;
2318 struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
2319 union l5cm_specific_data l5_data;
2320 int ret;
2321 u32 cid, l5_cid;
2322 struct cnic_local *cp = dev->cnic_priv;
2323
2324 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2325 cid = req->context_id;
2326 l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
2327
2328 if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
2329 netdev_err(dev->netdev, "fcoe_enable size too big\n");
2330 return -ENOMEM;
2331 }
2332 fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2333 if (!fcoe_enable)
2334 return -ENOMEM;
2335
2336 memset(fcoe_enable, 0, sizeof(*fcoe_enable));
2337 memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
2338 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
2339 FCOE_CONNECTION_TYPE, &l5_data);
2340 return ret;
2341}
2342
2343static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
2344{
2345 struct fcoe_kwqe_conn_enable_disable *req;
2346 struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
2347 union l5cm_specific_data l5_data;
2348 int ret;
2349 u32 cid, l5_cid;
2350 struct cnic_local *cp = dev->cnic_priv;
2351
2352 req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2353 cid = req->context_id;
2354 l5_cid = req->conn_id;
2355 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2356 return -EINVAL;
2357
2358 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2359
2360 if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
2361 netdev_err(dev->netdev, "fcoe_disable size too big\n");
2362 return -ENOMEM;
2363 }
2364 fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2365 if (!fcoe_disable)
2366 return -ENOMEM;
2367
2368 memset(fcoe_disable, 0, sizeof(*fcoe_disable));
2369 memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
2370 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
2371 FCOE_CONNECTION_TYPE, &l5_data);
2372 return ret;
2373}
2374
2375static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2376{
2377 struct fcoe_kwqe_conn_destroy *req;
2378 union l5cm_specific_data l5_data;
2379 int ret;
2380 u32 cid, l5_cid;
2381 struct cnic_local *cp = dev->cnic_priv;
2382 struct cnic_context *ctx;
2383 struct fcoe_kcqe kcqe;
2384 struct kcqe *cqes[1];
2385
2386 req = (struct fcoe_kwqe_conn_destroy *) kwqe;
2387 cid = req->context_id;
2388 l5_cid = req->conn_id;
2389 if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
2390 return -EINVAL;
2391
2392 l5_cid += BNX2X_FCOE_L5_CID_BASE;
2393
2394 ctx = &cp->ctx_tbl[l5_cid];
2395
2396 init_waitqueue_head(&ctx->waitq);
2397 ctx->wait_cond = 0;
2398
2399 memset(&l5_data, 0, sizeof(l5_data));
2400 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
2401 FCOE_CONNECTION_TYPE, &l5_data);
2402 if (ret == 0) {
2403 wait_event(ctx->waitq, ctx->wait_cond);
2404 set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
2405 queue_delayed_work(cnic_wq, &cp->delete_task,
2406 msecs_to_jiffies(2000));
2407 }
2408
2409 memset(&kcqe, 0, sizeof(kcqe));
2410 kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
2411 kcqe.fcoe_conn_id = req->conn_id;
2412 kcqe.fcoe_conn_context_id = cid;
2413
2414 cqes[0] = (struct kcqe *) &kcqe;
2415 cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2416 return ret;
2417}
2418
2419static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2420{
2421 struct fcoe_kwqe_destroy *req;
2422 union l5cm_specific_data l5_data;
2423 struct cnic_local *cp = dev->cnic_priv;
2424 int ret;
2425 u32 cid;
2426
2427 req = (struct fcoe_kwqe_destroy *) kwqe;
2428 cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
2429
2430 memset(&l5_data, 0, sizeof(l5_data));
2431 ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
2432 FCOE_CONNECTION_TYPE, &l5_data);
2433 return ret;
2434}
2435
2436static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
2437 struct kwqe *wqes[], u32 num_wqes)
2112{ 2438{
2113 int i, work, ret; 2439 int i, work, ret;
2114 u32 opcode; 2440 u32 opcode;
@@ -2172,6 +2498,98 @@ static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2172 return 0; 2498 return 0;
2173} 2499}
2174 2500
2501static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
2502 struct kwqe *wqes[], u32 num_wqes)
2503{
2504 struct cnic_local *cp = dev->cnic_priv;
2505 int i, work, ret;
2506 u32 opcode;
2507 struct kwqe *kwqe;
2508
2509 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2510 return -EAGAIN; /* bnx2 is down */
2511
2512 if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
2513 return -EINVAL;
2514
2515 for (i = 0; i < num_wqes; ) {
2516 kwqe = wqes[i];
2517 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2518 work = 1;
2519
2520 switch (opcode) {
2521 case FCOE_KWQE_OPCODE_INIT1:
2522 ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
2523 num_wqes - i, &work);
2524 break;
2525 case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
2526 ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
2527 num_wqes - i, &work);
2528 break;
2529 case FCOE_KWQE_OPCODE_ENABLE_CONN:
2530 ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
2531 break;
2532 case FCOE_KWQE_OPCODE_DISABLE_CONN:
2533 ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
2534 break;
2535 case FCOE_KWQE_OPCODE_DESTROY_CONN:
2536 ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
2537 break;
2538 case FCOE_KWQE_OPCODE_DESTROY:
2539 ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
2540 break;
2541 case FCOE_KWQE_OPCODE_STAT:
2542 ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
2543 break;
2544 default:
2545 ret = 0;
2546 netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2547 opcode);
2548 break;
2549 }
2550 if (ret < 0)
2551 netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2552 opcode);
2553 i += work;
2554 }
2555 return 0;
2556}
2557
2558static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2559 u32 num_wqes)
2560{
2561 int ret = -EINVAL;
2562 u32 layer_code;
2563
2564 if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2565 return -EAGAIN; /* bnx2x is down */
2566
2567 if (!num_wqes)
2568 return 0;
2569
2570 layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
2571 switch (layer_code) {
2572 case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
2573 case KWQE_FLAGS_LAYER_MASK_L4:
2574 case KWQE_FLAGS_LAYER_MASK_L2:
2575 ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
2576 break;
2577
2578 case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
2579 ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
2580 break;
2581 }
2582 return ret;
2583}
2584
2585static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
2586{
2587 if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
2588 return KCQE_FLAGS_LAYER_MASK_L4;
2589
2590 return opflag & KCQE_FLAGS_LAYER_MASK;
2591}
2592
2175static void service_kcqes(struct cnic_dev *dev, int num_cqes) 2593static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2176{ 2594{
2177 struct cnic_local *cp = dev->cnic_priv; 2595 struct cnic_local *cp = dev->cnic_priv;
@@ -2183,7 +2601,7 @@ static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2183 struct cnic_ulp_ops *ulp_ops; 2601 struct cnic_ulp_ops *ulp_ops;
2184 int ulp_type; 2602 int ulp_type;
2185 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag; 2603 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2186 u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK; 2604 u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
2187 2605
2188 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION)) 2606 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2189 comp++; 2607 comp++;
@@ -2191,7 +2609,7 @@ static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2191 while (j < num_cqes) { 2609 while (j < num_cqes) {
2192 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag; 2610 u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2193 2611
2194 if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer) 2612 if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
2195 break; 2613 break;
2196 2614
2197 if (unlikely(next_op & KCQE_RAMROD_COMPLETION)) 2615 if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
@@ -2203,6 +2621,8 @@ static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2203 ulp_type = CNIC_ULP_RDMA; 2621 ulp_type = CNIC_ULP_RDMA;
2204 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI) 2622 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2205 ulp_type = CNIC_ULP_ISCSI; 2623 ulp_type = CNIC_ULP_ISCSI;
2624 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
2625 ulp_type = CNIC_ULP_FCOE;
2206 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4) 2626 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2207 ulp_type = CNIC_ULP_L4; 2627 ulp_type = CNIC_ULP_L4;
2208 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2) 2628 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
@@ -3249,6 +3669,18 @@ done:
3249 csk_put(csk); 3669 csk_put(csk);
3250} 3670}
3251 3671
3672static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
3673{
3674 struct cnic_local *cp = dev->cnic_priv;
3675 struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
3676 u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
3677 struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3678
3679 ctx->timestamp = jiffies;
3680 ctx->wait_cond = 1;
3681 wake_up(&ctx->waitq);
3682}
3683
3252static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe) 3684static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3253{ 3685{
3254 struct cnic_local *cp = dev->cnic_priv; 3686 struct cnic_local *cp = dev->cnic_priv;
@@ -3257,6 +3689,10 @@ static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3257 u32 l5_cid; 3689 u32 l5_cid;
3258 struct cnic_sock *csk; 3690 struct cnic_sock *csk;
3259 3691
3692 if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
3693 cnic_process_fcoe_term_conn(dev, kcqe);
3694 return;
3695 }
3260 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG || 3696 if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3261 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) { 3697 opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3262 cnic_cm_process_offld_pg(dev, l4kcqe); 3698 cnic_cm_process_offld_pg(dev, l4kcqe);
@@ -3893,7 +4329,7 @@ static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
3893 4329
3894 memset(&l2kwqe, 0, sizeof(l2kwqe)); 4330 memset(&l2kwqe, 0, sizeof(l2kwqe));
3895 wqes[0] = &l2kwqe; 4331 wqes[0] = &l2kwqe;
3896 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) | 4332 l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
3897 (L2_KWQE_OPCODE_VALUE_FLUSH << 4333 (L2_KWQE_OPCODE_VALUE_FLUSH <<
3898 KWQE_OPCODE_SHIFT) | 2; 4334 KWQE_OPCODE_SHIFT) | 2;
3899 dev->submit_kwqes(dev, wqes, 1); 4335 dev->submit_kwqes(dev, wqes, 1);
@@ -4336,6 +4772,10 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
4336 val16 ^= 0x1e1e; 4772 val16 ^= 0x1e1e;
4337 dev->max_iscsi_conn = val16; 4773 dev->max_iscsi_conn = val16;
4338 } 4774 }
4775
4776 if (BNX2X_CHIP_IS_E2(cp->chip_id))
4777 dev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
4778
4339 if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) { 4779 if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
4340 int func = CNIC_FUNC(cp); 4780 int func = CNIC_FUNC(cp);
4341 u32 mf_cfg_addr; 4781 u32 mf_cfg_addr;
@@ -4362,6 +4802,9 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
4362 if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)) 4802 if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD))
4363 dev->max_iscsi_conn = 0; 4803 dev->max_iscsi_conn = 0;
4364 4804
4805 if (!(val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
4806 dev->max_fcoe_conn = 0;
4807
4365 addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr, 4808 addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
4366 func_ext_config[func]. 4809 func_ext_config[func].
4367 iscsi_mac_addr_upper); 4810 iscsi_mac_addr_upper);
@@ -4463,6 +4906,15 @@ static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
4463 if (ret) 4906 if (ret)
4464 return -ENOMEM; 4907 return -ENOMEM;
4465 4908
4909 if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
4910 ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
4911 BNX2X_FCOE_NUM_CONNECTIONS,
4912 cp->fcoe_start_cid);
4913
4914 if (ret)
4915 return -ENOMEM;
4916 }
4917
4466 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2; 4918 cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
4467 4919
4468 cnic_init_bnx2x_kcq(dev); 4920 cnic_init_bnx2x_kcq(dev);
diff --git a/drivers/net/cnic.h b/drivers/net/cnic.h
index e46b4c121948..b328f6c924c3 100644
--- a/drivers/net/cnic.h
+++ b/drivers/net/cnic.h
@@ -291,6 +291,10 @@ struct cnic_local {
291 atomic_t iscsi_conn; 291 atomic_t iscsi_conn;
292 u32 iscsi_start_cid; 292 u32 iscsi_start_cid;
293 293
294 u32 fcoe_init_cid;
295 u32 fcoe_start_cid;
296 struct cnic_id_tbl fcoe_cid_tbl;
297
294 u32 max_cid_space; 298 u32 max_cid_space;
295 299
296 /* per connection parameters */ 300 /* per connection parameters */
@@ -368,6 +372,10 @@ struct bnx2x_bd_chain_next {
368#define BNX2X_ISCSI_PBL_NOT_CACHED 0xff 372#define BNX2X_ISCSI_PBL_NOT_CACHED 0xff
369#define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff 373#define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff
370 374
375#define BNX2X_FCOE_NUM_CONNECTIONS 128
376
377#define BNX2X_FCOE_L5_CID_BASE MAX_ISCSI_TBL_SZ
378
371#define BNX2X_CHIP_NUM_57710 0x164e 379#define BNX2X_CHIP_NUM_57710 0x164e
372#define BNX2X_CHIP_NUM_57711 0x164f 380#define BNX2X_CHIP_NUM_57711 0x164f
373#define BNX2X_CHIP_NUM_57711E 0x1650 381#define BNX2X_CHIP_NUM_57711E 0x1650
@@ -426,6 +434,10 @@ struct bnx2x_bd_chain_next {
426#define BNX2X_MF_CFG_ADDR(base, field) \ 434#define BNX2X_MF_CFG_ADDR(base, field) \
427 ((base) + offsetof(struct mf_cfg, field)) 435 ((base) + offsetof(struct mf_cfg, field))
428 436
437#ifndef ETH_MAX_RX_CLIENTS_E2
438#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
439#endif
440
429#define CNIC_PORT(cp) ((cp)->pfid & 1) 441#define CNIC_PORT(cp) ((cp)->pfid & 1)
430#define CNIC_FUNC(cp) ((cp)->func) 442#define CNIC_FUNC(cp) ((cp)->func)
431#define CNIC_PATH(cp) (!BNX2X_CHIP_IS_E2(cp->chip_id) ? 0 :\ 443#define CNIC_PATH(cp) (!BNX2X_CHIP_IS_E2(cp->chip_id) ? 0 :\
@@ -438,7 +450,9 @@ struct bnx2x_bd_chain_next {
438#define BNX2X_SW_CID(x) (x & 0x1ffff) 450#define BNX2X_SW_CID(x) (x & 0x1ffff)
439 451
440#define BNX2X_CL_QZONE_ID(cp, cli) \ 452#define BNX2X_CL_QZONE_ID(cp, cli) \
441 (cli + (CNIC_PORT(cp) * ETH_MAX_RX_CLIENTS_E1H)) 453 (cli + (CNIC_PORT(cp) * (BNX2X_CHIP_IS_E2(cp->chip_id) ?\
454 ETH_MAX_RX_CLIENTS_E2 : \
455 ETH_MAX_RX_CLIENTS_E1H)))
442 456
443#define TCP_TSTORM_OOO_DROP_AND_PROC_ACK (0<<4) 457#define TCP_TSTORM_OOO_DROP_AND_PROC_ACK (0<<4)
444#endif 458#endif
diff --git a/drivers/net/cnic_defs.h b/drivers/net/cnic_defs.h
index 328e8b2765a3..fdbc00415603 100644
--- a/drivers/net/cnic_defs.h
+++ b/drivers/net/cnic_defs.h
@@ -35,6 +35,40 @@
35#define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE (L5CM_RAMROD_CMD_ID_BASE + 14) 35#define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE (L5CM_RAMROD_CMD_ID_BASE + 14)
36#define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD (L5CM_RAMROD_CMD_ID_BASE + 15) 36#define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD (L5CM_RAMROD_CMD_ID_BASE + 15)
37 37
38#define FCOE_KCQE_OPCODE_INIT_FUNC (0x10)
39#define FCOE_KCQE_OPCODE_DESTROY_FUNC (0x11)
40#define FCOE_KCQE_OPCODE_STAT_FUNC (0x12)
41#define FCOE_KCQE_OPCODE_OFFLOAD_CONN (0x15)
42#define FCOE_KCQE_OPCODE_ENABLE_CONN (0x16)
43#define FCOE_KCQE_OPCODE_DISABLE_CONN (0x17)
44#define FCOE_KCQE_OPCODE_DESTROY_CONN (0x18)
45#define FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION (0x20)
46#define FCOE_KCQE_OPCODE_FCOE_ERROR (0x21)
47
48#define FCOE_RAMROD_CMD_ID_INIT (FCOE_KCQE_OPCODE_INIT_FUNC)
49#define FCOE_RAMROD_CMD_ID_DESTROY (FCOE_KCQE_OPCODE_DESTROY_FUNC)
50#define FCOE_RAMROD_CMD_ID_OFFLOAD_CONN (FCOE_KCQE_OPCODE_OFFLOAD_CONN)
51#define FCOE_RAMROD_CMD_ID_ENABLE_CONN (FCOE_KCQE_OPCODE_ENABLE_CONN)
52#define FCOE_RAMROD_CMD_ID_DISABLE_CONN (FCOE_KCQE_OPCODE_DISABLE_CONN)
53#define FCOE_RAMROD_CMD_ID_DESTROY_CONN (FCOE_KCQE_OPCODE_DESTROY_CONN)
54#define FCOE_RAMROD_CMD_ID_STAT (FCOE_KCQE_OPCODE_STAT_FUNC)
55#define FCOE_RAMROD_CMD_ID_TERMINATE_CONN (0x81)
56
57#define FCOE_KWQE_OPCODE_INIT1 (0)
58#define FCOE_KWQE_OPCODE_INIT2 (1)
59#define FCOE_KWQE_OPCODE_INIT3 (2)
60#define FCOE_KWQE_OPCODE_OFFLOAD_CONN1 (3)
61#define FCOE_KWQE_OPCODE_OFFLOAD_CONN2 (4)
62#define FCOE_KWQE_OPCODE_OFFLOAD_CONN3 (5)
63#define FCOE_KWQE_OPCODE_OFFLOAD_CONN4 (6)
64#define FCOE_KWQE_OPCODE_ENABLE_CONN (7)
65#define FCOE_KWQE_OPCODE_DISABLE_CONN (8)
66#define FCOE_KWQE_OPCODE_DESTROY_CONN (9)
67#define FCOE_KWQE_OPCODE_DESTROY (10)
68#define FCOE_KWQE_OPCODE_STAT (11)
69
70#define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE (0x3)
71
38/* KCQ (kernel completion queue) response op codes */ 72/* KCQ (kernel completion queue) response op codes */
39#define L4_KCQE_OPCODE_VALUE_CLOSE_COMP (53) 73#define L4_KCQE_OPCODE_VALUE_CLOSE_COMP (53)
40#define L4_KCQE_OPCODE_VALUE_RESET_COMP (54) 74#define L4_KCQE_OPCODE_VALUE_RESET_COMP (54)
@@ -683,6 +717,1496 @@ struct cstorm_iscsi_ag_context {
683}; 717};
684 718
685/* 719/*
720 * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and used in FCoE context section
721 */
722struct ustorm_fcoe_params {
723#if defined(__BIG_ENDIAN)
724 u16 fcoe_conn_id;
725 u16 flags;
726#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
727#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
728#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
729#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
730#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
731#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
732#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
733#define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
734#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
735#define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
736#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
737#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
738#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
739#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
740#define USTORM_FCOE_PARAMS_B_C2_VALID (0x1<<7)
741#define USTORM_FCOE_PARAMS_B_C2_VALID_SHIFT 7
742#define USTORM_FCOE_PARAMS_B_ACK_0 (0x1<<8)
743#define USTORM_FCOE_PARAMS_B_ACK_0_SHIFT 8
744#define USTORM_FCOE_PARAMS_RSRV0 (0x7F<<9)
745#define USTORM_FCOE_PARAMS_RSRV0_SHIFT 9
746#elif defined(__LITTLE_ENDIAN)
747 u16 flags;
748#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
749#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
750#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
751#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
752#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
753#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
754#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
755#define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
756#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
757#define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
758#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
759#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
760#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
761#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
762#define USTORM_FCOE_PARAMS_B_C2_VALID (0x1<<7)
763#define USTORM_FCOE_PARAMS_B_C2_VALID_SHIFT 7
764#define USTORM_FCOE_PARAMS_B_ACK_0 (0x1<<8)
765#define USTORM_FCOE_PARAMS_B_ACK_0_SHIFT 8
766#define USTORM_FCOE_PARAMS_RSRV0 (0x7F<<9)
767#define USTORM_FCOE_PARAMS_RSRV0_SHIFT 9
768 u16 fcoe_conn_id;
769#endif
770#if defined(__BIG_ENDIAN)
771 u8 hc_csdm_byte_en;
772 u8 func_id;
773 u8 port_id;
774 u8 vnic_id;
775#elif defined(__LITTLE_ENDIAN)
776 u8 vnic_id;
777 u8 port_id;
778 u8 func_id;
779 u8 hc_csdm_byte_en;
780#endif
781#if defined(__BIG_ENDIAN)
782 u16 rx_total_conc_seqs;
783 u16 rx_max_fc_pay_len;
784#elif defined(__LITTLE_ENDIAN)
785 u16 rx_max_fc_pay_len;
786 u16 rx_total_conc_seqs;
787#endif
788#if defined(__BIG_ENDIAN)
789 u16 ox_id;
790 u16 rx_max_conc_seqs;
791#elif defined(__LITTLE_ENDIAN)
792 u16 rx_max_conc_seqs;
793 u16 ox_id;
794#endif
795};
796
797/*
798 * FCoE 16-bits index structure
799 */
800struct fcoe_idx16_fields {
801 u16 fields;
802#define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0)
803#define FCOE_IDX16_FIELDS_IDX_SHIFT 0
804#define FCOE_IDX16_FIELDS_MSB (0x1<<15)
805#define FCOE_IDX16_FIELDS_MSB_SHIFT 15
806};
807
808/*
809 * FCoE 16-bits index union
810 */
811union fcoe_idx16_field_union {
812 struct fcoe_idx16_fields fields;
813 u16 val;
814};
815
816/*
817 * 4 regs size
818 */
819struct fcoe_bd_ctx {
820 u32 buf_addr_hi;
821 u32 buf_addr_lo;
822#if defined(__BIG_ENDIAN)
823 u16 rsrv0;
824 u16 buf_len;
825#elif defined(__LITTLE_ENDIAN)
826 u16 buf_len;
827 u16 rsrv0;
828#endif
829#if defined(__BIG_ENDIAN)
830 u16 rsrv1;
831 u16 flags;
832#elif defined(__LITTLE_ENDIAN)
833 u16 flags;
834 u16 rsrv1;
835#endif
836};
837
838/*
839 * Parameters required for placement according to SGL
840 */
841struct ustorm_fcoe_data_place {
842#if defined(__BIG_ENDIAN)
843 u16 cached_sge_off;
844 u8 cached_num_sges;
845 u8 cached_sge_idx;
846#elif defined(__LITTLE_ENDIAN)
847 u8 cached_sge_idx;
848 u8 cached_num_sges;
849 u16 cached_sge_off;
850#endif
851 struct fcoe_bd_ctx cached_sge[3];
852};
853
854struct fcoe_task_ctx_entry_txwr_rxrd {
855#if defined(__BIG_ENDIAN)
856 u16 verify_tx_seq;
857 u8 init_flags;
858#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
859#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
860#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
861#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
862#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
863#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
864#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
865#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
866#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
867#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
868 u8 tx_flags;
869#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
870#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
871#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
872#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
873#elif defined(__LITTLE_ENDIAN)
874 u8 tx_flags;
875#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
876#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
877#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
878#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
879 u8 init_flags;
880#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
881#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
882#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
883#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
884#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
885#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
886#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
887#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
888#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
889#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
890 u16 verify_tx_seq;
891#endif
892};
893
894struct fcoe_fcp_cmd_payload {
895 u32 opaque[8];
896};
897
898struct fcoe_fc_hdr {
899#if defined(__BIG_ENDIAN)
900 u8 cs_ctl;
901 u8 s_id[3];
902#elif defined(__LITTLE_ENDIAN)
903 u8 s_id[3];
904 u8 cs_ctl;
905#endif
906#if defined(__BIG_ENDIAN)
907 u8 r_ctl;
908 u8 d_id[3];
909#elif defined(__LITTLE_ENDIAN)
910 u8 d_id[3];
911 u8 r_ctl;
912#endif
913#if defined(__BIG_ENDIAN)
914 u8 seq_id;
915 u8 df_ctl;
916 u16 seq_cnt;
917#elif defined(__LITTLE_ENDIAN)
918 u16 seq_cnt;
919 u8 df_ctl;
920 u8 seq_id;
921#endif
922#if defined(__BIG_ENDIAN)
923 u8 type;
924 u8 f_ctl[3];
925#elif defined(__LITTLE_ENDIAN)
926 u8 f_ctl[3];
927 u8 type;
928#endif
929 u32 parameters;
930#if defined(__BIG_ENDIAN)
931 u16 ox_id;
932 u16 rx_id;
933#elif defined(__LITTLE_ENDIAN)
934 u16 rx_id;
935 u16 ox_id;
936#endif
937};
938
939struct fcoe_fc_frame {
940 struct fcoe_fc_hdr fc_hdr;
941 u32 reserved0[2];
942};
943
944union fcoe_cmd_flow_info {
945 struct fcoe_fcp_cmd_payload fcp_cmd_payload;
946 struct fcoe_fc_frame mp_fc_frame;
947};
948
949struct fcoe_read_flow_info {
950 struct fcoe_fc_hdr fc_data_in_hdr;
951 u32 reserved[2];
952};
953
954struct fcoe_fcp_xfr_rdy_payload {
955 u32 burst_len;
956 u32 data_ro;
957};
958
959struct fcoe_write_flow_info {
960 struct fcoe_fc_hdr fc_data_out_hdr;
961 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_payload;
962};
963
964struct fcoe_fcp_rsp_flags {
965 u8 flags;
966#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
967#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
968#define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
969#define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
970#define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
971#define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
972#define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
973#define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
974#define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
975#define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
976#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
977#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
978};
979
980struct fcoe_fcp_rsp_payload {
981 struct regpair reserved0;
982 u32 fcp_resid;
983#if defined(__BIG_ENDIAN)
984 u16 retry_delay_timer;
985 struct fcoe_fcp_rsp_flags fcp_flags;
986 u8 scsi_status_code;
987#elif defined(__LITTLE_ENDIAN)
988 u8 scsi_status_code;
989 struct fcoe_fcp_rsp_flags fcp_flags;
990 u16 retry_delay_timer;
991#endif
992 u32 fcp_rsp_len;
993 u32 fcp_sns_len;
994};
995
996/*
997 * Fixed size structure in order to plant it in Union structure
998 */
999struct fcoe_fcp_rsp_union {
1000 struct fcoe_fcp_rsp_payload payload;
1001 struct regpair reserved0;
1002};
1003
1004/*
1005 * Fixed size structure in order to plant it in Union structure
1006 */
1007struct fcoe_abts_rsp_union {
1008 u32 r_ctl;
1009 u32 abts_rsp_payload[7];
1010};
1011
1012union fcoe_rsp_flow_info {
1013 struct fcoe_fcp_rsp_union fcp_rsp;
1014 struct fcoe_abts_rsp_union abts_rsp;
1015};
1016
1017struct fcoe_cleanup_flow_info {
1018#if defined(__BIG_ENDIAN)
1019 u16 reserved1;
1020 u16 task_id;
1021#elif defined(__LITTLE_ENDIAN)
1022 u16 task_id;
1023 u16 reserved1;
1024#endif
1025 u32 reserved2[7];
1026};
1027
1028/*
1029 * 32 bytes used for general purposes
1030 */
1031union fcoe_general_task_ctx {
1032 union fcoe_cmd_flow_info cmd_info;
1033 struct fcoe_read_flow_info read_info;
1034 struct fcoe_write_flow_info write_info;
1035 union fcoe_rsp_flow_info rsp_info;
1036 struct fcoe_cleanup_flow_info cleanup_info;
1037 u32 comp_info[8];
1038};
1039
1040struct fcoe_s_stat_ctx {
1041 u8 flags;
1042#define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
1043#define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
1044#define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
1045#define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
1046#define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
1047#define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
1048#define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
1049#define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
1050#define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
1051#define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
1052#define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
1053#define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
1054#define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
1055#define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
1056};
1057
1058/*
1059 * Common section. Both TX and RX processing might write and read from it in different flows
1060 */
1061struct fcoe_task_ctx_entry_tx_rx_cmn {
1062 u32 data_2_trns;
1063 union fcoe_general_task_ctx general;
1064#if defined(__BIG_ENDIAN)
1065 u16 tx_low_seq_cnt;
1066 struct fcoe_s_stat_ctx tx_s_stat;
1067 u8 tx_seq_id;
1068#elif defined(__LITTLE_ENDIAN)
1069 u8 tx_seq_id;
1070 struct fcoe_s_stat_ctx tx_s_stat;
1071 u16 tx_low_seq_cnt;
1072#endif
1073 u32 common_flags;
1074#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID (0xFFFFFF<<0)
1075#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT 0
1076#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID (0x1<<24)
1077#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT 24
1078#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT (0x1<<25)
1079#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT_SHIFT 25
1080#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER (0x1<<26)
1081#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER_SHIFT 26
1082#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF (0x1<<27)
1083#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF_SHIFT 27
1084#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME (0x1<<28)
1085#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT 28
1086#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV (0x7<<29)
1087#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV_SHIFT 29
1088};
1089
1090struct fcoe_task_ctx_entry_rxwr_txrd {
1091#if defined(__BIG_ENDIAN)
1092 u16 rx_id;
1093 u16 rx_flags;
1094#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
1095#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
1096#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
1097#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
1098#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
1099#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
1100#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
1101#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
1102#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
1103#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
1104#elif defined(__LITTLE_ENDIAN)
1105 u16 rx_flags;
1106#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
1107#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
1108#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
1109#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
1110#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
1111#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
1112#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
1113#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
1114#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
1115#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
1116 u16 rx_id;
1117#endif
1118};
1119
1120struct fcoe_seq_ctx {
1121#if defined(__BIG_ENDIAN)
1122 u16 low_seq_cnt;
1123 struct fcoe_s_stat_ctx s_stat;
1124 u8 seq_id;
1125#elif defined(__LITTLE_ENDIAN)
1126 u8 seq_id;
1127 struct fcoe_s_stat_ctx s_stat;
1128 u16 low_seq_cnt;
1129#endif
1130#if defined(__BIG_ENDIAN)
1131 u16 err_seq_cnt;
1132 u16 high_seq_cnt;
1133#elif defined(__LITTLE_ENDIAN)
1134 u16 high_seq_cnt;
1135 u16 err_seq_cnt;
1136#endif
1137 u32 low_exp_ro;
1138 u32 high_exp_ro;
1139};
1140
1141struct fcoe_single_sge_ctx {
1142 struct regpair cur_buf_addr;
1143#if defined(__BIG_ENDIAN)
1144 u16 reserved0;
1145 u16 cur_buf_rem;
1146#elif defined(__LITTLE_ENDIAN)
1147 u16 cur_buf_rem;
1148 u16 reserved0;
1149#endif
1150};
1151
1152struct fcoe_mul_sges_ctx {
1153 struct regpair cur_sge_addr;
1154#if defined(__BIG_ENDIAN)
1155 u8 sgl_size;
1156 u8 cur_sge_idx;
1157 u16 cur_sge_off;
1158#elif defined(__LITTLE_ENDIAN)
1159 u16 cur_sge_off;
1160 u8 cur_sge_idx;
1161 u8 sgl_size;
1162#endif
1163};
1164
1165union fcoe_sgl_ctx {
1166 struct fcoe_single_sge_ctx single_sge;
1167 struct fcoe_mul_sges_ctx mul_sges;
1168};
1169
1170struct fcoe_task_ctx_entry_rx_only {
1171 struct fcoe_seq_ctx seq_ctx;
1172 struct fcoe_seq_ctx ooo_seq_ctx;
1173 u32 rsrv3;
1174 union fcoe_sgl_ctx sgl_ctx;
1175};
1176
1177struct ustorm_fcoe_task_ctx_entry_rd {
1178 struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
1179 struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
1180 struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
1181 struct fcoe_task_ctx_entry_rx_only rx_wr;
1182 u32 reserved;
1183};
1184
1185/*
1186 * Ustorm FCoE Storm Context
1187 */
1188struct ustorm_fcoe_st_context {
1189 struct ustorm_fcoe_params fcoe_params;
1190 struct regpair task_addr;
1191 struct regpair cq_base_addr;
1192 struct regpair rq_pbl_base;
1193 struct regpair rq_cur_page_addr;
1194 struct regpair confq_pbl_base_addr;
1195 struct regpair conn_db_base;
1196 struct regpair xfrq_base_addr;
1197 struct regpair lcq_base_addr;
1198#if defined(__BIG_ENDIAN)
1199 union fcoe_idx16_field_union rq_cons;
1200 union fcoe_idx16_field_union rq_prod;
1201#elif defined(__LITTLE_ENDIAN)
1202 union fcoe_idx16_field_union rq_prod;
1203 union fcoe_idx16_field_union rq_cons;
1204#endif
1205#if defined(__BIG_ENDIAN)
1206 u16 xfrq_prod;
1207 u16 cq_cons;
1208#elif defined(__LITTLE_ENDIAN)
1209 u16 cq_cons;
1210 u16 xfrq_prod;
1211#endif
1212#if defined(__BIG_ENDIAN)
1213 u16 lcq_cons;
1214 u16 hc_cram_address;
1215#elif defined(__LITTLE_ENDIAN)
1216 u16 hc_cram_address;
1217 u16 lcq_cons;
1218#endif
1219#if defined(__BIG_ENDIAN)
1220 u16 sq_xfrq_lcq_confq_size;
1221 u16 confq_prod;
1222#elif defined(__LITTLE_ENDIAN)
1223 u16 confq_prod;
1224 u16 sq_xfrq_lcq_confq_size;
1225#endif
1226#if defined(__BIG_ENDIAN)
1227 u8 hc_csdm_agg_int;
1228 u8 flags;
1229#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG (0x1<<0)
1230#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG_SHIFT 0
1231#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG (0x1<<1)
1232#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG_SHIFT 1
1233#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG (0x1<<2)
1234#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG_SHIFT 2
1235#define USTORM_FCOE_ST_CONTEXT_RSRV1 (0x1F<<3)
1236#define USTORM_FCOE_ST_CONTEXT_RSRV1_SHIFT 3
1237 u8 available_rqes;
1238 u8 sp_q_flush_cnt;
1239#elif defined(__LITTLE_ENDIAN)
1240 u8 sp_q_flush_cnt;
1241 u8 available_rqes;
1242 u8 flags;
1243#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG (0x1<<0)
1244#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG_SHIFT 0
1245#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG (0x1<<1)
1246#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG_SHIFT 1
1247#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG (0x1<<2)
1248#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG_SHIFT 2
1249#define USTORM_FCOE_ST_CONTEXT_RSRV1 (0x1F<<3)
1250#define USTORM_FCOE_ST_CONTEXT_RSRV1_SHIFT 3
1251 u8 hc_csdm_agg_int;
1252#endif
1253 struct ustorm_fcoe_data_place data_place;
1254 struct ustorm_fcoe_task_ctx_entry_rd tce;
1255};
1256
1257/*
1258 * The FCoE non-aggregative context of Tstorm
1259 */
1260struct tstorm_fcoe_st_context {
1261 struct regpair reserved0;
1262 struct regpair reserved1;
1263};
1264
1265/*
1266 * The fcoe aggregative context section of Xstorm
1267 */
1268struct xstorm_fcoe_extra_ag_context_section {
1269#if defined(__BIG_ENDIAN)
1270 u8 tcp_agg_vars1;
1271#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
1272#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
1273#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1274#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1275#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF (0x3<<4)
1276#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_SHIFT 4
1277#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
1278#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
1279#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
1280#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
1281 u8 __reserved_da_cnt;
1282 u16 __mtu;
1283#elif defined(__LITTLE_ENDIAN)
1284 u16 __mtu;
1285 u8 __reserved_da_cnt;
1286 u8 tcp_agg_vars1;
1287#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
1288#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
1289#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
1290#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
1291#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF (0x3<<4)
1292#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_SHIFT 4
1293#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
1294#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
1295#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
1296#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
1297#endif
1298 u32 __task_addr_lo;
1299 u32 __task_addr_hi;
1300 u32 __reserved55;
1301 u32 __tx_prods;
1302#if defined(__BIG_ENDIAN)
1303 u8 __agg_val8_th;
1304 u8 __agg_val8;
1305 u16 tcp_agg_vars2;
1306#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
1307#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
1308#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
1309#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
1310#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
1311#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
1312#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1313#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1314#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1315#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1316#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
1317#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
1318#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
1319#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
1320#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN (0x1<<7)
1321#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN_SHIFT 7
1322#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
1323#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
1324#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1325#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1326#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1327#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1328#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1329#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1330#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14)
1331#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14
1332#elif defined(__LITTLE_ENDIAN)
1333 u16 tcp_agg_vars2;
1334#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
1335#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
1336#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
1337#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
1338#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
1339#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
1340#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
1341#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
1342#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
1343#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
1344#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
1345#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
1346#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
1347#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
1348#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN (0x1<<7)
1349#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN_SHIFT 7
1350#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
1351#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
1352#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
1353#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
1354#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
1355#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
1356#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
1357#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
1358#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14)
1359#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14
1360 u8 __agg_val8;
1361 u8 __agg_val8_th;
1362#endif
1363 u32 __sq_base_addr_lo;
1364 u32 __sq_base_addr_hi;
1365 u32 __xfrq_base_addr_lo;
1366 u32 __xfrq_base_addr_hi;
1367#if defined(__BIG_ENDIAN)
1368 u16 __xfrq_cons;
1369 u16 __xfrq_prod;
1370#elif defined(__LITTLE_ENDIAN)
1371 u16 __xfrq_prod;
1372 u16 __xfrq_cons;
1373#endif
1374#if defined(__BIG_ENDIAN)
1375 u8 __tcp_agg_vars5;
1376 u8 __tcp_agg_vars4;
1377 u8 __tcp_agg_vars3;
1378 u8 __reserved_force_pure_ack_cnt;
1379#elif defined(__LITTLE_ENDIAN)
1380 u8 __reserved_force_pure_ack_cnt;
1381 u8 __tcp_agg_vars3;
1382 u8 __tcp_agg_vars4;
1383 u8 __tcp_agg_vars5;
1384#endif
1385 u32 __tcp_agg_vars6;
1386#if defined(__BIG_ENDIAN)
1387 u16 __agg_misc6;
1388 u16 __tcp_agg_vars7;
1389#elif defined(__LITTLE_ENDIAN)
1390 u16 __tcp_agg_vars7;
1391 u16 __agg_misc6;
1392#endif
1393 u32 __agg_val10;
1394 u32 __agg_val10_th;
1395#if defined(__BIG_ENDIAN)
1396 u16 __reserved3;
1397 u8 __reserved2;
1398 u8 __da_only_cnt;
1399#elif defined(__LITTLE_ENDIAN)
1400 u8 __da_only_cnt;
1401 u8 __reserved2;
1402 u16 __reserved3;
1403#endif
1404};
1405
1406/*
1407 * The fcoe aggregative context of Xstorm
1408 */
1409struct xstorm_fcoe_ag_context {
1410#if defined(__BIG_ENDIAN)
1411 u16 agg_val1;
1412 u8 agg_vars1;
1413#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1414#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1415#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1416#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1417#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
1418#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
1419#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
1420#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
1421#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1422#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1423#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
1424#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
1425#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1426#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1427#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
1428#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
1429 u8 __state;
1430#elif defined(__LITTLE_ENDIAN)
1431 u8 __state;
1432 u8 agg_vars1;
1433#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1434#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1435#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1436#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1437#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
1438#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
1439#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
1440#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
1441#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
1442#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
1443#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
1444#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
1445#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
1446#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
1447#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
1448#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
1449 u16 agg_val1;
1450#endif
1451#if defined(__BIG_ENDIAN)
1452 u8 cdu_reserved;
1453 u8 __agg_vars4;
1454 u8 agg_vars3;
1455#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1456#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1457#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
1458#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
1459 u8 agg_vars2;
1460#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
1461#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
1462#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1463#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1464#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1465#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1466#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1467#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1468#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1469#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1470#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1471#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1472#elif defined(__LITTLE_ENDIAN)
1473 u8 agg_vars2;
1474#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
1475#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
1476#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
1477#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
1478#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
1479#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
1480#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
1481#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
1482#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
1483#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
1484#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1485#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1486 u8 agg_vars3;
1487#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
1488#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
1489#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
1490#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
1491 u8 __agg_vars4;
1492 u8 cdu_reserved;
1493#endif
1494 u32 more_to_send;
1495#if defined(__BIG_ENDIAN)
1496 u16 agg_vars5;
1497#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
1498#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
1499#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
1500#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
1501#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
1502#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
1503#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
1504#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
1505 u16 sq_cons;
1506#elif defined(__LITTLE_ENDIAN)
1507 u16 sq_cons;
1508 u16 agg_vars5;
1509#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
1510#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
1511#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
1512#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
1513#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
1514#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
1515#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
1516#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
1517#endif
1518 struct xstorm_fcoe_extra_ag_context_section __extra_section;
1519#if defined(__BIG_ENDIAN)
1520 u16 agg_vars7;
1521#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
1522#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
1523#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
1524#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
1525#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
1526#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
1527#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
1528#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
1529#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
1530#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
1531#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
1532#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
1533#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
1534#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
1535#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
1536#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
1537#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
1538#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
1539#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
1540#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
1541#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
1542#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
1543 u8 agg_val3_th;
1544 u8 agg_vars6;
1545#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
1546#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
1547#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
1548#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
1549#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
1550#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
1551#elif defined(__LITTLE_ENDIAN)
1552 u8 agg_vars6;
1553#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
1554#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
1555#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
1556#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
1557#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
1558#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
1559 u8 agg_val3_th;
1560 u16 agg_vars7;
1561#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
1562#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
1563#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
1564#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
1565#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
1566#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
1567#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
1568#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
1569#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
1570#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
1571#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
1572#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
1573#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
1574#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
1575#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
1576#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
1577#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
1578#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
1579#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
1580#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
1581#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
1582#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
1583#endif
1584#if defined(__BIG_ENDIAN)
1585 u16 __agg_val11_th;
1586 u16 __agg_val11;
1587#elif defined(__LITTLE_ENDIAN)
1588 u16 __agg_val11;
1589 u16 __agg_val11_th;
1590#endif
1591#if defined(__BIG_ENDIAN)
1592 u8 __reserved1;
1593 u8 __agg_val6_th;
1594 u16 __confq_tx_prod;
1595#elif defined(__LITTLE_ENDIAN)
1596 u16 __confq_tx_prod;
1597 u8 __agg_val6_th;
1598 u8 __reserved1;
1599#endif
1600#if defined(__BIG_ENDIAN)
1601 u16 confq_cons;
1602 u16 confq_prod;
1603#elif defined(__LITTLE_ENDIAN)
1604 u16 confq_prod;
1605 u16 confq_cons;
1606#endif
1607 u32 agg_vars8;
1608#define __XSTORM_FCOE_AG_CONTEXT_CACHE_WQE_IDX (0xFFFFFF<<0)
1609#define __XSTORM_FCOE_AG_CONTEXT_CACHE_WQE_IDX_SHIFT 0
1610#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
1611#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
1612#if defined(__BIG_ENDIAN)
1613 u16 ox_id;
1614 u16 sq_prod;
1615#elif defined(__LITTLE_ENDIAN)
1616 u16 sq_prod;
1617 u16 ox_id;
1618#endif
1619#if defined(__BIG_ENDIAN)
1620 u8 agg_val3;
1621 u8 agg_val6;
1622 u8 agg_val5_th;
1623 u8 agg_val5;
1624#elif defined(__LITTLE_ENDIAN)
1625 u8 agg_val5;
1626 u8 agg_val5_th;
1627 u8 agg_val6;
1628 u8 agg_val3;
1629#endif
1630#if defined(__BIG_ENDIAN)
1631 u16 __pbf_tx_seq_ack;
1632 u16 agg_limit1;
1633#elif defined(__LITTLE_ENDIAN)
1634 u16 agg_limit1;
1635 u16 __pbf_tx_seq_ack;
1636#endif
1637 u32 completion_seq;
1638 u32 confq_pbl_base_lo;
1639 u32 confq_pbl_base_hi;
1640};
1641
1642/*
1643 * The fcoe extra aggregative context section of Tstorm
1644 */
1645struct tstorm_fcoe_extra_ag_context_section {
1646 u32 __agg_val1;
1647#if defined(__BIG_ENDIAN)
1648 u8 __tcp_agg_vars2;
1649 u8 __agg_val3;
1650 u16 __agg_val2;
1651#elif defined(__LITTLE_ENDIAN)
1652 u16 __agg_val2;
1653 u8 __agg_val3;
1654 u8 __tcp_agg_vars2;
1655#endif
1656#if defined(__BIG_ENDIAN)
1657 u16 __agg_val5;
1658 u8 __agg_val6;
1659 u8 __tcp_agg_vars3;
1660#elif defined(__LITTLE_ENDIAN)
1661 u8 __tcp_agg_vars3;
1662 u8 __agg_val6;
1663 u16 __agg_val5;
1664#endif
1665 u32 __lcq_prod;
1666 u32 rtt_seq;
1667 u32 rtt_time;
1668 u32 __reserved66;
1669 u32 wnd_right_edge;
1670 u32 tcp_agg_vars1;
1671#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
1672#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
1673#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
1674#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
1675#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
1676#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
1677#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
1678#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
1679#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
1680#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
1681#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
1682#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
1683#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
1684#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
1685#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9)
1686#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9
1687#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
1688#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
1689#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
1690#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
1691#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
1692#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
1693#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
1694#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
1695#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
1696#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
1697#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
1698#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
1699#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
1700#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
1701#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
1702#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
1703#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
1704#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
1705#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
1706#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
1707#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
1708#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
1709#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
1710#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
1711#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
1712#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
1713 u32 snd_max;
1714 u32 __lcq_cons;
1715 u32 __reserved2;
1716};
1717
1718/*
1719 * The fcoe aggregative context of Tstorm
1720 */
1721struct tstorm_fcoe_ag_context {
1722#if defined(__BIG_ENDIAN)
1723 u16 ulp_credit;
1724 u8 agg_vars1;
1725#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1726#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1727#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1728#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1729#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1730#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1731#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1732#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1733#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
1734#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
1735#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
1736#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
1737#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
1738#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
1739 u8 state;
1740#elif defined(__LITTLE_ENDIAN)
1741 u8 state;
1742 u8 agg_vars1;
1743#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1744#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1745#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1746#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1747#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1748#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1749#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1750#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1751#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
1752#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
1753#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
1754#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
1755#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
1756#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
1757 u16 ulp_credit;
1758#endif
1759#if defined(__BIG_ENDIAN)
1760 u16 __agg_val4;
1761 u16 agg_vars2;
1762#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
1763#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
1764#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
1765#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
1766#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
1767#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
1768#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
1769#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
1770#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
1771#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
1772#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
1773#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
1774#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
1775#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
1776#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
1777#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
1778#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
1779#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
1780#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
1781#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
1782#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
1783#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
1784#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
1785#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
1786#elif defined(__LITTLE_ENDIAN)
1787 u16 agg_vars2;
1788#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
1789#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
1790#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
1791#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
1792#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
1793#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
1794#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
1795#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
1796#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
1797#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
1798#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
1799#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
1800#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
1801#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
1802#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
1803#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
1804#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
1805#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
1806#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
1807#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
1808#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
1809#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
1810#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
1811#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
1812 u16 __agg_val4;
1813#endif
1814 struct tstorm_fcoe_extra_ag_context_section __extra_section;
1815};
1816
1817/*
1818 * The fcoe aggregative context of Ustorm
1819 */
1820struct ustorm_fcoe_ag_context {
1821#if defined(__BIG_ENDIAN)
1822 u8 __aux_counter_flags;
1823 u8 agg_vars2;
1824#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
1825#define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
1826#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
1827#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
1828#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1829#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1830#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1831#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1832 u8 agg_vars1;
1833#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1834#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1835#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1836#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1837#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1838#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1839#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1840#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1841#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
1842#define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
1843#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1844#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1845 u8 state;
1846#elif defined(__LITTLE_ENDIAN)
1847 u8 state;
1848 u8 agg_vars1;
1849#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
1850#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
1851#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
1852#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
1853#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
1854#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
1855#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
1856#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
1857#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
1858#define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
1859#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
1860#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
1861 u8 agg_vars2;
1862#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
1863#define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
1864#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
1865#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
1866#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
1867#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
1868#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
1869#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
1870 u8 __aux_counter_flags;
1871#endif
1872#if defined(__BIG_ENDIAN)
1873 u8 cdu_usage;
1874 u8 agg_misc2;
1875 u16 pbf_tx_seq_ack;
1876#elif defined(__LITTLE_ENDIAN)
1877 u16 pbf_tx_seq_ack;
1878 u8 agg_misc2;
1879 u8 cdu_usage;
1880#endif
1881 u32 agg_misc4;
1882#if defined(__BIG_ENDIAN)
1883 u8 agg_val3_th;
1884 u8 agg_val3;
1885 u16 agg_misc3;
1886#elif defined(__LITTLE_ENDIAN)
1887 u16 agg_misc3;
1888 u8 agg_val3;
1889 u8 agg_val3_th;
1890#endif
1891 u32 expired_task_id;
1892 u32 agg_misc4_th;
1893#if defined(__BIG_ENDIAN)
1894 u16 cq_prod;
1895 u16 cq_cons;
1896#elif defined(__LITTLE_ENDIAN)
1897 u16 cq_cons;
1898 u16 cq_prod;
1899#endif
1900#if defined(__BIG_ENDIAN)
1901 u16 __reserved2;
1902 u8 decision_rules;
1903#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
1904#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
1905#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1906#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1907#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
1908#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
1909#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
1910#define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
1911 u8 decision_rule_enable_bits;
1912#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
1913#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
1914#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1915#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1916#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
1917#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
1918#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1919#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1920#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
1921#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
1922#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
1923#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
1924#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1925#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1926#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1927#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1928#elif defined(__LITTLE_ENDIAN)
1929 u8 decision_rule_enable_bits;
1930#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
1931#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
1932#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
1933#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
1934#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
1935#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
1936#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
1937#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
1938#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
1939#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
1940#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
1941#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
1942#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
1943#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
1944#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
1945#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
1946 u8 decision_rules;
1947#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
1948#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
1949#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
1950#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
1951#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
1952#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
1953#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
1954#define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
1955 u16 __reserved2;
1956#endif
1957};
1958
1959/*
1960 * Ethernet context section
1961 */
1962struct xstorm_fcoe_eth_context_section {
1963#if defined(__BIG_ENDIAN)
1964 u8 remote_addr_4;
1965 u8 remote_addr_5;
1966 u8 local_addr_0;
1967 u8 local_addr_1;
1968#elif defined(__LITTLE_ENDIAN)
1969 u8 local_addr_1;
1970 u8 local_addr_0;
1971 u8 remote_addr_5;
1972 u8 remote_addr_4;
1973#endif
1974#if defined(__BIG_ENDIAN)
1975 u8 remote_addr_0;
1976 u8 remote_addr_1;
1977 u8 remote_addr_2;
1978 u8 remote_addr_3;
1979#elif defined(__LITTLE_ENDIAN)
1980 u8 remote_addr_3;
1981 u8 remote_addr_2;
1982 u8 remote_addr_1;
1983 u8 remote_addr_0;
1984#endif
1985#if defined(__BIG_ENDIAN)
1986 u16 reserved_vlan_type;
1987 u16 params;
1988#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
1989#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
1990#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
1991#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
1992#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
1993#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
1994#elif defined(__LITTLE_ENDIAN)
1995 u16 params;
1996#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
1997#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
1998#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
1999#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
2000#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
2001#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
2002 u16 reserved_vlan_type;
2003#endif
2004#if defined(__BIG_ENDIAN)
2005 u8 local_addr_2;
2006 u8 local_addr_3;
2007 u8 local_addr_4;
2008 u8 local_addr_5;
2009#elif defined(__LITTLE_ENDIAN)
2010 u8 local_addr_5;
2011 u8 local_addr_4;
2012 u8 local_addr_3;
2013 u8 local_addr_2;
2014#endif
2015};
2016
2017/*
2018 * Flags used in FCoE context section - 1 byte
2019 */
2020struct xstorm_fcoe_context_flags {
2021 u8 flags;
2022#define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0)
2023#define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
2024#define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2)
2025#define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2
2026#define XSTORM_FCOE_CONTEXT_FLAGS_B_EXCHANGE_CLEANUP_DEFFERED (0x1<<3)
2027#define XSTORM_FCOE_CONTEXT_FLAGS_B_EXCHANGE_CLEANUP_DEFFERED_SHIFT 3
2028#define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4)
2029#define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4
2030#define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5)
2031#define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5
2032#define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6)
2033#define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6
2034#define XSTORM_FCOE_CONTEXT_FLAGS_B_ABTS_DEFFERED (0x1<<7)
2035#define XSTORM_FCOE_CONTEXT_FLAGS_B_ABTS_DEFFERED_SHIFT 7
2036};
2037
2038/*
2039 * FCoE SQ element
2040 */
2041struct fcoe_sqe {
2042 u16 wqe;
2043#define FCOE_SQE_TASK_ID (0x7FFF<<0)
2044#define FCOE_SQE_TASK_ID_SHIFT 0
2045#define FCOE_SQE_TOGGLE_BIT (0x1<<15)
2046#define FCOE_SQE_TOGGLE_BIT_SHIFT 15
2047};
2048
2049/*
2050 * FCoE XFRQ element
2051 */
2052struct fcoe_xfrqe {
2053 u16 wqe;
2054#define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
2055#define FCOE_XFRQE_TASK_ID_SHIFT 0
2056#define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
2057#define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
2058};
2059
2060/*
2061 * FCoE SQ\XFRQ element
2062 */
2063struct fcoe_cached_wqe {
2064#if defined(__BIG_ENDIAN)
2065 struct fcoe_xfrqe xfrqe;
2066 struct fcoe_sqe sqe;
2067#elif defined(__LITTLE_ENDIAN)
2068 struct fcoe_sqe sqe;
2069 struct fcoe_xfrqe xfrqe;
2070#endif
2071};
2072
2073struct fcoe_task_ctx_entry_tx_only {
2074 union fcoe_sgl_ctx sgl_ctx;
2075};
2076
2077struct xstorm_fcoe_task_ctx_entry_rd {
2078 struct fcoe_task_ctx_entry_tx_only tx_wr;
2079 struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
2080 struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
2081 struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
2082};
2083
2084/*
2085 * Cached SGEs
2086 */
2087struct common_fcoe_sgl {
2088 struct fcoe_bd_ctx sge[2];
2089};
2090
2091/*
2092 * FCP_DATA parameters required for transmission
2093 */
2094struct xstorm_fcoe_fcp_data {
2095 u32 io_rem;
2096#if defined(__BIG_ENDIAN)
2097 u16 cached_sge_off;
2098 u8 cached_num_sges;
2099 u8 cached_sge_idx;
2100#elif defined(__LITTLE_ENDIAN)
2101 u8 cached_sge_idx;
2102 u8 cached_num_sges;
2103 u16 cached_sge_off;
2104#endif
2105 struct common_fcoe_sgl cached_sgl;
2106};
2107
2108/*
2109 * FCoE context section
2110 */
2111struct xstorm_fcoe_context_section {
2112#if defined(__BIG_ENDIAN)
2113 u8 vlan_flag;
2114 u8 s_id[3];
2115#elif defined(__LITTLE_ENDIAN)
2116 u8 s_id[3];
2117 u8 vlan_flag;
2118#endif
2119#if defined(__BIG_ENDIAN)
2120 u8 func_id;
2121 u8 d_id[3];
2122#elif defined(__LITTLE_ENDIAN)
2123 u8 d_id[3];
2124 u8 func_id;
2125#endif
2126#if defined(__BIG_ENDIAN)
2127 u16 sq_xfrq_lcq_confq_size;
2128 u16 tx_max_fc_pay_len;
2129#elif defined(__LITTLE_ENDIAN)
2130 u16 tx_max_fc_pay_len;
2131 u16 sq_xfrq_lcq_confq_size;
2132#endif
2133 u32 lcq_prod;
2134#if defined(__BIG_ENDIAN)
2135 u8 port_id;
2136 u8 tx_max_conc_seqs_c3;
2137 u8 seq_id;
2138 struct xstorm_fcoe_context_flags tx_flags;
2139#elif defined(__LITTLE_ENDIAN)
2140 struct xstorm_fcoe_context_flags tx_flags;
2141 u8 seq_id;
2142 u8 tx_max_conc_seqs_c3;
2143 u8 port_id;
2144#endif
2145#if defined(__BIG_ENDIAN)
2146 u16 verify_tx_seq;
2147 u8 func_mode;
2148 u8 vnic_id;
2149#elif defined(__LITTLE_ENDIAN)
2150 u8 vnic_id;
2151 u8 func_mode;
2152 u16 verify_tx_seq;
2153#endif
2154 struct regpair confq_curr_page_addr;
2155 struct fcoe_cached_wqe cached_wqe[8];
2156 struct regpair lcq_base_addr;
2157 struct xstorm_fcoe_task_ctx_entry_rd tce;
2158 struct xstorm_fcoe_fcp_data fcp_data;
2159#if defined(__BIG_ENDIAN)
2160 u16 fcoe_tx_stat_params_ram_addr;
2161 u16 cmng_port_ram_addr;
2162#elif defined(__LITTLE_ENDIAN)
2163 u16 cmng_port_ram_addr;
2164 u16 fcoe_tx_stat_params_ram_addr;
2165#endif
2166#if defined(__BIG_ENDIAN)
2167 u8 fcp_cmd_pb_cmd_size;
2168 u8 eth_hdr_size;
2169 u16 pbf_addr;
2170#elif defined(__LITTLE_ENDIAN)
2171 u16 pbf_addr;
2172 u8 eth_hdr_size;
2173 u8 fcp_cmd_pb_cmd_size;
2174#endif
2175#if defined(__BIG_ENDIAN)
2176 u8 reserved2[2];
2177 u8 cos;
2178 u8 dcb_version;
2179#elif defined(__LITTLE_ENDIAN)
2180 u8 dcb_version;
2181 u8 cos;
2182 u8 reserved2[2];
2183#endif
2184 u32 reserved3;
2185 struct regpair reserved4[2];
2186};
2187
2188/*
2189 * Xstorm FCoE Storm Context
2190 */
2191struct xstorm_fcoe_st_context {
2192 struct xstorm_fcoe_eth_context_section eth;
2193 struct xstorm_fcoe_context_section fcoe;
2194};
2195
2196/*
2197 * Fcoe connection context
2198 */
2199struct fcoe_context {
2200 struct ustorm_fcoe_st_context ustorm_st_context;
2201 struct tstorm_fcoe_st_context tstorm_st_context;
2202 struct xstorm_fcoe_ag_context xstorm_ag_context;
2203 struct tstorm_fcoe_ag_context tstorm_ag_context;
2204 struct ustorm_fcoe_ag_context ustorm_ag_context;
2205 struct timers_block_context timers_context;
2206 struct xstorm_fcoe_st_context xstorm_st_context;
2207};
2208
2209/*
686 * iSCSI context region, used only in iSCSI 2210 * iSCSI context region, used only in iSCSI
687 */ 2211 */
688struct ustorm_iscsi_rq_db { 2212struct ustorm_iscsi_rq_db {
@@ -2268,6 +3792,577 @@ struct iscsi_context {
2268}; 3792};
2269 3793
2270/* 3794/*
3795 * FCoE KCQ CQE parameters
3796 */
3797union fcoe_kcqe_params {
3798 u32 reserved0[4];
3799};
3800
3801/*
3802 * FCoE KCQ CQE
3803 */
3804struct fcoe_kcqe {
3805 u32 fcoe_conn_id;
3806 u32 completion_status;
3807 u32 fcoe_conn_context_id;
3808 union fcoe_kcqe_params params;
3809#if defined(__BIG_ENDIAN)
3810 u8 flags;
3811#define FCOE_KCQE_RESERVED0 (0x7<<0)
3812#define FCOE_KCQE_RESERVED0_SHIFT 0
3813#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
3814#define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
3815#define FCOE_KCQE_LAYER_CODE (0x7<<4)
3816#define FCOE_KCQE_LAYER_CODE_SHIFT 4
3817#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
3818#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
3819 u8 op_code;
3820 u16 qe_self_seq;
3821#elif defined(__LITTLE_ENDIAN)
3822 u16 qe_self_seq;
3823 u8 op_code;
3824 u8 flags;
3825#define FCOE_KCQE_RESERVED0 (0x7<<0)
3826#define FCOE_KCQE_RESERVED0_SHIFT 0
3827#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
3828#define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
3829#define FCOE_KCQE_LAYER_CODE (0x7<<4)
3830#define FCOE_KCQE_LAYER_CODE_SHIFT 4
3831#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
3832#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
3833#endif
3834};
3835
3836/*
3837 * FCoE KWQE header
3838 */
3839struct fcoe_kwqe_header {
3840#if defined(__BIG_ENDIAN)
3841 u8 flags;
3842#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
3843#define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
3844#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
3845#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
3846#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
3847#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
3848 u8 op_code;
3849#elif defined(__LITTLE_ENDIAN)
3850 u8 op_code;
3851 u8 flags;
3852#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
3853#define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
3854#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
3855#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
3856#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
3857#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
3858#endif
3859};
3860
3861/*
3862 * FCoE firmware init request 1
3863 */
3864struct fcoe_kwqe_init1 {
3865#if defined(__BIG_ENDIAN)
3866 struct fcoe_kwqe_header hdr;
3867 u16 num_tasks;
3868#elif defined(__LITTLE_ENDIAN)
3869 u16 num_tasks;
3870 struct fcoe_kwqe_header hdr;
3871#endif
3872 u32 task_list_pbl_addr_lo;
3873 u32 task_list_pbl_addr_hi;
3874 u32 dummy_buffer_addr_lo;
3875 u32 dummy_buffer_addr_hi;
3876#if defined(__BIG_ENDIAN)
3877 u16 rq_num_wqes;
3878 u16 sq_num_wqes;
3879#elif defined(__LITTLE_ENDIAN)
3880 u16 sq_num_wqes;
3881 u16 rq_num_wqes;
3882#endif
3883#if defined(__BIG_ENDIAN)
3884 u16 cq_num_wqes;
3885 u16 rq_buffer_log_size;
3886#elif defined(__LITTLE_ENDIAN)
3887 u16 rq_buffer_log_size;
3888 u16 cq_num_wqes;
3889#endif
3890#if defined(__BIG_ENDIAN)
3891 u8 flags;
3892#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
3893#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
3894#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
3895#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
3896#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
3897#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
3898 u8 num_sessions_log;
3899 u16 mtu;
3900#elif defined(__LITTLE_ENDIAN)
3901 u16 mtu;
3902 u8 num_sessions_log;
3903 u8 flags;
3904#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
3905#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
3906#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
3907#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
3908#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
3909#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
3910#endif
3911};
3912
3913/*
3914 * FCoE firmware init request 2
3915 */
3916struct fcoe_kwqe_init2 {
3917#if defined(__BIG_ENDIAN)
3918 struct fcoe_kwqe_header hdr;
3919 u16 reserved0;
3920#elif defined(__LITTLE_ENDIAN)
3921 u16 reserved0;
3922 struct fcoe_kwqe_header hdr;
3923#endif
3924 u32 hash_tbl_pbl_addr_lo;
3925 u32 hash_tbl_pbl_addr_hi;
3926 u32 t2_hash_tbl_addr_lo;
3927 u32 t2_hash_tbl_addr_hi;
3928 u32 t2_ptr_hash_tbl_addr_lo;
3929 u32 t2_ptr_hash_tbl_addr_hi;
3930 u32 free_list_count;
3931};
3932
3933/*
3934 * FCoE firmware init request 3
3935 */
3936struct fcoe_kwqe_init3 {
3937#if defined(__BIG_ENDIAN)
3938 struct fcoe_kwqe_header hdr;
3939 u16 reserved0;
3940#elif defined(__LITTLE_ENDIAN)
3941 u16 reserved0;
3942 struct fcoe_kwqe_header hdr;
3943#endif
3944 u32 error_bit_map_lo;
3945 u32 error_bit_map_hi;
3946#if defined(__BIG_ENDIAN)
3947 u8 reserved21[3];
3948 u8 cached_session_enable;
3949#elif defined(__LITTLE_ENDIAN)
3950 u8 cached_session_enable;
3951 u8 reserved21[3];
3952#endif
3953 u32 reserved2[4];
3954};
3955
3956/*
3957 * FCoE connection offload request 1
3958 */
3959struct fcoe_kwqe_conn_offload1 {
3960#if defined(__BIG_ENDIAN)
3961 struct fcoe_kwqe_header hdr;
3962 u16 fcoe_conn_id;
3963#elif defined(__LITTLE_ENDIAN)
3964 u16 fcoe_conn_id;
3965 struct fcoe_kwqe_header hdr;
3966#endif
3967 u32 sq_addr_lo;
3968 u32 sq_addr_hi;
3969 u32 rq_pbl_addr_lo;
3970 u32 rq_pbl_addr_hi;
3971 u32 rq_first_pbe_addr_lo;
3972 u32 rq_first_pbe_addr_hi;
3973#if defined(__BIG_ENDIAN)
3974 u16 reserved0;
3975 u16 rq_prod;
3976#elif defined(__LITTLE_ENDIAN)
3977 u16 rq_prod;
3978 u16 reserved0;
3979#endif
3980};
3981
3982/*
3983 * FCoE connection offload request 2
3984 */
3985struct fcoe_kwqe_conn_offload2 {
3986#if defined(__BIG_ENDIAN)
3987 struct fcoe_kwqe_header hdr;
3988 u16 tx_max_fc_pay_len;
3989#elif defined(__LITTLE_ENDIAN)
3990 u16 tx_max_fc_pay_len;
3991 struct fcoe_kwqe_header hdr;
3992#endif
3993 u32 cq_addr_lo;
3994 u32 cq_addr_hi;
3995 u32 xferq_addr_lo;
3996 u32 xferq_addr_hi;
3997 u32 conn_db_addr_lo;
3998 u32 conn_db_addr_hi;
3999 u32 reserved1;
4000};
4001
4002/*
4003 * FCoE connection offload request 3
4004 */
4005struct fcoe_kwqe_conn_offload3 {
4006#if defined(__BIG_ENDIAN)
4007 struct fcoe_kwqe_header hdr;
4008 u16 vlan_tag;
4009#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
4010#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
4011#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
4012#define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
4013#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
4014#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
4015#elif defined(__LITTLE_ENDIAN)
4016 u16 vlan_tag;
4017#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
4018#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
4019#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
4020#define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
4021#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
4022#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
4023 struct fcoe_kwqe_header hdr;
4024#endif
4025#if defined(__BIG_ENDIAN)
4026 u8 tx_max_conc_seqs_c3;
4027 u8 s_id[3];
4028#elif defined(__LITTLE_ENDIAN)
4029 u8 s_id[3];
4030 u8 tx_max_conc_seqs_c3;
4031#endif
4032#if defined(__BIG_ENDIAN)
4033 u8 flags;
4034#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
4035#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
4036#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
4037#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
4038#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
4039#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
4040#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
4041#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
4042#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
4043#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
4044#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
4045#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
4046#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
4047#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
4048#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
4049#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
4050 u8 d_id[3];
4051#elif defined(__LITTLE_ENDIAN)
4052 u8 d_id[3];
4053 u8 flags;
4054#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
4055#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
4056#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
4057#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
4058#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
4059#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
4060#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
4061#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
4062#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
4063#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
4064#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
4065#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
4066#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
4067#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
4068#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
4069#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
4070#endif
4071 u32 reserved;
4072 u32 confq_first_pbe_addr_lo;
4073 u32 confq_first_pbe_addr_hi;
4074#if defined(__BIG_ENDIAN)
4075 u16 rx_max_fc_pay_len;
4076 u16 tx_total_conc_seqs;
4077#elif defined(__LITTLE_ENDIAN)
4078 u16 tx_total_conc_seqs;
4079 u16 rx_max_fc_pay_len;
4080#endif
4081#if defined(__BIG_ENDIAN)
4082 u8 rx_open_seqs_exch_c3;
4083 u8 rx_max_conc_seqs_c3;
4084 u16 rx_total_conc_seqs;
4085#elif defined(__LITTLE_ENDIAN)
4086 u16 rx_total_conc_seqs;
4087 u8 rx_max_conc_seqs_c3;
4088 u8 rx_open_seqs_exch_c3;
4089#endif
4090};
4091
4092/*
4093 * FCoE connection offload request 4
4094 */
4095struct fcoe_kwqe_conn_offload4 {
4096#if defined(__BIG_ENDIAN)
4097 struct fcoe_kwqe_header hdr;
4098 u8 reserved2;
4099 u8 e_d_tov_timer_val;
4100#elif defined(__LITTLE_ENDIAN)
4101 u8 e_d_tov_timer_val;
4102 u8 reserved2;
4103 struct fcoe_kwqe_header hdr;
4104#endif
4105 u8 src_mac_addr_lo32[4];
4106#if defined(__BIG_ENDIAN)
4107 u8 dst_mac_addr_hi16[2];
4108 u8 src_mac_addr_hi16[2];
4109#elif defined(__LITTLE_ENDIAN)
4110 u8 src_mac_addr_hi16[2];
4111 u8 dst_mac_addr_hi16[2];
4112#endif
4113 u8 dst_mac_addr_lo32[4];
4114 u32 lcq_addr_lo;
4115 u32 lcq_addr_hi;
4116 u32 confq_pbl_base_addr_lo;
4117 u32 confq_pbl_base_addr_hi;
4118};
4119
4120/*
4121 * FCoE connection enable request
4122 */
4123struct fcoe_kwqe_conn_enable_disable {
4124#if defined(__BIG_ENDIAN)
4125 struct fcoe_kwqe_header hdr;
4126 u16 reserved0;
4127#elif defined(__LITTLE_ENDIAN)
4128 u16 reserved0;
4129 struct fcoe_kwqe_header hdr;
4130#endif
4131 u8 src_mac_addr_lo32[4];
4132#if defined(__BIG_ENDIAN)
4133 u16 vlan_tag;
4134#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
4135#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
4136#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
4137#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
4138#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
4139#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
4140 u8 src_mac_addr_hi16[2];
4141#elif defined(__LITTLE_ENDIAN)
4142 u8 src_mac_addr_hi16[2];
4143 u16 vlan_tag;
4144#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
4145#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
4146#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
4147#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
4148#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
4149#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
4150#endif
4151 u8 dst_mac_addr_lo32[4];
4152#if defined(__BIG_ENDIAN)
4153 u16 reserved1;
4154 u8 dst_mac_addr_hi16[2];
4155#elif defined(__LITTLE_ENDIAN)
4156 u8 dst_mac_addr_hi16[2];
4157 u16 reserved1;
4158#endif
4159#if defined(__BIG_ENDIAN)
4160 u8 vlan_flag;
4161 u8 s_id[3];
4162#elif defined(__LITTLE_ENDIAN)
4163 u8 s_id[3];
4164 u8 vlan_flag;
4165#endif
4166#if defined(__BIG_ENDIAN)
4167 u8 reserved3;
4168 u8 d_id[3];
4169#elif defined(__LITTLE_ENDIAN)
4170 u8 d_id[3];
4171 u8 reserved3;
4172#endif
4173 u32 context_id;
4174 u32 conn_id;
4175 u32 reserved4;
4176};
4177
4178/*
4179 * FCoE connection destroy request
4180 */
4181struct fcoe_kwqe_conn_destroy {
4182#if defined(__BIG_ENDIAN)
4183 struct fcoe_kwqe_header hdr;
4184 u16 reserved0;
4185#elif defined(__LITTLE_ENDIAN)
4186 u16 reserved0;
4187 struct fcoe_kwqe_header hdr;
4188#endif
4189 u32 context_id;
4190 u32 conn_id;
4191 u32 reserved1[5];
4192};
4193
4194/*
4195 * FCoe destroy request
4196 */
4197struct fcoe_kwqe_destroy {
4198#if defined(__BIG_ENDIAN)
4199 struct fcoe_kwqe_header hdr;
4200 u16 reserved0;
4201#elif defined(__LITTLE_ENDIAN)
4202 u16 reserved0;
4203 struct fcoe_kwqe_header hdr;
4204#endif
4205 u32 reserved1[7];
4206};
4207
4208/*
4209 * FCoe statistics request
4210 */
4211struct fcoe_kwqe_stat {
4212#if defined(__BIG_ENDIAN)
4213 struct fcoe_kwqe_header hdr;
4214 u16 reserved0;
4215#elif defined(__LITTLE_ENDIAN)
4216 u16 reserved0;
4217 struct fcoe_kwqe_header hdr;
4218#endif
4219 u32 stat_params_addr_lo;
4220 u32 stat_params_addr_hi;
4221 u32 reserved1[5];
4222};
4223
4224/*
4225 * FCoE KWQ WQE
4226 */
4227union fcoe_kwqe {
4228 struct fcoe_kwqe_init1 init1;
4229 struct fcoe_kwqe_init2 init2;
4230 struct fcoe_kwqe_init3 init3;
4231 struct fcoe_kwqe_conn_offload1 conn_offload1;
4232 struct fcoe_kwqe_conn_offload2 conn_offload2;
4233 struct fcoe_kwqe_conn_offload3 conn_offload3;
4234 struct fcoe_kwqe_conn_offload4 conn_offload4;
4235 struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
4236 struct fcoe_kwqe_conn_destroy conn_destroy;
4237 struct fcoe_kwqe_destroy destroy;
4238 struct fcoe_kwqe_stat statistics;
4239};
4240
4241struct fcoe_task_ctx_entry {
4242 struct fcoe_task_ctx_entry_tx_only tx_wr_only;
4243 struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
4244 struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
4245 struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
4246 struct fcoe_task_ctx_entry_rx_only rx_wr_only;
4247 u32 reserved[4];
4248};
4249
4250/*
4251 * FCoE connection enable\disable params passed by driver to FW in FCoE enable ramrod
4252 */
4253struct fcoe_conn_enable_disable_ramrod_params {
4254 struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe;
4255};
4256
4257
4258/*
4259 * FCoE connection offload params passed by driver to FW in FCoE offload ramrod
4260 */
4261struct fcoe_conn_offload_ramrod_params {
4262 struct fcoe_kwqe_conn_offload1 offload_kwqe1;
4263 struct fcoe_kwqe_conn_offload2 offload_kwqe2;
4264 struct fcoe_kwqe_conn_offload3 offload_kwqe3;
4265 struct fcoe_kwqe_conn_offload4 offload_kwqe4;
4266};
4267
4268/*
4269 * FCoE init params passed by driver to FW in FCoE init ramrod
4270 */
4271struct fcoe_init_ramrod_params {
4272 struct fcoe_kwqe_init1 init_kwqe1;
4273 struct fcoe_kwqe_init2 init_kwqe2;
4274 struct fcoe_kwqe_init3 init_kwqe3;
4275 struct regpair eq_addr;
4276 struct regpair eq_next_page_addr;
4277#if defined(__BIG_ENDIAN)
4278 u16 sb_num;
4279 u16 eq_prod;
4280#elif defined(__LITTLE_ENDIAN)
4281 u16 eq_prod;
4282 u16 sb_num;
4283#endif
4284#if defined(__BIG_ENDIAN)
4285 u16 reserved1;
4286 u8 reserved0;
4287 u8 sb_id;
4288#elif defined(__LITTLE_ENDIAN)
4289 u8 sb_id;
4290 u8 reserved0;
4291 u16 reserved1;
4292#endif
4293};
4294
4295
4296/*
4297 * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod
4298 */
4299struct fcoe_stat_ramrod_params {
4300 struct fcoe_kwqe_stat stat_kwqe;
4301};
4302
4303
4304/*
4305 * FCoE 16-bits vlan structure
4306 */
4307struct fcoe_vlan_fields {
4308 u16 fields;
4309#define FCOE_VLAN_FIELDS_VID (0xFFF<<0)
4310#define FCOE_VLAN_FIELDS_VID_SHIFT 0
4311#define FCOE_VLAN_FIELDS_CLI (0x1<<12)
4312#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
4313#define FCOE_VLAN_FIELDS_PRI (0x7<<13)
4314#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
4315};
4316
4317
4318/*
4319 * FCoE 16-bits vlan union
4320 */
4321union fcoe_vlan_field_union {
4322 struct fcoe_vlan_fields fields;
4323 u16 val;
4324};
4325
4326/*
4327 * Parameters used for Class 2 verifications
4328 */
4329struct ustorm_fcoe_c2_params {
4330#if defined(__BIG_ENDIAN)
4331 u16 e2e_credit;
4332 u16 con_seq;
4333#elif defined(__LITTLE_ENDIAN)
4334 u16 con_seq;
4335 u16 e2e_credit;
4336#endif
4337#if defined(__BIG_ENDIAN)
4338 u16 ackq_prod;
4339 u16 open_seq_per_exch;
4340#elif defined(__LITTLE_ENDIAN)
4341 u16 open_seq_per_exch;
4342 u16 ackq_prod;
4343#endif
4344 struct regpair ackq_pbl_base;
4345 struct regpair ackq_cur_seg;
4346};
4347
4348/*
4349 * Parameters used for Class 2 verifications
4350 */
4351struct xstorm_fcoe_c2_params {
4352#if defined(__BIG_ENDIAN)
4353 u16 reserved0;
4354 u8 ackq_x_prod;
4355 u8 max_conc_seqs_c2;
4356#elif defined(__LITTLE_ENDIAN)
4357 u8 max_conc_seqs_c2;
4358 u8 ackq_x_prod;
4359 u16 reserved0;
4360#endif
4361 struct regpair ackq_pbl_base;
4362 struct regpair ackq_cur_seg;
4363};
4364
4365/*
2271 * Buffer per connection, used in Tstorm 4366 * Buffer per connection, used in Tstorm
2272 */ 4367 */
2273struct iscsi_conn_buf { 4368struct iscsi_conn_buf {
diff --git a/drivers/net/cnic_if.h b/drivers/net/cnic_if.h
index 33333e735f95..ccd814068c4d 100644
--- a/drivers/net/cnic_if.h
+++ b/drivers/net/cnic_if.h
@@ -12,22 +12,31 @@
12#ifndef CNIC_IF_H 12#ifndef CNIC_IF_H
13#define CNIC_IF_H 13#define CNIC_IF_H
14 14
15#define CNIC_MODULE_VERSION "2.2.6" 15#define CNIC_MODULE_VERSION "2.2.11"
16#define CNIC_MODULE_RELDATE "Oct 12, 2010" 16#define CNIC_MODULE_RELDATE "Dec 22, 2010"
17 17
18#define CNIC_ULP_RDMA 0 18#define CNIC_ULP_RDMA 0
19#define CNIC_ULP_ISCSI 1 19#define CNIC_ULP_ISCSI 1
20#define CNIC_ULP_L4 2 20#define CNIC_ULP_FCOE 2
21#define MAX_CNIC_ULP_TYPE_EXT 2 21#define CNIC_ULP_L4 3
22#define MAX_CNIC_ULP_TYPE 3 22#define MAX_CNIC_ULP_TYPE_EXT 3
23#define MAX_CNIC_ULP_TYPE 4
23 24
24struct kwqe { 25struct kwqe {
25 u32 kwqe_op_flag; 26 u32 kwqe_op_flag;
26 27
28#define KWQE_QID_SHIFT 8
27#define KWQE_OPCODE_MASK 0x00ff0000 29#define KWQE_OPCODE_MASK 0x00ff0000
28#define KWQE_OPCODE_SHIFT 16 30#define KWQE_OPCODE_SHIFT 16
29#define KWQE_FLAGS_LAYER_SHIFT 28
30#define KWQE_OPCODE(x) ((x & KWQE_OPCODE_MASK) >> KWQE_OPCODE_SHIFT) 31#define KWQE_OPCODE(x) ((x & KWQE_OPCODE_MASK) >> KWQE_OPCODE_SHIFT)
32#define KWQE_LAYER_MASK 0x70000000
33#define KWQE_LAYER_SHIFT 28
34#define KWQE_FLAGS_LAYER_MASK_L2 (2<<28)
35#define KWQE_FLAGS_LAYER_MASK_L3 (3<<28)
36#define KWQE_FLAGS_LAYER_MASK_L4 (4<<28)
37#define KWQE_FLAGS_LAYER_MASK_L5_RDMA (5<<28)
38#define KWQE_FLAGS_LAYER_MASK_L5_ISCSI (6<<28)
39#define KWQE_FLAGS_LAYER_MASK_L5_FCOE (7<<28)
31 40
32 u32 kwqe_info0; 41 u32 kwqe_info0;
33 u32 kwqe_info1; 42 u32 kwqe_info1;
@@ -62,6 +71,7 @@ struct kcqe {
62 #define KCQE_FLAGS_LAYER_MASK_L4 (4<<28) 71 #define KCQE_FLAGS_LAYER_MASK_L4 (4<<28)
63 #define KCQE_FLAGS_LAYER_MASK_L5_RDMA (5<<28) 72 #define KCQE_FLAGS_LAYER_MASK_L5_RDMA (5<<28)
64 #define KCQE_FLAGS_LAYER_MASK_L5_ISCSI (6<<28) 73 #define KCQE_FLAGS_LAYER_MASK_L5_ISCSI (6<<28)
74 #define KCQE_FLAGS_LAYER_MASK_L5_FCOE (7<<28)
65 #define KCQE_FLAGS_NEXT (1<<31) 75 #define KCQE_FLAGS_NEXT (1<<31)
66 #define KCQE_FLAGS_OPCODE_MASK (0xff<<16) 76 #define KCQE_FLAGS_OPCODE_MASK (0xff<<16)
67 #define KCQE_FLAGS_OPCODE_SHIFT (16) 77 #define KCQE_FLAGS_OPCODE_SHIFT (16)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 07:49:32 -0500