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authorVinod Koul <vinod.koul@linux.intel.com>2011-10-13 13:04:23 -0400
committerVinod Koul <vinod.koul@linux.intel.com>2011-10-27 11:23:43 -0400
commitdb8196df4bb6f117caa163aa73b0f16fd62290bd (patch)
treeb86531031482037d9b31ad57479f2f7091020957
parent49920bc66984a512f4bcc7735a61642cd0e4d6f2 (diff)
dmaengine: move drivers to dma_transfer_direction
fixup usage of dma direction by introducing dma_transfer_direction, this patch moves dma/drivers/* to use new enum Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Mika Westerberg <mika.westerberg@iki.fi> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Li Yang <leoli@freescale.com> Cc: Zhang Wei <zw@zh-kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Yong Wang <yong.y.wang@intel.com> Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com> Cc: Boojin Kim <boojin.kim@samsung.com> Cc: Barry Song <Baohua.Song@csr.com> Acked-by: Mika Westerberg <mika.westerberg@iki.fi> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
-rw-r--r--arch/arm/mach-ep93xx/include/mach/dma.h6
-rw-r--r--arch/arm/plat-nomadik/include/plat/ste_dma40.h4
-rw-r--r--drivers/dma/amba-pl08x.c24
-rw-r--r--drivers/dma/at_hdmac.c22
-rw-r--r--drivers/dma/coh901318.c12
-rw-r--r--drivers/dma/coh901318_lli.c23
-rw-r--r--drivers/dma/coh901318_lli.h4
-rw-r--r--drivers/dma/dw_dmac.c14
-rw-r--r--drivers/dma/ep93xx_dma.c22
-rw-r--r--drivers/dma/fsldma.c4
-rw-r--r--drivers/dma/imx-dma.c10
-rw-r--r--drivers/dma/imx-sdma.c10
-rw-r--r--drivers/dma/intel_mid_dma.c14
-rw-r--r--drivers/dma/intel_mid_dma_regs.h2
-rw-r--r--drivers/dma/ipu/ipu_idmac.c4
-rw-r--r--drivers/dma/mxs-dma.c8
-rw-r--r--drivers/dma/pch_dma.c12
-rw-r--r--drivers/dma/pl330.c18
-rw-r--r--drivers/dma/shdma.c25
-rw-r--r--drivers/dma/ste_dma40.c26
-rw-r--r--drivers/dma/timb_dma.c18
-rw-r--r--drivers/dma/txx9dmac.c12
-rw-r--r--include/linux/amba/pl08x.h4
-rw-r--r--include/linux/dw_dmac.h2
-rw-r--r--include/linux/sh_dma.h2
25 files changed, 150 insertions, 152 deletions
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
index 46d4d876e6fb..e82c642fa53c 100644
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -37,7 +37,7 @@
37 */ 37 */
38struct ep93xx_dma_data { 38struct ep93xx_dma_data {
39 int port; 39 int port;
40 enum dma_data_direction direction; 40 enum dma_transfer_direction direction;
41 const char *name; 41 const char *name;
42}; 42};
43 43
@@ -80,14 +80,14 @@ static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
80 * channel supports given DMA direction. Only M2P channels have such 80 * channel supports given DMA direction. Only M2P channels have such
81 * limitation, for M2M channels the direction is configurable. 81 * limitation, for M2M channels the direction is configurable.
82 */ 82 */
83static inline enum dma_data_direction 83static inline enum dma_transfer_direction
84ep93xx_dma_chan_direction(struct dma_chan *chan) 84ep93xx_dma_chan_direction(struct dma_chan *chan)
85{ 85{
86 if (!ep93xx_dma_chan_is_m2p(chan)) 86 if (!ep93xx_dma_chan_is_m2p(chan))
87 return DMA_NONE; 87 return DMA_NONE;
88 88
89 /* even channels are for TX, odd for RX */ 89 /* even channels are for TX, odd for RX */
90 return (chan->chan_id % 2 == 0) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 90 return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
91} 91}
92 92
93#endif /* __ASM_ARCH_DMA_H */ 93#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
index 685c78716d95..38b041a40db4 100644
--- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h
+++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
@@ -187,7 +187,7 @@ static inline struct
187dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, 187dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
188 dma_addr_t addr, 188 dma_addr_t addr,
189 unsigned int size, 189 unsigned int size,
190 enum dma_data_direction direction, 190 enum dma_transfer_direction direction,
191 unsigned long flags) 191 unsigned long flags)
192{ 192{
193 struct scatterlist sg; 193 struct scatterlist sg;
@@ -209,7 +209,7 @@ static inline struct
209dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, 209dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
210 dma_addr_t addr, 210 dma_addr_t addr,
211 unsigned int size, 211 unsigned int size,
212 enum dma_data_direction direction, 212 enum dma_transfer_direction direction,
213 unsigned long flags) 213 unsigned long flags)
214{ 214{
215 return NULL; 215 return NULL;
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index b7cbd1ab1db1..41c62fd0680d 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -882,9 +882,9 @@ static int prep_phy_channel(struct pl08x_dma_chan *plchan,
882 ch->signal = ret; 882 ch->signal = ret;
883 883
884 /* Assign the flow control signal to this channel */ 884 /* Assign the flow control signal to this channel */
885 if (txd->direction == DMA_TO_DEVICE) 885 if (txd->direction == DMA_MEM_TO_DEV)
886 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT; 886 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
887 else if (txd->direction == DMA_FROM_DEVICE) 887 else if (txd->direction == DMA_DEV_TO_MEM)
888 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT; 888 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
889 } 889 }
890 890
@@ -1102,10 +1102,10 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1102 1102
1103 /* Transfer direction */ 1103 /* Transfer direction */
1104 plchan->runtime_direction = config->direction; 1104 plchan->runtime_direction = config->direction;
1105 if (config->direction == DMA_TO_DEVICE) { 1105 if (config->direction == DMA_MEM_TO_DEV) {
1106 addr_width = config->dst_addr_width; 1106 addr_width = config->dst_addr_width;
1107 maxburst = config->dst_maxburst; 1107 maxburst = config->dst_maxburst;
1108 } else if (config->direction == DMA_FROM_DEVICE) { 1108 } else if (config->direction == DMA_DEV_TO_MEM) {
1109 addr_width = config->src_addr_width; 1109 addr_width = config->src_addr_width;
1110 maxburst = config->src_maxburst; 1110 maxburst = config->src_maxburst;
1111 } else { 1111 } else {
@@ -1136,7 +1136,7 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1136 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; 1136 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1137 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; 1137 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1138 1138
1139 if (plchan->runtime_direction == DMA_FROM_DEVICE) { 1139 if (plchan->runtime_direction == DMA_DEV_TO_MEM) {
1140 plchan->src_addr = config->src_addr; 1140 plchan->src_addr = config->src_addr;
1141 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR | 1141 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1142 pl08x_select_bus(plchan->cd->periph_buses, 1142 pl08x_select_bus(plchan->cd->periph_buses,
@@ -1152,7 +1152,7 @@ static int dma_set_runtime_config(struct dma_chan *chan,
1152 "configured channel %s (%s) for %s, data width %d, " 1152 "configured channel %s (%s) for %s, data width %d, "
1153 "maxburst %d words, LE, CCTL=0x%08x\n", 1153 "maxburst %d words, LE, CCTL=0x%08x\n",
1154 dma_chan_name(chan), plchan->name, 1154 dma_chan_name(chan), plchan->name,
1155 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", 1155 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
1156 addr_width, 1156 addr_width,
1157 maxburst, 1157 maxburst,
1158 cctl); 1158 cctl);
@@ -1322,7 +1322,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1322 1322
1323static struct dma_async_tx_descriptor *pl08x_prep_slave_sg( 1323static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1324 struct dma_chan *chan, struct scatterlist *sgl, 1324 struct dma_chan *chan, struct scatterlist *sgl,
1325 unsigned int sg_len, enum dma_data_direction direction, 1325 unsigned int sg_len, enum dma_transfer_direction direction,
1326 unsigned long flags) 1326 unsigned long flags)
1327{ 1327{
1328 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan); 1328 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
@@ -1354,10 +1354,10 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1354 */ 1354 */
1355 txd->direction = direction; 1355 txd->direction = direction;
1356 1356
1357 if (direction == DMA_TO_DEVICE) { 1357 if (direction == DMA_MEM_TO_DEV) {
1358 txd->cctl = plchan->dst_cctl; 1358 txd->cctl = plchan->dst_cctl;
1359 slave_addr = plchan->dst_addr; 1359 slave_addr = plchan->dst_addr;
1360 } else if (direction == DMA_FROM_DEVICE) { 1360 } else if (direction == DMA_DEV_TO_MEM) {
1361 txd->cctl = plchan->src_cctl; 1361 txd->cctl = plchan->src_cctl;
1362 slave_addr = plchan->src_addr; 1362 slave_addr = plchan->src_addr;
1363 } else { 1363 } else {
@@ -1368,10 +1368,10 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1368 } 1368 }
1369 1369
1370 if (plchan->cd->device_fc) 1370 if (plchan->cd->device_fc)
1371 tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER_PER : 1371 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
1372 PL080_FLOW_PER2MEM_PER; 1372 PL080_FLOW_PER2MEM_PER;
1373 else 1373 else
1374 tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER : 1374 tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
1375 PL080_FLOW_PER2MEM; 1375 PL080_FLOW_PER2MEM;
1376 1376
1377 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT; 1377 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
@@ -1387,7 +1387,7 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1387 list_add_tail(&dsg->node, &txd->dsg_list); 1387 list_add_tail(&dsg->node, &txd->dsg_list);
1388 1388
1389 dsg->len = sg_dma_len(sg); 1389 dsg->len = sg_dma_len(sg);
1390 if (direction == DMA_TO_DEVICE) { 1390 if (direction == DMA_MEM_TO_DEV) {
1391 dsg->src_addr = sg_phys(sg); 1391 dsg->src_addr = sg_phys(sg);
1392 dsg->dst_addr = slave_addr; 1392 dsg->dst_addr = slave_addr;
1393 } else { 1393 } else {
diff --git a/drivers/dma/at_hdmac.c b/drivers/dma/at_hdmac.c
index fcfa0a8b5c59..7e76574e83ec 100644
--- a/drivers/dma/at_hdmac.c
+++ b/drivers/dma/at_hdmac.c
@@ -660,7 +660,7 @@ err_desc_get:
660 */ 660 */
661static struct dma_async_tx_descriptor * 661static struct dma_async_tx_descriptor *
662atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 662atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
663 unsigned int sg_len, enum dma_data_direction direction, 663 unsigned int sg_len, enum dma_transfer_direction direction,
664 unsigned long flags) 664 unsigned long flags)
665{ 665{
666 struct at_dma_chan *atchan = to_at_dma_chan(chan); 666 struct at_dma_chan *atchan = to_at_dma_chan(chan);
@@ -678,7 +678,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
678 678
679 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", 679 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
680 sg_len, 680 sg_len,
681 direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", 681 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
682 flags); 682 flags);
683 683
684 if (unlikely(!atslave || !sg_len)) { 684 if (unlikely(!atslave || !sg_len)) {
@@ -692,7 +692,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
692 ctrlb = ATC_IEN; 692 ctrlb = ATC_IEN;
693 693
694 switch (direction) { 694 switch (direction) {
695 case DMA_TO_DEVICE: 695 case DMA_MEM_TO_DEV:
696 ctrla |= ATC_DST_WIDTH(reg_width); 696 ctrla |= ATC_DST_WIDTH(reg_width);
697 ctrlb |= ATC_DST_ADDR_MODE_FIXED 697 ctrlb |= ATC_DST_ADDR_MODE_FIXED
698 | ATC_SRC_ADDR_MODE_INCR 698 | ATC_SRC_ADDR_MODE_INCR
@@ -725,7 +725,7 @@ atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
725 total_len += len; 725 total_len += len;
726 } 726 }
727 break; 727 break;
728 case DMA_FROM_DEVICE: 728 case DMA_DEV_TO_MEM:
729 ctrla |= ATC_SRC_WIDTH(reg_width); 729 ctrla |= ATC_SRC_WIDTH(reg_width);
730 ctrlb |= ATC_DST_ADDR_MODE_INCR 730 ctrlb |= ATC_DST_ADDR_MODE_INCR
731 | ATC_SRC_ADDR_MODE_FIXED 731 | ATC_SRC_ADDR_MODE_FIXED
@@ -787,7 +787,7 @@ err_desc_get:
787 */ 787 */
788static int 788static int
789atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, 789atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
790 size_t period_len, enum dma_data_direction direction) 790 size_t period_len, enum dma_transfer_direction direction)
791{ 791{
792 if (period_len > (ATC_BTSIZE_MAX << reg_width)) 792 if (period_len > (ATC_BTSIZE_MAX << reg_width))
793 goto err_out; 793 goto err_out;
@@ -795,7 +795,7 @@ atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
795 goto err_out; 795 goto err_out;
796 if (unlikely(buf_addr & ((1 << reg_width) - 1))) 796 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
797 goto err_out; 797 goto err_out;
798 if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) 798 if (unlikely(!(direction & (DMA_DEV_TO_MEM | DMA_MEM_TO_DEV))))
799 goto err_out; 799 goto err_out;
800 800
801 return 0; 801 return 0;
@@ -810,7 +810,7 @@ err_out:
810static int 810static int
811atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc, 811atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
812 unsigned int period_index, dma_addr_t buf_addr, 812 unsigned int period_index, dma_addr_t buf_addr,
813 size_t period_len, enum dma_data_direction direction) 813 size_t period_len, enum dma_transfer_direction direction)
814{ 814{
815 u32 ctrla; 815 u32 ctrla;
816 unsigned int reg_width = atslave->reg_width; 816 unsigned int reg_width = atslave->reg_width;
@@ -822,7 +822,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
822 | period_len >> reg_width; 822 | period_len >> reg_width;
823 823
824 switch (direction) { 824 switch (direction) {
825 case DMA_TO_DEVICE: 825 case DMA_MEM_TO_DEV:
826 desc->lli.saddr = buf_addr + (period_len * period_index); 826 desc->lli.saddr = buf_addr + (period_len * period_index);
827 desc->lli.daddr = atslave->tx_reg; 827 desc->lli.daddr = atslave->tx_reg;
828 desc->lli.ctrla = ctrla; 828 desc->lli.ctrla = ctrla;
@@ -833,7 +833,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
833 | ATC_DIF(AT_DMA_PER_IF); 833 | ATC_DIF(AT_DMA_PER_IF);
834 break; 834 break;
835 835
836 case DMA_FROM_DEVICE: 836 case DMA_DEV_TO_MEM:
837 desc->lli.saddr = atslave->rx_reg; 837 desc->lli.saddr = atslave->rx_reg;
838 desc->lli.daddr = buf_addr + (period_len * period_index); 838 desc->lli.daddr = buf_addr + (period_len * period_index);
839 desc->lli.ctrla = ctrla; 839 desc->lli.ctrla = ctrla;
@@ -861,7 +861,7 @@ atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc,
861 */ 861 */
862static struct dma_async_tx_descriptor * 862static struct dma_async_tx_descriptor *
863atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 863atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
864 size_t period_len, enum dma_data_direction direction) 864 size_t period_len, enum dma_transfer_direction direction)
865{ 865{
866 struct at_dma_chan *atchan = to_at_dma_chan(chan); 866 struct at_dma_chan *atchan = to_at_dma_chan(chan);
867 struct at_dma_slave *atslave = chan->private; 867 struct at_dma_slave *atslave = chan->private;
@@ -872,7 +872,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
872 unsigned int i; 872 unsigned int i;
873 873
874 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", 874 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
875 direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", 875 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
876 buf_addr, 876 buf_addr,
877 periods, buf_len, period_len); 877 periods, buf_len, period_len);
878 878
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 4234f416ef11..d65a718c0f9b 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -39,7 +39,7 @@ struct coh901318_desc {
39 struct scatterlist *sg; 39 struct scatterlist *sg;
40 unsigned int sg_len; 40 unsigned int sg_len;
41 struct coh901318_lli *lli; 41 struct coh901318_lli *lli;
42 enum dma_data_direction dir; 42 enum dma_transfer_direction dir;
43 unsigned long flags; 43 unsigned long flags;
44 u32 head_config; 44 u32 head_config;
45 u32 head_ctrl; 45 u32 head_ctrl;
@@ -1034,7 +1034,7 @@ coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1034 1034
1035static struct dma_async_tx_descriptor * 1035static struct dma_async_tx_descriptor *
1036coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 1036coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1037 unsigned int sg_len, enum dma_data_direction direction, 1037 unsigned int sg_len, enum dma_transfer_direction direction,
1038 unsigned long flags) 1038 unsigned long flags)
1039{ 1039{
1040 struct coh901318_chan *cohc = to_coh901318_chan(chan); 1040 struct coh901318_chan *cohc = to_coh901318_chan(chan);
@@ -1077,7 +1077,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1077 ctrl_last |= cohc->runtime_ctrl; 1077 ctrl_last |= cohc->runtime_ctrl;
1078 ctrl |= cohc->runtime_ctrl; 1078 ctrl |= cohc->runtime_ctrl;
1079 1079
1080 if (direction == DMA_TO_DEVICE) { 1080 if (direction == DMA_MEM_TO_DEV) {
1081 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | 1081 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1082 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE; 1082 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1083 1083
@@ -1085,7 +1085,7 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1085 ctrl_chained |= tx_flags; 1085 ctrl_chained |= tx_flags;
1086 ctrl_last |= tx_flags; 1086 ctrl_last |= tx_flags;
1087 ctrl |= tx_flags; 1087 ctrl |= tx_flags;
1088 } else if (direction == DMA_FROM_DEVICE) { 1088 } else if (direction == DMA_DEV_TO_MEM) {
1089 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST | 1089 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1090 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE; 1090 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1091 1091
@@ -1274,11 +1274,11 @@ static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
1274 int i = 0; 1274 int i = 0;
1275 1275
1276 /* We only support mem to per or per to mem transfers */ 1276 /* We only support mem to per or per to mem transfers */
1277 if (config->direction == DMA_FROM_DEVICE) { 1277 if (config->direction == DMA_DEV_TO_MEM) {
1278 addr = config->src_addr; 1278 addr = config->src_addr;
1279 addr_width = config->src_addr_width; 1279 addr_width = config->src_addr_width;
1280 maxburst = config->src_maxburst; 1280 maxburst = config->src_maxburst;
1281 } else if (config->direction == DMA_TO_DEVICE) { 1281 } else if (config->direction == DMA_MEM_TO_DEV) {
1282 addr = config->dst_addr; 1282 addr = config->dst_addr;
1283 addr_width = config->dst_addr_width; 1283 addr_width = config->dst_addr_width;
1284 maxburst = config->dst_maxburst; 1284 maxburst = config->dst_maxburst;
diff --git a/drivers/dma/coh901318_lli.c b/drivers/dma/coh901318_lli.c
index 9f7e0e6a7eea..6c0e2d4c6682 100644
--- a/drivers/dma/coh901318_lli.c
+++ b/drivers/dma/coh901318_lli.c
@@ -7,11 +7,10 @@
7 * Author: Per Friden <per.friden@stericsson.com> 7 * Author: Per Friden <per.friden@stericsson.com>
8 */ 8 */
9 9
10#include <linux/dma-mapping.h>
11#include <linux/spinlock.h> 10#include <linux/spinlock.h>
12#include <linux/dmapool.h>
13#include <linux/memory.h> 11#include <linux/memory.h>
14#include <linux/gfp.h> 12#include <linux/gfp.h>
13#include <linux/dmapool.h>
15#include <mach/coh901318.h> 14#include <mach/coh901318.h>
16 15
17#include "coh901318_lli.h" 16#include "coh901318_lli.h"
@@ -177,18 +176,18 @@ coh901318_lli_fill_single(struct coh901318_pool *pool,
177 struct coh901318_lli *lli, 176 struct coh901318_lli *lli,
178 dma_addr_t buf, unsigned int size, 177 dma_addr_t buf, unsigned int size,
179 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom, 178 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
180 enum dma_data_direction dir) 179 enum dma_transfer_direction dir)
181{ 180{
182 int s = size; 181 int s = size;
183 dma_addr_t src; 182 dma_addr_t src;
184 dma_addr_t dst; 183 dma_addr_t dst;
185 184
186 185
187 if (dir == DMA_TO_DEVICE) { 186 if (dir == DMA_MEM_TO_DEV) {
188 src = buf; 187 src = buf;
189 dst = dev_addr; 188 dst = dev_addr;
190 189
191 } else if (dir == DMA_FROM_DEVICE) { 190 } else if (dir == DMA_DEV_TO_MEM) {
192 191
193 src = dev_addr; 192 src = dev_addr;
194 dst = buf; 193 dst = buf;
@@ -215,9 +214,9 @@ coh901318_lli_fill_single(struct coh901318_pool *pool,
215 214
216 lli = coh901318_lli_next(lli); 215 lli = coh901318_lli_next(lli);
217 216
218 if (dir == DMA_TO_DEVICE) 217 if (dir == DMA_MEM_TO_DEV)
219 src += block_size; 218 src += block_size;
220 else if (dir == DMA_FROM_DEVICE) 219 else if (dir == DMA_DEV_TO_MEM)
221 dst += block_size; 220 dst += block_size;
222 } 221 }
223 222
@@ -234,7 +233,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
234 struct scatterlist *sgl, unsigned int nents, 233 struct scatterlist *sgl, unsigned int nents,
235 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl, 234 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
236 u32 ctrl_last, 235 u32 ctrl_last,
237 enum dma_data_direction dir, u32 ctrl_irq_mask) 236 enum dma_transfer_direction dir, u32 ctrl_irq_mask)
238{ 237{
239 int i; 238 int i;
240 struct scatterlist *sg; 239 struct scatterlist *sg;
@@ -249,9 +248,9 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
249 248
250 spin_lock(&pool->lock); 249 spin_lock(&pool->lock);
251 250
252 if (dir == DMA_TO_DEVICE) 251 if (dir == DMA_MEM_TO_DEV)
253 dst = dev_addr; 252 dst = dev_addr;
254 else if (dir == DMA_FROM_DEVICE) 253 else if (dir == DMA_DEV_TO_MEM)
255 src = dev_addr; 254 src = dev_addr;
256 else 255 else
257 goto err; 256 goto err;
@@ -269,7 +268,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
269 ctrl_sg = ctrl ? ctrl : ctrl_last; 268 ctrl_sg = ctrl ? ctrl : ctrl_last;
270 269
271 270
272 if (dir == DMA_TO_DEVICE) 271 if (dir == DMA_MEM_TO_DEV)
273 /* increment source address */ 272 /* increment source address */
274 src = sg_phys(sg); 273 src = sg_phys(sg);
275 else 274 else
@@ -293,7 +292,7 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
293 lli->src_addr = src; 292 lli->src_addr = src;
294 lli->dst_addr = dst; 293 lli->dst_addr = dst;
295 294
296 if (dir == DMA_FROM_DEVICE) 295 if (dir == DMA_DEV_TO_MEM)
297 dst += elem_size; 296 dst += elem_size;
298 else 297 else
299 src += elem_size; 298 src += elem_size;
diff --git a/drivers/dma/coh901318_lli.h b/drivers/dma/coh901318_lli.h
index 7a5c80990e9e..abff3714fdda 100644
--- a/drivers/dma/coh901318_lli.h
+++ b/drivers/dma/coh901318_lli.h
@@ -97,7 +97,7 @@ coh901318_lli_fill_single(struct coh901318_pool *pool,
97 struct coh901318_lli *lli, 97 struct coh901318_lli *lli,
98 dma_addr_t buf, unsigned int size, 98 dma_addr_t buf, unsigned int size,
99 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last, 99 dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last,
100 enum dma_data_direction dir); 100 enum dma_transfer_direction dir);
101 101
102/** 102/**
103 * coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer 103 * coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer
@@ -119,6 +119,6 @@ coh901318_lli_fill_sg(struct coh901318_pool *pool,
119 struct scatterlist *sg, unsigned int nents, 119 struct scatterlist *sg, unsigned int nents,
120 dma_addr_t dev_addr, u32 ctrl_chained, 120 dma_addr_t dev_addr, u32 ctrl_chained,
121 u32 ctrl, u32 ctrl_last, 121 u32 ctrl, u32 ctrl_last,
122 enum dma_data_direction dir, u32 ctrl_irq_mask); 122 enum dma_transfer_direction dir, u32 ctrl_irq_mask);
123 123
124#endif /* COH901318_LLI_H */ 124#endif /* COH901318_LLI_H */
diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
index 9bfd6d360718..decca1c3c83d 100644
--- a/drivers/dma/dw_dmac.c
+++ b/drivers/dma/dw_dmac.c
@@ -696,7 +696,7 @@ err_desc_get:
696 696
697static struct dma_async_tx_descriptor * 697static struct dma_async_tx_descriptor *
698dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 698dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
699 unsigned int sg_len, enum dma_data_direction direction, 699 unsigned int sg_len, enum dma_transfer_direction direction,
700 unsigned long flags) 700 unsigned long flags)
701{ 701{
702 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 702 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
@@ -720,7 +720,7 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
720 prev = first = NULL; 720 prev = first = NULL;
721 721
722 switch (direction) { 722 switch (direction) {
723 case DMA_TO_DEVICE: 723 case DMA_MEM_TO_DEV:
724 ctllo = (DWC_DEFAULT_CTLLO(chan->private) 724 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
725 | DWC_CTLL_DST_WIDTH(reg_width) 725 | DWC_CTLL_DST_WIDTH(reg_width)
726 | DWC_CTLL_DST_FIX 726 | DWC_CTLL_DST_FIX
@@ -777,7 +777,7 @@ slave_sg_todev_fill_desc:
777 goto slave_sg_todev_fill_desc; 777 goto slave_sg_todev_fill_desc;
778 } 778 }
779 break; 779 break;
780 case DMA_FROM_DEVICE: 780 case DMA_DEV_TO_MEM:
781 ctllo = (DWC_DEFAULT_CTLLO(chan->private) 781 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
782 | DWC_CTLL_SRC_WIDTH(reg_width) 782 | DWC_CTLL_SRC_WIDTH(reg_width)
783 | DWC_CTLL_DST_INC 783 | DWC_CTLL_DST_INC
@@ -1165,7 +1165,7 @@ EXPORT_SYMBOL(dw_dma_cyclic_stop);
1165 */ 1165 */
1166struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 1166struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1167 dma_addr_t buf_addr, size_t buf_len, size_t period_len, 1167 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1168 enum dma_data_direction direction) 1168 enum dma_transfer_direction direction)
1169{ 1169{
1170 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1170 struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
1171 struct dw_cyclic_desc *cdesc; 1171 struct dw_cyclic_desc *cdesc;
@@ -1206,7 +1206,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1206 goto out_err; 1206 goto out_err;
1207 if (unlikely(buf_addr & ((1 << reg_width) - 1))) 1207 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1208 goto out_err; 1208 goto out_err;
1209 if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) 1209 if (unlikely(!(direction & (DMA_MEM_TO_DEV | DMA_DEV_TO_MEM))))
1210 goto out_err; 1210 goto out_err;
1211 1211
1212 retval = ERR_PTR(-ENOMEM); 1212 retval = ERR_PTR(-ENOMEM);
@@ -1228,7 +1228,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1228 goto out_err_desc_get; 1228 goto out_err_desc_get;
1229 1229
1230 switch (direction) { 1230 switch (direction) {
1231 case DMA_TO_DEVICE: 1231 case DMA_MEM_TO_DEV:
1232 desc->lli.dar = dws->tx_reg; 1232 desc->lli.dar = dws->tx_reg;
1233 desc->lli.sar = buf_addr + (period_len * i); 1233 desc->lli.sar = buf_addr + (period_len * i);
1234 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) 1234 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
@@ -1239,7 +1239,7 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1239 | DWC_CTLL_FC(dws->fc) 1239 | DWC_CTLL_FC(dws->fc)
1240 | DWC_CTLL_INT_EN); 1240 | DWC_CTLL_INT_EN);
1241 break; 1241 break;
1242 case DMA_FROM_DEVICE: 1242 case DMA_DEV_TO_MEM:
1243 desc->lli.dar = buf_addr + (period_len * i); 1243 desc->lli.dar = buf_addr + (period_len * i);
1244 desc->lli.sar = dws->rx_reg; 1244 desc->lli.sar = dws->rx_reg;
1245 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private) 1245 desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c
index b47e2b803faf..009851b2aeea 100644
--- a/drivers/dma/ep93xx_dma.c
+++ b/drivers/dma/ep93xx_dma.c
@@ -330,7 +330,7 @@ static void m2p_fill_desc(struct ep93xx_dma_chan *edmac)
330 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac); 330 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
331 u32 bus_addr; 331 u32 bus_addr;
332 332
333 if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_TO_DEVICE) 333 if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_MEM_TO_DEV)
334 bus_addr = desc->src_addr; 334 bus_addr = desc->src_addr;
335 else 335 else
336 bus_addr = desc->dst_addr; 336 bus_addr = desc->dst_addr;
@@ -443,7 +443,7 @@ static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
443 control = (5 << M2M_CONTROL_PWSC_SHIFT); 443 control = (5 << M2M_CONTROL_PWSC_SHIFT);
444 control |= M2M_CONTROL_NO_HDSK; 444 control |= M2M_CONTROL_NO_HDSK;
445 445
446 if (data->direction == DMA_TO_DEVICE) { 446 if (data->direction == DMA_MEM_TO_DEV) {
447 control |= M2M_CONTROL_DAH; 447 control |= M2M_CONTROL_DAH;
448 control |= M2M_CONTROL_TM_TX; 448 control |= M2M_CONTROL_TM_TX;
449 control |= M2M_CONTROL_RSS_SSPTX; 449 control |= M2M_CONTROL_RSS_SSPTX;
@@ -463,7 +463,7 @@ static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
463 control |= M2M_CONTROL_RSS_IDE; 463 control |= M2M_CONTROL_RSS_IDE;
464 control |= M2M_CONTROL_PW_16; 464 control |= M2M_CONTROL_PW_16;
465 465
466 if (data->direction == DMA_TO_DEVICE) { 466 if (data->direction == DMA_MEM_TO_DEV) {
467 /* Worst case from the UG */ 467 /* Worst case from the UG */
468 control = (3 << M2M_CONTROL_PWSC_SHIFT); 468 control = (3 << M2M_CONTROL_PWSC_SHIFT);
469 control |= M2M_CONTROL_DAH; 469 control |= M2M_CONTROL_DAH;
@@ -803,8 +803,8 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
803 switch (data->port) { 803 switch (data->port) {
804 case EP93XX_DMA_SSP: 804 case EP93XX_DMA_SSP:
805 case EP93XX_DMA_IDE: 805 case EP93XX_DMA_IDE:
806 if (data->direction != DMA_TO_DEVICE && 806 if (data->direction != DMA_MEM_TO_DEV &&
807 data->direction != DMA_FROM_DEVICE) 807 data->direction != DMA_DEV_TO_MEM)
808 return -EINVAL; 808 return -EINVAL;
809 break; 809 break;
810 default: 810 default:
@@ -952,7 +952,7 @@ fail:
952 */ 952 */
953static struct dma_async_tx_descriptor * 953static struct dma_async_tx_descriptor *
954ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 954ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
955 unsigned int sg_len, enum dma_data_direction dir, 955 unsigned int sg_len, enum dma_transfer_direction dir,
956 unsigned long flags) 956 unsigned long flags)
957{ 957{
958 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan); 958 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
@@ -988,7 +988,7 @@ ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
988 goto fail; 988 goto fail;
989 } 989 }
990 990
991 if (dir == DMA_TO_DEVICE) { 991 if (dir == DMA_MEM_TO_DEV) {
992 desc->src_addr = sg_dma_address(sg); 992 desc->src_addr = sg_dma_address(sg);
993 desc->dst_addr = edmac->runtime_addr; 993 desc->dst_addr = edmac->runtime_addr;
994 } else { 994 } else {
@@ -1032,7 +1032,7 @@ fail:
1032static struct dma_async_tx_descriptor * 1032static struct dma_async_tx_descriptor *
1033ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, 1033ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
1034 size_t buf_len, size_t period_len, 1034 size_t buf_len, size_t period_len,
1035 enum dma_data_direction dir) 1035 enum dma_transfer_direction dir)
1036{ 1036{
1037 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan); 1037 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1038 struct ep93xx_dma_desc *desc, *first; 1038 struct ep93xx_dma_desc *desc, *first;
@@ -1065,7 +1065,7 @@ ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
1065 goto fail; 1065 goto fail;
1066 } 1066 }
1067 1067
1068 if (dir == DMA_TO_DEVICE) { 1068 if (dir == DMA_MEM_TO_DEV) {
1069 desc->src_addr = dma_addr + offset; 1069 desc->src_addr = dma_addr + offset;
1070 desc->dst_addr = edmac->runtime_addr; 1070 desc->dst_addr = edmac->runtime_addr;
1071 } else { 1071 } else {
@@ -1133,12 +1133,12 @@ static int ep93xx_dma_slave_config(struct ep93xx_dma_chan *edmac,
1133 return -EINVAL; 1133 return -EINVAL;
1134 1134
1135 switch (config->direction) { 1135 switch (config->direction) {
1136 case DMA_FROM_DEVICE: 1136 case DMA_DEV_TO_MEM:
1137 width = config->src_addr_width; 1137 width = config->src_addr_width;
1138 addr = config->src_addr; 1138 addr = config->src_addr;
1139 break; 1139 break;
1140 1140
1141 case DMA_TO_DEVICE: 1141 case DMA_MEM_TO_DEV:
1142 width = config->dst_addr_width; 1142 width = config->dst_addr_width;
1143 addr = config->dst_addr; 1143 addr = config->dst_addr;
1144 break; 1144 break;
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 8a781540590c..b98070c33ca9 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -772,7 +772,7 @@ fail:
772 */ 772 */
773static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( 773static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
774 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 774 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
775 enum dma_data_direction direction, unsigned long flags) 775 enum dma_transfer_direction direction, unsigned long flags)
776{ 776{
777 /* 777 /*
778 * This operation is not supported on the Freescale DMA controller 778 * This operation is not supported on the Freescale DMA controller
@@ -819,7 +819,7 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
819 return -ENXIO; 819 return -ENXIO;
820 820
821 /* we set the controller burst size depending on direction */ 821 /* we set the controller burst size depending on direction */
822 if (config->direction == DMA_TO_DEVICE) 822 if (config->direction == DMA_MEM_TO_DEV)
823 size = config->dst_addr_width * config->dst_maxburst; 823 size = config->dst_addr_width * config->dst_maxburst;
824 else 824 else
825 size = config->src_addr_width * config->src_maxburst; 825 size = config->src_addr_width * config->src_maxburst;
diff --git a/drivers/dma/imx-dma.c b/drivers/dma/imx-dma.c
index d746899f36e1..678cd01dc42c 100644
--- a/drivers/dma/imx-dma.c
+++ b/drivers/dma/imx-dma.c
@@ -106,7 +106,7 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
106 imx_dma_disable(imxdmac->imxdma_channel); 106 imx_dma_disable(imxdmac->imxdma_channel);
107 return 0; 107 return 0;
108 case DMA_SLAVE_CONFIG: 108 case DMA_SLAVE_CONFIG:
109 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) { 109 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
110 imxdmac->per_address = dmaengine_cfg->src_addr; 110 imxdmac->per_address = dmaengine_cfg->src_addr;
111 imxdmac->watermark_level = dmaengine_cfg->src_maxburst; 111 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
112 imxdmac->word_size = dmaengine_cfg->src_addr_width; 112 imxdmac->word_size = dmaengine_cfg->src_addr_width;
@@ -223,7 +223,7 @@ static void imxdma_free_chan_resources(struct dma_chan *chan)
223 223
224static struct dma_async_tx_descriptor *imxdma_prep_slave_sg( 224static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
225 struct dma_chan *chan, struct scatterlist *sgl, 225 struct dma_chan *chan, struct scatterlist *sgl,
226 unsigned int sg_len, enum dma_data_direction direction, 226 unsigned int sg_len, enum dma_transfer_direction direction,
227 unsigned long flags) 227 unsigned long flags)
228{ 228{
229 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 229 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
@@ -240,7 +240,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
240 dma_length += sg->length; 240 dma_length += sg->length;
241 } 241 }
242 242
243 if (direction == DMA_FROM_DEVICE) 243 if (direction == DMA_DEV_TO_MEM)
244 dmamode = DMA_MODE_READ; 244 dmamode = DMA_MODE_READ;
245 else 245 else
246 dmamode = DMA_MODE_WRITE; 246 dmamode = DMA_MODE_WRITE;
@@ -270,7 +270,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
270 270
271static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic( 271static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
272 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 272 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
273 size_t period_len, enum dma_data_direction direction) 273 size_t period_len, enum dma_transfer_direction direction)
274{ 274{
275 struct imxdma_channel *imxdmac = to_imxdma_chan(chan); 275 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
276 struct imxdma_engine *imxdma = imxdmac->imxdma; 276 struct imxdma_engine *imxdma = imxdmac->imxdma;
@@ -316,7 +316,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
316 imxdmac->sg_list[periods].page_link = 316 imxdmac->sg_list[periods].page_link =
317 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02; 317 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
318 318
319 if (direction == DMA_FROM_DEVICE) 319 if (direction == DMA_DEV_TO_MEM)
320 dmamode = DMA_MODE_READ; 320 dmamode = DMA_MODE_READ;
321 else 321 else
322 dmamode = DMA_MODE_WRITE; 322 dmamode = DMA_MODE_WRITE;
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index eab1fe71259e..065de5442c93 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -246,7 +246,7 @@ struct sdma_engine;
246struct sdma_channel { 246struct sdma_channel {
247 struct sdma_engine *sdma; 247 struct sdma_engine *sdma;
248 unsigned int channel; 248 unsigned int channel;
249 enum dma_data_direction direction; 249 enum dma_transfer_direction direction;
250 enum sdma_peripheral_type peripheral_type; 250 enum sdma_peripheral_type peripheral_type;
251 unsigned int event_id0; 251 unsigned int event_id0;
252 unsigned int event_id1; 252 unsigned int event_id1;
@@ -649,7 +649,7 @@ static int sdma_load_context(struct sdma_channel *sdmac)
649 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd; 649 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
650 int ret; 650 int ret;
651 651
652 if (sdmac->direction == DMA_FROM_DEVICE) { 652 if (sdmac->direction == DMA_DEV_TO_MEM) {
653 load_address = sdmac->pc_from_device; 653 load_address = sdmac->pc_from_device;
654 } else { 654 } else {
655 load_address = sdmac->pc_to_device; 655 load_address = sdmac->pc_to_device;
@@ -910,7 +910,7 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
910 910
911static struct dma_async_tx_descriptor *sdma_prep_slave_sg( 911static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
912 struct dma_chan *chan, struct scatterlist *sgl, 912 struct dma_chan *chan, struct scatterlist *sgl,
913 unsigned int sg_len, enum dma_data_direction direction, 913 unsigned int sg_len, enum dma_transfer_direction direction,
914 unsigned long flags) 914 unsigned long flags)
915{ 915{
916 struct sdma_channel *sdmac = to_sdma_chan(chan); 916 struct sdma_channel *sdmac = to_sdma_chan(chan);
@@ -1007,7 +1007,7 @@ err_out:
1007 1007
1008static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( 1008static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1009 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 1009 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1010 size_t period_len, enum dma_data_direction direction) 1010 size_t period_len, enum dma_transfer_direction direction)
1011{ 1011{
1012 struct sdma_channel *sdmac = to_sdma_chan(chan); 1012 struct sdma_channel *sdmac = to_sdma_chan(chan);
1013 struct sdma_engine *sdma = sdmac->sdma; 1013 struct sdma_engine *sdma = sdmac->sdma;
@@ -1092,7 +1092,7 @@ static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1092 sdma_disable_channel(sdmac); 1092 sdma_disable_channel(sdmac);
1093 return 0; 1093 return 0;
1094 case DMA_SLAVE_CONFIG: 1094 case DMA_SLAVE_CONFIG:
1095 if (dmaengine_cfg->direction == DMA_FROM_DEVICE) { 1095 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1096 sdmac->per_address = dmaengine_cfg->src_addr; 1096 sdmac->per_address = dmaengine_cfg->src_addr;
1097 sdmac->watermark_level = dmaengine_cfg->src_maxburst; 1097 sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1098 sdmac->word_size = dmaengine_cfg->src_addr_width; 1098 sdmac->word_size = dmaengine_cfg->src_addr_width;
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 9e96c43a846a..6deda25fd0a8 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -394,10 +394,10 @@ static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc,
394 midc->dma->block_size); 394 midc->dma->block_size);
395 /*Populate SAR and DAR values*/ 395 /*Populate SAR and DAR values*/
396 sg_phy_addr = sg_phys(sg); 396 sg_phy_addr = sg_phys(sg);
397 if (desc->dirn == DMA_TO_DEVICE) { 397 if (desc->dirn == DMA_MEM_TO_DEV) {
398 lli_bloc_desc->sar = sg_phy_addr; 398 lli_bloc_desc->sar = sg_phy_addr;
399 lli_bloc_desc->dar = mids->dma_slave.dst_addr; 399 lli_bloc_desc->dar = mids->dma_slave.dst_addr;
400 } else if (desc->dirn == DMA_FROM_DEVICE) { 400 } else if (desc->dirn == DMA_DEV_TO_MEM) {
401 lli_bloc_desc->sar = mids->dma_slave.src_addr; 401 lli_bloc_desc->sar = mids->dma_slave.src_addr;
402 lli_bloc_desc->dar = sg_phy_addr; 402 lli_bloc_desc->dar = sg_phy_addr;
403 } 403 }
@@ -631,13 +631,13 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
631 if (midc->dma->pimr_mask) { 631 if (midc->dma->pimr_mask) {
632 cfg_hi.cfgx.protctl = 0x0; /*default value*/ 632 cfg_hi.cfgx.protctl = 0x0; /*default value*/
633 cfg_hi.cfgx.fifo_mode = 1; 633 cfg_hi.cfgx.fifo_mode = 1;
634 if (mids->dma_slave.direction == DMA_TO_DEVICE) { 634 if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
635 cfg_hi.cfgx.src_per = 0; 635 cfg_hi.cfgx.src_per = 0;
636 if (mids->device_instance == 0) 636 if (mids->device_instance == 0)
637 cfg_hi.cfgx.dst_per = 3; 637 cfg_hi.cfgx.dst_per = 3;
638 if (mids->device_instance == 1) 638 if (mids->device_instance == 1)
639 cfg_hi.cfgx.dst_per = 1; 639 cfg_hi.cfgx.dst_per = 1;
640 } else if (mids->dma_slave.direction == DMA_FROM_DEVICE) { 640 } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
641 if (mids->device_instance == 0) 641 if (mids->device_instance == 0)
642 cfg_hi.cfgx.src_per = 2; 642 cfg_hi.cfgx.src_per = 2;
643 if (mids->device_instance == 1) 643 if (mids->device_instance == 1)
@@ -681,11 +681,11 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
681 ctl_lo.ctlx.sinc = 0; 681 ctl_lo.ctlx.sinc = 0;
682 ctl_lo.ctlx.dinc = 0; 682 ctl_lo.ctlx.dinc = 0;
683 } else { 683 } else {
684 if (mids->dma_slave.direction == DMA_TO_DEVICE) { 684 if (mids->dma_slave.direction == DMA_MEM_TO_DEV) {
685 ctl_lo.ctlx.sinc = 0; 685 ctl_lo.ctlx.sinc = 0;
686 ctl_lo.ctlx.dinc = 2; 686 ctl_lo.ctlx.dinc = 2;
687 ctl_lo.ctlx.tt_fc = 1; 687 ctl_lo.ctlx.tt_fc = 1;
688 } else if (mids->dma_slave.direction == DMA_FROM_DEVICE) { 688 } else if (mids->dma_slave.direction == DMA_DEV_TO_MEM) {
689 ctl_lo.ctlx.sinc = 2; 689 ctl_lo.ctlx.sinc = 2;
690 ctl_lo.ctlx.dinc = 0; 690 ctl_lo.ctlx.dinc = 0;
691 ctl_lo.ctlx.tt_fc = 2; 691 ctl_lo.ctlx.tt_fc = 2;
@@ -731,7 +731,7 @@ err_desc_get:
731 */ 731 */
732static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg( 732static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
733 struct dma_chan *chan, struct scatterlist *sgl, 733 struct dma_chan *chan, struct scatterlist *sgl,
734 unsigned int sg_len, enum dma_data_direction direction, 734 unsigned int sg_len, enum dma_transfer_direction direction,
735 unsigned long flags) 735 unsigned long flags)
736{ 736{
737 struct intel_mid_dma_chan *midc = NULL; 737 struct intel_mid_dma_chan *midc = NULL;
diff --git a/drivers/dma/intel_mid_dma_regs.h b/drivers/dma/intel_mid_dma_regs.h
index aea5ee88ce03..c6de919a6401 100644
--- a/drivers/dma/intel_mid_dma_regs.h
+++ b/drivers/dma/intel_mid_dma_regs.h
@@ -262,7 +262,7 @@ struct intel_mid_dma_desc {
262 unsigned int lli_length; 262 unsigned int lli_length;
263 unsigned int current_lli; 263 unsigned int current_lli;
264 dma_addr_t next; 264 dma_addr_t next;
265 enum dma_data_direction dirn; 265 enum dma_transfer_direction dirn;
266 enum dma_status status; 266 enum dma_status status;
267 enum dma_slave_buswidth width; /*width of DMA txn*/ 267 enum dma_slave_buswidth width; /*width of DMA txn*/
268 enum intel_mid_dma_mode cfg_mode; /*mode configuration*/ 268 enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index 6815905a772f..0cee3b30cd77 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1362,7 +1362,7 @@ static void ipu_gc_tasklet(unsigned long arg)
1362/* Allocate and initialise a transfer descriptor. */ 1362/* Allocate and initialise a transfer descriptor. */
1363static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan, 1363static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1364 struct scatterlist *sgl, unsigned int sg_len, 1364 struct scatterlist *sgl, unsigned int sg_len,
1365 enum dma_data_direction direction, unsigned long tx_flags) 1365 enum dma_transfer_direction direction, unsigned long tx_flags)
1366{ 1366{
1367 struct idmac_channel *ichan = to_idmac_chan(chan); 1367 struct idmac_channel *ichan = to_idmac_chan(chan);
1368 struct idmac_tx_desc *desc = NULL; 1368 struct idmac_tx_desc *desc = NULL;
@@ -1374,7 +1374,7 @@ static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan
1374 chan->chan_id != IDMAC_IC_7) 1374 chan->chan_id != IDMAC_IC_7)
1375 return NULL; 1375 return NULL;
1376 1376
1377 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) { 1377 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) {
1378 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction); 1378 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1379 return NULL; 1379 return NULL;
1380 } 1380 }
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index b4588bdd98bb..bdf4672b2553 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -377,7 +377,7 @@ static void mxs_dma_free_chan_resources(struct dma_chan *chan)
377 377
378static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg( 378static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
379 struct dma_chan *chan, struct scatterlist *sgl, 379 struct dma_chan *chan, struct scatterlist *sgl,
380 unsigned int sg_len, enum dma_data_direction direction, 380 unsigned int sg_len, enum dma_transfer_direction direction,
381 unsigned long append) 381 unsigned long append)
382{ 382{
383 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 383 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
@@ -450,7 +450,7 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
450 ccw->bits |= CCW_CHAIN; 450 ccw->bits |= CCW_CHAIN;
451 ccw->bits |= CCW_HALT_ON_TERM; 451 ccw->bits |= CCW_HALT_ON_TERM;
452 ccw->bits |= CCW_TERM_FLUSH; 452 ccw->bits |= CCW_TERM_FLUSH;
453 ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ? 453 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
454 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, 454 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
455 COMMAND); 455 COMMAND);
456 456
@@ -472,7 +472,7 @@ err_out:
472 472
473static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic( 473static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
474 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 474 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
475 size_t period_len, enum dma_data_direction direction) 475 size_t period_len, enum dma_transfer_direction direction)
476{ 476{
477 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan); 477 struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
478 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma; 478 struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
@@ -515,7 +515,7 @@ static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
515 ccw->bits |= CCW_IRQ; 515 ccw->bits |= CCW_IRQ;
516 ccw->bits |= CCW_HALT_ON_TERM; 516 ccw->bits |= CCW_HALT_ON_TERM;
517 ccw->bits |= CCW_TERM_FLUSH; 517 ccw->bits |= CCW_TERM_FLUSH;
518 ccw->bits |= BF_CCW(direction == DMA_FROM_DEVICE ? 518 ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
519 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND); 519 MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
520 520
521 dma_addr += period_len; 521 dma_addr += period_len;
diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index a6d0e3dbed07..9944e8295498 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -99,7 +99,7 @@ struct pch_dma_desc {
99struct pch_dma_chan { 99struct pch_dma_chan {
100 struct dma_chan chan; 100 struct dma_chan chan;
101 void __iomem *membase; 101 void __iomem *membase;
102 enum dma_data_direction dir; 102 enum dma_transfer_direction dir;
103 struct tasklet_struct tasklet; 103 struct tasklet_struct tasklet;
104 unsigned long err_status; 104 unsigned long err_status;
105 105
@@ -224,7 +224,7 @@ static void pdc_set_dir(struct dma_chan *chan)
224 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS << 224 mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
225 (DMA_CTL0_BITS_PER_CH * chan->chan_id)); 225 (DMA_CTL0_BITS_PER_CH * chan->chan_id));
226 val &= mask_mode; 226 val &= mask_mode;
227 if (pd_chan->dir == DMA_TO_DEVICE) 227 if (pd_chan->dir == DMA_MEM_TO_DEV)
228 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id + 228 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
229 DMA_CTL0_DIR_SHIFT_BITS); 229 DMA_CTL0_DIR_SHIFT_BITS);
230 else 230 else
@@ -242,7 +242,7 @@ static void pdc_set_dir(struct dma_chan *chan)
242 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS << 242 mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
243 (DMA_CTL0_BITS_PER_CH * ch)); 243 (DMA_CTL0_BITS_PER_CH * ch));
244 val &= mask_mode; 244 val &= mask_mode;
245 if (pd_chan->dir == DMA_TO_DEVICE) 245 if (pd_chan->dir == DMA_MEM_TO_DEV)
246 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch + 246 val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch +
247 DMA_CTL0_DIR_SHIFT_BITS); 247 DMA_CTL0_DIR_SHIFT_BITS);
248 else 248 else
@@ -607,7 +607,7 @@ static void pd_issue_pending(struct dma_chan *chan)
607 607
608static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan, 608static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
609 struct scatterlist *sgl, unsigned int sg_len, 609 struct scatterlist *sgl, unsigned int sg_len,
610 enum dma_data_direction direction, unsigned long flags) 610 enum dma_transfer_direction direction, unsigned long flags)
611{ 611{
612 struct pch_dma_chan *pd_chan = to_pd_chan(chan); 612 struct pch_dma_chan *pd_chan = to_pd_chan(chan);
613 struct pch_dma_slave *pd_slave = chan->private; 613 struct pch_dma_slave *pd_slave = chan->private;
@@ -623,9 +623,9 @@ static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan,
623 return NULL; 623 return NULL;
624 } 624 }
625 625
626 if (direction == DMA_FROM_DEVICE) 626 if (direction == DMA_DEV_TO_MEM)
627 reg = pd_slave->rx_reg; 627 reg = pd_slave->rx_reg;
628 else if (direction == DMA_TO_DEVICE) 628 else if (direction == DMA_MEM_TO_DEV)
629 reg = pd_slave->tx_reg; 629 reg = pd_slave->tx_reg;
630 else 630 else
631 return NULL; 631 return NULL;
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 571041477ab2..1e58eeb030d8 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -320,14 +320,14 @@ static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned
320 case DMA_SLAVE_CONFIG: 320 case DMA_SLAVE_CONFIG:
321 slave_config = (struct dma_slave_config *)arg; 321 slave_config = (struct dma_slave_config *)arg;
322 322
323 if (slave_config->direction == DMA_TO_DEVICE) { 323 if (slave_config->direction == DMA_MEM_TO_DEV) {
324 if (slave_config->dst_addr) 324 if (slave_config->dst_addr)
325 pch->fifo_addr = slave_config->dst_addr; 325 pch->fifo_addr = slave_config->dst_addr;
326 if (slave_config->dst_addr_width) 326 if (slave_config->dst_addr_width)
327 pch->burst_sz = __ffs(slave_config->dst_addr_width); 327 pch->burst_sz = __ffs(slave_config->dst_addr_width);
328 if (slave_config->dst_maxburst) 328 if (slave_config->dst_maxburst)
329 pch->burst_len = slave_config->dst_maxburst; 329 pch->burst_len = slave_config->dst_maxburst;
330 } else if (slave_config->direction == DMA_FROM_DEVICE) { 330 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
331 if (slave_config->src_addr) 331 if (slave_config->src_addr)
332 pch->fifo_addr = slave_config->src_addr; 332 pch->fifo_addr = slave_config->src_addr;
333 if (slave_config->src_addr_width) 333 if (slave_config->src_addr_width)
@@ -597,7 +597,7 @@ static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
597 597
598static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 598static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
599 struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 599 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
600 size_t period_len, enum dma_data_direction direction) 600 size_t period_len, enum dma_transfer_direction direction)
601{ 601{
602 struct dma_pl330_desc *desc; 602 struct dma_pl330_desc *desc;
603 struct dma_pl330_chan *pch = to_pchan(chan); 603 struct dma_pl330_chan *pch = to_pchan(chan);
@@ -612,13 +612,13 @@ static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
612 } 612 }
613 613
614 switch (direction) { 614 switch (direction) {
615 case DMA_TO_DEVICE: 615 case DMA_MEM_TO_DEV:
616 desc->rqcfg.src_inc = 1; 616 desc->rqcfg.src_inc = 1;
617 desc->rqcfg.dst_inc = 0; 617 desc->rqcfg.dst_inc = 0;
618 src = dma_addr; 618 src = dma_addr;
619 dst = pch->fifo_addr; 619 dst = pch->fifo_addr;
620 break; 620 break;
621 case DMA_FROM_DEVICE: 621 case DMA_DEV_TO_MEM:
622 desc->rqcfg.src_inc = 0; 622 desc->rqcfg.src_inc = 0;
623 desc->rqcfg.dst_inc = 1; 623 desc->rqcfg.dst_inc = 1;
624 src = pch->fifo_addr; 624 src = pch->fifo_addr;
@@ -687,7 +687,7 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
687 687
688static struct dma_async_tx_descriptor * 688static struct dma_async_tx_descriptor *
689pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 689pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
690 unsigned int sg_len, enum dma_data_direction direction, 690 unsigned int sg_len, enum dma_transfer_direction direction,
691 unsigned long flg) 691 unsigned long flg)
692{ 692{
693 struct dma_pl330_desc *first, *desc = NULL; 693 struct dma_pl330_desc *first, *desc = NULL;
@@ -702,9 +702,9 @@ pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
702 return NULL; 702 return NULL;
703 703
704 /* Make sure the direction is consistent */ 704 /* Make sure the direction is consistent */
705 if ((direction == DMA_TO_DEVICE && 705 if ((direction == DMA_MEM_TO_DEV &&
706 peri->rqtype != MEMTODEV) || 706 peri->rqtype != MEMTODEV) ||
707 (direction == DMA_FROM_DEVICE && 707 (direction == DMA_DEV_TO_MEM &&
708 peri->rqtype != DEVTOMEM)) { 708 peri->rqtype != DEVTOMEM)) {
709 dev_err(pch->dmac->pif.dev, "%s:%d Invalid Direction\n", 709 dev_err(pch->dmac->pif.dev, "%s:%d Invalid Direction\n",
710 __func__, __LINE__); 710 __func__, __LINE__);
@@ -747,7 +747,7 @@ pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
747 else 747 else
748 list_add_tail(&desc->node, &first->node); 748 list_add_tail(&desc->node, &first->node);
749 749
750 if (direction == DMA_TO_DEVICE) { 750 if (direction == DMA_MEM_TO_DEV) {
751 desc->rqcfg.src_inc = 1; 751 desc->rqcfg.src_inc = 1;
752 desc->rqcfg.dst_inc = 0; 752 desc->rqcfg.dst_inc = 0;
753 fill_px(&desc->px, 753 fill_px(&desc->px,
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index 81809c2b46ab..592304fb41a6 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -23,7 +23,6 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/dmaengine.h> 24#include <linux/dmaengine.h>
25#include <linux/delay.h> 25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h> 26#include <linux/platform_device.h>
28#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
29#include <linux/sh_dma.h> 28#include <linux/sh_dma.h>
@@ -479,19 +478,19 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan)
479 * @sh_chan: DMA channel 478 * @sh_chan: DMA channel
480 * @flags: DMA transfer flags 479 * @flags: DMA transfer flags
481 * @dest: destination DMA address, incremented when direction equals 480 * @dest: destination DMA address, incremented when direction equals
482 * DMA_FROM_DEVICE or DMA_BIDIRECTIONAL 481 * DMA_DEV_TO_MEM
483 * @src: source DMA address, incremented when direction equals 482 * @src: source DMA address, incremented when direction equals
484 * DMA_TO_DEVICE or DMA_BIDIRECTIONAL 483 * DMA_MEM_TO_DEV
485 * @len: DMA transfer length 484 * @len: DMA transfer length
486 * @first: if NULL, set to the current descriptor and cookie set to -EBUSY 485 * @first: if NULL, set to the current descriptor and cookie set to -EBUSY
487 * @direction: needed for slave DMA to decide which address to keep constant, 486 * @direction: needed for slave DMA to decide which address to keep constant,
488 * equals DMA_BIDIRECTIONAL for MEMCPY 487 * equals DMA_MEM_TO_MEM for MEMCPY
489 * Returns 0 or an error 488 * Returns 0 or an error
490 * Locks: called with desc_lock held 489 * Locks: called with desc_lock held
491 */ 490 */
492static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan, 491static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
493 unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len, 492 unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len,
494 struct sh_desc **first, enum dma_data_direction direction) 493 struct sh_desc **first, enum dma_transfer_direction direction)
495{ 494{
496 struct sh_desc *new; 495 struct sh_desc *new;
497 size_t copy_size; 496 size_t copy_size;
@@ -531,9 +530,9 @@ static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
531 new->direction = direction; 530 new->direction = direction;
532 531
533 *len -= copy_size; 532 *len -= copy_size;
534 if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE) 533 if (direction == DMA_MEM_TO_MEM || direction == DMA_MEM_TO_DEV)
535 *src += copy_size; 534 *src += copy_size;
536 if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE) 535 if (direction == DMA_MEM_TO_MEM || direction == DMA_DEV_TO_MEM)
537 *dest += copy_size; 536 *dest += copy_size;
538 537
539 return new; 538 return new;
@@ -546,12 +545,12 @@ static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan,
546 * converted to scatter-gather to guarantee consistent locking and a correct 545 * converted to scatter-gather to guarantee consistent locking and a correct
547 * list manipulation. For slave DMA direction carries the usual meaning, and, 546 * list manipulation. For slave DMA direction carries the usual meaning, and,
548 * logically, the SG list is RAM and the addr variable contains slave address, 547 * logically, the SG list is RAM and the addr variable contains slave address,
549 * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL 548 * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
550 * and the SG list contains only one element and points at the source buffer. 549 * and the SG list contains only one element and points at the source buffer.
551 */ 550 */
552static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan, 551static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan,
553 struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr, 552 struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
554 enum dma_data_direction direction, unsigned long flags) 553 enum dma_transfer_direction direction, unsigned long flags)
555{ 554{
556 struct scatterlist *sg; 555 struct scatterlist *sg;
557 struct sh_desc *first = NULL, *new = NULL /* compiler... */; 556 struct sh_desc *first = NULL, *new = NULL /* compiler... */;
@@ -592,7 +591,7 @@ static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_c
592 dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n", 591 dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n",
593 i, sg, len, (unsigned long long)sg_addr); 592 i, sg, len, (unsigned long long)sg_addr);
594 593
595 if (direction == DMA_FROM_DEVICE) 594 if (direction == DMA_DEV_TO_MEM)
596 new = sh_dmae_add_desc(sh_chan, flags, 595 new = sh_dmae_add_desc(sh_chan, flags,
597 &sg_addr, addr, &len, &first, 596 &sg_addr, addr, &len, &first,
598 direction); 597 direction);
@@ -646,13 +645,13 @@ static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy(
646 sg_dma_address(&sg) = dma_src; 645 sg_dma_address(&sg) = dma_src;
647 sg_dma_len(&sg) = len; 646 sg_dma_len(&sg) = len;
648 647
649 return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL, 648 return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_MEM_TO_MEM,
650 flags); 649 flags);
651} 650}
652 651
653static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg( 652static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg(
654 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 653 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
655 enum dma_data_direction direction, unsigned long flags) 654 enum dma_transfer_direction direction, unsigned long flags)
656{ 655{
657 struct sh_dmae_slave *param; 656 struct sh_dmae_slave *param;
658 struct sh_dmae_chan *sh_chan; 657 struct sh_dmae_chan *sh_chan;
@@ -996,7 +995,7 @@ static void dmae_do_tasklet(unsigned long data)
996 spin_lock_irq(&sh_chan->desc_lock); 995 spin_lock_irq(&sh_chan->desc_lock);
997 list_for_each_entry(desc, &sh_chan->ld_queue, node) { 996 list_for_each_entry(desc, &sh_chan->ld_queue, node) {
998 if (desc->mark == DESC_SUBMITTED && 997 if (desc->mark == DESC_SUBMITTED &&
999 ((desc->direction == DMA_FROM_DEVICE && 998 ((desc->direction == DMA_DEV_TO_MEM &&
1000 (desc->hw.dar + desc->hw.tcr) == dar_buf) || 999 (desc->hw.dar + desc->hw.tcr) == dar_buf) ||
1001 (desc->hw.sar + desc->hw.tcr) == sar_buf)) { 1000 (desc->hw.sar + desc->hw.tcr) == sar_buf)) {
1002 dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n", 1001 dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n",
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 467e4dcb20a0..0c6cbacb8321 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -216,7 +216,7 @@ struct d40_chan {
216 struct d40_log_lli_full *lcpa; 216 struct d40_log_lli_full *lcpa;
217 /* Runtime reconfiguration */ 217 /* Runtime reconfiguration */
218 dma_addr_t runtime_addr; 218 dma_addr_t runtime_addr;
219 enum dma_data_direction runtime_direction; 219 enum dma_transfer_direction runtime_direction;
220}; 220};
221 221
222/** 222/**
@@ -1854,7 +1854,7 @@ err:
1854} 1854}
1855 1855
1856static dma_addr_t 1856static dma_addr_t
1857d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction) 1857d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
1858{ 1858{
1859 struct stedma40_platform_data *plat = chan->base->plat_data; 1859 struct stedma40_platform_data *plat = chan->base->plat_data;
1860 struct stedma40_chan_cfg *cfg = &chan->dma_cfg; 1860 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
@@ -1863,9 +1863,9 @@ d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
1863 if (chan->runtime_addr) 1863 if (chan->runtime_addr)
1864 return chan->runtime_addr; 1864 return chan->runtime_addr;
1865 1865
1866 if (direction == DMA_FROM_DEVICE) 1866 if (direction == DMA_DEV_TO_MEM)
1867 addr = plat->dev_rx[cfg->src_dev_type]; 1867 addr = plat->dev_rx[cfg->src_dev_type];
1868 else if (direction == DMA_TO_DEVICE) 1868 else if (direction == DMA_MEM_TO_DEV)
1869 addr = plat->dev_tx[cfg->dst_dev_type]; 1869 addr = plat->dev_tx[cfg->dst_dev_type];
1870 1870
1871 return addr; 1871 return addr;
@@ -1874,7 +1874,7 @@ d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
1874static struct dma_async_tx_descriptor * 1874static struct dma_async_tx_descriptor *
1875d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, 1875d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
1876 struct scatterlist *sg_dst, unsigned int sg_len, 1876 struct scatterlist *sg_dst, unsigned int sg_len,
1877 enum dma_data_direction direction, unsigned long dma_flags) 1877 enum dma_transfer_direction direction, unsigned long dma_flags)
1878{ 1878{
1879 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); 1879 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
1880 dma_addr_t src_dev_addr = 0; 1880 dma_addr_t src_dev_addr = 0;
@@ -1901,9 +1901,9 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
1901 if (direction != DMA_NONE) { 1901 if (direction != DMA_NONE) {
1902 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); 1902 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
1903 1903
1904 if (direction == DMA_FROM_DEVICE) 1904 if (direction == DMA_DEV_TO_MEM)
1905 src_dev_addr = dev_addr; 1905 src_dev_addr = dev_addr;
1906 else if (direction == DMA_TO_DEVICE) 1906 else if (direction == DMA_MEM_TO_DEV)
1907 dst_dev_addr = dev_addr; 1907 dst_dev_addr = dev_addr;
1908 } 1908 }
1909 1909
@@ -2107,10 +2107,10 @@ d40_prep_memcpy_sg(struct dma_chan *chan,
2107static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan, 2107static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2108 struct scatterlist *sgl, 2108 struct scatterlist *sgl,
2109 unsigned int sg_len, 2109 unsigned int sg_len,
2110 enum dma_data_direction direction, 2110 enum dma_transfer_direction direction,
2111 unsigned long dma_flags) 2111 unsigned long dma_flags)
2112{ 2112{
2113 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) 2113 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV)
2114 return NULL; 2114 return NULL;
2115 2115
2116 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); 2116 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
@@ -2119,7 +2119,7 @@ static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2119static struct dma_async_tx_descriptor * 2119static struct dma_async_tx_descriptor *
2120dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr, 2120dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2121 size_t buf_len, size_t period_len, 2121 size_t buf_len, size_t period_len,
2122 enum dma_data_direction direction) 2122 enum dma_transfer_direction direction)
2123{ 2123{
2124 unsigned int periods = buf_len / period_len; 2124 unsigned int periods = buf_len / period_len;
2125 struct dma_async_tx_descriptor *txd; 2125 struct dma_async_tx_descriptor *txd;
@@ -2268,7 +2268,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2268 dst_addr_width = config->dst_addr_width; 2268 dst_addr_width = config->dst_addr_width;
2269 dst_maxburst = config->dst_maxburst; 2269 dst_maxburst = config->dst_maxburst;
2270 2270
2271 if (config->direction == DMA_FROM_DEVICE) { 2271 if (config->direction == DMA_DEV_TO_MEM) {
2272 dma_addr_t dev_addr_rx = 2272 dma_addr_t dev_addr_rx =
2273 d40c->base->plat_data->dev_rx[cfg->src_dev_type]; 2273 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2274 2274
@@ -2291,7 +2291,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2291 if (dst_maxburst == 0) 2291 if (dst_maxburst == 0)
2292 dst_maxburst = src_maxburst; 2292 dst_maxburst = src_maxburst;
2293 2293
2294 } else if (config->direction == DMA_TO_DEVICE) { 2294 } else if (config->direction == DMA_MEM_TO_DEV) {
2295 dma_addr_t dev_addr_tx = 2295 dma_addr_t dev_addr_tx =
2296 d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; 2296 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2297 2297
@@ -2356,7 +2356,7 @@ static int d40_set_runtime_config(struct dma_chan *chan,
2356 "configured channel %s for %s, data width %d/%d, " 2356 "configured channel %s for %s, data width %d/%d, "
2357 "maxburst %d/%d elements, LE, no flow control\n", 2357 "maxburst %d/%d elements, LE, no flow control\n",
2358 dma_chan_name(chan), 2358 dma_chan_name(chan),
2359 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", 2359 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2360 src_addr_width, dst_addr_width, 2360 src_addr_width, dst_addr_width,
2361 src_maxburst, dst_maxburst); 2361 src_maxburst, dst_maxburst);
2362 2362
diff --git a/drivers/dma/timb_dma.c b/drivers/dma/timb_dma.c
index a4a398f2ef61..8c880729b094 100644
--- a/drivers/dma/timb_dma.c
+++ b/drivers/dma/timb_dma.c
@@ -90,7 +90,7 @@ struct timb_dma_chan {
90 struct list_head queue; 90 struct list_head queue;
91 struct list_head free_list; 91 struct list_head free_list;
92 unsigned int bytes_per_line; 92 unsigned int bytes_per_line;
93 enum dma_data_direction direction; 93 enum dma_transfer_direction direction;
94 unsigned int descs; /* Descriptors to allocate */ 94 unsigned int descs; /* Descriptors to allocate */
95 unsigned int desc_elems; /* number of elems per descriptor */ 95 unsigned int desc_elems; /* number of elems per descriptor */
96}; 96};
@@ -235,7 +235,7 @@ static void __td_start_dma(struct timb_dma_chan *td_chan)
235 "td_chan: %p, chan: %d, membase: %p\n", 235 "td_chan: %p, chan: %d, membase: %p\n",
236 td_chan, td_chan->chan.chan_id, td_chan->membase); 236 td_chan, td_chan->chan.chan_id, td_chan->membase);
237 237
238 if (td_chan->direction == DMA_FROM_DEVICE) { 238 if (td_chan->direction == DMA_DEV_TO_MEM) {
239 239
240 /* descriptor address */ 240 /* descriptor address */
241 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); 241 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR);
@@ -278,7 +278,7 @@ static void __td_finish(struct timb_dma_chan *td_chan)
278 txd->cookie); 278 txd->cookie);
279 279
280 /* make sure to stop the transfer */ 280 /* make sure to stop the transfer */
281 if (td_chan->direction == DMA_FROM_DEVICE) 281 if (td_chan->direction == DMA_DEV_TO_MEM)
282 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER); 282 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER);
283/* Currently no support for stopping DMA transfers 283/* Currently no support for stopping DMA transfers
284 else 284 else
@@ -398,7 +398,7 @@ static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan)
398 td_desc->txd.flags = DMA_CTRL_ACK; 398 td_desc->txd.flags = DMA_CTRL_ACK;
399 399
400 td_desc->txd.phys = dma_map_single(chan2dmadev(chan), 400 td_desc->txd.phys = dma_map_single(chan2dmadev(chan),
401 td_desc->desc_list, td_desc->desc_list_len, DMA_TO_DEVICE); 401 td_desc->desc_list, td_desc->desc_list_len, DMA_MEM_TO_DEV);
402 402
403 err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys); 403 err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys);
404 if (err) { 404 if (err) {
@@ -419,7 +419,7 @@ static void td_free_desc(struct timb_dma_desc *td_desc)
419{ 419{
420 dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc); 420 dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc);
421 dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys, 421 dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys,
422 td_desc->desc_list_len, DMA_TO_DEVICE); 422 td_desc->desc_list_len, DMA_MEM_TO_DEV);
423 423
424 kfree(td_desc->desc_list); 424 kfree(td_desc->desc_list);
425 kfree(td_desc); 425 kfree(td_desc);
@@ -558,7 +558,7 @@ static void td_issue_pending(struct dma_chan *chan)
558 558
559static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan, 559static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
560 struct scatterlist *sgl, unsigned int sg_len, 560 struct scatterlist *sgl, unsigned int sg_len,
561 enum dma_data_direction direction, unsigned long flags) 561 enum dma_transfer_direction direction, unsigned long flags)
562{ 562{
563 struct timb_dma_chan *td_chan = 563 struct timb_dma_chan *td_chan =
564 container_of(chan, struct timb_dma_chan, chan); 564 container_of(chan, struct timb_dma_chan, chan);
@@ -606,7 +606,7 @@ static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
606 } 606 }
607 607
608 dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys, 608 dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys,
609 td_desc->desc_list_len, DMA_TO_DEVICE); 609 td_desc->desc_list_len, DMA_MEM_TO_DEV);
610 610
611 return &td_desc->txd; 611 return &td_desc->txd;
612} 612}
@@ -775,8 +775,8 @@ static int __devinit td_probe(struct platform_device *pdev)
775 td_chan->descs = pchan->descriptors; 775 td_chan->descs = pchan->descriptors;
776 td_chan->desc_elems = pchan->descriptor_elements; 776 td_chan->desc_elems = pchan->descriptor_elements;
777 td_chan->bytes_per_line = pchan->bytes_per_line; 777 td_chan->bytes_per_line = pchan->bytes_per_line;
778 td_chan->direction = pchan->rx ? DMA_FROM_DEVICE : 778 td_chan->direction = pchan->rx ? DMA_DEV_TO_MEM :
779 DMA_TO_DEVICE; 779 DMA_MEM_TO_DEV;
780 780
781 td_chan->membase = td->membase + 781 td_chan->membase = td->membase +
782 (i / 2) * TIMBDMA_INSTANCE_OFFSET + 782 (i / 2) * TIMBDMA_INSTANCE_OFFSET +
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
index cbd83e362b5e..6122c364cf11 100644
--- a/drivers/dma/txx9dmac.c
+++ b/drivers/dma/txx9dmac.c
@@ -845,7 +845,7 @@ txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
845 845
846static struct dma_async_tx_descriptor * 846static struct dma_async_tx_descriptor *
847txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 847txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
848 unsigned int sg_len, enum dma_data_direction direction, 848 unsigned int sg_len, enum dma_transfer_direction direction,
849 unsigned long flags) 849 unsigned long flags)
850{ 850{
851 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan); 851 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
@@ -860,9 +860,9 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
860 860
861 BUG_ON(!ds || !ds->reg_width); 861 BUG_ON(!ds || !ds->reg_width);
862 if (ds->tx_reg) 862 if (ds->tx_reg)
863 BUG_ON(direction != DMA_TO_DEVICE); 863 BUG_ON(direction != DMA_MEM_TO_DEV);
864 else 864 else
865 BUG_ON(direction != DMA_FROM_DEVICE); 865 BUG_ON(direction != DMA_DEV_TO_MEM);
866 if (unlikely(!sg_len)) 866 if (unlikely(!sg_len))
867 return NULL; 867 return NULL;
868 868
@@ -882,7 +882,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
882 mem = sg_dma_address(sg); 882 mem = sg_dma_address(sg);
883 883
884 if (__is_dmac64(ddev)) { 884 if (__is_dmac64(ddev)) {
885 if (direction == DMA_TO_DEVICE) { 885 if (direction == DMA_MEM_TO_DEV) {
886 desc->hwdesc.SAR = mem; 886 desc->hwdesc.SAR = mem;
887 desc->hwdesc.DAR = ds->tx_reg; 887 desc->hwdesc.DAR = ds->tx_reg;
888 } else { 888 } else {
@@ -891,7 +891,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
891 } 891 }
892 desc->hwdesc.CNTR = sg_dma_len(sg); 892 desc->hwdesc.CNTR = sg_dma_len(sg);
893 } else { 893 } else {
894 if (direction == DMA_TO_DEVICE) { 894 if (direction == DMA_MEM_TO_DEV) {
895 desc->hwdesc32.SAR = mem; 895 desc->hwdesc32.SAR = mem;
896 desc->hwdesc32.DAR = ds->tx_reg; 896 desc->hwdesc32.DAR = ds->tx_reg;
897 } else { 897 } else {
@@ -900,7 +900,7 @@ txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
900 } 900 }
901 desc->hwdesc32.CNTR = sg_dma_len(sg); 901 desc->hwdesc32.CNTR = sg_dma_len(sg);
902 } 902 }
903 if (direction == DMA_TO_DEVICE) { 903 if (direction == DMA_MEM_TO_DEV) {
904 sai = ds->reg_width; 904 sai = ds->reg_width;
905 dai = 0; 905 dai = 0;
906 } else { 906 } else {
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
index 9eabffbc4e50..033f6aa670de 100644
--- a/include/linux/amba/pl08x.h
+++ b/include/linux/amba/pl08x.h
@@ -134,7 +134,7 @@ struct pl08x_txd {
134 struct dma_async_tx_descriptor tx; 134 struct dma_async_tx_descriptor tx;
135 struct list_head node; 135 struct list_head node;
136 struct list_head dsg_list; 136 struct list_head dsg_list;
137 enum dma_data_direction direction; 137 enum dma_transfer_direction direction;
138 dma_addr_t llis_bus; 138 dma_addr_t llis_bus;
139 struct pl08x_lli *llis_va; 139 struct pl08x_lli *llis_va;
140 /* Default cctl value for LLIs */ 140 /* Default cctl value for LLIs */
@@ -197,7 +197,7 @@ struct pl08x_dma_chan {
197 dma_addr_t dst_addr; 197 dma_addr_t dst_addr;
198 u32 src_cctl; 198 u32 src_cctl;
199 u32 dst_cctl; 199 u32 dst_cctl;
200 enum dma_data_direction runtime_direction; 200 enum dma_transfer_direction runtime_direction;
201 dma_cookie_t lc; 201 dma_cookie_t lc;
202 struct list_head pend_list; 202 struct list_head pend_list;
203 struct pl08x_txd *at; 203 struct pl08x_txd *at;
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index 4bfe0a2f7d50..f2c64f92c4a0 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -127,7 +127,7 @@ struct dw_cyclic_desc {
127 127
128struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 128struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
129 dma_addr_t buf_addr, size_t buf_len, size_t period_len, 129 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
130 enum dma_data_direction direction); 130 enum dma_transfer_direction direction);
131void dw_dma_cyclic_free(struct dma_chan *chan); 131void dw_dma_cyclic_free(struct dma_chan *chan);
132int dw_dma_cyclic_start(struct dma_chan *chan); 132int dw_dma_cyclic_start(struct dma_chan *chan);
133void dw_dma_cyclic_stop(struct dma_chan *chan); 133void dw_dma_cyclic_stop(struct dma_chan *chan);
diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
index cb2dd118cc0f..62ef6938da10 100644
--- a/include/linux/sh_dma.h
+++ b/include/linux/sh_dma.h
@@ -30,7 +30,7 @@ struct sh_desc {
30 struct sh_dmae_regs hw; 30 struct sh_dmae_regs hw;
31 struct list_head node; 31 struct list_head node;
32 struct dma_async_tx_descriptor async_tx; 32 struct dma_async_tx_descriptor async_tx;
33 enum dma_data_direction direction; 33 enum dma_transfer_direction direction;
34 dma_cookie_t cookie; 34 dma_cookie_t cookie;
35 size_t partial; 35 size_t partial;
36 int chunks; 36 int chunks;