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authorAlan <alan@lxorguk.ukuu.org.uk>2007-01-10 12:13:38 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-09 17:39:34 -0500
commitd2cdfc0db39247518585db13a3abdc633a158e0e (patch)
tree542e8f9c82de2303205d8222b9b3aaec9d875e67
parentfba6edbd3bbd5e6c10b8247d3c3794e718bbc811 (diff)
libata: PIIX3 support
This I believe completes the PIIX range of support for libata This adds the table entries needed for the PIIX3, both a new PCI identifier and a new mode list. It also fixes an erroneous access to PCI configuration 0x48 on non UDMA capable chips. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r--drivers/ata/ata_piix.c18
1 files changed, 15 insertions, 3 deletions
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index aadfcb3ceb1b..33bbeac785cc 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -118,7 +118,7 @@ enum {
118 PIIX_80C_SEC = (1 << 7) | (1 << 6), 118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119 119
120 /* controller IDs */ 120 /* controller IDs */
121 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */ 121 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */ 122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
123 ich_pata_66 = 2, /* ICH up to 66 Mhz */ 123 ich_pata_66 = 2, /* ICH up to 66 Mhz */
124 ich_pata_100 = 3, /* ICH up to UDMA 100 */ 124 ich_pata_100 = 3, /* ICH up to UDMA 100 */
@@ -128,6 +128,7 @@ enum {
128 ich6_sata_ahci = 7, 128 ich6_sata_ahci = 7,
129 ich6m_sata_ahci = 8, 129 ich6m_sata_ahci = 8,
130 ich8_sata_ahci = 9, 130 ich8_sata_ahci = 9,
131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
131 132
132 /* constants for mapping table */ 133 /* constants for mapping table */
133 P0 = 0, /* port 0 */ 134 P0 = 0, /* port 0 */
@@ -165,6 +166,8 @@ static unsigned int in_module_init = 1;
165 166
166static const struct pci_device_id piix_pci_tbl[] = { 167static const struct pci_device_id piix_pci_tbl[] = {
167#ifdef ATA_ENABLE_PATA 168#ifdef ATA_ENABLE_PATA
169 /* Intel PIIX3 for the 430HX etc */
170 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
168 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ 171 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
169 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ 172 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
170 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, 173 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
@@ -441,7 +444,7 @@ static const struct piix_map_db *piix_map_db_table[] = {
441}; 444};
442 445
443static struct ata_port_info piix_port_info[] = { 446static struct ata_port_info piix_port_info[] = {
444 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */ 447 /* piix_pata_33: 0: PIIX4 at 33MHz */
445 { 448 {
446 .sht = &piix_sht, 449 .sht = &piix_sht,
447 .flags = PIIX_PATA_FLAGS, 450 .flags = PIIX_PATA_FLAGS,
@@ -543,6 +546,14 @@ static struct ata_port_info piix_port_info[] = {
543 .port_ops = &piix_sata_ops, 546 .port_ops = &piix_sata_ops,
544 }, 547 },
545 548
549 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
550 {
551 .sht = &piix_sht,
552 .flags = PIIX_PATA_FLAGS,
553 .pio_mask = 0x1f, /* pio0-4 */
554 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
555 .port_ops = &piix_pata_ops,
556 },
546}; 557};
547 558
548static struct pci_bits piix_enable_bits[] = { 559static struct pci_bits piix_enable_bits[] = {
@@ -787,7 +798,8 @@ static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, i
787 { 2, 3 }, }; 798 { 2, 3 }, };
788 799
789 pci_read_config_word(dev, master_port, &master_data); 800 pci_read_config_word(dev, master_port, &master_data);
790 pci_read_config_byte(dev, 0x48, &udma_enable); 801 if (ap->udma_mask)
802 pci_read_config_byte(dev, 0x48, &udma_enable);
791 803
792 if (speed >= XFER_UDMA_0) { 804 if (speed >= XFER_UDMA_0) {
793 unsigned int udma = adev->dma_mode - XFER_UDMA_0; 805 unsigned int udma = adev->dma_mode - XFER_UDMA_0;