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authorfrançois romieu <romieu@fr.zoreil.com>2011-01-19 23:59:23 -0500
committerDavid S. Miller <davem@davemloft.net>2011-01-20 19:50:05 -0500
commitccd5c8ef24590bd0e1277ae6f6c0b7790afd371d (patch)
treedad76b9c70bcbae001a88a69684f59b785ff7105
parent34aac66cc2c32f6cd0bd08e0a0e6de851d261e36 (diff)
atl1e: remove private #define.
Either unused or duplicates from mii.h. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Jay Cliburn <jcliburn@gmail.com> Cc: Chris Snook <chris.snook@gmail.com> Cc: Jie Yang <jie.yang@atheros.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/atl1e/atl1e_ethtool.c12
-rw-r--r--drivers/net/atl1e/atl1e_hw.c34
-rw-r--r--drivers/net/atl1e/atl1e_hw.h111
-rw-r--r--drivers/net/atl1e/atl1e_main.c4
4 files changed, 25 insertions, 136 deletions
diff --git a/drivers/net/atl1e/atl1e_ethtool.c b/drivers/net/atl1e/atl1e_ethtool.c
index 6943a6c3b948..1209297433b8 100644
--- a/drivers/net/atl1e/atl1e_ethtool.c
+++ b/drivers/net/atl1e/atl1e_ethtool.c
@@ -95,18 +95,18 @@ static int atl1e_set_settings(struct net_device *netdev,
95 ecmd->advertising = hw->autoneg_advertised | 95 ecmd->advertising = hw->autoneg_advertised |
96 ADVERTISED_TP | ADVERTISED_Autoneg; 96 ADVERTISED_TP | ADVERTISED_Autoneg;
97 97
98 adv4 = hw->mii_autoneg_adv_reg & ~MII_AR_SPEED_MASK; 98 adv4 = hw->mii_autoneg_adv_reg & ~ADVERTISE_ALL;
99 adv9 = hw->mii_1000t_ctrl_reg & ~MII_AT001_CR_1000T_SPEED_MASK; 99 adv9 = hw->mii_1000t_ctrl_reg & ~MII_AT001_CR_1000T_SPEED_MASK;
100 if (hw->autoneg_advertised & ADVERTISE_10_HALF) 100 if (hw->autoneg_advertised & ADVERTISE_10_HALF)
101 adv4 |= MII_AR_10T_HD_CAPS; 101 adv4 |= ADVERTISE_10HALF;
102 if (hw->autoneg_advertised & ADVERTISE_10_FULL) 102 if (hw->autoneg_advertised & ADVERTISE_10_FULL)
103 adv4 |= MII_AR_10T_FD_CAPS; 103 adv4 |= ADVERTISE_10FULL;
104 if (hw->autoneg_advertised & ADVERTISE_100_HALF) 104 if (hw->autoneg_advertised & ADVERTISE_100_HALF)
105 adv4 |= MII_AR_100TX_HD_CAPS; 105 adv4 |= ADVERTISE_100HALF;
106 if (hw->autoneg_advertised & ADVERTISE_100_FULL) 106 if (hw->autoneg_advertised & ADVERTISE_100_FULL)
107 adv4 |= MII_AR_100TX_FD_CAPS; 107 adv4 |= ADVERTISE_100FULL;
108 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) 108 if (hw->autoneg_advertised & ADVERTISE_1000_FULL)
109 adv9 |= MII_AT001_CR_1000T_FD_CAPS; 109 adv9 |= ADVERTISE_1000FULL;
110 110
111 if (adv4 != hw->mii_autoneg_adv_reg || 111 if (adv4 != hw->mii_autoneg_adv_reg ||
112 adv9 != hw->mii_1000t_ctrl_reg) { 112 adv9 != hw->mii_1000t_ctrl_reg) {
diff --git a/drivers/net/atl1e/atl1e_hw.c b/drivers/net/atl1e/atl1e_hw.c
index 76cc043def8c..923063d2e5bb 100644
--- a/drivers/net/atl1e/atl1e_hw.c
+++ b/drivers/net/atl1e/atl1e_hw.c
@@ -318,7 +318,7 @@ static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
318 * Advertisement Register (Address 4) and the 1000 mb speed bits in 318 * Advertisement Register (Address 4) and the 1000 mb speed bits in
319 * the 1000Base-T control Register (Address 9). 319 * the 1000Base-T control Register (Address 9).
320 */ 320 */
321 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 321 mii_autoneg_adv_reg &= ~ADVERTISE_ALL;
322 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK; 322 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
323 323
324 /* 324 /*
@@ -327,44 +327,37 @@ static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
327 */ 327 */
328 switch (hw->media_type) { 328 switch (hw->media_type) {
329 case MEDIA_TYPE_AUTO_SENSOR: 329 case MEDIA_TYPE_AUTO_SENSOR:
330 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | 330 mii_autoneg_adv_reg |= ADVERTISE_ALL;
331 MII_AR_10T_FD_CAPS | 331 hw->autoneg_advertised = ADVERTISE_ALL;
332 MII_AR_100TX_HD_CAPS |
333 MII_AR_100TX_FD_CAPS);
334 hw->autoneg_advertised = ADVERTISE_10_HALF |
335 ADVERTISE_10_FULL |
336 ADVERTISE_100_HALF |
337 ADVERTISE_100_FULL;
338 if (hw->nic_type == athr_l1e) { 332 if (hw->nic_type == athr_l1e) {
339 mii_1000t_ctrl_reg |= 333 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
340 MII_AT001_CR_1000T_FD_CAPS;
341 hw->autoneg_advertised |= ADVERTISE_1000_FULL; 334 hw->autoneg_advertised |= ADVERTISE_1000_FULL;
342 } 335 }
343 break; 336 break;
344 337
345 case MEDIA_TYPE_100M_FULL: 338 case MEDIA_TYPE_100M_FULL:
346 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; 339 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
347 hw->autoneg_advertised = ADVERTISE_100_FULL; 340 hw->autoneg_advertised = ADVERTISE_100_FULL;
348 break; 341 break;
349 342
350 case MEDIA_TYPE_100M_HALF: 343 case MEDIA_TYPE_100M_HALF:
351 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; 344 mii_autoneg_adv_reg |= ADVERTISE_100_HALF;
352 hw->autoneg_advertised = ADVERTISE_100_HALF; 345 hw->autoneg_advertised = ADVERTISE_100_HALF;
353 break; 346 break;
354 347
355 case MEDIA_TYPE_10M_FULL: 348 case MEDIA_TYPE_10M_FULL:
356 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; 349 mii_autoneg_adv_reg |= ADVERTISE_10_FULL;
357 hw->autoneg_advertised = ADVERTISE_10_FULL; 350 hw->autoneg_advertised = ADVERTISE_10_FULL;
358 break; 351 break;
359 352
360 default: 353 default:
361 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; 354 mii_autoneg_adv_reg |= ADVERTISE_10_HALF;
362 hw->autoneg_advertised = ADVERTISE_10_HALF; 355 hw->autoneg_advertised = ADVERTISE_10_HALF;
363 break; 356 break;
364 } 357 }
365 358
366 /* flow control fixed to enable all */ 359 /* flow control fixed to enable all */
367 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 360 mii_autoneg_adv_reg |= (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
368 361
369 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 362 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
370 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; 363 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
@@ -374,7 +367,7 @@ static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
374 return ret_val; 367 return ret_val;
375 368
376 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { 369 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
377 ret_val = atl1e_write_phy_reg(hw, MII_AT001_CR, 370 ret_val = atl1e_write_phy_reg(hw, MII_CTRL1000,
378 mii_1000t_ctrl_reg); 371 mii_1000t_ctrl_reg);
379 if (ret_val) 372 if (ret_val)
380 return ret_val; 373 return ret_val;
@@ -397,7 +390,7 @@ int atl1e_phy_commit(struct atl1e_hw *hw)
397 int ret_val; 390 int ret_val;
398 u16 phy_data; 391 u16 phy_data;
399 392
400 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 393 phy_data = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
401 394
402 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data); 395 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
403 if (ret_val) { 396 if (ret_val) {
@@ -645,15 +638,14 @@ int atl1e_restart_autoneg(struct atl1e_hw *hw)
645 return err; 638 return err;
646 639
647 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { 640 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
648 err = atl1e_write_phy_reg(hw, MII_AT001_CR, 641 err = atl1e_write_phy_reg(hw, MII_CTRL1000,
649 hw->mii_1000t_ctrl_reg); 642 hw->mii_1000t_ctrl_reg);
650 if (err) 643 if (err)
651 return err; 644 return err;
652 } 645 }
653 646
654 err = atl1e_write_phy_reg(hw, MII_BMCR, 647 err = atl1e_write_phy_reg(hw, MII_BMCR,
655 MII_CR_RESET | MII_CR_AUTO_NEG_EN | 648 BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART);
656 MII_CR_RESTART_AUTO_NEG);
657 return err; 649 return err;
658} 650}
659 651
diff --git a/drivers/net/atl1e/atl1e_hw.h b/drivers/net/atl1e/atl1e_hw.h
index 5ea2f4d86cfa..74df16aef793 100644
--- a/drivers/net/atl1e/atl1e_hw.h
+++ b/drivers/net/atl1e/atl1e_hw.h
@@ -629,127 +629,24 @@ s32 atl1e_restart_autoneg(struct atl1e_hw *hw);
629 629
630/***************************** MII definition ***************************************/ 630/***************************** MII definition ***************************************/
631/* PHY Common Register */ 631/* PHY Common Register */
632#define MII_BMCR 0x00
633#define MII_BMSR 0x01
634#define MII_PHYSID1 0x02
635#define MII_PHYSID2 0x03
636#define MII_ADVERTISE 0x04
637#define MII_LPA 0x05
638#define MII_EXPANSION 0x06
639#define MII_AT001_CR 0x09
640#define MII_AT001_SR 0x0A
641#define MII_AT001_ESR 0x0F
642#define MII_AT001_PSCR 0x10 632#define MII_AT001_PSCR 0x10
643#define MII_AT001_PSSR 0x11 633#define MII_AT001_PSSR 0x11
644#define MII_INT_CTRL 0x12 634#define MII_INT_CTRL 0x12
645#define MII_INT_STATUS 0x13 635#define MII_INT_STATUS 0x13
646#define MII_SMARTSPEED 0x14 636#define MII_SMARTSPEED 0x14
647#define MII_RERRCOUNTER 0x15
648#define MII_SREVISION 0x16
649#define MII_RESV1 0x17
650#define MII_LBRERROR 0x18 637#define MII_LBRERROR 0x18
651#define MII_PHYADDR 0x19
652#define MII_RESV2 0x1a 638#define MII_RESV2 0x1a
653#define MII_TPISTATUS 0x1b
654#define MII_NCONFIG 0x1c
655 639
656#define MII_DBG_ADDR 0x1D 640#define MII_DBG_ADDR 0x1D
657#define MII_DBG_DATA 0x1E 641#define MII_DBG_DATA 0x1E
658 642
659
660/* PHY Control Register */
661#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
662#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
663#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
664#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
665#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
666#define MII_CR_POWER_DOWN 0x0800 /* Power down */
667#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
668#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
669#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
670#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
671#define MII_CR_SPEED_MASK 0x2040
672#define MII_CR_SPEED_1000 0x0040
673#define MII_CR_SPEED_100 0x2000
674#define MII_CR_SPEED_10 0x0000
675
676
677/* PHY Status Register */
678#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
679#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
680#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
681#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
682#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
683#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
684#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
685#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
686#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
687#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
688#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
689#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
690#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
691#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
692#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
693
694/* Link partner ability register. */
695#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
696#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
697#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
698#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
699#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
700#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
701#define MII_LPA_PAUSE 0x0400 /* PAUSE */
702#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
703#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
704#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
705#define MII_LPA_NPAGE 0x8000 /* Next page bit */
706
707/* Autoneg Advertisement Register */ 643/* Autoneg Advertisement Register */
708#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 644#define MII_AR_DEFAULT_CAP_MASK 0
709#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
710#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
711#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
712#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
713#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
714#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
715#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
716#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
717#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
718#define MII_AR_SPEED_MASK 0x01E0
719#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
720 645
721/* 1000BASE-T Control Register */ 646/* 1000BASE-T Control Register */
722#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 647#define MII_AT001_CR_1000T_SPEED_MASK \
723#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 648 (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
724#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 649#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK MII_AT001_CR_1000T_SPEED_MASK
725/* 0=DTE device */
726#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
727/* 0=Configure PHY as Slave */
728#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
729/* 0=Automatic Master/Slave config */
730#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
731#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
732#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
733#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
734#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
735#define MII_AT001_CR_1000T_SPEED_MASK 0x0300
736#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
737
738/* 1000BASE-T Status Register */
739#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
740#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
741#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
742#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
743#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
744#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
745#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
746#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
747
748/* Extended Status Register */
749#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
750#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
751#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
752#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
753 650
754/* AT001 PHY Specific Control Register */ 651/* AT001 PHY Specific Control Register */
755#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 652#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
diff --git a/drivers/net/atl1e/atl1e_main.c b/drivers/net/atl1e/atl1e_main.c
index e28f8baf394e..bf7500ccd73f 100644
--- a/drivers/net/atl1e/atl1e_main.c
+++ b/drivers/net/atl1e/atl1e_main.c
@@ -2051,9 +2051,9 @@ static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
2051 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data); 2051 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2052 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data); 2052 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2053 2053
2054 mii_advertise_data = MII_AR_10T_HD_CAPS; 2054 mii_advertise_data = ADVERTISE_10HALF;
2055 2055
2056 if ((atl1e_write_phy_reg(hw, MII_AT001_CR, 0) != 0) || 2056 if ((atl1e_write_phy_reg(hw, MII_CTRL1000, 0) != 0) ||
2057 (atl1e_write_phy_reg(hw, 2057 (atl1e_write_phy_reg(hw,
2058 MII_ADVERTISE, mii_advertise_data) != 0) || 2058 MII_ADVERTISE, mii_advertise_data) != 0) ||
2059 (atl1e_phy_commit(hw)) != 0) { 2059 (atl1e_phy_commit(hw)) != 0) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-02 07:24:27 -0400