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authoreric miao <eric.miao@marvell.com>2008-02-12 19:52:38 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-04-19 06:29:05 -0400
commit9b02b2df0099c083ea40ba8c7068e3dcbe381302 (patch)
tree1d3c7ec4bc1b930c072c32bd87589dab88319510
parentfef06d274feb9b0e5a2d20c29b2979634514243f (diff)
[ARM] pxa: use new pin configuration mechanism for lubbock
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-pxa/lubbock.c82
1 files changed, 37 insertions, 45 deletions
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 81567ec983a4..a9e32066a54a 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -42,7 +42,7 @@
42 42
43#include <asm/arch/pxa-regs.h> 43#include <asm/arch/pxa-regs.h>
44#include <asm/arch/pxa2xx-regs.h> 44#include <asm/arch/pxa2xx-regs.h>
45#include <asm/arch/pxa2xx-gpio.h> 45#include <asm/arch/mfp-pxa25x.h>
46#include <asm/arch/lubbock.h> 46#include <asm/arch/lubbock.h>
47#include <asm/arch/udc.h> 47#include <asm/arch/udc.h>
48#include <asm/arch/irda.h> 48#include <asm/arch/irda.h>
@@ -52,6 +52,40 @@
52#include "generic.h" 52#include "generic.h"
53#include "devices.h" 53#include "devices.h"
54 54
55static unsigned long lubbock_pin_config[] __initdata = {
56 GPIO15_nCS_1, /* CS1 - Flash */
57 GPIO79_nCS_3, /* CS3 - SMC ethernet */
58
59 /* SSP data pins */
60 GPIO23_SSP1_SCLK,
61 GPIO25_SSP1_TXD,
62 GPIO26_SSP1_RXD,
63
64 /* BTUART */
65 GPIO42_BTUART_RXD,
66 GPIO43_BTUART_TXD,
67 GPIO44_BTUART_CTS,
68 GPIO45_BTUART_RTS,
69
70 /* PC Card */
71 GPIO48_nPOE,
72 GPIO49_nPWE,
73 GPIO50_nPIOR,
74 GPIO51_nPIOW,
75 GPIO52_nPCE_1,
76 GPIO53_nPCE_2,
77 GPIO54_nPSKTSEL,
78 GPIO55_nPREG,
79 GPIO56_nPWAIT,
80 GPIO57_nIOIS16,
81
82 /* MMC */
83 GPIO6_MMC_CLK,
84 GPIO8_MMC_CS0,
85
86 /* wakeup */
87 GPIO1_GPIO | WAKEUP_ON_EDGE_RISE,
88};
55 89
56#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) 90#define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
57 91
@@ -405,10 +439,6 @@ static int lubbock_mci_init(struct device *dev,
405 irq_handler_t detect_int, 439 irq_handler_t detect_int,
406 void *data) 440 void *data)
407{ 441{
408 /* setup GPIO for PXA25x MMC controller */
409 pxa_gpio_mode(GPIO6_MMCCLK_MD);
410 pxa_gpio_mode(GPIO8_MMCCS0_MD);
411
412 /* detect card insert/eject */ 442 /* detect card insert/eject */
413 mmc_detect_int = detect_int; 443 mmc_detect_int = detect_int;
414 init_timer(&mmc_timer); 444 init_timer(&mmc_timer);
@@ -458,6 +488,8 @@ static void __init lubbock_init(void)
458{ 488{
459 int flashboot = (LUB_CONF_SWITCHES & 1); 489 int flashboot = (LUB_CONF_SWITCHES & 1);
460 490
491 pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config));
492
461 pxa_set_udc_info(&udc_info); 493 pxa_set_udc_info(&udc_info);
462 set_pxa_fb_info(&sharp_lm8v31); 494 set_pxa_fb_info(&sharp_lm8v31);
463 pxa_set_mci_info(&lubbock_mci_platform_data); 495 pxa_set_mci_info(&lubbock_mci_platform_data);
@@ -490,46 +522,6 @@ static void __init lubbock_map_io(void)
490 pxa_map_io(); 522 pxa_map_io();
491 iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc)); 523 iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
492 524
493 /* SSP data pins */
494 pxa_gpio_mode(GPIO23_SCLK_MD);
495 pxa_gpio_mode(GPIO25_STXD_MD);
496 pxa_gpio_mode(GPIO26_SRXD_MD);
497
498 /* This enables the BTUART */
499 pxa_gpio_mode(GPIO42_BTRXD_MD);
500 pxa_gpio_mode(GPIO43_BTTXD_MD);
501 pxa_gpio_mode(GPIO44_BTCTS_MD);
502 pxa_gpio_mode(GPIO45_BTRTS_MD);
503
504 GPSR(GPIO48_nPOE) =
505 GPIO_bit(GPIO48_nPOE) |
506 GPIO_bit(GPIO49_nPWE) |
507 GPIO_bit(GPIO50_nPIOR) |
508 GPIO_bit(GPIO51_nPIOW) |
509 GPIO_bit(GPIO52_nPCE_1) |
510 GPIO_bit(GPIO53_nPCE_2);
511
512 pxa_gpio_mode(GPIO48_nPOE_MD);
513 pxa_gpio_mode(GPIO49_nPWE_MD);
514 pxa_gpio_mode(GPIO50_nPIOR_MD);
515 pxa_gpio_mode(GPIO51_nPIOW_MD);
516 pxa_gpio_mode(GPIO52_nPCE_1_MD);
517 pxa_gpio_mode(GPIO53_nPCE_2_MD);
518 pxa_gpio_mode(GPIO54_pSKTSEL_MD);
519 pxa_gpio_mode(GPIO55_nPREG_MD);
520 pxa_gpio_mode(GPIO56_nPWAIT_MD);
521 pxa_gpio_mode(GPIO57_nIOIS16_MD);
522
523 /* This is for the SMC chip select */
524 pxa_gpio_mode(GPIO79_nCS_3_MD);
525
526 /* setup sleep mode values */
527 PWER = 0x00000002;
528 PFER = 0x00000000;
529 PRER = 0x00000002;
530 PGSR0 = 0x00008000;
531 PGSR1 = 0x003F0202;
532 PGSR2 = 0x0001C000;
533 PCFR |= PCFR_OPDE; 525 PCFR |= PCFR_OPDE;
534} 526}
535 527